1 /***************************************************************************** 2 * 3 * Copyright (C) 2014 Atmel Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * 17 * * Neither the name of the copyright holders nor the names of 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 ****************************************************************************/ 33 34 35 /* $Id: iox128d4.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iox128d4.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 #ifndef _AVR_ATXMEGA128D4_H_INCLUDED 48 #define _AVR_ATXMEGA128D4_H_INCLUDED 49 50 /* Ungrouped common registers */ 51 #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 52 #define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 53 #define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 54 #define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 55 56 /* Deprecated */ 57 #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 58 #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 59 #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 60 #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 61 62 #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ 63 #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ 64 #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ 65 #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ 66 #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ 67 #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ 68 #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ 69 #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ 70 #define SREG _SFR_MEM8(0x003F) /* Status Register */ 71 72 /* C Language Only */ 73 #if !defined (__ASSEMBLER__) 74 75 #include <stdint.h> 76 77 typedef volatile uint8_t register8_t; 78 typedef volatile uint16_t register16_t; 79 typedef volatile uint32_t register32_t; 80 81 82 #ifdef _WORDREGISTER 83 #undef _WORDREGISTER 84 #endif 85 #define _WORDREGISTER(regname) \ 86 __extension__ union \ 87 { \ 88 register16_t regname; \ 89 struct \ 90 { \ 91 register8_t regname ## L; \ 92 register8_t regname ## H; \ 93 }; \ 94 } 95 96 #ifdef _DWORDREGISTER 97 #undef _DWORDREGISTER 98 #endif 99 #define _DWORDREGISTER(regname) \ 100 __extension__ union \ 101 { \ 102 register32_t regname; \ 103 struct \ 104 { \ 105 register8_t regname ## 0; \ 106 register8_t regname ## 1; \ 107 register8_t regname ## 2; \ 108 register8_t regname ## 3; \ 109 }; \ 110 } 111 112 113 /* 114 ========================================================================== 115 IO Module Structures 116 ========================================================================== 117 */ 118 119 120 /* 121 -------------------------------------------------------------------------- 122 VPORT - Virtual Ports 123 -------------------------------------------------------------------------- 124 */ 125 126 /* Virtual Port */ 127 typedef struct VPORT_struct 128 { 129 register8_t DIR; /* I/O Port Data Direction */ 130 register8_t OUT; /* I/O Port Output */ 131 register8_t IN; /* I/O Port Input */ 132 register8_t INTFLAGS; /* Interrupt Flag Register */ 133 } VPORT_t; 134 135 136 /* 137 -------------------------------------------------------------------------- 138 XOCD - On-Chip Debug System 139 -------------------------------------------------------------------------- 140 */ 141 142 /* On-Chip Debug System */ 143 typedef struct OCD_struct 144 { 145 register8_t OCDR0; /* OCD Register 0 */ 146 register8_t OCDR1; /* OCD Register 1 */ 147 } OCD_t; 148 149 150 /* 151 -------------------------------------------------------------------------- 152 CPU - CPU 153 -------------------------------------------------------------------------- 154 */ 155 156 /* CCP signatures */ 157 typedef enum CCP_enum 158 { 159 CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ 160 CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ 161 } CCP_t; 162 163 164 /* 165 -------------------------------------------------------------------------- 166 CLK - Clock System 167 -------------------------------------------------------------------------- 168 */ 169 170 /* Clock System */ 171 typedef struct CLK_struct 172 { 173 register8_t CTRL; /* Control Register */ 174 register8_t PSCTRL; /* Prescaler Control Register */ 175 register8_t LOCK; /* Lock register */ 176 register8_t RTCCTRL; /* RTC Control Register */ 177 register8_t reserved_0x04; 178 } CLK_t; 179 180 181 /* Power Reduction */ 182 typedef struct PR_struct 183 { 184 register8_t PRGEN; /* General Power Reduction */ 185 register8_t PRPA; /* Power Reduction Port A */ 186 register8_t reserved_0x02; 187 register8_t PRPC; /* Power Reduction Port C */ 188 register8_t PRPD; /* Power Reduction Port D */ 189 register8_t PRPE; /* Power Reduction Port E */ 190 register8_t PRPF; /* Power Reduction Port F */ 191 } PR_t; 192 193 /* System Clock Selection */ 194 typedef enum CLK_SCLKSEL_enum 195 { 196 CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ 197 CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ 198 CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ 199 CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ 200 CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ 201 } CLK_SCLKSEL_t; 202 203 /* Prescaler A Division Factor */ 204 typedef enum CLK_PSADIV_enum 205 { 206 CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ 207 CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ 208 CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ 209 CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ 210 CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ 211 CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ 212 CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ 213 CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ 214 CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ 215 CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ 216 } CLK_PSADIV_t; 217 218 /* Prescaler B and C Division Factor */ 219 typedef enum CLK_PSBCDIV_enum 220 { 221 CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ 222 CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ 223 CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ 224 CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ 225 } CLK_PSBCDIV_t; 226 227 /* RTC Clock Source */ 228 typedef enum CLK_RTCSRC_enum 229 { 230 CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ 231 CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ 232 CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ 233 CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ 234 CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ 235 CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ 236 } CLK_RTCSRC_t; 237 238 239 /* 240 -------------------------------------------------------------------------- 241 SLEEP - Sleep Controller 242 -------------------------------------------------------------------------- 243 */ 244 245 /* Sleep Controller */ 246 typedef struct SLEEP_struct 247 { 248 register8_t CTRL; /* Control Register */ 249 } SLEEP_t; 250 251 /* Sleep Mode */ 252 typedef enum SLEEP_SMODE_enum 253 { 254 SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ 255 SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ 256 SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ 257 SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ 258 SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ 259 } SLEEP_SMODE_t; 260 261 262 #define SLEEP_MODE_IDLE (0x00<<1) 263 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 264 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 265 #define SLEEP_MODE_STANDBY (0x06<<1) 266 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 267 268 269 /* 270 -------------------------------------------------------------------------- 271 OSC - Oscillator 272 -------------------------------------------------------------------------- 273 */ 274 275 /* Oscillator */ 276 typedef struct OSC_struct 277 { 278 register8_t CTRL; /* Control Register */ 279 register8_t STATUS; /* Status Register */ 280 register8_t XOSCCTRL; /* External Oscillator Control Register */ 281 register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ 282 register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ 283 register8_t PLLCTRL; /* PLL Control Register */ 284 register8_t DFLLCTRL; /* DFLL Control Register */ 285 } OSC_t; 286 287 /* Oscillator Frequency Range */ 288 typedef enum OSC_FRQRANGE_enum 289 { 290 OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ 291 OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ 292 OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ 293 OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ 294 } OSC_FRQRANGE_t; 295 296 /* External Oscillator Selection and Startup Time */ 297 typedef enum OSC_XOSCSEL_enum 298 { 299 OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ 300 OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ 301 OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ 302 OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ 303 OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ 304 } OSC_XOSCSEL_t; 305 306 /* PLL Clock Source */ 307 typedef enum OSC_PLLSRC_enum 308 { 309 OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ 310 OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ 311 OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ 312 } OSC_PLLSRC_t; 313 314 /* 2 MHz DFLL Calibration Reference */ 315 typedef enum OSC_RC2MCREF_enum 316 { 317 OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ 318 OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ 319 } OSC_RC2MCREF_t; 320 321 /* 32 MHz DFLL Calibration Reference */ 322 typedef enum OSC_RC32MCREF_enum 323 { 324 OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ 325 OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ 326 } OSC_RC32MCREF_t; 327 328 329 /* 330 -------------------------------------------------------------------------- 331 DFLL - DFLL 332 -------------------------------------------------------------------------- 333 */ 334 335 /* DFLL */ 336 typedef struct DFLL_struct 337 { 338 register8_t CTRL; /* Control Register */ 339 register8_t reserved_0x01; 340 register8_t CALA; /* Calibration Register A */ 341 register8_t CALB; /* Calibration Register B */ 342 register8_t COMP0; /* Oscillator Compare Register 0 */ 343 register8_t COMP1; /* Oscillator Compare Register 1 */ 344 register8_t COMP2; /* Oscillator Compare Register 2 */ 345 register8_t reserved_0x07; 346 } DFLL_t; 347 348 349 /* 350 -------------------------------------------------------------------------- 351 RST - Reset 352 -------------------------------------------------------------------------- 353 */ 354 355 /* Reset */ 356 typedef struct RST_struct 357 { 358 register8_t STATUS; /* Status Register */ 359 register8_t CTRL; /* Control Register */ 360 } RST_t; 361 362 363 /* 364 -------------------------------------------------------------------------- 365 WDT - Watch-Dog Timer 366 -------------------------------------------------------------------------- 367 */ 368 369 /* Watch-Dog Timer */ 370 typedef struct WDT_struct 371 { 372 register8_t CTRL; /* Control */ 373 register8_t WINCTRL; /* Windowed Mode Control */ 374 register8_t STATUS; /* Status */ 375 } WDT_t; 376 377 /* Period setting */ 378 typedef enum WDT_PER_enum 379 { 380 WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 381 WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 382 WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 383 WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 384 WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ 385 WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ 386 WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ 387 WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 388 WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 389 WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 390 WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 391 } WDT_PER_t; 392 393 /* Closed window period */ 394 typedef enum WDT_WPER_enum 395 { 396 WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 397 WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 398 WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 399 WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 400 WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ 401 WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ 402 WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ 403 WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 404 WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 405 WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 406 WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 407 } WDT_WPER_t; 408 409 410 /* 411 -------------------------------------------------------------------------- 412 MCU - MCU Control 413 -------------------------------------------------------------------------- 414 */ 415 416 /* MCU Control */ 417 typedef struct MCU_struct 418 { 419 register8_t DEVID0; /* Device ID byte 0 */ 420 register8_t DEVID1; /* Device ID byte 1 */ 421 register8_t DEVID2; /* Device ID byte 2 */ 422 register8_t REVID; /* Revision ID */ 423 register8_t reserved_0x04; 424 register8_t reserved_0x05; 425 register8_t reserved_0x06; 426 register8_t ANAINIT; /* Analog Startup Delay */ 427 register8_t EVSYSLOCK; /* Event System Lock */ 428 register8_t AWEXLOCK; /* AWEX Lock */ 429 register8_t reserved_0x0A; 430 register8_t reserved_0x0B; 431 } MCU_t; 432 433 434 /* 435 -------------------------------------------------------------------------- 436 PMIC - Programmable Multi-level Interrupt Controller 437 -------------------------------------------------------------------------- 438 */ 439 440 /* Programmable Multi-level Interrupt Controller */ 441 typedef struct PMIC_struct 442 { 443 register8_t STATUS; /* Status Register */ 444 register8_t INTPRI; /* Interrupt Priority */ 445 register8_t CTRL; /* Control Register */ 446 register8_t reserved_0x03; 447 register8_t reserved_0x04; 448 register8_t reserved_0x05; 449 register8_t reserved_0x06; 450 register8_t reserved_0x07; 451 register8_t reserved_0x08; 452 register8_t reserved_0x09; 453 register8_t reserved_0x0A; 454 register8_t reserved_0x0B; 455 register8_t reserved_0x0C; 456 register8_t reserved_0x0D; 457 register8_t reserved_0x0E; 458 register8_t reserved_0x0F; 459 } PMIC_t; 460 461 462 /* 463 -------------------------------------------------------------------------- 464 PORTCFG - Port Configuration 465 -------------------------------------------------------------------------- 466 */ 467 468 /* I/O port Configuration */ 469 typedef struct PORTCFG_struct 470 { 471 register8_t MPCMASK; /* Multi-pin Configuration Mask */ 472 register8_t reserved_0x01; 473 register8_t VPCTRLA; /* Virtual Port Control Register A */ 474 register8_t VPCTRLB; /* Virtual Port Control Register B */ 475 register8_t CLKEVOUT; /* Clock and Event Out Register */ 476 register8_t reserved_0x05; 477 register8_t EVOUTSEL; /* Event Output Select */ 478 } PORTCFG_t; 479 480 /* Virtual Port Mapping */ 481 typedef enum PORTCFG_VP02MAP_enum 482 { 483 PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 484 PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 485 PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 486 PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 487 PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 488 PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 489 PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 490 PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 491 PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 492 PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 493 PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 494 PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 495 PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 496 PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 497 PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 498 PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 499 } PORTCFG_VP02MAP_t; 500 501 /* Virtual Port Mapping */ 502 typedef enum PORTCFG_VP13MAP_enum 503 { 504 PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 505 PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 506 PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 507 PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 508 PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 509 PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 510 PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 511 PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 512 PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 513 PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 514 PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 515 PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 516 PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 517 PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 518 PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 519 PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 520 } PORTCFG_VP13MAP_t; 521 522 /* System Clock Output Port */ 523 typedef enum PORTCFG_CLKOUT_enum 524 { 525 PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ 526 PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ 527 PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ 528 PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ 529 } PORTCFG_CLKOUT_t; 530 531 /* Peripheral Clock Output Select */ 532 typedef enum PORTCFG_CLKOUTSEL_enum 533 { 534 PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ 535 PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ 536 PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ 537 } PORTCFG_CLKOUTSEL_t; 538 539 /* Event Output Port */ 540 typedef enum PORTCFG_EVOUT_enum 541 { 542 PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ 543 PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ 544 PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ 545 PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ 546 } PORTCFG_EVOUT_t; 547 548 /* Event Output Select */ 549 typedef enum PORTCFG_EVOUTSEL_enum 550 { 551 PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ 552 PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ 553 PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ 554 PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ 555 } PORTCFG_EVOUTSEL_t; 556 557 558 /* 559 -------------------------------------------------------------------------- 560 CRC - Cyclic Redundancy Checker 561 -------------------------------------------------------------------------- 562 */ 563 564 /* Cyclic Redundancy Checker */ 565 typedef struct CRC_struct 566 { 567 register8_t CTRL; /* Control Register */ 568 register8_t STATUS; /* Status Register */ 569 register8_t reserved_0x02; 570 register8_t DATAIN; /* Data Input */ 571 register8_t CHECKSUM0; /* Checksum byte 0 */ 572 register8_t CHECKSUM1; /* Checksum byte 1 */ 573 register8_t CHECKSUM2; /* Checksum byte 2 */ 574 register8_t CHECKSUM3; /* Checksum byte 3 */ 575 } CRC_t; 576 577 /* Reset */ 578 typedef enum CRC_RESET_enum 579 { 580 CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ 581 CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ 582 CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ 583 } CRC_RESET_t; 584 585 /* Input Source */ 586 typedef enum CRC_SOURCE_enum 587 { 588 CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ 589 CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ 590 CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ 591 } CRC_SOURCE_t; 592 593 594 /* 595 -------------------------------------------------------------------------- 596 EVSYS - Event System 597 -------------------------------------------------------------------------- 598 */ 599 600 /* Event System */ 601 typedef struct EVSYS_struct 602 { 603 register8_t CH0MUX; /* Event Channel 0 Multiplexer */ 604 register8_t CH1MUX; /* Event Channel 1 Multiplexer */ 605 register8_t CH2MUX; /* Event Channel 2 Multiplexer */ 606 register8_t CH3MUX; /* Event Channel 3 Multiplexer */ 607 register8_t reserved_0x04; 608 register8_t reserved_0x05; 609 register8_t reserved_0x06; 610 register8_t reserved_0x07; 611 register8_t CH0CTRL; /* Channel 0 Control Register */ 612 register8_t CH1CTRL; /* Channel 1 Control Register */ 613 register8_t CH2CTRL; /* Channel 2 Control Register */ 614 register8_t CH3CTRL; /* Channel 3 Control Register */ 615 register8_t reserved_0x0C; 616 register8_t reserved_0x0D; 617 register8_t reserved_0x0E; 618 register8_t reserved_0x0F; 619 register8_t STROBE; /* Event Strobe */ 620 register8_t DATA; /* Event Data */ 621 } EVSYS_t; 622 623 /* Quadrature Decoder Index Recognition Mode */ 624 typedef enum EVSYS_QDIRM_enum 625 { 626 EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ 627 EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ 628 EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ 629 EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ 630 } EVSYS_QDIRM_t; 631 632 /* Digital filter coefficient */ 633 typedef enum EVSYS_DIGFILT_enum 634 { 635 EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ 636 EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ 637 EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ 638 EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ 639 EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ 640 EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ 641 EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ 642 EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ 643 } EVSYS_DIGFILT_t; 644 645 /* Event Channel multiplexer input selection */ 646 typedef enum EVSYS_CHMUX_enum 647 { 648 EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ 649 EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ 650 EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ 651 EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ 652 EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ 653 EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ 654 EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ 655 EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ 656 EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ 657 EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ 658 EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ 659 EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ 660 EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ 661 EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ 662 EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ 663 EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ 664 EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ 665 EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ 666 EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ 667 EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ 668 EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ 669 EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ 670 EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ 671 EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ 672 EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ 673 EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ 674 EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ 675 EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ 676 EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ 677 EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ 678 EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ 679 EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ 680 EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ 681 EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ 682 EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ 683 EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ 684 EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ 685 EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ 686 EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ 687 EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ 688 EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ 689 EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ 690 EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ 691 EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ 692 EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ 693 EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ 694 EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ 695 EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ 696 EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ 697 EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ 698 EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ 699 EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ 700 EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ 701 EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ 702 EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ 703 EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ 704 EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ 705 EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ 706 EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ 707 EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ 708 EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ 709 EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ 710 EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ 711 EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ 712 EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ 713 EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ 714 EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ 715 EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ 716 EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ 717 EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ 718 EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ 719 EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ 720 EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ 721 EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ 722 EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ 723 EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ 724 EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ 725 EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ 726 EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ 727 EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ 728 EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ 729 EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ 730 EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ 731 EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ 732 EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ 733 EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ 734 EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ 735 EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ 736 EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ 737 EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ 738 EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ 739 EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ 740 EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ 741 EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ 742 EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ 743 EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ 744 EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ 745 EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ 746 EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ 747 } EVSYS_CHMUX_t; 748 749 750 /* 751 -------------------------------------------------------------------------- 752 NVM - Non Volatile Memory Controller 753 -------------------------------------------------------------------------- 754 */ 755 756 /* Non-volatile Memory Controller */ 757 typedef struct NVM_struct 758 { 759 register8_t ADDR0; /* Address Register 0 */ 760 register8_t ADDR1; /* Address Register 1 */ 761 register8_t ADDR2; /* Address Register 2 */ 762 register8_t reserved_0x03; 763 register8_t DATA0; /* Data Register 0 */ 764 register8_t DATA1; /* Data Register 1 */ 765 register8_t DATA2; /* Data Register 2 */ 766 register8_t reserved_0x07; 767 register8_t reserved_0x08; 768 register8_t reserved_0x09; 769 register8_t CMD; /* Command */ 770 register8_t CTRLA; /* Control Register A */ 771 register8_t CTRLB; /* Control Register B */ 772 register8_t INTCTRL; /* Interrupt Control */ 773 register8_t reserved_0x0E; 774 register8_t STATUS; /* Status */ 775 register8_t LOCKBITS; /* Lock Bits */ 776 } NVM_t; 777 778 /* NVM Command */ 779 typedef enum NVM_CMD_enum 780 { 781 NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ 782 NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ 783 NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ 784 NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ 785 NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ 786 NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ 787 NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ 788 NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ 789 NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ 790 NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ 791 NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ 792 NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ 793 NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ 794 NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ 795 NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ 796 NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ 797 NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ 798 NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ 799 NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ 800 NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ 801 NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ 802 NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ 803 NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ 804 NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ 805 NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ 806 NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ 807 NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ 808 NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ 809 NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ 810 NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ 811 NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ 812 NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ 813 NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ 814 NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ 815 } NVM_CMD_t; 816 817 /* SPM ready interrupt level */ 818 typedef enum NVM_SPMLVL_enum 819 { 820 NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 821 NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ 822 NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ 823 NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ 824 } NVM_SPMLVL_t; 825 826 /* EEPROM ready interrupt level */ 827 typedef enum NVM_EELVL_enum 828 { 829 NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 830 NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ 831 NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ 832 NVM_EELVL_HI_gc = (0x03<<0), /* High level */ 833 } NVM_EELVL_t; 834 835 /* Boot lock bits - boot setcion */ 836 typedef enum NVM_BLBB_enum 837 { 838 NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 839 NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 840 NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 841 NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 842 } NVM_BLBB_t; 843 844 /* Boot lock bits - application section */ 845 typedef enum NVM_BLBA_enum 846 { 847 NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 848 NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 849 NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 850 NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 851 } NVM_BLBA_t; 852 853 /* Boot lock bits - application table section */ 854 typedef enum NVM_BLBAT_enum 855 { 856 NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 857 NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 858 NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 859 NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 860 } NVM_BLBAT_t; 861 862 /* Lock bits */ 863 typedef enum NVM_LB_enum 864 { 865 NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 866 NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 867 NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 868 } NVM_LB_t; 869 870 871 /* 872 -------------------------------------------------------------------------- 873 ADC - Analog/Digital Converter 874 -------------------------------------------------------------------------- 875 */ 876 877 /* ADC Channel */ 878 typedef struct ADC_CH_struct 879 { 880 register8_t CTRL; /* Control Register */ 881 register8_t MUXCTRL; /* MUX Control */ 882 register8_t INTCTRL; /* Channel Interrupt Control Register */ 883 register8_t INTFLAGS; /* Interrupt Flags */ 884 _WORDREGISTER(RES); /* Channel Result */ 885 register8_t SCAN; /* Input Channel Scan */ 886 register8_t reserved_0x07; 887 } ADC_CH_t; 888 889 890 /* Analog-to-Digital Converter */ 891 typedef struct ADC_struct 892 { 893 register8_t CTRLA; /* Control Register A */ 894 register8_t CTRLB; /* Control Register B */ 895 register8_t REFCTRL; /* Reference Control */ 896 register8_t EVCTRL; /* Event Control */ 897 register8_t PRESCALER; /* Clock Prescaler */ 898 register8_t reserved_0x05; 899 register8_t INTFLAGS; /* Interrupt Flags */ 900 register8_t TEMP; /* Temporary Register */ 901 register8_t reserved_0x08; 902 register8_t reserved_0x09; 903 register8_t reserved_0x0A; 904 register8_t reserved_0x0B; 905 _WORDREGISTER(CAL); /* Calibration Value */ 906 register8_t reserved_0x0E; 907 register8_t reserved_0x0F; 908 _WORDREGISTER(CH0RES); /* Channel 0 Result */ 909 register8_t reserved_0x12; 910 register8_t reserved_0x13; 911 register8_t reserved_0x14; 912 register8_t reserved_0x15; 913 register8_t reserved_0x16; 914 register8_t reserved_0x17; 915 _WORDREGISTER(CMP); /* Compare Value */ 916 register8_t reserved_0x1A; 917 register8_t reserved_0x1B; 918 register8_t reserved_0x1C; 919 register8_t reserved_0x1D; 920 register8_t reserved_0x1E; 921 register8_t reserved_0x1F; 922 ADC_CH_t CH0; /* ADC Channel 0 */ 923 } ADC_t; 924 925 /* Current Limitation */ 926 typedef enum ADC_CURRLIMIT_enum 927 { 928 ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ 929 ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ 930 ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ 931 ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ 932 } ADC_CURRLIMIT_t; 933 934 /* Positive input multiplexer selection */ 935 typedef enum ADC_CH_MUXPOS_enum 936 { 937 ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ 938 ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ 939 ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ 940 ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ 941 ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ 942 ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ 943 ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ 944 ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ 945 ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ 946 ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ 947 ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ 948 ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ 949 } ADC_CH_MUXPOS_t; 950 951 /* Internal input multiplexer selections */ 952 typedef enum ADC_CH_MUXINT_enum 953 { 954 ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ 955 ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ 956 ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ 957 } ADC_CH_MUXINT_t; 958 959 /* Negative input multiplexer selection */ 960 typedef enum ADC_CH_MUXNEG_enum 961 { 962 ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ 963 ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ 964 ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ 965 ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ 966 ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ 967 ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ 968 ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ 969 ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ 970 } ADC_CH_MUXNEG_t; 971 972 /* Input mode */ 973 typedef enum ADC_CH_INPUTMODE_enum 974 { 975 ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ 976 ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ 977 ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ 978 ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ 979 } ADC_CH_INPUTMODE_t; 980 981 /* Gain factor */ 982 typedef enum ADC_CH_GAIN_enum 983 { 984 ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ 985 ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ 986 ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ 987 ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ 988 ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ 989 ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ 990 ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ 991 ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ 992 } ADC_CH_GAIN_t; 993 994 /* Conversion result resolution */ 995 typedef enum ADC_RESOLUTION_enum 996 { 997 ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ 998 ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ 999 ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ 1000 } ADC_RESOLUTION_t; 1001 1002 /* Voltage reference selection */ 1003 typedef enum ADC_REFSEL_enum 1004 { 1005 ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ 1006 ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ 1007 ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ 1008 ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ 1009 ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ 1010 } ADC_REFSEL_t; 1011 1012 /* Event channel input selection */ 1013 typedef enum ADC_EVSEL_enum 1014 { 1015 ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ 1016 ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ 1017 ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ 1018 ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ 1019 } ADC_EVSEL_t; 1020 1021 /* Event action selection */ 1022 typedef enum ADC_EVACT_enum 1023 { 1024 ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ 1025 ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ 1026 ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ 1027 } ADC_EVACT_t; 1028 1029 /* Interupt mode */ 1030 typedef enum ADC_CH_INTMODE_enum 1031 { 1032 ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ 1033 ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ 1034 ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ 1035 } ADC_CH_INTMODE_t; 1036 1037 /* Interrupt level */ 1038 typedef enum ADC_CH_INTLVL_enum 1039 { 1040 ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1041 ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1042 ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1043 ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ 1044 } ADC_CH_INTLVL_t; 1045 1046 /* Clock prescaler */ 1047 typedef enum ADC_PRESCALER_enum 1048 { 1049 ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ 1050 ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ 1051 ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ 1052 ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ 1053 ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ 1054 ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ 1055 ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ 1056 ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ 1057 } ADC_PRESCALER_t; 1058 1059 1060 /* 1061 -------------------------------------------------------------------------- 1062 AC - Analog Comparator 1063 -------------------------------------------------------------------------- 1064 */ 1065 1066 /* Analog Comparator */ 1067 typedef struct AC_struct 1068 { 1069 register8_t AC0CTRL; /* Analog Comparator 0 Control */ 1070 register8_t AC1CTRL; /* Analog Comparator 1 Control */ 1071 register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ 1072 register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ 1073 register8_t CTRLA; /* Control Register A */ 1074 register8_t CTRLB; /* Control Register B */ 1075 register8_t WINCTRL; /* Window Mode Control */ 1076 register8_t STATUS; /* Status */ 1077 } AC_t; 1078 1079 /* Interrupt mode */ 1080 typedef enum AC_INTMODE_enum 1081 { 1082 AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ 1083 AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ 1084 AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ 1085 } AC_INTMODE_t; 1086 1087 /* Interrupt level */ 1088 typedef enum AC_INTLVL_enum 1089 { 1090 AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ 1091 AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ 1092 AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ 1093 AC_INTLVL_HI_gc = (0x03<<4), /* High level */ 1094 } AC_INTLVL_t; 1095 1096 /* Hysteresis mode selection */ 1097 typedef enum AC_HYSMODE_enum 1098 { 1099 AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ 1100 AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ 1101 AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ 1102 } AC_HYSMODE_t; 1103 1104 /* Positive input multiplexer selection */ 1105 typedef enum AC_MUXPOS_enum 1106 { 1107 AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ 1108 AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ 1109 AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ 1110 AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ 1111 AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ 1112 AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ 1113 AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ 1114 } AC_MUXPOS_t; 1115 1116 /* Negative input multiplexer selection */ 1117 typedef enum AC_MUXNEG_enum 1118 { 1119 AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ 1120 AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ 1121 AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ 1122 AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ 1123 AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ 1124 AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ 1125 AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ 1126 } AC_MUXNEG_t; 1127 1128 /* Windows interrupt mode */ 1129 typedef enum AC_WINTMODE_enum 1130 { 1131 AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ 1132 AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ 1133 AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ 1134 AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ 1135 } AC_WINTMODE_t; 1136 1137 /* Window interrupt level */ 1138 typedef enum AC_WINTLVL_enum 1139 { 1140 AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1141 AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ 1142 AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ 1143 AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ 1144 } AC_WINTLVL_t; 1145 1146 /* Window mode state */ 1147 typedef enum AC_WSTATE_enum 1148 { 1149 AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ 1150 AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ 1151 AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ 1152 } AC_WSTATE_t; 1153 1154 1155 /* 1156 -------------------------------------------------------------------------- 1157 RTC - Real-Time Counter 1158 -------------------------------------------------------------------------- 1159 */ 1160 1161 /* Real-Time Counter */ 1162 typedef struct RTC_struct 1163 { 1164 register8_t CTRL; /* Control Register */ 1165 register8_t STATUS; /* Status Register */ 1166 register8_t INTCTRL; /* Interrupt Control Register */ 1167 register8_t INTFLAGS; /* Interrupt Flags */ 1168 register8_t TEMP; /* Temporary register */ 1169 register8_t reserved_0x05; 1170 register8_t reserved_0x06; 1171 register8_t reserved_0x07; 1172 _WORDREGISTER(CNT); /* Count Register */ 1173 _WORDREGISTER(PER); /* Period Register */ 1174 _WORDREGISTER(COMP); /* Compare Register */ 1175 } RTC_t; 1176 1177 /* Prescaler Factor */ 1178 typedef enum RTC_PRESCALER_enum 1179 { 1180 RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ 1181 RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ 1182 RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ 1183 RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ 1184 RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ 1185 RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ 1186 RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ 1187 RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ 1188 } RTC_PRESCALER_t; 1189 1190 /* Compare Interrupt level */ 1191 typedef enum RTC_COMPINTLVL_enum 1192 { 1193 RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1194 RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1195 RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1196 RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ 1197 } RTC_COMPINTLVL_t; 1198 1199 /* Overflow Interrupt level */ 1200 typedef enum RTC_OVFINTLVL_enum 1201 { 1202 RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1203 RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1204 RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1205 RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1206 } RTC_OVFINTLVL_t; 1207 1208 1209 /* 1210 -------------------------------------------------------------------------- 1211 TWI - Two-Wire Interface 1212 -------------------------------------------------------------------------- 1213 */ 1214 1215 /* */ 1216 typedef struct TWI_MASTER_struct 1217 { 1218 register8_t CTRLA; /* Control Register A */ 1219 register8_t CTRLB; /* Control Register B */ 1220 register8_t CTRLC; /* Control Register C */ 1221 register8_t STATUS; /* Status Register */ 1222 register8_t BAUD; /* Baurd Rate Control Register */ 1223 register8_t ADDR; /* Address Register */ 1224 register8_t DATA; /* Data Register */ 1225 } TWI_MASTER_t; 1226 1227 1228 /* */ 1229 typedef struct TWI_SLAVE_struct 1230 { 1231 register8_t CTRLA; /* Control Register A */ 1232 register8_t CTRLB; /* Control Register B */ 1233 register8_t STATUS; /* Status Register */ 1234 register8_t ADDR; /* Address Register */ 1235 register8_t DATA; /* Data Register */ 1236 register8_t ADDRMASK; /* Address Mask Register */ 1237 } TWI_SLAVE_t; 1238 1239 1240 /* Two-Wire Interface */ 1241 typedef struct TWI_struct 1242 { 1243 register8_t CTRL; /* TWI Common Control Register */ 1244 TWI_MASTER_t MASTER; /* TWI master module */ 1245 TWI_SLAVE_t SLAVE; /* TWI slave module */ 1246 } TWI_t; 1247 1248 /* SDA Hold Time */ 1249 typedef enum TWI_SDAHOLD_enum 1250 { 1251 TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ 1252 TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ 1253 TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ 1254 TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ 1255 } TWI_SDAHOLD_t; 1256 1257 /* Master Interrupt Level */ 1258 typedef enum TWI_MASTER_INTLVL_enum 1259 { 1260 TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1261 TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1262 TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1263 TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1264 } TWI_MASTER_INTLVL_t; 1265 1266 /* Inactive Timeout */ 1267 typedef enum TWI_MASTER_TIMEOUT_enum 1268 { 1269 TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ 1270 TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ 1271 TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ 1272 TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ 1273 } TWI_MASTER_TIMEOUT_t; 1274 1275 /* Master Command */ 1276 typedef enum TWI_MASTER_CMD_enum 1277 { 1278 TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1279 TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ 1280 TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ 1281 TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ 1282 } TWI_MASTER_CMD_t; 1283 1284 /* Master Bus State */ 1285 typedef enum TWI_MASTER_BUSSTATE_enum 1286 { 1287 TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ 1288 TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ 1289 TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ 1290 TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ 1291 } TWI_MASTER_BUSSTATE_t; 1292 1293 /* Slave Interrupt Level */ 1294 typedef enum TWI_SLAVE_INTLVL_enum 1295 { 1296 TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1297 TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1298 TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1299 TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1300 } TWI_SLAVE_INTLVL_t; 1301 1302 /* Slave Command */ 1303 typedef enum TWI_SLAVE_CMD_enum 1304 { 1305 TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1306 TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ 1307 TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ 1308 } TWI_SLAVE_CMD_t; 1309 1310 1311 /* 1312 -------------------------------------------------------------------------- 1313 PORT - I/O Port Configuration 1314 -------------------------------------------------------------------------- 1315 */ 1316 1317 /* I/O Ports */ 1318 typedef struct PORT_struct 1319 { 1320 register8_t DIR; /* I/O Port Data Direction */ 1321 register8_t DIRSET; /* I/O Port Data Direction Set */ 1322 register8_t DIRCLR; /* I/O Port Data Direction Clear */ 1323 register8_t DIRTGL; /* I/O Port Data Direction Toggle */ 1324 register8_t OUT; /* I/O Port Output */ 1325 register8_t OUTSET; /* I/O Port Output Set */ 1326 register8_t OUTCLR; /* I/O Port Output Clear */ 1327 register8_t OUTTGL; /* I/O Port Output Toggle */ 1328 register8_t IN; /* I/O port Input */ 1329 register8_t INTCTRL; /* Interrupt Control Register */ 1330 register8_t INT0MASK; /* Port Interrupt 0 Mask */ 1331 register8_t INT1MASK; /* Port Interrupt 1 Mask */ 1332 register8_t INTFLAGS; /* Interrupt Flag Register */ 1333 register8_t reserved_0x0D; 1334 register8_t REMAP; /* I/O Port Pin Remap Register */ 1335 register8_t reserved_0x0F; 1336 register8_t PIN0CTRL; /* Pin 0 Control Register */ 1337 register8_t PIN1CTRL; /* Pin 1 Control Register */ 1338 register8_t PIN2CTRL; /* Pin 2 Control Register */ 1339 register8_t PIN3CTRL; /* Pin 3 Control Register */ 1340 register8_t PIN4CTRL; /* Pin 4 Control Register */ 1341 register8_t PIN5CTRL; /* Pin 5 Control Register */ 1342 register8_t PIN6CTRL; /* Pin 6 Control Register */ 1343 register8_t PIN7CTRL; /* Pin 7 Control Register */ 1344 } PORT_t; 1345 1346 /* Port Interrupt 0 Level */ 1347 typedef enum PORT_INT0LVL_enum 1348 { 1349 PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1350 PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ 1351 PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ 1352 PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ 1353 } PORT_INT0LVL_t; 1354 1355 /* Port Interrupt 1 Level */ 1356 typedef enum PORT_INT1LVL_enum 1357 { 1358 PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1359 PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ 1360 PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ 1361 PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ 1362 } PORT_INT1LVL_t; 1363 1364 /* Output/Pull Configuration */ 1365 typedef enum PORT_OPC_enum 1366 { 1367 PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ 1368 PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ 1369 PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ 1370 PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ 1371 PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ 1372 PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ 1373 PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ 1374 PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ 1375 } PORT_OPC_t; 1376 1377 /* Input/Sense Configuration */ 1378 typedef enum PORT_ISC_enum 1379 { 1380 PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ 1381 PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ 1382 PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ 1383 PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ 1384 PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ 1385 } PORT_ISC_t; 1386 1387 1388 /* 1389 -------------------------------------------------------------------------- 1390 TC - 16-bit Timer/Counter With PWM 1391 -------------------------------------------------------------------------- 1392 */ 1393 1394 /* 16-bit Timer/Counter 0 */ 1395 typedef struct TC0_struct 1396 { 1397 register8_t CTRLA; /* Control Register A */ 1398 register8_t CTRLB; /* Control Register B */ 1399 register8_t CTRLC; /* Control register C */ 1400 register8_t CTRLD; /* Control Register D */ 1401 register8_t CTRLE; /* Control Register E */ 1402 register8_t reserved_0x05; 1403 register8_t INTCTRLA; /* Interrupt Control Register A */ 1404 register8_t INTCTRLB; /* Interrupt Control Register B */ 1405 register8_t CTRLFCLR; /* Control Register F Clear */ 1406 register8_t CTRLFSET; /* Control Register F Set */ 1407 register8_t CTRLGCLR; /* Control Register G Clear */ 1408 register8_t CTRLGSET; /* Control Register G Set */ 1409 register8_t INTFLAGS; /* Interrupt Flag Register */ 1410 register8_t reserved_0x0D; 1411 register8_t reserved_0x0E; 1412 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1413 register8_t reserved_0x10; 1414 register8_t reserved_0x11; 1415 register8_t reserved_0x12; 1416 register8_t reserved_0x13; 1417 register8_t reserved_0x14; 1418 register8_t reserved_0x15; 1419 register8_t reserved_0x16; 1420 register8_t reserved_0x17; 1421 register8_t reserved_0x18; 1422 register8_t reserved_0x19; 1423 register8_t reserved_0x1A; 1424 register8_t reserved_0x1B; 1425 register8_t reserved_0x1C; 1426 register8_t reserved_0x1D; 1427 register8_t reserved_0x1E; 1428 register8_t reserved_0x1F; 1429 _WORDREGISTER(CNT); /* Count */ 1430 register8_t reserved_0x22; 1431 register8_t reserved_0x23; 1432 register8_t reserved_0x24; 1433 register8_t reserved_0x25; 1434 _WORDREGISTER(PER); /* Period */ 1435 _WORDREGISTER(CCA); /* Compare or Capture A */ 1436 _WORDREGISTER(CCB); /* Compare or Capture B */ 1437 _WORDREGISTER(CCC); /* Compare or Capture C */ 1438 _WORDREGISTER(CCD); /* Compare or Capture D */ 1439 register8_t reserved_0x30; 1440 register8_t reserved_0x31; 1441 register8_t reserved_0x32; 1442 register8_t reserved_0x33; 1443 register8_t reserved_0x34; 1444 register8_t reserved_0x35; 1445 _WORDREGISTER(PERBUF); /* Period Buffer */ 1446 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1447 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1448 _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ 1449 _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ 1450 } TC0_t; 1451 1452 1453 /* 16-bit Timer/Counter 1 */ 1454 typedef struct TC1_struct 1455 { 1456 register8_t CTRLA; /* Control Register A */ 1457 register8_t CTRLB; /* Control Register B */ 1458 register8_t CTRLC; /* Control register C */ 1459 register8_t CTRLD; /* Control Register D */ 1460 register8_t CTRLE; /* Control Register E */ 1461 register8_t reserved_0x05; 1462 register8_t INTCTRLA; /* Interrupt Control Register A */ 1463 register8_t INTCTRLB; /* Interrupt Control Register B */ 1464 register8_t CTRLFCLR; /* Control Register F Clear */ 1465 register8_t CTRLFSET; /* Control Register F Set */ 1466 register8_t CTRLGCLR; /* Control Register G Clear */ 1467 register8_t CTRLGSET; /* Control Register G Set */ 1468 register8_t INTFLAGS; /* Interrupt Flag Register */ 1469 register8_t reserved_0x0D; 1470 register8_t reserved_0x0E; 1471 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1472 register8_t reserved_0x10; 1473 register8_t reserved_0x11; 1474 register8_t reserved_0x12; 1475 register8_t reserved_0x13; 1476 register8_t reserved_0x14; 1477 register8_t reserved_0x15; 1478 register8_t reserved_0x16; 1479 register8_t reserved_0x17; 1480 register8_t reserved_0x18; 1481 register8_t reserved_0x19; 1482 register8_t reserved_0x1A; 1483 register8_t reserved_0x1B; 1484 register8_t reserved_0x1C; 1485 register8_t reserved_0x1D; 1486 register8_t reserved_0x1E; 1487 register8_t reserved_0x1F; 1488 _WORDREGISTER(CNT); /* Count */ 1489 register8_t reserved_0x22; 1490 register8_t reserved_0x23; 1491 register8_t reserved_0x24; 1492 register8_t reserved_0x25; 1493 _WORDREGISTER(PER); /* Period */ 1494 _WORDREGISTER(CCA); /* Compare or Capture A */ 1495 _WORDREGISTER(CCB); /* Compare or Capture B */ 1496 register8_t reserved_0x2C; 1497 register8_t reserved_0x2D; 1498 register8_t reserved_0x2E; 1499 register8_t reserved_0x2F; 1500 register8_t reserved_0x30; 1501 register8_t reserved_0x31; 1502 register8_t reserved_0x32; 1503 register8_t reserved_0x33; 1504 register8_t reserved_0x34; 1505 register8_t reserved_0x35; 1506 _WORDREGISTER(PERBUF); /* Period Buffer */ 1507 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1508 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1509 } TC1_t; 1510 1511 /* Clock Selection */ 1512 typedef enum TC_CLKSEL_enum 1513 { 1514 TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 1515 TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 1516 TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 1517 TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 1518 TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 1519 TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 1520 TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 1521 TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 1522 TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 1523 TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 1524 TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 1525 TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 1526 } TC_CLKSEL_t; 1527 1528 /* Waveform Generation Mode */ 1529 typedef enum TC_WGMODE_enum 1530 { 1531 TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ 1532 TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ 1533 TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ 1534 TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ 1535 TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 1536 TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 1537 TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ 1538 TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ 1539 TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 1540 TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 1541 } TC_WGMODE_t; 1542 1543 /* Byte Mode */ 1544 typedef enum TC_BYTEM_enum 1545 { 1546 TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ 1547 TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ 1548 TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ 1549 } TC_BYTEM_t; 1550 1551 /* Event Action */ 1552 typedef enum TC_EVACT_enum 1553 { 1554 TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ 1555 TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ 1556 TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ 1557 TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ 1558 TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ 1559 TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ 1560 TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ 1561 } TC_EVACT_t; 1562 1563 /* Event Selection */ 1564 typedef enum TC_EVSEL_enum 1565 { 1566 TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 1567 TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ 1568 TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ 1569 TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ 1570 TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ 1571 } TC_EVSEL_t; 1572 1573 /* Error Interrupt Level */ 1574 typedef enum TC_ERRINTLVL_enum 1575 { 1576 TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1577 TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1578 TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1579 TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ 1580 } TC_ERRINTLVL_t; 1581 1582 /* Overflow Interrupt Level */ 1583 typedef enum TC_OVFINTLVL_enum 1584 { 1585 TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1586 TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1587 TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1588 TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1589 } TC_OVFINTLVL_t; 1590 1591 /* Compare or Capture D Interrupt Level */ 1592 typedef enum TC_CCDINTLVL_enum 1593 { 1594 TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1595 TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 1596 TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1597 TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ 1598 } TC_CCDINTLVL_t; 1599 1600 /* Compare or Capture C Interrupt Level */ 1601 typedef enum TC_CCCINTLVL_enum 1602 { 1603 TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 1604 TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 1605 TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 1606 TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ 1607 } TC_CCCINTLVL_t; 1608 1609 /* Compare or Capture B Interrupt Level */ 1610 typedef enum TC_CCBINTLVL_enum 1611 { 1612 TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1613 TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1614 TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1615 TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ 1616 } TC_CCBINTLVL_t; 1617 1618 /* Compare or Capture A Interrupt Level */ 1619 typedef enum TC_CCAINTLVL_enum 1620 { 1621 TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1622 TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1623 TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1624 TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ 1625 } TC_CCAINTLVL_t; 1626 1627 /* Timer/Counter Command */ 1628 typedef enum TC_CMD_enum 1629 { 1630 TC_CMD_NONE_gc = (0x00<<2), /* No Command */ 1631 TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ 1632 TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 1633 TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 1634 } TC_CMD_t; 1635 1636 1637 /* 1638 -------------------------------------------------------------------------- 1639 TC2 - 16-bit Timer/Counter type 2 1640 -------------------------------------------------------------------------- 1641 */ 1642 1643 /* 16-bit Timer/Counter type 2 */ 1644 typedef struct TC2_struct 1645 { 1646 register8_t CTRLA; /* Control Register A */ 1647 register8_t CTRLB; /* Control Register B */ 1648 register8_t CTRLC; /* Control register C */ 1649 register8_t reserved_0x03; 1650 register8_t CTRLE; /* Control Register E */ 1651 register8_t reserved_0x05; 1652 register8_t INTCTRLA; /* Interrupt Control Register A */ 1653 register8_t INTCTRLB; /* Interrupt Control Register B */ 1654 register8_t reserved_0x08; 1655 register8_t CTRLF; /* Control Register F */ 1656 register8_t reserved_0x0A; 1657 register8_t reserved_0x0B; 1658 register8_t INTFLAGS; /* Interrupt Flag Register */ 1659 register8_t reserved_0x0D; 1660 register8_t reserved_0x0E; 1661 register8_t reserved_0x0F; 1662 register8_t reserved_0x10; 1663 register8_t reserved_0x11; 1664 register8_t reserved_0x12; 1665 register8_t reserved_0x13; 1666 register8_t reserved_0x14; 1667 register8_t reserved_0x15; 1668 register8_t reserved_0x16; 1669 register8_t reserved_0x17; 1670 register8_t reserved_0x18; 1671 register8_t reserved_0x19; 1672 register8_t reserved_0x1A; 1673 register8_t reserved_0x1B; 1674 register8_t reserved_0x1C; 1675 register8_t reserved_0x1D; 1676 register8_t reserved_0x1E; 1677 register8_t reserved_0x1F; 1678 register8_t LCNT; /* Low Byte Count */ 1679 register8_t HCNT; /* High Byte Count */ 1680 register8_t reserved_0x22; 1681 register8_t reserved_0x23; 1682 register8_t reserved_0x24; 1683 register8_t reserved_0x25; 1684 register8_t LPER; /* Low Byte Period */ 1685 register8_t HPER; /* High Byte Period */ 1686 register8_t LCMPA; /* Low Byte Compare A */ 1687 register8_t HCMPA; /* High Byte Compare A */ 1688 register8_t LCMPB; /* Low Byte Compare B */ 1689 register8_t HCMPB; /* High Byte Compare B */ 1690 register8_t LCMPC; /* Low Byte Compare C */ 1691 register8_t HCMPC; /* High Byte Compare C */ 1692 register8_t LCMPD; /* Low Byte Compare D */ 1693 register8_t HCMPD; /* High Byte Compare D */ 1694 } TC2_t; 1695 1696 /* Clock Selection */ 1697 typedef enum TC2_CLKSEL_enum 1698 { 1699 TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 1700 TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 1701 TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 1702 TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 1703 TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 1704 TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 1705 TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 1706 TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 1707 TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 1708 TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 1709 TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 1710 TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 1711 } TC2_CLKSEL_t; 1712 1713 /* Byte Mode */ 1714 typedef enum TC2_BYTEM_enum 1715 { 1716 TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ 1717 TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ 1718 TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ 1719 } TC2_BYTEM_t; 1720 1721 /* High Byte Underflow Interrupt Level */ 1722 typedef enum TC2_HUNFINTLVL_enum 1723 { 1724 TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1725 TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1726 TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1727 TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ 1728 } TC2_HUNFINTLVL_t; 1729 1730 /* Low Byte Underflow Interrupt Level */ 1731 typedef enum TC2_LUNFINTLVL_enum 1732 { 1733 TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1734 TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1735 TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1736 TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1737 } TC2_LUNFINTLVL_t; 1738 1739 /* Low Byte Compare D Interrupt Level */ 1740 typedef enum TC2_LCMPDINTLVL_enum 1741 { 1742 TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1743 TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 1744 TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1745 TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ 1746 } TC2_LCMPDINTLVL_t; 1747 1748 /* Low Byte Compare C Interrupt Level */ 1749 typedef enum TC2_LCMPCINTLVL_enum 1750 { 1751 TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 1752 TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 1753 TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 1754 TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ 1755 } TC2_LCMPCINTLVL_t; 1756 1757 /* Low Byte Compare B Interrupt Level */ 1758 typedef enum TC2_LCMPBINTLVL_enum 1759 { 1760 TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1761 TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1762 TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1763 TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ 1764 } TC2_LCMPBINTLVL_t; 1765 1766 /* Low Byte Compare A Interrupt Level */ 1767 typedef enum TC2_LCMPAINTLVL_enum 1768 { 1769 TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1770 TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1771 TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1772 TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ 1773 } TC2_LCMPAINTLVL_t; 1774 1775 /* Timer/Counter Command */ 1776 typedef enum TC2_CMD_enum 1777 { 1778 TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ 1779 TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 1780 TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 1781 } TC2_CMD_t; 1782 1783 /* Timer/Counter Command */ 1784 typedef enum TC2_CMDEN_enum 1785 { 1786 TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ 1787 TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ 1788 TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ 1789 } TC2_CMDEN_t; 1790 1791 1792 /* 1793 -------------------------------------------------------------------------- 1794 AWEX - Timer/Counter Advanced Waveform Extension 1795 -------------------------------------------------------------------------- 1796 */ 1797 1798 /* Advanced Waveform Extension */ 1799 typedef struct AWEX_struct 1800 { 1801 register8_t CTRL; /* Control Register */ 1802 register8_t reserved_0x01; 1803 register8_t FDEMASK; /* Fault Detection Event Mask */ 1804 register8_t FDCTRL; /* Fault Detection Control Register */ 1805 register8_t STATUS; /* Status Register */ 1806 register8_t STATUSSET; /* Status Set Register */ 1807 register8_t DTBOTH; /* Dead Time Both Sides */ 1808 register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ 1809 register8_t DTLS; /* Dead Time Low Side */ 1810 register8_t DTHS; /* Dead Time High Side */ 1811 register8_t DTLSBUF; /* Dead Time Low Side Buffer */ 1812 register8_t DTHSBUF; /* Dead Time High Side Buffer */ 1813 register8_t OUTOVEN; /* Output Override Enable */ 1814 } AWEX_t; 1815 1816 /* Fault Detect Action */ 1817 typedef enum AWEX_FDACT_enum 1818 { 1819 AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ 1820 AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ 1821 AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ 1822 } AWEX_FDACT_t; 1823 1824 1825 /* 1826 -------------------------------------------------------------------------- 1827 HIRES - Timer/Counter High-Resolution Extension 1828 -------------------------------------------------------------------------- 1829 */ 1830 1831 /* High-Resolution Extension */ 1832 typedef struct HIRES_struct 1833 { 1834 register8_t CTRLA; /* Control Register */ 1835 } HIRES_t; 1836 1837 /* High Resolution Enable */ 1838 typedef enum HIRES_HREN_enum 1839 { 1840 HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ 1841 HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ 1842 HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ 1843 HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ 1844 } HIRES_HREN_t; 1845 1846 1847 /* 1848 -------------------------------------------------------------------------- 1849 USART - Universal Asynchronous Receiver-Transmitter 1850 -------------------------------------------------------------------------- 1851 */ 1852 1853 /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 1854 typedef struct USART_struct 1855 { 1856 register8_t DATA; /* Data Register */ 1857 register8_t STATUS; /* Status Register */ 1858 register8_t reserved_0x02; 1859 register8_t CTRLA; /* Control Register A */ 1860 register8_t CTRLB; /* Control Register B */ 1861 register8_t CTRLC; /* Control Register C */ 1862 register8_t BAUDCTRLA; /* Baud Rate Control Register A */ 1863 register8_t BAUDCTRLB; /* Baud Rate Control Register B */ 1864 } USART_t; 1865 1866 /* Receive Complete Interrupt level */ 1867 typedef enum USART_RXCINTLVL_enum 1868 { 1869 USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 1870 USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 1871 USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 1872 USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ 1873 } USART_RXCINTLVL_t; 1874 1875 /* Transmit Complete Interrupt level */ 1876 typedef enum USART_TXCINTLVL_enum 1877 { 1878 USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1879 USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1880 USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1881 USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ 1882 } USART_TXCINTLVL_t; 1883 1884 /* Data Register Empty Interrupt level */ 1885 typedef enum USART_DREINTLVL_enum 1886 { 1887 USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1888 USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1889 USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1890 USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ 1891 } USART_DREINTLVL_t; 1892 1893 /* Character Size */ 1894 typedef enum USART_CHSIZE_enum 1895 { 1896 USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ 1897 USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ 1898 USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ 1899 USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ 1900 USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ 1901 } USART_CHSIZE_t; 1902 1903 /* Communication Mode */ 1904 typedef enum USART_CMODE_enum 1905 { 1906 USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ 1907 USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ 1908 USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ 1909 USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ 1910 } USART_CMODE_t; 1911 1912 /* Parity Mode */ 1913 typedef enum USART_PMODE_enum 1914 { 1915 USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ 1916 USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ 1917 USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ 1918 } USART_PMODE_t; 1919 1920 1921 /* 1922 -------------------------------------------------------------------------- 1923 SPI - Serial Peripheral Interface 1924 -------------------------------------------------------------------------- 1925 */ 1926 1927 /* Serial Peripheral Interface */ 1928 typedef struct SPI_struct 1929 { 1930 register8_t CTRL; /* Control Register */ 1931 register8_t INTCTRL; /* Interrupt Control Register */ 1932 register8_t STATUS; /* Status Register */ 1933 register8_t DATA; /* Data Register */ 1934 } SPI_t; 1935 1936 /* SPI Mode */ 1937 typedef enum SPI_MODE_enum 1938 { 1939 SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ 1940 SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ 1941 SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ 1942 SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ 1943 } SPI_MODE_t; 1944 1945 /* Prescaler setting */ 1946 typedef enum SPI_PRESCALER_enum 1947 { 1948 SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ 1949 SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ 1950 SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ 1951 SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ 1952 } SPI_PRESCALER_t; 1953 1954 /* Interrupt level */ 1955 typedef enum SPI_INTLVL_enum 1956 { 1957 SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1958 SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 1959 SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1960 SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ 1961 } SPI_INTLVL_t; 1962 1963 1964 /* 1965 -------------------------------------------------------------------------- 1966 IRCOM - IR Communication Module 1967 -------------------------------------------------------------------------- 1968 */ 1969 1970 /* IR Communication Module */ 1971 typedef struct IRCOM_struct 1972 { 1973 register8_t CTRL; /* Control Register */ 1974 register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ 1975 register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ 1976 } IRCOM_t; 1977 1978 /* Event channel selection */ 1979 typedef enum IRDA_EVSEL_enum 1980 { 1981 IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 1982 IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ 1983 IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ 1984 IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ 1985 IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ 1986 } IRDA_EVSEL_t; 1987 1988 1989 /* 1990 -------------------------------------------------------------------------- 1991 FUSE - Fuses and Lockbits 1992 -------------------------------------------------------------------------- 1993 */ 1994 1995 /* Fuses */ 1996 typedef struct NVM_FUSES_struct 1997 { 1998 register8_t reserved_0x00; 1999 register8_t FUSEBYTE1; /* Watchdog Configuration */ 2000 register8_t FUSEBYTE2; /* Reset Configuration */ 2001 register8_t reserved_0x03; 2002 register8_t FUSEBYTE4; /* Start-up Configuration */ 2003 register8_t FUSEBYTE5; /* EESAVE and BOD Level */ 2004 } NVM_FUSES_t; 2005 2006 /* Boot Loader Section Reset Vector */ 2007 typedef enum BOOTRST_enum 2008 { 2009 BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ 2010 BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ 2011 } BOOTRST_t; 2012 2013 /* Timer Oscillator pin location */ 2014 typedef enum TOSCSEL_enum 2015 { 2016 TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ 2017 TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ 2018 } TOSCSEL_t; 2019 2020 /* BOD operation */ 2021 typedef enum BOD_enum 2022 { 2023 BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ 2024 BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ 2025 BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ 2026 } BOD_t; 2027 2028 /* BOD operation */ 2029 typedef enum BODACT_enum 2030 { 2031 BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ 2032 BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ 2033 BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ 2034 } BODACT_t; 2035 2036 /* Watchdog (Window) Timeout Period */ 2037 typedef enum WD_enum 2038 { 2039 WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ 2040 WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ 2041 WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ 2042 WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ 2043 WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ 2044 WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ 2045 WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ 2046 WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ 2047 WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ 2048 WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ 2049 WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ 2050 } WD_t; 2051 2052 /* Watchdog (Window) Timeout Period */ 2053 typedef enum WDP_enum 2054 { 2055 WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ 2056 WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ 2057 WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ 2058 WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ 2059 WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ 2060 WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ 2061 WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ 2062 WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ 2063 WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ 2064 WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ 2065 WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ 2066 } WDP_t; 2067 2068 /* Start-up Time */ 2069 typedef enum SUT_enum 2070 { 2071 SUT_0MS_gc = (0x03<<2), /* 0 ms */ 2072 SUT_4MS_gc = (0x01<<2), /* 4 ms */ 2073 SUT_64MS_gc = (0x00<<2), /* 64 ms */ 2074 } SUT_t; 2075 2076 /* Brown Out Detection Voltage Level */ 2077 typedef enum BODLVL_enum 2078 { 2079 BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ 2080 BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ 2081 BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ 2082 BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ 2083 BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ 2084 BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ 2085 BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ 2086 BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ 2087 } BODLVL_t; 2088 2089 2090 /* 2091 -------------------------------------------------------------------------- 2092 LOCKBIT - Fuses and Lockbits 2093 -------------------------------------------------------------------------- 2094 */ 2095 2096 /* Lock Bits */ 2097 typedef struct NVM_LOCKBITS_struct 2098 { 2099 register8_t LOCKBITS; /* Lock Bits */ 2100 } NVM_LOCKBITS_t; 2101 2102 /* Boot lock bits - boot setcion */ 2103 typedef enum FUSE_BLBB_enum 2104 { 2105 FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 2106 FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 2107 FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 2108 FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 2109 } FUSE_BLBB_t; 2110 2111 /* Boot lock bits - application section */ 2112 typedef enum FUSE_BLBA_enum 2113 { 2114 FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 2115 FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 2116 FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 2117 FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 2118 } FUSE_BLBA_t; 2119 2120 /* Boot lock bits - application table section */ 2121 typedef enum FUSE_BLBAT_enum 2122 { 2123 FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 2124 FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 2125 FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 2126 FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 2127 } FUSE_BLBAT_t; 2128 2129 /* Lock bits */ 2130 typedef enum FUSE_LB_enum 2131 { 2132 FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 2133 FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 2134 FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 2135 } FUSE_LB_t; 2136 2137 2138 /* 2139 -------------------------------------------------------------------------- 2140 SIGROW - Signature Row 2141 -------------------------------------------------------------------------- 2142 */ 2143 2144 /* Production Signatures */ 2145 typedef struct NVM_PROD_SIGNATURES_struct 2146 { 2147 register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ 2148 register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ 2149 register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ 2150 register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ 2151 register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ 2152 register8_t reserved_0x05; 2153 register8_t reserved_0x06; 2154 register8_t reserved_0x07; 2155 register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ 2156 register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ 2157 register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ 2158 register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ 2159 register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ 2160 register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ 2161 register8_t reserved_0x0E; 2162 register8_t reserved_0x0F; 2163 register8_t WAFNUM; /* Wafer Number */ 2164 register8_t reserved_0x11; 2165 register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ 2166 register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ 2167 register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ 2168 register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ 2169 register8_t reserved_0x16; 2170 register8_t reserved_0x17; 2171 register8_t reserved_0x18; 2172 register8_t reserved_0x19; 2173 register8_t reserved_0x1A; 2174 register8_t reserved_0x1B; 2175 register8_t reserved_0x1C; 2176 register8_t reserved_0x1D; 2177 register8_t reserved_0x1E; 2178 register8_t reserved_0x1F; 2179 register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ 2180 register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ 2181 register8_t reserved_0x22; 2182 register8_t reserved_0x23; 2183 register8_t reserved_0x24; 2184 register8_t reserved_0x25; 2185 register8_t reserved_0x26; 2186 register8_t reserved_0x27; 2187 register8_t reserved_0x28; 2188 register8_t reserved_0x29; 2189 register8_t reserved_0x2A; 2190 register8_t reserved_0x2B; 2191 register8_t reserved_0x2C; 2192 register8_t reserved_0x2D; 2193 register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ 2194 register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ 2195 register8_t reserved_0x30; 2196 register8_t reserved_0x31; 2197 register8_t reserved_0x32; 2198 register8_t reserved_0x33; 2199 register8_t reserved_0x34; 2200 register8_t reserved_0x35; 2201 register8_t reserved_0x36; 2202 register8_t reserved_0x37; 2203 register8_t reserved_0x38; 2204 register8_t reserved_0x39; 2205 register8_t reserved_0x3A; 2206 register8_t reserved_0x3B; 2207 register8_t reserved_0x3C; 2208 register8_t reserved_0x3D; 2209 register8_t reserved_0x3E; 2210 register8_t reserved_0x3F; 2211 } NVM_PROD_SIGNATURES_t; 2212 2213 /* 2214 ========================================================================== 2215 IO Module Instances. Mapped to memory. 2216 ========================================================================== 2217 */ 2218 2219 #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ 2220 #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ 2221 #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ 2222 #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ 2223 #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ 2224 #define CLK (*(CLK_t *) 0x0040) /* Clock System */ 2225 #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ 2226 #define OSC (*(OSC_t *) 0x0050) /* Oscillator */ 2227 #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ 2228 #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ 2229 #define PR (*(PR_t *) 0x0070) /* Power Reduction */ 2230 #define RST (*(RST_t *) 0x0078) /* Reset */ 2231 #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ 2232 #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ 2233 #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ 2234 #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ 2235 #define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ 2236 #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ 2237 #define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ 2238 #define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ 2239 #define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ 2240 #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ 2241 #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ 2242 #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ 2243 #define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ 2244 #define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ 2245 #define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ 2246 #define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ 2247 #define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ 2248 #define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ 2249 #define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ 2250 #define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ 2251 #define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ 2252 #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ 2253 #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ 2254 #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2255 #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ 2256 #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ 2257 #define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ 2258 #define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ 2259 #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2260 #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ 2261 #define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ 2262 2263 2264 #endif /* !defined (__ASSEMBLER__) */ 2265 2266 2267 /* ========== Flattened fully qualified IO register names ========== */ 2268 2269 /* GPIO - General Purpose IO Registers */ 2270 #define GPIO_GPIOR0 _SFR_MEM8(0x0000) 2271 #define GPIO_GPIOR1 _SFR_MEM8(0x0001) 2272 #define GPIO_GPIOR2 _SFR_MEM8(0x0002) 2273 #define GPIO_GPIOR3 _SFR_MEM8(0x0003) 2274 2275 /* Deprecated */ 2276 #define GPIO_GPIO0 _SFR_MEM8(0x0000) 2277 #define GPIO_GPIO1 _SFR_MEM8(0x0001) 2278 #define GPIO_GPIO2 _SFR_MEM8(0x0002) 2279 #define GPIO_GPIO3 _SFR_MEM8(0x0003) 2280 2281 /* NVM_FUSES - Fuses */ 2282 #define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) 2283 #define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) 2284 #define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) 2285 #define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) 2286 2287 /* NVM_LOCKBITS - Lock Bits */ 2288 #define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) 2289 2290 /* NVM_PROD_SIGNATURES - Production Signatures */ 2291 #define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) 2292 #define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) 2293 #define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) 2294 #define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) 2295 #define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) 2296 #define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) 2297 #define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) 2298 #define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) 2299 #define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) 2300 #define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) 2301 #define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) 2302 #define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) 2303 #define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) 2304 #define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) 2305 #define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) 2306 #define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) 2307 #define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) 2308 #define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) 2309 #define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) 2310 #define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) 2311 2312 /* VPORT - Virtual Port */ 2313 #define VPORT0_DIR _SFR_MEM8(0x0010) 2314 #define VPORT0_OUT _SFR_MEM8(0x0011) 2315 #define VPORT0_IN _SFR_MEM8(0x0012) 2316 #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) 2317 2318 /* VPORT - Virtual Port */ 2319 #define VPORT1_DIR _SFR_MEM8(0x0014) 2320 #define VPORT1_OUT _SFR_MEM8(0x0015) 2321 #define VPORT1_IN _SFR_MEM8(0x0016) 2322 #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) 2323 2324 /* VPORT - Virtual Port */ 2325 #define VPORT2_DIR _SFR_MEM8(0x0018) 2326 #define VPORT2_OUT _SFR_MEM8(0x0019) 2327 #define VPORT2_IN _SFR_MEM8(0x001A) 2328 #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) 2329 2330 /* VPORT - Virtual Port */ 2331 #define VPORT3_DIR _SFR_MEM8(0x001C) 2332 #define VPORT3_OUT _SFR_MEM8(0x001D) 2333 #define VPORT3_IN _SFR_MEM8(0x001E) 2334 #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) 2335 2336 /* OCD - On-Chip Debug System */ 2337 #define OCD_OCDR0 _SFR_MEM8(0x002E) 2338 #define OCD_OCDR1 _SFR_MEM8(0x002F) 2339 2340 /* CPU - CPU registers */ 2341 #define CPU_CCP _SFR_MEM8(0x0034) 2342 #define CPU_RAMPD _SFR_MEM8(0x0038) 2343 #define CPU_RAMPX _SFR_MEM8(0x0039) 2344 #define CPU_RAMPY _SFR_MEM8(0x003A) 2345 #define CPU_RAMPZ _SFR_MEM8(0x003B) 2346 #define CPU_EIND _SFR_MEM8(0x003C) 2347 #define CPU_SPL _SFR_MEM8(0x003D) 2348 #define CPU_SPH _SFR_MEM8(0x003E) 2349 #define CPU_SREG _SFR_MEM8(0x003F) 2350 2351 /* CLK - Clock System */ 2352 #define CLK_CTRL _SFR_MEM8(0x0040) 2353 #define CLK_PSCTRL _SFR_MEM8(0x0041) 2354 #define CLK_LOCK _SFR_MEM8(0x0042) 2355 #define CLK_RTCCTRL _SFR_MEM8(0x0043) 2356 2357 /* SLEEP - Sleep Controller */ 2358 #define SLEEP_CTRL _SFR_MEM8(0x0048) 2359 2360 /* OSC - Oscillator */ 2361 #define OSC_CTRL _SFR_MEM8(0x0050) 2362 #define OSC_STATUS _SFR_MEM8(0x0051) 2363 #define OSC_XOSCCTRL _SFR_MEM8(0x0052) 2364 #define OSC_XOSCFAIL _SFR_MEM8(0x0053) 2365 #define OSC_RC32KCAL _SFR_MEM8(0x0054) 2366 #define OSC_PLLCTRL _SFR_MEM8(0x0055) 2367 #define OSC_DFLLCTRL _SFR_MEM8(0x0056) 2368 2369 /* DFLL - DFLL */ 2370 #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) 2371 #define DFLLRC32M_CALA _SFR_MEM8(0x0062) 2372 #define DFLLRC32M_CALB _SFR_MEM8(0x0063) 2373 #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) 2374 #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) 2375 #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) 2376 2377 /* DFLL - DFLL */ 2378 #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) 2379 #define DFLLRC2M_CALA _SFR_MEM8(0x006A) 2380 #define DFLLRC2M_CALB _SFR_MEM8(0x006B) 2381 #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) 2382 #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) 2383 #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) 2384 2385 /* PR - Power Reduction */ 2386 #define PR_PRGEN _SFR_MEM8(0x0070) 2387 #define PR_PRPA _SFR_MEM8(0x0071) 2388 #define PR_PRPC _SFR_MEM8(0x0073) 2389 #define PR_PRPD _SFR_MEM8(0x0074) 2390 #define PR_PRPE _SFR_MEM8(0x0075) 2391 #define PR_PRPF _SFR_MEM8(0x0076) 2392 2393 /* RST - Reset */ 2394 #define RST_STATUS _SFR_MEM8(0x0078) 2395 #define RST_CTRL _SFR_MEM8(0x0079) 2396 2397 /* WDT - Watch-Dog Timer */ 2398 #define WDT_CTRL _SFR_MEM8(0x0080) 2399 #define WDT_WINCTRL _SFR_MEM8(0x0081) 2400 #define WDT_STATUS _SFR_MEM8(0x0082) 2401 2402 /* MCU - MCU Control */ 2403 #define MCU_DEVID0 _SFR_MEM8(0x0090) 2404 #define MCU_DEVID1 _SFR_MEM8(0x0091) 2405 #define MCU_DEVID2 _SFR_MEM8(0x0092) 2406 #define MCU_REVID _SFR_MEM8(0x0093) 2407 #define MCU_ANAINIT _SFR_MEM8(0x0097) 2408 #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) 2409 #define MCU_AWEXLOCK _SFR_MEM8(0x0099) 2410 2411 /* PMIC - Programmable Multi-level Interrupt Controller */ 2412 #define PMIC_STATUS _SFR_MEM8(0x00A0) 2413 #define PMIC_INTPRI _SFR_MEM8(0x00A1) 2414 #define PMIC_CTRL _SFR_MEM8(0x00A2) 2415 2416 /* PORTCFG - I/O port Configuration */ 2417 #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) 2418 #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) 2419 #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) 2420 #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) 2421 #define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) 2422 2423 /* CRC - Cyclic Redundancy Checker */ 2424 #define CRC_CTRL _SFR_MEM8(0x00D0) 2425 #define CRC_STATUS _SFR_MEM8(0x00D1) 2426 #define CRC_DATAIN _SFR_MEM8(0x00D3) 2427 #define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) 2428 #define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) 2429 #define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) 2430 #define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) 2431 2432 /* EVSYS - Event System */ 2433 #define EVSYS_CH0MUX _SFR_MEM8(0x0180) 2434 #define EVSYS_CH1MUX _SFR_MEM8(0x0181) 2435 #define EVSYS_CH2MUX _SFR_MEM8(0x0182) 2436 #define EVSYS_CH3MUX _SFR_MEM8(0x0183) 2437 #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) 2438 #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) 2439 #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) 2440 #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) 2441 #define EVSYS_STROBE _SFR_MEM8(0x0190) 2442 #define EVSYS_DATA _SFR_MEM8(0x0191) 2443 2444 /* NVM - Non-volatile Memory Controller */ 2445 #define NVM_ADDR0 _SFR_MEM8(0x01C0) 2446 #define NVM_ADDR1 _SFR_MEM8(0x01C1) 2447 #define NVM_ADDR2 _SFR_MEM8(0x01C2) 2448 #define NVM_DATA0 _SFR_MEM8(0x01C4) 2449 #define NVM_DATA1 _SFR_MEM8(0x01C5) 2450 #define NVM_DATA2 _SFR_MEM8(0x01C6) 2451 #define NVM_CMD _SFR_MEM8(0x01CA) 2452 #define NVM_CTRLA _SFR_MEM8(0x01CB) 2453 #define NVM_CTRLB _SFR_MEM8(0x01CC) 2454 #define NVM_INTCTRL _SFR_MEM8(0x01CD) 2455 #define NVM_STATUS _SFR_MEM8(0x01CF) 2456 #define NVM_LOCKBITS _SFR_MEM8(0x01D0) 2457 2458 /* ADC - Analog-to-Digital Converter */ 2459 #define ADCA_CTRLA _SFR_MEM8(0x0200) 2460 #define ADCA_CTRLB _SFR_MEM8(0x0201) 2461 #define ADCA_REFCTRL _SFR_MEM8(0x0202) 2462 #define ADCA_EVCTRL _SFR_MEM8(0x0203) 2463 #define ADCA_PRESCALER _SFR_MEM8(0x0204) 2464 #define ADCA_INTFLAGS _SFR_MEM8(0x0206) 2465 #define ADCA_TEMP _SFR_MEM8(0x0207) 2466 #define ADCA_CAL _SFR_MEM16(0x020C) 2467 #define ADCA_CH0RES _SFR_MEM16(0x0210) 2468 #define ADCA_CMP _SFR_MEM16(0x0218) 2469 #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) 2470 #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) 2471 #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) 2472 #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) 2473 #define ADCA_CH0_RES _SFR_MEM16(0x0224) 2474 #define ADCA_CH0_SCAN _SFR_MEM8(0x0226) 2475 2476 /* AC - Analog Comparator */ 2477 #define ACA_AC0CTRL _SFR_MEM8(0x0380) 2478 #define ACA_AC1CTRL _SFR_MEM8(0x0381) 2479 #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) 2480 #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) 2481 #define ACA_CTRLA _SFR_MEM8(0x0384) 2482 #define ACA_CTRLB _SFR_MEM8(0x0385) 2483 #define ACA_WINCTRL _SFR_MEM8(0x0386) 2484 #define ACA_STATUS _SFR_MEM8(0x0387) 2485 2486 /* RTC - Real-Time Counter */ 2487 #define RTC_CTRL _SFR_MEM8(0x0400) 2488 #define RTC_STATUS _SFR_MEM8(0x0401) 2489 #define RTC_INTCTRL _SFR_MEM8(0x0402) 2490 #define RTC_INTFLAGS _SFR_MEM8(0x0403) 2491 #define RTC_TEMP _SFR_MEM8(0x0404) 2492 #define RTC_CNT _SFR_MEM16(0x0408) 2493 #define RTC_PER _SFR_MEM16(0x040A) 2494 #define RTC_COMP _SFR_MEM16(0x040C) 2495 2496 /* TWI - Two-Wire Interface */ 2497 #define TWIC_CTRL _SFR_MEM8(0x0480) 2498 #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) 2499 #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) 2500 #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) 2501 #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) 2502 #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) 2503 #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) 2504 #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) 2505 #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) 2506 #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) 2507 #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) 2508 #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) 2509 #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) 2510 #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) 2511 2512 /* TWI - Two-Wire Interface */ 2513 #define TWIE_CTRL _SFR_MEM8(0x04A0) 2514 #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) 2515 #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) 2516 #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) 2517 #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) 2518 #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) 2519 #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) 2520 #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) 2521 #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) 2522 #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) 2523 #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) 2524 #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) 2525 #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) 2526 #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) 2527 2528 /* PORT - I/O Ports */ 2529 #define PORTA_DIR _SFR_MEM8(0x0600) 2530 #define PORTA_DIRSET _SFR_MEM8(0x0601) 2531 #define PORTA_DIRCLR _SFR_MEM8(0x0602) 2532 #define PORTA_DIRTGL _SFR_MEM8(0x0603) 2533 #define PORTA_OUT _SFR_MEM8(0x0604) 2534 #define PORTA_OUTSET _SFR_MEM8(0x0605) 2535 #define PORTA_OUTCLR _SFR_MEM8(0x0606) 2536 #define PORTA_OUTTGL _SFR_MEM8(0x0607) 2537 #define PORTA_IN _SFR_MEM8(0x0608) 2538 #define PORTA_INTCTRL _SFR_MEM8(0x0609) 2539 #define PORTA_INT0MASK _SFR_MEM8(0x060A) 2540 #define PORTA_INT1MASK _SFR_MEM8(0x060B) 2541 #define PORTA_INTFLAGS _SFR_MEM8(0x060C) 2542 #define PORTA_REMAP _SFR_MEM8(0x060E) 2543 #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) 2544 #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) 2545 #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) 2546 #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) 2547 #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) 2548 #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) 2549 #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) 2550 #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) 2551 2552 /* PORT - I/O Ports */ 2553 #define PORTB_DIR _SFR_MEM8(0x0620) 2554 #define PORTB_DIRSET _SFR_MEM8(0x0621) 2555 #define PORTB_DIRCLR _SFR_MEM8(0x0622) 2556 #define PORTB_DIRTGL _SFR_MEM8(0x0623) 2557 #define PORTB_OUT _SFR_MEM8(0x0624) 2558 #define PORTB_OUTSET _SFR_MEM8(0x0625) 2559 #define PORTB_OUTCLR _SFR_MEM8(0x0626) 2560 #define PORTB_OUTTGL _SFR_MEM8(0x0627) 2561 #define PORTB_IN _SFR_MEM8(0x0628) 2562 #define PORTB_INTCTRL _SFR_MEM8(0x0629) 2563 #define PORTB_INT0MASK _SFR_MEM8(0x062A) 2564 #define PORTB_INT1MASK _SFR_MEM8(0x062B) 2565 #define PORTB_INTFLAGS _SFR_MEM8(0x062C) 2566 #define PORTB_REMAP _SFR_MEM8(0x062E) 2567 #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) 2568 #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) 2569 #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) 2570 #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) 2571 #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) 2572 #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) 2573 #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) 2574 #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) 2575 2576 /* PORT - I/O Ports */ 2577 #define PORTC_DIR _SFR_MEM8(0x0640) 2578 #define PORTC_DIRSET _SFR_MEM8(0x0641) 2579 #define PORTC_DIRCLR _SFR_MEM8(0x0642) 2580 #define PORTC_DIRTGL _SFR_MEM8(0x0643) 2581 #define PORTC_OUT _SFR_MEM8(0x0644) 2582 #define PORTC_OUTSET _SFR_MEM8(0x0645) 2583 #define PORTC_OUTCLR _SFR_MEM8(0x0646) 2584 #define PORTC_OUTTGL _SFR_MEM8(0x0647) 2585 #define PORTC_IN _SFR_MEM8(0x0648) 2586 #define PORTC_INTCTRL _SFR_MEM8(0x0649) 2587 #define PORTC_INT0MASK _SFR_MEM8(0x064A) 2588 #define PORTC_INT1MASK _SFR_MEM8(0x064B) 2589 #define PORTC_INTFLAGS _SFR_MEM8(0x064C) 2590 #define PORTC_REMAP _SFR_MEM8(0x064E) 2591 #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) 2592 #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) 2593 #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) 2594 #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) 2595 #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) 2596 #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) 2597 #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) 2598 #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) 2599 2600 /* PORT - I/O Ports */ 2601 #define PORTD_DIR _SFR_MEM8(0x0660) 2602 #define PORTD_DIRSET _SFR_MEM8(0x0661) 2603 #define PORTD_DIRCLR _SFR_MEM8(0x0662) 2604 #define PORTD_DIRTGL _SFR_MEM8(0x0663) 2605 #define PORTD_OUT _SFR_MEM8(0x0664) 2606 #define PORTD_OUTSET _SFR_MEM8(0x0665) 2607 #define PORTD_OUTCLR _SFR_MEM8(0x0666) 2608 #define PORTD_OUTTGL _SFR_MEM8(0x0667) 2609 #define PORTD_IN _SFR_MEM8(0x0668) 2610 #define PORTD_INTCTRL _SFR_MEM8(0x0669) 2611 #define PORTD_INT0MASK _SFR_MEM8(0x066A) 2612 #define PORTD_INT1MASK _SFR_MEM8(0x066B) 2613 #define PORTD_INTFLAGS _SFR_MEM8(0x066C) 2614 #define PORTD_REMAP _SFR_MEM8(0x066E) 2615 #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) 2616 #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) 2617 #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) 2618 #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) 2619 #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) 2620 #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) 2621 #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) 2622 #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) 2623 2624 /* PORT - I/O Ports */ 2625 #define PORTE_DIR _SFR_MEM8(0x0680) 2626 #define PORTE_DIRSET _SFR_MEM8(0x0681) 2627 #define PORTE_DIRCLR _SFR_MEM8(0x0682) 2628 #define PORTE_DIRTGL _SFR_MEM8(0x0683) 2629 #define PORTE_OUT _SFR_MEM8(0x0684) 2630 #define PORTE_OUTSET _SFR_MEM8(0x0685) 2631 #define PORTE_OUTCLR _SFR_MEM8(0x0686) 2632 #define PORTE_OUTTGL _SFR_MEM8(0x0687) 2633 #define PORTE_IN _SFR_MEM8(0x0688) 2634 #define PORTE_INTCTRL _SFR_MEM8(0x0689) 2635 #define PORTE_INT0MASK _SFR_MEM8(0x068A) 2636 #define PORTE_INT1MASK _SFR_MEM8(0x068B) 2637 #define PORTE_INTFLAGS _SFR_MEM8(0x068C) 2638 #define PORTE_REMAP _SFR_MEM8(0x068E) 2639 #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) 2640 #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) 2641 #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) 2642 #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) 2643 #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) 2644 #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) 2645 #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) 2646 #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) 2647 2648 /* PORT - I/O Ports */ 2649 #define PORTR_DIR _SFR_MEM8(0x07E0) 2650 #define PORTR_DIRSET _SFR_MEM8(0x07E1) 2651 #define PORTR_DIRCLR _SFR_MEM8(0x07E2) 2652 #define PORTR_DIRTGL _SFR_MEM8(0x07E3) 2653 #define PORTR_OUT _SFR_MEM8(0x07E4) 2654 #define PORTR_OUTSET _SFR_MEM8(0x07E5) 2655 #define PORTR_OUTCLR _SFR_MEM8(0x07E6) 2656 #define PORTR_OUTTGL _SFR_MEM8(0x07E7) 2657 #define PORTR_IN _SFR_MEM8(0x07E8) 2658 #define PORTR_INTCTRL _SFR_MEM8(0x07E9) 2659 #define PORTR_INT0MASK _SFR_MEM8(0x07EA) 2660 #define PORTR_INT1MASK _SFR_MEM8(0x07EB) 2661 #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) 2662 #define PORTR_REMAP _SFR_MEM8(0x07EE) 2663 #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) 2664 #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) 2665 #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) 2666 #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) 2667 #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) 2668 #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) 2669 #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) 2670 #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) 2671 2672 /* TC0 - 16-bit Timer/Counter 0 */ 2673 #define TCC0_CTRLA _SFR_MEM8(0x0800) 2674 #define TCC0_CTRLB _SFR_MEM8(0x0801) 2675 #define TCC0_CTRLC _SFR_MEM8(0x0802) 2676 #define TCC0_CTRLD _SFR_MEM8(0x0803) 2677 #define TCC0_CTRLE _SFR_MEM8(0x0804) 2678 #define TCC0_INTCTRLA _SFR_MEM8(0x0806) 2679 #define TCC0_INTCTRLB _SFR_MEM8(0x0807) 2680 #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) 2681 #define TCC0_CTRLFSET _SFR_MEM8(0x0809) 2682 #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) 2683 #define TCC0_CTRLGSET _SFR_MEM8(0x080B) 2684 #define TCC0_INTFLAGS _SFR_MEM8(0x080C) 2685 #define TCC0_TEMP _SFR_MEM8(0x080F) 2686 #define TCC0_CNT _SFR_MEM16(0x0820) 2687 #define TCC0_PER _SFR_MEM16(0x0826) 2688 #define TCC0_CCA _SFR_MEM16(0x0828) 2689 #define TCC0_CCB _SFR_MEM16(0x082A) 2690 #define TCC0_CCC _SFR_MEM16(0x082C) 2691 #define TCC0_CCD _SFR_MEM16(0x082E) 2692 #define TCC0_PERBUF _SFR_MEM16(0x0836) 2693 #define TCC0_CCABUF _SFR_MEM16(0x0838) 2694 #define TCC0_CCBBUF _SFR_MEM16(0x083A) 2695 #define TCC0_CCCBUF _SFR_MEM16(0x083C) 2696 #define TCC0_CCDBUF _SFR_MEM16(0x083E) 2697 2698 /* TC2 - 16-bit Timer/Counter type 2 */ 2699 #define TCC2_CTRLA _SFR_MEM8(0x0800) 2700 #define TCC2_CTRLB _SFR_MEM8(0x0801) 2701 #define TCC2_CTRLC _SFR_MEM8(0x0802) 2702 #define TCC2_CTRLE _SFR_MEM8(0x0804) 2703 #define TCC2_INTCTRLA _SFR_MEM8(0x0806) 2704 #define TCC2_INTCTRLB _SFR_MEM8(0x0807) 2705 #define TCC2_CTRLF _SFR_MEM8(0x0809) 2706 #define TCC2_INTFLAGS _SFR_MEM8(0x080C) 2707 #define TCC2_LCNT _SFR_MEM8(0x0820) 2708 #define TCC2_HCNT _SFR_MEM8(0x0821) 2709 #define TCC2_LPER _SFR_MEM8(0x0826) 2710 #define TCC2_HPER _SFR_MEM8(0x0827) 2711 #define TCC2_LCMPA _SFR_MEM8(0x0828) 2712 #define TCC2_HCMPA _SFR_MEM8(0x0829) 2713 #define TCC2_LCMPB _SFR_MEM8(0x082A) 2714 #define TCC2_HCMPB _SFR_MEM8(0x082B) 2715 #define TCC2_LCMPC _SFR_MEM8(0x082C) 2716 #define TCC2_HCMPC _SFR_MEM8(0x082D) 2717 #define TCC2_LCMPD _SFR_MEM8(0x082E) 2718 #define TCC2_HCMPD _SFR_MEM8(0x082F) 2719 2720 /* TC1 - 16-bit Timer/Counter 1 */ 2721 #define TCC1_CTRLA _SFR_MEM8(0x0840) 2722 #define TCC1_CTRLB _SFR_MEM8(0x0841) 2723 #define TCC1_CTRLC _SFR_MEM8(0x0842) 2724 #define TCC1_CTRLD _SFR_MEM8(0x0843) 2725 #define TCC1_CTRLE _SFR_MEM8(0x0844) 2726 #define TCC1_INTCTRLA _SFR_MEM8(0x0846) 2727 #define TCC1_INTCTRLB _SFR_MEM8(0x0847) 2728 #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) 2729 #define TCC1_CTRLFSET _SFR_MEM8(0x0849) 2730 #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) 2731 #define TCC1_CTRLGSET _SFR_MEM8(0x084B) 2732 #define TCC1_INTFLAGS _SFR_MEM8(0x084C) 2733 #define TCC1_TEMP _SFR_MEM8(0x084F) 2734 #define TCC1_CNT _SFR_MEM16(0x0860) 2735 #define TCC1_PER _SFR_MEM16(0x0866) 2736 #define TCC1_CCA _SFR_MEM16(0x0868) 2737 #define TCC1_CCB _SFR_MEM16(0x086A) 2738 #define TCC1_PERBUF _SFR_MEM16(0x0876) 2739 #define TCC1_CCABUF _SFR_MEM16(0x0878) 2740 #define TCC1_CCBBUF _SFR_MEM16(0x087A) 2741 2742 /* AWEX - Advanced Waveform Extension */ 2743 #define AWEXC_CTRL _SFR_MEM8(0x0880) 2744 #define AWEXC_FDEMASK _SFR_MEM8(0x0882) 2745 #define AWEXC_FDCTRL _SFR_MEM8(0x0883) 2746 #define AWEXC_STATUS _SFR_MEM8(0x0884) 2747 #define AWEXC_STATUSSET _SFR_MEM8(0x0885) 2748 #define AWEXC_DTBOTH _SFR_MEM8(0x0886) 2749 #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) 2750 #define AWEXC_DTLS _SFR_MEM8(0x0888) 2751 #define AWEXC_DTHS _SFR_MEM8(0x0889) 2752 #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) 2753 #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) 2754 #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) 2755 2756 /* HIRES - High-Resolution Extension */ 2757 #define HIRESC_CTRLA _SFR_MEM8(0x0890) 2758 2759 /* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ 2760 #define USARTC0_DATA _SFR_MEM8(0x08A0) 2761 #define USARTC0_STATUS _SFR_MEM8(0x08A1) 2762 #define USARTC0_CTRLA _SFR_MEM8(0x08A3) 2763 #define USARTC0_CTRLB _SFR_MEM8(0x08A4) 2764 #define USARTC0_CTRLC _SFR_MEM8(0x08A5) 2765 #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) 2766 #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) 2767 2768 /* SPI - Serial Peripheral Interface */ 2769 #define SPIC_CTRL _SFR_MEM8(0x08C0) 2770 #define SPIC_INTCTRL _SFR_MEM8(0x08C1) 2771 #define SPIC_STATUS _SFR_MEM8(0x08C2) 2772 #define SPIC_DATA _SFR_MEM8(0x08C3) 2773 2774 /* IRCOM - IR Communication Module */ 2775 #define IRCOM_CTRL _SFR_MEM8(0x08F8) 2776 #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) 2777 #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) 2778 2779 /* TC0 - 16-bit Timer/Counter 0 */ 2780 #define TCD0_CTRLA _SFR_MEM8(0x0900) 2781 #define TCD0_CTRLB _SFR_MEM8(0x0901) 2782 #define TCD0_CTRLC _SFR_MEM8(0x0902) 2783 #define TCD0_CTRLD _SFR_MEM8(0x0903) 2784 #define TCD0_CTRLE _SFR_MEM8(0x0904) 2785 #define TCD0_INTCTRLA _SFR_MEM8(0x0906) 2786 #define TCD0_INTCTRLB _SFR_MEM8(0x0907) 2787 #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) 2788 #define TCD0_CTRLFSET _SFR_MEM8(0x0909) 2789 #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) 2790 #define TCD0_CTRLGSET _SFR_MEM8(0x090B) 2791 #define TCD0_INTFLAGS _SFR_MEM8(0x090C) 2792 #define TCD0_TEMP _SFR_MEM8(0x090F) 2793 #define TCD0_CNT _SFR_MEM16(0x0920) 2794 #define TCD0_PER _SFR_MEM16(0x0926) 2795 #define TCD0_CCA _SFR_MEM16(0x0928) 2796 #define TCD0_CCB _SFR_MEM16(0x092A) 2797 #define TCD0_CCC _SFR_MEM16(0x092C) 2798 #define TCD0_CCD _SFR_MEM16(0x092E) 2799 #define TCD0_PERBUF _SFR_MEM16(0x0936) 2800 #define TCD0_CCABUF _SFR_MEM16(0x0938) 2801 #define TCD0_CCBBUF _SFR_MEM16(0x093A) 2802 #define TCD0_CCCBUF _SFR_MEM16(0x093C) 2803 #define TCD0_CCDBUF _SFR_MEM16(0x093E) 2804 2805 /* TC2 - 16-bit Timer/Counter type 2 */ 2806 #define TCD2_CTRLA _SFR_MEM8(0x0900) 2807 #define TCD2_CTRLB _SFR_MEM8(0x0901) 2808 #define TCD2_CTRLC _SFR_MEM8(0x0902) 2809 #define TCD2_CTRLE _SFR_MEM8(0x0904) 2810 #define TCD2_INTCTRLA _SFR_MEM8(0x0906) 2811 #define TCD2_INTCTRLB _SFR_MEM8(0x0907) 2812 #define TCD2_CTRLF _SFR_MEM8(0x0909) 2813 #define TCD2_INTFLAGS _SFR_MEM8(0x090C) 2814 #define TCD2_LCNT _SFR_MEM8(0x0920) 2815 #define TCD2_HCNT _SFR_MEM8(0x0921) 2816 #define TCD2_LPER _SFR_MEM8(0x0926) 2817 #define TCD2_HPER _SFR_MEM8(0x0927) 2818 #define TCD2_LCMPA _SFR_MEM8(0x0928) 2819 #define TCD2_HCMPA _SFR_MEM8(0x0929) 2820 #define TCD2_LCMPB _SFR_MEM8(0x092A) 2821 #define TCD2_HCMPB _SFR_MEM8(0x092B) 2822 #define TCD2_LCMPC _SFR_MEM8(0x092C) 2823 #define TCD2_HCMPC _SFR_MEM8(0x092D) 2824 #define TCD2_LCMPD _SFR_MEM8(0x092E) 2825 #define TCD2_HCMPD _SFR_MEM8(0x092F) 2826 2827 /* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ 2828 #define USARTD0_DATA _SFR_MEM8(0x09A0) 2829 #define USARTD0_STATUS _SFR_MEM8(0x09A1) 2830 #define USARTD0_CTRLA _SFR_MEM8(0x09A3) 2831 #define USARTD0_CTRLB _SFR_MEM8(0x09A4) 2832 #define USARTD0_CTRLC _SFR_MEM8(0x09A5) 2833 #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) 2834 #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) 2835 2836 /* SPI - Serial Peripheral Interface */ 2837 #define SPID_CTRL _SFR_MEM8(0x09C0) 2838 #define SPID_INTCTRL _SFR_MEM8(0x09C1) 2839 #define SPID_STATUS _SFR_MEM8(0x09C2) 2840 #define SPID_DATA _SFR_MEM8(0x09C3) 2841 2842 /* TC0 - 16-bit Timer/Counter 0 */ 2843 #define TCE0_CTRLA _SFR_MEM8(0x0A00) 2844 #define TCE0_CTRLB _SFR_MEM8(0x0A01) 2845 #define TCE0_CTRLC _SFR_MEM8(0x0A02) 2846 #define TCE0_CTRLD _SFR_MEM8(0x0A03) 2847 #define TCE0_CTRLE _SFR_MEM8(0x0A04) 2848 #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) 2849 #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) 2850 #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) 2851 #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) 2852 #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) 2853 #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) 2854 #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) 2855 #define TCE0_TEMP _SFR_MEM8(0x0A0F) 2856 #define TCE0_CNT _SFR_MEM16(0x0A20) 2857 #define TCE0_PER _SFR_MEM16(0x0A26) 2858 #define TCE0_CCA _SFR_MEM16(0x0A28) 2859 #define TCE0_CCB _SFR_MEM16(0x0A2A) 2860 #define TCE0_CCC _SFR_MEM16(0x0A2C) 2861 #define TCE0_CCD _SFR_MEM16(0x0A2E) 2862 #define TCE0_PERBUF _SFR_MEM16(0x0A36) 2863 #define TCE0_CCABUF _SFR_MEM16(0x0A38) 2864 #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) 2865 #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) 2866 #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) 2867 2868 2869 2870 /*================== Bitfield Definitions ================== */ 2871 2872 /* VPORT - Virtual Ports */ 2873 /* VPORT.INTFLAGS bit masks and bit positions */ 2874 #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 2875 #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 2876 2877 #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 2878 #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 2879 2880 /* XOCD - On-Chip Debug System */ 2881 /* OCD.OCDR0 bit masks and bit positions */ 2882 #define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ 2883 #define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ 2884 #define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ 2885 #define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ 2886 #define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ 2887 #define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ 2888 #define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ 2889 #define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ 2890 #define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ 2891 #define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ 2892 #define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ 2893 #define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ 2894 #define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ 2895 #define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ 2896 #define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ 2897 #define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ 2898 #define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ 2899 #define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ 2900 2901 /* OCD.OCDR1 bit masks and bit positions */ 2902 /* OCD_OCDRD Predefined. */ 2903 /* OCD_OCDRD Predefined. */ 2904 2905 /* CPU - CPU */ 2906 /* CPU.CCP bit masks and bit positions */ 2907 #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ 2908 #define CPU_CCP_gp 0 /* CCP signature group position. */ 2909 #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ 2910 #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ 2911 #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ 2912 #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ 2913 #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ 2914 #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ 2915 #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ 2916 #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ 2917 #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ 2918 #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ 2919 #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ 2920 #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ 2921 #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ 2922 #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ 2923 #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ 2924 #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ 2925 2926 /* CPU.SREG bit masks and bit positions */ 2927 #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ 2928 #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ 2929 2930 #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ 2931 #define CPU_T_bp 6 /* Transfer Bit bit position. */ 2932 2933 #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ 2934 #define CPU_H_bp 5 /* Half Carry Flag bit position. */ 2935 2936 #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ 2937 #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ 2938 2939 #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ 2940 #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ 2941 2942 #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ 2943 #define CPU_N_bp 2 /* Negative Flag bit position. */ 2944 2945 #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ 2946 #define CPU_Z_bp 1 /* Zero Flag bit position. */ 2947 2948 #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ 2949 #define CPU_C_bp 0 /* Carry Flag bit position. */ 2950 2951 /* CLK - Clock System */ 2952 /* CLK.CTRL bit masks and bit positions */ 2953 #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ 2954 #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ 2955 #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ 2956 #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ 2957 #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ 2958 #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ 2959 #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ 2960 #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ 2961 2962 /* CLK.PSCTRL bit masks and bit positions */ 2963 #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ 2964 #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ 2965 #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ 2966 #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ 2967 #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ 2968 #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ 2969 #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ 2970 #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ 2971 #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ 2972 #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ 2973 #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ 2974 #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ 2975 2976 #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ 2977 #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ 2978 #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ 2979 #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ 2980 #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ 2981 #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ 2982 2983 /* CLK.LOCK bit masks and bit positions */ 2984 #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ 2985 #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ 2986 2987 /* CLK.RTCCTRL bit masks and bit positions */ 2988 #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ 2989 #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ 2990 #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 2991 #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ 2992 #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 2993 #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ 2994 #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ 2995 #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ 2996 2997 #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ 2998 #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ 2999 3000 /* PR.PRGEN bit masks and bit positions */ 3001 #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ 3002 #define PR_RTC_bp 2 /* Real-time Counter bit position. */ 3003 3004 #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ 3005 #define PR_EVSYS_bp 1 /* Event System bit position. */ 3006 3007 /* PR.PRPA bit masks and bit positions */ 3008 #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ 3009 #define PR_ADC_bp 1 /* Port A ADC bit position. */ 3010 3011 #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ 3012 #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ 3013 3014 /* PR.PRPC bit masks and bit positions */ 3015 #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ 3016 #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ 3017 3018 #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ 3019 #define PR_USART0_bp 4 /* Port C USART0 bit position. */ 3020 3021 #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ 3022 #define PR_SPI_bp 3 /* Port C SPI bit position. */ 3023 3024 #define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ 3025 #define PR_HIRES_bp 2 /* Port C HIRES bit position. */ 3026 3027 #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ 3028 #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ 3029 3030 #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ 3031 #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ 3032 3033 /* PR.PRPD bit masks and bit positions */ 3034 /* PR_USART0 Predefined. */ 3035 /* PR_USART0 Predefined. */ 3036 3037 /* PR_SPI Predefined. */ 3038 /* PR_SPI Predefined. */ 3039 3040 /* PR_TC0 Predefined. */ 3041 /* PR_TC0 Predefined. */ 3042 3043 /* PR.PRPE bit masks and bit positions */ 3044 /* PR_TWI Predefined. */ 3045 /* PR_TWI Predefined. */ 3046 3047 /* PR_USART0 Predefined. */ 3048 /* PR_USART0 Predefined. */ 3049 3050 /* PR_TC0 Predefined. */ 3051 /* PR_TC0 Predefined. */ 3052 3053 /* PR.PRPF bit masks and bit positions */ 3054 /* PR_USART0 Predefined. */ 3055 /* PR_USART0 Predefined. */ 3056 3057 /* PR_TC0 Predefined. */ 3058 /* PR_TC0 Predefined. */ 3059 3060 /* SLEEP - Sleep Controller */ 3061 /* SLEEP.CTRL bit masks and bit positions */ 3062 #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ 3063 #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ 3064 #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ 3065 #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ 3066 #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ 3067 #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ 3068 #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ 3069 #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ 3070 3071 #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ 3072 #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ 3073 3074 /* OSC - Oscillator */ 3075 /* OSC.CTRL bit masks and bit positions */ 3076 #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ 3077 #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ 3078 3079 #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ 3080 #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ 3081 3082 #define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ 3083 #define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ 3084 3085 #define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ 3086 #define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ 3087 3088 #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ 3089 #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ 3090 3091 /* OSC.STATUS bit masks and bit positions */ 3092 #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ 3093 #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ 3094 3095 #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ 3096 #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ 3097 3098 #define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ 3099 #define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ 3100 3101 #define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ 3102 #define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ 3103 3104 #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ 3105 #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ 3106 3107 /* OSC.XOSCCTRL bit masks and bit positions */ 3108 #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ 3109 #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ 3110 #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ 3111 #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ 3112 #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ 3113 #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ 3114 3115 #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ 3116 #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ 3117 3118 #define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ 3119 #define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ 3120 3121 #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ 3122 #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ 3123 #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ 3124 #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ 3125 #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ 3126 #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ 3127 #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ 3128 #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ 3129 #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ 3130 #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ 3131 3132 /* OSC.XOSCFAIL bit masks and bit positions */ 3133 #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ 3134 #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ 3135 3136 #define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ 3137 #define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ 3138 3139 #define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ 3140 #define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ 3141 3142 #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ 3143 #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ 3144 3145 /* OSC.PLLCTRL bit masks and bit positions */ 3146 #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ 3147 #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ 3148 #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ 3149 #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ 3150 #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ 3151 #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ 3152 3153 #define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ 3154 #define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ 3155 3156 #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ 3157 #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ 3158 #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ 3159 #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ 3160 #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ 3161 #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ 3162 #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ 3163 #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ 3164 #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ 3165 #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ 3166 #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ 3167 #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ 3168 3169 /* OSC.DFLLCTRL bit masks and bit positions */ 3170 #define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ 3171 #define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ 3172 #define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ 3173 #define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ 3174 #define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ 3175 #define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ 3176 3177 #define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ 3178 #define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ 3179 3180 /* DFLL - DFLL */ 3181 /* DFLL.CTRL bit masks and bit positions */ 3182 #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ 3183 #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ 3184 3185 /* DFLL.CALA bit masks and bit positions */ 3186 #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ 3187 #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ 3188 #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ 3189 #define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ 3190 #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ 3191 #define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ 3192 #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ 3193 #define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ 3194 #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ 3195 #define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ 3196 #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ 3197 #define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ 3198 #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ 3199 #define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ 3200 #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ 3201 #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ 3202 3203 /* DFLL.CALB bit masks and bit positions */ 3204 #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ 3205 #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ 3206 #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ 3207 #define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ 3208 #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ 3209 #define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ 3210 #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ 3211 #define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ 3212 #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ 3213 #define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ 3214 #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ 3215 #define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ 3216 #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ 3217 #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ 3218 3219 /* RST - Reset */ 3220 /* RST.STATUS bit masks and bit positions */ 3221 #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ 3222 #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ 3223 3224 #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ 3225 #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ 3226 3227 #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ 3228 #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ 3229 3230 #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ 3231 #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ 3232 3233 #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ 3234 #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ 3235 3236 #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ 3237 #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ 3238 3239 #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ 3240 #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ 3241 3242 /* RST.CTRL bit masks and bit positions */ 3243 #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ 3244 #define RST_SWRST_bp 0 /* Software Reset bit position. */ 3245 3246 /* WDT - Watch-Dog Timer */ 3247 /* WDT.CTRL bit masks and bit positions */ 3248 #define WDT_PER_gm 0x3C /* Period group mask. */ 3249 #define WDT_PER_gp 2 /* Period group position. */ 3250 #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ 3251 #define WDT_PER0_bp 2 /* Period bit 0 position. */ 3252 #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ 3253 #define WDT_PER1_bp 3 /* Period bit 1 position. */ 3254 #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ 3255 #define WDT_PER2_bp 4 /* Period bit 2 position. */ 3256 #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ 3257 #define WDT_PER3_bp 5 /* Period bit 3 position. */ 3258 3259 #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ 3260 #define WDT_ENABLE_bp 1 /* Enable bit position. */ 3261 3262 #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ 3263 #define WDT_CEN_bp 0 /* Change Enable bit position. */ 3264 3265 /* WDT.WINCTRL bit masks and bit positions */ 3266 #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ 3267 #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ 3268 #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ 3269 #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ 3270 #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ 3271 #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ 3272 #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ 3273 #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ 3274 #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ 3275 #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ 3276 3277 #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ 3278 #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ 3279 3280 #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ 3281 #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ 3282 3283 /* WDT.STATUS bit masks and bit positions */ 3284 #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ 3285 #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ 3286 3287 /* MCU - MCU Control */ 3288 /* MCU.ANAINIT bit masks and bit positions */ 3289 #define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ 3290 #define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ 3291 #define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ 3292 #define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ 3293 #define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ 3294 #define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ 3295 3296 /* MCU.EVSYSLOCK bit masks and bit positions */ 3297 #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ 3298 #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ 3299 3300 /* MCU.AWEXLOCK bit masks and bit positions */ 3301 #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ 3302 #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ 3303 3304 /* PMIC - Programmable Multi-level Interrupt Controller */ 3305 /* PMIC.STATUS bit masks and bit positions */ 3306 #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ 3307 #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ 3308 3309 #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ 3310 #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ 3311 3312 #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ 3313 #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ 3314 3315 #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ 3316 #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ 3317 3318 /* PMIC.INTPRI bit masks and bit positions */ 3319 #define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ 3320 #define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ 3321 #define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ 3322 #define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ 3323 #define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ 3324 #define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ 3325 #define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ 3326 #define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ 3327 #define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ 3328 #define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ 3329 #define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ 3330 #define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ 3331 #define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ 3332 #define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ 3333 #define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ 3334 #define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ 3335 #define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ 3336 #define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ 3337 3338 /* PMIC.CTRL bit masks and bit positions */ 3339 #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ 3340 #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ 3341 3342 #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ 3343 #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ 3344 3345 #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ 3346 #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ 3347 3348 #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ 3349 #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ 3350 3351 #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ 3352 #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ 3353 3354 /* PORTCFG - Port Configuration */ 3355 /* PORTCFG.VPCTRLA bit masks and bit positions */ 3356 #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ 3357 #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ 3358 #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ 3359 #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ 3360 #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ 3361 #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ 3362 #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ 3363 #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ 3364 #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ 3365 #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ 3366 3367 #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ 3368 #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ 3369 #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ 3370 #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ 3371 #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ 3372 #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ 3373 #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ 3374 #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ 3375 #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ 3376 #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ 3377 3378 /* PORTCFG.VPCTRLB bit masks and bit positions */ 3379 #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ 3380 #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ 3381 #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ 3382 #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ 3383 #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ 3384 #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ 3385 #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ 3386 #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ 3387 #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ 3388 #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ 3389 3390 #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ 3391 #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ 3392 #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ 3393 #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ 3394 #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ 3395 #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ 3396 #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ 3397 #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ 3398 #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ 3399 #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ 3400 3401 /* PORTCFG.CLKEVOUT bit masks and bit positions */ 3402 #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ 3403 #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ 3404 #define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ 3405 #define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ 3406 #define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ 3407 #define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ 3408 3409 #define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ 3410 #define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ 3411 #define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ 3412 #define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ 3413 #define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ 3414 #define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ 3415 3416 #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ 3417 #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ 3418 #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ 3419 #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ 3420 #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ 3421 #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ 3422 3423 #define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ 3424 #define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ 3425 3426 #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ 3427 #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ 3428 3429 /* PORTCFG.EVOUTSEL bit masks and bit positions */ 3430 #define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ 3431 #define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ 3432 #define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ 3433 #define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ 3434 #define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ 3435 #define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ 3436 #define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ 3437 #define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ 3438 3439 /* CRC - Cyclic Redundancy Checker */ 3440 /* CRC.CTRL bit masks and bit positions */ 3441 #define CRC_RESET_gm 0xC0 /* Reset group mask. */ 3442 #define CRC_RESET_gp 6 /* Reset group position. */ 3443 #define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ 3444 #define CRC_RESET0_bp 6 /* Reset bit 0 position. */ 3445 #define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ 3446 #define CRC_RESET1_bp 7 /* Reset bit 1 position. */ 3447 3448 #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ 3449 #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ 3450 3451 #define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ 3452 #define CRC_SOURCE_gp 0 /* Input Source group position. */ 3453 #define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ 3454 #define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ 3455 #define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ 3456 #define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ 3457 #define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ 3458 #define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ 3459 #define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ 3460 #define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ 3461 3462 /* CRC.STATUS bit masks and bit positions */ 3463 #define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ 3464 #define CRC_ZERO_bp 1 /* Zero detection bit position. */ 3465 3466 #define CRC_BUSY_bm 0x01 /* Busy bit mask. */ 3467 #define CRC_BUSY_bp 0 /* Busy bit position. */ 3468 3469 /* EVSYS - Event System */ 3470 /* EVSYS.CH0MUX bit masks and bit positions */ 3471 #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ 3472 #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ 3473 #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ 3474 #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ 3475 #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ 3476 #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ 3477 #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ 3478 #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ 3479 #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ 3480 #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ 3481 #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ 3482 #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ 3483 #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ 3484 #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ 3485 #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ 3486 #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ 3487 #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ 3488 #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ 3489 3490 /* EVSYS.CH1MUX bit masks and bit positions */ 3491 /* EVSYS_CHMUX Predefined. */ 3492 /* EVSYS_CHMUX Predefined. */ 3493 3494 /* EVSYS.CH2MUX bit masks and bit positions */ 3495 /* EVSYS_CHMUX Predefined. */ 3496 /* EVSYS_CHMUX Predefined. */ 3497 3498 /* EVSYS.CH3MUX bit masks and bit positions */ 3499 /* EVSYS_CHMUX Predefined. */ 3500 /* EVSYS_CHMUX Predefined. */ 3501 3502 /* EVSYS.CH0CTRL bit masks and bit positions */ 3503 #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ 3504 #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ 3505 #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ 3506 #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ 3507 #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ 3508 #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ 3509 3510 #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ 3511 #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ 3512 3513 #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ 3514 #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ 3515 3516 #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ 3517 #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ 3518 #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ 3519 #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ 3520 #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ 3521 #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ 3522 #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ 3523 #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ 3524 3525 /* EVSYS.CH1CTRL bit masks and bit positions */ 3526 /* EVSYS_DIGFILT Predefined. */ 3527 /* EVSYS_DIGFILT Predefined. */ 3528 3529 /* EVSYS.CH2CTRL bit masks and bit positions */ 3530 /* EVSYS_DIGFILT Predefined. */ 3531 /* EVSYS_DIGFILT Predefined. */ 3532 3533 /* EVSYS.CH3CTRL bit masks and bit positions */ 3534 /* EVSYS_DIGFILT Predefined. */ 3535 /* EVSYS_DIGFILT Predefined. */ 3536 3537 /* NVM - Non Volatile Memory Controller */ 3538 /* NVM.CMD bit masks and bit positions */ 3539 #define NVM_CMD_gm 0x7F /* Command group mask. */ 3540 #define NVM_CMD_gp 0 /* Command group position. */ 3541 #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ 3542 #define NVM_CMD0_bp 0 /* Command bit 0 position. */ 3543 #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ 3544 #define NVM_CMD1_bp 1 /* Command bit 1 position. */ 3545 #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ 3546 #define NVM_CMD2_bp 2 /* Command bit 2 position. */ 3547 #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ 3548 #define NVM_CMD3_bp 3 /* Command bit 3 position. */ 3549 #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ 3550 #define NVM_CMD4_bp 4 /* Command bit 4 position. */ 3551 #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ 3552 #define NVM_CMD5_bp 5 /* Command bit 5 position. */ 3553 #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ 3554 #define NVM_CMD6_bp 6 /* Command bit 6 position. */ 3555 3556 /* NVM.CTRLA bit masks and bit positions */ 3557 #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ 3558 #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ 3559 3560 /* NVM.CTRLB bit masks and bit positions */ 3561 #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ 3562 #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ 3563 3564 #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ 3565 #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ 3566 3567 #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ 3568 #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ 3569 3570 #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ 3571 #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ 3572 3573 /* NVM.INTCTRL bit masks and bit positions */ 3574 #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ 3575 #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ 3576 #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ 3577 #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ 3578 #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ 3579 #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ 3580 3581 #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ 3582 #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ 3583 #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ 3584 #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ 3585 #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ 3586 #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ 3587 3588 /* NVM.STATUS bit masks and bit positions */ 3589 #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ 3590 #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ 3591 3592 #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ 3593 #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ 3594 3595 #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ 3596 #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ 3597 3598 #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ 3599 #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ 3600 3601 /* NVM.LOCKBITS bit masks and bit positions */ 3602 #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 3603 #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 3604 #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 3605 #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 3606 #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 3607 #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 3608 3609 #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 3610 #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 3611 #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 3612 #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 3613 #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 3614 #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 3615 3616 #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 3617 #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 3618 #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 3619 #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 3620 #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 3621 #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 3622 3623 #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ 3624 #define NVM_LB_gp 0 /* Lock Bits group position. */ 3625 #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 3626 #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ 3627 #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 3628 #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ 3629 3630 /* ADC - Analog/Digital Converter */ 3631 /* ADC_CH.CTRL bit masks and bit positions */ 3632 #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ 3633 #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ 3634 3635 #define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ 3636 #define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ 3637 #define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ 3638 #define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ 3639 #define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ 3640 #define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ 3641 #define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ 3642 #define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ 3643 3644 #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ 3645 #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ 3646 #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ 3647 #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ 3648 #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ 3649 #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ 3650 3651 /* ADC_CH.MUXCTRL bit masks and bit positions */ 3652 #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ 3653 #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ 3654 #define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ 3655 #define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ 3656 #define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ 3657 #define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ 3658 #define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ 3659 #define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ 3660 #define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ 3661 #define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ 3662 3663 #define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ 3664 #define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ 3665 #define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ 3666 #define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ 3667 #define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ 3668 #define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ 3669 #define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ 3670 #define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ 3671 #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ 3672 #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ 3673 3674 #define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ 3675 #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ 3676 #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ 3677 #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ 3678 #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ 3679 #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ 3680 3681 /* ADC_CH.INTCTRL bit masks and bit positions */ 3682 #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ 3683 #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ 3684 #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ 3685 #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ 3686 #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ 3687 #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ 3688 3689 #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 3690 #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ 3691 #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 3692 #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 3693 #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 3694 #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 3695 3696 /* ADC_CH.INTFLAGS bit masks and bit positions */ 3697 #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ 3698 #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ 3699 3700 /* ADC_CH.SCAN bit masks and bit positions */ 3701 #define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ 3702 #define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ 3703 #define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ 3704 #define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ 3705 #define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ 3706 #define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ 3707 #define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ 3708 #define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ 3709 #define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ 3710 #define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ 3711 3712 #define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ 3713 #define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ 3714 #define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ 3715 #define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ 3716 #define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ 3717 #define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ 3718 #define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ 3719 #define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ 3720 #define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ 3721 #define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ 3722 3723 /* ADC.CTRLA bit masks and bit positions */ 3724 #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ 3725 #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ 3726 3727 #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ 3728 #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ 3729 3730 #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ 3731 #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ 3732 3733 /* ADC.CTRLB bit masks and bit positions */ 3734 #define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ 3735 #define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ 3736 #define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ 3737 #define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ 3738 #define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ 3739 #define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ 3740 3741 #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ 3742 #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ 3743 3744 #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ 3745 #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ 3746 3747 #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ 3748 #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ 3749 #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ 3750 #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ 3751 #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ 3752 #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ 3753 3754 /* ADC.REFCTRL bit masks and bit positions */ 3755 #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ 3756 #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ 3757 #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ 3758 #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ 3759 #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ 3760 #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ 3761 #define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ 3762 #define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ 3763 3764 #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ 3765 #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ 3766 3767 #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ 3768 #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ 3769 3770 /* ADC.EVCTRL bit masks and bit positions */ 3771 #define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ 3772 #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ 3773 #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ 3774 #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ 3775 #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ 3776 #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ 3777 3778 #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ 3779 #define ADC_EVACT_gp 0 /* Event Action Select group position. */ 3780 #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ 3781 #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ 3782 #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ 3783 #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ 3784 #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ 3785 #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ 3786 3787 /* ADC.PRESCALER bit masks and bit positions */ 3788 #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ 3789 #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ 3790 #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ 3791 #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ 3792 #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ 3793 #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ 3794 #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ 3795 #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ 3796 3797 /* ADC.INTFLAGS bit masks and bit positions */ 3798 #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ 3799 #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ 3800 3801 /* AC - Analog Comparator */ 3802 /* AC.AC0CTRL bit masks and bit positions */ 3803 #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ 3804 #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ 3805 #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ 3806 #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ 3807 #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ 3808 #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ 3809 3810 #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ 3811 #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ 3812 #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ 3813 #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ 3814 #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ 3815 #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ 3816 3817 #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ 3818 #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ 3819 #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ 3820 #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ 3821 #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ 3822 #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ 3823 3824 #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ 3825 #define AC_ENABLE_bp 0 /* Enable bit position. */ 3826 3827 /* AC.AC1CTRL bit masks and bit positions */ 3828 /* AC_INTMODE Predefined. */ 3829 /* AC_INTMODE Predefined. */ 3830 3831 /* AC_INTLVL Predefined. */ 3832 /* AC_INTLVL Predefined. */ 3833 3834 /* AC_HYSMODE Predefined. */ 3835 /* AC_HYSMODE Predefined. */ 3836 3837 /* AC_ENABLE Predefined. */ 3838 /* AC_ENABLE Predefined. */ 3839 3840 /* AC.AC0MUXCTRL bit masks and bit positions */ 3841 #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ 3842 #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ 3843 #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ 3844 #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ 3845 #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ 3846 #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ 3847 #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ 3848 #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ 3849 3850 #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ 3851 #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ 3852 #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ 3853 #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ 3854 #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ 3855 #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ 3856 #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ 3857 #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ 3858 3859 /* AC.AC1MUXCTRL bit masks and bit positions */ 3860 /* AC_MUXPOS Predefined. */ 3861 /* AC_MUXPOS Predefined. */ 3862 3863 /* AC_MUXNEG Predefined. */ 3864 /* AC_MUXNEG Predefined. */ 3865 3866 /* AC.CTRLA bit masks and bit positions */ 3867 #define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ 3868 #define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ 3869 3870 #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ 3871 #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ 3872 3873 /* AC.CTRLB bit masks and bit positions */ 3874 #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ 3875 #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ 3876 #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ 3877 #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ 3878 #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ 3879 #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ 3880 #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ 3881 #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ 3882 #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ 3883 #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ 3884 #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ 3885 #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ 3886 #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ 3887 #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ 3888 3889 /* AC.WINCTRL bit masks and bit positions */ 3890 #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ 3891 #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ 3892 3893 #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ 3894 #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ 3895 #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ 3896 #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ 3897 #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ 3898 #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ 3899 3900 #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ 3901 #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ 3902 #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ 3903 #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ 3904 #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ 3905 #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ 3906 3907 /* AC.STATUS bit masks and bit positions */ 3908 #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ 3909 #define AC_WSTATE_gp 6 /* Window Mode State group position. */ 3910 #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ 3911 #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ 3912 #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ 3913 #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ 3914 3915 #define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ 3916 #define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ 3917 3918 #define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ 3919 #define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ 3920 3921 #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ 3922 #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ 3923 3924 #define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ 3925 #define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ 3926 3927 #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ 3928 #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ 3929 3930 /* RTC - Real-Time Counter */ 3931 /* RTC.CTRL bit masks and bit positions */ 3932 #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ 3933 #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ 3934 #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ 3935 #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ 3936 #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ 3937 #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ 3938 #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ 3939 #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ 3940 3941 /* RTC.STATUS bit masks and bit positions */ 3942 #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ 3943 #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ 3944 3945 /* RTC.INTCTRL bit masks and bit positions */ 3946 #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ 3947 #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ 3948 #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ 3949 #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ 3950 #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ 3951 #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ 3952 3953 #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ 3954 #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ 3955 #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ 3956 #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ 3957 #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ 3958 #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ 3959 3960 /* RTC.INTFLAGS bit masks and bit positions */ 3961 #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ 3962 #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ 3963 3964 #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 3965 #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 3966 3967 /* TWI - Two-Wire Interface */ 3968 /* TWI_MASTER.CTRLA bit masks and bit positions */ 3969 #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 3970 #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ 3971 #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 3972 #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 3973 #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 3974 #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 3975 3976 #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ 3977 #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ 3978 3979 #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ 3980 #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ 3981 3982 #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ 3983 #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ 3984 3985 /* TWI_MASTER.CTRLB bit masks and bit positions */ 3986 #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ 3987 #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ 3988 #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ 3989 #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ 3990 #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ 3991 #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ 3992 3993 #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ 3994 #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ 3995 3996 #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 3997 #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ 3998 3999 /* TWI_MASTER.CTRLC bit masks and bit positions */ 4000 #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4001 #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4002 4003 #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ 4004 #define TWI_MASTER_CMD_gp 0 /* Command group position. */ 4005 #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4006 #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ 4007 #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4008 #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ 4009 4010 /* TWI_MASTER.STATUS bit masks and bit positions */ 4011 #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ 4012 #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ 4013 4014 #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ 4015 #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ 4016 4017 #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4018 #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4019 4020 #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4021 #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ 4022 4023 #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ 4024 #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ 4025 4026 #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4027 #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ 4028 4029 #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ 4030 #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ 4031 #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ 4032 #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ 4033 #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ 4034 #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ 4035 4036 /* TWI_SLAVE.CTRLA bit masks and bit positions */ 4037 #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4038 #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ 4039 #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4040 #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4041 #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4042 #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4043 4044 #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ 4045 #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ 4046 4047 #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ 4048 #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ 4049 4050 #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ 4051 #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ 4052 4053 #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ 4054 #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ 4055 4056 #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ 4057 #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ 4058 4059 #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4060 #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4061 4062 /* TWI_SLAVE.CTRLB bit masks and bit positions */ 4063 #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4064 #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4065 4066 #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ 4067 #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ 4068 #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4069 #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ 4070 #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4071 #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ 4072 4073 /* TWI_SLAVE.STATUS bit masks and bit positions */ 4074 #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ 4075 #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ 4076 4077 #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ 4078 #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ 4079 4080 #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4081 #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4082 4083 #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4084 #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ 4085 4086 #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ 4087 #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ 4088 4089 #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4090 #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ 4091 4092 #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ 4093 #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ 4094 4095 #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ 4096 #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ 4097 4098 /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ 4099 #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ 4100 #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ 4101 #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ 4102 #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ 4103 #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ 4104 #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ 4105 #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ 4106 #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ 4107 #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ 4108 #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ 4109 #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ 4110 #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ 4111 #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ 4112 #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ 4113 #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ 4114 #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ 4115 4116 #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ 4117 #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ 4118 4119 /* TWI.CTRL bit masks and bit positions */ 4120 #define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ 4121 #define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ 4122 #define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ 4123 #define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ 4124 #define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ 4125 #define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ 4126 4127 #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ 4128 #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ 4129 4130 /* PORT - I/O Port Configuration */ 4131 /* PORT.INTCTRL bit masks and bit positions */ 4132 #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ 4133 #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ 4134 #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ 4135 #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ 4136 #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ 4137 #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ 4138 4139 #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ 4140 #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ 4141 #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ 4142 #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ 4143 #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ 4144 #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ 4145 4146 /* PORT.INTFLAGS bit masks and bit positions */ 4147 #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 4148 #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 4149 4150 #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 4151 #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 4152 4153 /* PORT.REMAP bit masks and bit positions */ 4154 #define PORT_SPI_bm 0x20 /* SPI bit mask. */ 4155 #define PORT_SPI_bp 5 /* SPI bit position. */ 4156 4157 #define PORT_USART0_bm 0x10 /* USART0 bit mask. */ 4158 #define PORT_USART0_bp 4 /* USART0 bit position. */ 4159 4160 #define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ 4161 #define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ 4162 4163 #define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ 4164 #define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ 4165 4166 #define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ 4167 #define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ 4168 4169 #define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ 4170 #define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ 4171 4172 /* PORT.PIN0CTRL bit masks and bit positions */ 4173 #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ 4174 #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ 4175 4176 #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ 4177 #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ 4178 4179 #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ 4180 #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ 4181 #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ 4182 #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ 4183 #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ 4184 #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ 4185 #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ 4186 #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ 4187 4188 #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ 4189 #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ 4190 #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ 4191 #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ 4192 #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ 4193 #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ 4194 #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ 4195 #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ 4196 4197 /* PORT.PIN1CTRL bit masks and bit positions */ 4198 /* PORT_SRLEN Predefined. */ 4199 /* PORT_SRLEN Predefined. */ 4200 4201 /* PORT_INVEN Predefined. */ 4202 /* PORT_INVEN Predefined. */ 4203 4204 /* PORT_OPC Predefined. */ 4205 /* PORT_OPC Predefined. */ 4206 4207 /* PORT_ISC Predefined. */ 4208 /* PORT_ISC Predefined. */ 4209 4210 /* PORT.PIN2CTRL bit masks and bit positions */ 4211 /* PORT_SRLEN Predefined. */ 4212 /* PORT_SRLEN Predefined. */ 4213 4214 /* PORT_INVEN Predefined. */ 4215 /* PORT_INVEN Predefined. */ 4216 4217 /* PORT_OPC Predefined. */ 4218 /* PORT_OPC Predefined. */ 4219 4220 /* PORT_ISC Predefined. */ 4221 /* PORT_ISC Predefined. */ 4222 4223 /* PORT.PIN3CTRL bit masks and bit positions */ 4224 /* PORT_SRLEN Predefined. */ 4225 /* PORT_SRLEN Predefined. */ 4226 4227 /* PORT_INVEN Predefined. */ 4228 /* PORT_INVEN Predefined. */ 4229 4230 /* PORT_OPC Predefined. */ 4231 /* PORT_OPC Predefined. */ 4232 4233 /* PORT_ISC Predefined. */ 4234 /* PORT_ISC Predefined. */ 4235 4236 /* PORT.PIN4CTRL bit masks and bit positions */ 4237 /* PORT_SRLEN Predefined. */ 4238 /* PORT_SRLEN Predefined. */ 4239 4240 /* PORT_INVEN Predefined. */ 4241 /* PORT_INVEN Predefined. */ 4242 4243 /* PORT_OPC Predefined. */ 4244 /* PORT_OPC Predefined. */ 4245 4246 /* PORT_ISC Predefined. */ 4247 /* PORT_ISC Predefined. */ 4248 4249 /* PORT.PIN5CTRL bit masks and bit positions */ 4250 /* PORT_SRLEN Predefined. */ 4251 /* PORT_SRLEN Predefined. */ 4252 4253 /* PORT_INVEN Predefined. */ 4254 /* PORT_INVEN Predefined. */ 4255 4256 /* PORT_OPC Predefined. */ 4257 /* PORT_OPC Predefined. */ 4258 4259 /* PORT_ISC Predefined. */ 4260 /* PORT_ISC Predefined. */ 4261 4262 /* PORT.PIN6CTRL bit masks and bit positions */ 4263 /* PORT_SRLEN Predefined. */ 4264 /* PORT_SRLEN Predefined. */ 4265 4266 /* PORT_INVEN Predefined. */ 4267 /* PORT_INVEN Predefined. */ 4268 4269 /* PORT_OPC Predefined. */ 4270 /* PORT_OPC Predefined. */ 4271 4272 /* PORT_ISC Predefined. */ 4273 /* PORT_ISC Predefined. */ 4274 4275 /* PORT.PIN7CTRL bit masks and bit positions */ 4276 /* PORT_SRLEN Predefined. */ 4277 /* PORT_SRLEN Predefined. */ 4278 4279 /* PORT_INVEN Predefined. */ 4280 /* PORT_INVEN Predefined. */ 4281 4282 /* PORT_OPC Predefined. */ 4283 /* PORT_OPC Predefined. */ 4284 4285 /* PORT_ISC Predefined. */ 4286 /* PORT_ISC Predefined. */ 4287 4288 /* TC - 16-bit Timer/Counter With PWM */ 4289 /* TC0.CTRLA bit masks and bit positions */ 4290 #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 4291 #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ 4292 #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 4293 #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 4294 #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 4295 #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 4296 #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 4297 #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 4298 #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 4299 #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 4300 4301 /* TC0.CTRLB bit masks and bit positions */ 4302 #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ 4303 #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ 4304 4305 #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ 4306 #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ 4307 4308 #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 4309 #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 4310 4311 #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 4312 #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 4313 4314 #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 4315 #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ 4316 #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 4317 #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 4318 #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 4319 #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 4320 #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 4321 #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 4322 4323 /* TC0.CTRLC bit masks and bit positions */ 4324 #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ 4325 #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ 4326 4327 #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ 4328 #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ 4329 4330 #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 4331 #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ 4332 4333 #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 4334 #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ 4335 4336 /* TC0.CTRLD bit masks and bit positions */ 4337 #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ 4338 #define TC0_EVACT_gp 5 /* Event Action group position. */ 4339 #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 4340 #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ 4341 #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 4342 #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ 4343 #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 4344 #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ 4345 4346 #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ 4347 #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ 4348 4349 #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ 4350 #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ 4351 #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 4352 #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 4353 #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 4354 #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 4355 #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 4356 #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 4357 #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 4358 #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 4359 4360 /* TC0.CTRLE bit masks and bit positions */ 4361 #define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ 4362 #define TC0_BYTEM_gp 0 /* Byte Mode group position. */ 4363 #define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ 4364 #define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ 4365 #define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ 4366 #define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ 4367 4368 /* TC0.INTCTRLA bit masks and bit positions */ 4369 #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 4370 #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 4371 #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 4372 #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 4373 #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 4374 #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 4375 4376 #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 4377 #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 4378 #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 4379 #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 4380 #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 4381 #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 4382 4383 /* TC0.INTCTRLB bit masks and bit positions */ 4384 #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ 4385 #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ 4386 #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ 4387 #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ 4388 #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ 4389 #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ 4390 4391 #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ 4392 #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ 4393 #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ 4394 #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ 4395 #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ 4396 #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ 4397 4398 #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 4399 #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 4400 #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 4401 #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 4402 #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 4403 #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 4404 4405 #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 4406 #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 4407 #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 4408 #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 4409 #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 4410 #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 4411 4412 /* TC0.CTRLFCLR bit masks and bit positions */ 4413 #define TC0_CMD_gm 0x0C /* Command group mask. */ 4414 #define TC0_CMD_gp 2 /* Command group position. */ 4415 #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ 4416 #define TC0_CMD0_bp 2 /* Command bit 0 position. */ 4417 #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ 4418 #define TC0_CMD1_bp 3 /* Command bit 1 position. */ 4419 4420 #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ 4421 #define TC0_LUPD_bp 1 /* Lock Update bit position. */ 4422 4423 #define TC0_DIR_bm 0x01 /* Direction bit mask. */ 4424 #define TC0_DIR_bp 0 /* Direction bit position. */ 4425 4426 /* TC0.CTRLFSET bit masks and bit positions */ 4427 /* TC0_CMD Predefined. */ 4428 /* TC0_CMD Predefined. */ 4429 4430 /* TC0_LUPD Predefined. */ 4431 /* TC0_LUPD Predefined. */ 4432 4433 /* TC0_DIR Predefined. */ 4434 /* TC0_DIR Predefined. */ 4435 4436 /* TC0.CTRLGCLR bit masks and bit positions */ 4437 #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ 4438 #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ 4439 4440 #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ 4441 #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ 4442 4443 #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 4444 #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 4445 4446 #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 4447 #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 4448 4449 #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 4450 #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ 4451 4452 /* TC0.CTRLGSET bit masks and bit positions */ 4453 /* TC0_CCDBV Predefined. */ 4454 /* TC0_CCDBV Predefined. */ 4455 4456 /* TC0_CCCBV Predefined. */ 4457 /* TC0_CCCBV Predefined. */ 4458 4459 /* TC0_CCBBV Predefined. */ 4460 /* TC0_CCBBV Predefined. */ 4461 4462 /* TC0_CCABV Predefined. */ 4463 /* TC0_CCABV Predefined. */ 4464 4465 /* TC0_PERBV Predefined. */ 4466 /* TC0_PERBV Predefined. */ 4467 4468 /* TC0.INTFLAGS bit masks and bit positions */ 4469 #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ 4470 #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ 4471 4472 #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ 4473 #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ 4474 4475 #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 4476 #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 4477 4478 #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 4479 #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 4480 4481 #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 4482 #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 4483 4484 #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4485 #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 4486 4487 /* TC1.CTRLA bit masks and bit positions */ 4488 #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 4489 #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ 4490 #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 4491 #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 4492 #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 4493 #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 4494 #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 4495 #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 4496 #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 4497 #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 4498 4499 /* TC1.CTRLB bit masks and bit positions */ 4500 #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 4501 #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 4502 4503 #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 4504 #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 4505 4506 #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 4507 #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ 4508 #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 4509 #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 4510 #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 4511 #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 4512 #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 4513 #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 4514 4515 /* TC1.CTRLC bit masks and bit positions */ 4516 #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 4517 #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ 4518 4519 #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 4520 #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ 4521 4522 /* TC1.CTRLD bit masks and bit positions */ 4523 #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ 4524 #define TC1_EVACT_gp 5 /* Event Action group position. */ 4525 #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 4526 #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ 4527 #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 4528 #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ 4529 #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 4530 #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ 4531 4532 #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ 4533 #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ 4534 4535 #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ 4536 #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ 4537 #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 4538 #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 4539 #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 4540 #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 4541 #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 4542 #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 4543 #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 4544 #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 4545 4546 /* TC1.CTRLE bit masks and bit positions */ 4547 #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 4548 #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ 4549 4550 /* TC1.INTCTRLA bit masks and bit positions */ 4551 #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 4552 #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 4553 #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 4554 #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 4555 #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 4556 #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 4557 4558 #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 4559 #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 4560 #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 4561 #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 4562 #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 4563 #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 4564 4565 /* TC1.INTCTRLB bit masks and bit positions */ 4566 #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 4567 #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 4568 #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 4569 #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 4570 #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 4571 #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 4572 4573 #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 4574 #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 4575 #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 4576 #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 4577 #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 4578 #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 4579 4580 /* TC1.CTRLFCLR bit masks and bit positions */ 4581 #define TC1_CMD_gm 0x0C /* Command group mask. */ 4582 #define TC1_CMD_gp 2 /* Command group position. */ 4583 #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ 4584 #define TC1_CMD0_bp 2 /* Command bit 0 position. */ 4585 #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ 4586 #define TC1_CMD1_bp 3 /* Command bit 1 position. */ 4587 4588 #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ 4589 #define TC1_LUPD_bp 1 /* Lock Update bit position. */ 4590 4591 #define TC1_DIR_bm 0x01 /* Direction bit mask. */ 4592 #define TC1_DIR_bp 0 /* Direction bit position. */ 4593 4594 /* TC1.CTRLFSET bit masks and bit positions */ 4595 /* TC1_CMD Predefined. */ 4596 /* TC1_CMD Predefined. */ 4597 4598 /* TC1_LUPD Predefined. */ 4599 /* TC1_LUPD Predefined. */ 4600 4601 /* TC1_DIR Predefined. */ 4602 /* TC1_DIR Predefined. */ 4603 4604 /* TC1.CTRLGCLR bit masks and bit positions */ 4605 #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 4606 #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 4607 4608 #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 4609 #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 4610 4611 #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 4612 #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ 4613 4614 /* TC1.CTRLGSET bit masks and bit positions */ 4615 /* TC1_CCBBV Predefined. */ 4616 /* TC1_CCBBV Predefined. */ 4617 4618 /* TC1_CCABV Predefined. */ 4619 /* TC1_CCABV Predefined. */ 4620 4621 /* TC1_PERBV Predefined. */ 4622 /* TC1_PERBV Predefined. */ 4623 4624 /* TC1.INTFLAGS bit masks and bit positions */ 4625 #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 4626 #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 4627 4628 #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 4629 #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 4630 4631 #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 4632 #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 4633 4634 #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4635 #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 4636 4637 /* TC2 - 16-bit Timer/Counter type 2 */ 4638 /* TC2.CTRLA bit masks and bit positions */ 4639 #define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 4640 #define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ 4641 #define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 4642 #define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 4643 #define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 4644 #define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 4645 #define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 4646 #define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 4647 #define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 4648 #define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 4649 4650 /* TC2.CTRLB bit masks and bit positions */ 4651 #define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ 4652 #define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ 4653 4654 #define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ 4655 #define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ 4656 4657 #define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ 4658 #define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ 4659 4660 #define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ 4661 #define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ 4662 4663 #define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ 4664 #define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ 4665 4666 #define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ 4667 #define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ 4668 4669 #define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ 4670 #define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ 4671 4672 #define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ 4673 #define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ 4674 4675 /* TC2.CTRLC bit masks and bit positions */ 4676 #define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ 4677 #define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ 4678 4679 #define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ 4680 #define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ 4681 4682 #define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ 4683 #define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ 4684 4685 #define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ 4686 #define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ 4687 4688 #define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ 4689 #define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ 4690 4691 #define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ 4692 #define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ 4693 4694 #define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ 4695 #define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ 4696 4697 #define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ 4698 #define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ 4699 4700 /* TC2.CTRLE bit masks and bit positions */ 4701 #define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ 4702 #define TC2_BYTEM_gp 0 /* Byte Mode group position. */ 4703 #define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ 4704 #define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ 4705 #define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ 4706 #define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ 4707 4708 /* TC2.INTCTRLA bit masks and bit positions */ 4709 #define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ 4710 #define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ 4711 #define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ 4712 #define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ 4713 #define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ 4714 #define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ 4715 4716 #define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ 4717 #define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ 4718 #define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ 4719 #define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ 4720 #define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ 4721 #define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ 4722 4723 /* TC2.INTCTRLB bit masks and bit positions */ 4724 #define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ 4725 #define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ 4726 #define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ 4727 #define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ 4728 #define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ 4729 #define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ 4730 4731 #define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ 4732 #define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ 4733 #define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ 4734 #define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ 4735 #define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ 4736 #define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ 4737 4738 #define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ 4739 #define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ 4740 #define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ 4741 #define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ 4742 #define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ 4743 #define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ 4744 4745 #define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ 4746 #define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ 4747 #define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ 4748 #define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ 4749 #define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ 4750 #define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ 4751 4752 /* TC2.CTRLF bit masks and bit positions */ 4753 #define TC2_CMD_gm 0x0C /* Command group mask. */ 4754 #define TC2_CMD_gp 2 /* Command group position. */ 4755 #define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ 4756 #define TC2_CMD0_bp 2 /* Command bit 0 position. */ 4757 #define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ 4758 #define TC2_CMD1_bp 3 /* Command bit 1 position. */ 4759 4760 #define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ 4761 #define TC2_CMDEN_gp 0 /* Command Enable group position. */ 4762 #define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ 4763 #define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ 4764 #define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ 4765 #define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ 4766 4767 /* TC2.INTFLAGS bit masks and bit positions */ 4768 #define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ 4769 #define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ 4770 4771 #define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ 4772 #define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ 4773 4774 #define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ 4775 #define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ 4776 4777 #define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ 4778 #define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ 4779 4780 #define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ 4781 #define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ 4782 4783 #define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ 4784 #define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ 4785 4786 /* AWEX - Timer/Counter Advanced Waveform Extension */ 4787 /* AWEX.CTRL bit masks and bit positions */ 4788 #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ 4789 #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ 4790 4791 #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ 4792 #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ 4793 4794 #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ 4795 #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ 4796 4797 #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ 4798 #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ 4799 4800 #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ 4801 #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ 4802 4803 #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ 4804 #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ 4805 4806 /* AWEX.FDCTRL bit masks and bit positions */ 4807 #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ 4808 #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ 4809 4810 #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ 4811 #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ 4812 4813 #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ 4814 #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ 4815 #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ 4816 #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ 4817 #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ 4818 #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ 4819 4820 /* AWEX.STATUS bit masks and bit positions */ 4821 #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ 4822 #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ 4823 4824 #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ 4825 #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ 4826 4827 #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ 4828 #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ 4829 4830 /* AWEX.STATUSSET bit masks and bit positions */ 4831 /* AWEX_FDF Predefined. */ 4832 /* AWEX_FDF Predefined. */ 4833 4834 /* AWEX_DTHSBUFV Predefined. */ 4835 /* AWEX_DTHSBUFV Predefined. */ 4836 4837 /* AWEX_DTLSBUFV Predefined. */ 4838 /* AWEX_DTLSBUFV Predefined. */ 4839 4840 /* HIRES - Timer/Counter High-Resolution Extension */ 4841 /* HIRES.CTRLA bit masks and bit positions */ 4842 #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ 4843 #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ 4844 #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ 4845 #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ 4846 #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ 4847 #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ 4848 4849 /* USART - Universal Asynchronous Receiver-Transmitter */ 4850 /* USART.STATUS bit masks and bit positions */ 4851 #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ 4852 #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ 4853 4854 #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ 4855 #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ 4856 4857 #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ 4858 #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ 4859 4860 #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ 4861 #define USART_FERR_bp 4 /* Frame Error bit position. */ 4862 4863 #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ 4864 #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ 4865 4866 #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ 4867 #define USART_PERR_bp 2 /* Parity Error bit position. */ 4868 4869 #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ 4870 #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ 4871 4872 /* USART.CTRLA bit masks and bit positions */ 4873 #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ 4874 #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ 4875 #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ 4876 #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ 4877 #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ 4878 #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ 4879 4880 #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ 4881 #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ 4882 #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ 4883 #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ 4884 #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ 4885 #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ 4886 4887 #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ 4888 #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ 4889 #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ 4890 #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ 4891 #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ 4892 #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ 4893 4894 /* USART.CTRLB bit masks and bit positions */ 4895 #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ 4896 #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ 4897 4898 #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ 4899 #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ 4900 4901 #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ 4902 #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ 4903 4904 #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ 4905 #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ 4906 4907 #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ 4908 #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ 4909 4910 /* USART.CTRLC bit masks and bit positions */ 4911 #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ 4912 #define USART_CMODE_gp 6 /* Communication Mode group position. */ 4913 #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ 4914 #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ 4915 #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ 4916 #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ 4917 4918 #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ 4919 #define USART_PMODE_gp 4 /* Parity Mode group position. */ 4920 #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ 4921 #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ 4922 #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ 4923 #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ 4924 4925 #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ 4926 #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ 4927 4928 #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ 4929 #define USART_CHSIZE_gp 0 /* Character Size group position. */ 4930 #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ 4931 #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ 4932 #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ 4933 #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ 4934 #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ 4935 #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ 4936 4937 /* USART.BAUDCTRLA bit masks and bit positions */ 4938 #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ 4939 #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ 4940 #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ 4941 #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ 4942 #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ 4943 #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ 4944 #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ 4945 #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ 4946 #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ 4947 #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ 4948 #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ 4949 #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ 4950 #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ 4951 #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ 4952 #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ 4953 #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ 4954 #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ 4955 #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ 4956 4957 /* USART.BAUDCTRLB bit masks and bit positions */ 4958 #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ 4959 #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ 4960 #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ 4961 #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ 4962 #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ 4963 #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ 4964 #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ 4965 #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ 4966 #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ 4967 #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ 4968 4969 /* USART_BSEL Predefined. */ 4970 /* USART_BSEL Predefined. */ 4971 4972 /* SPI - Serial Peripheral Interface */ 4973 /* SPI.CTRL bit masks and bit positions */ 4974 #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ 4975 #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ 4976 4977 #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ 4978 #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ 4979 4980 #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ 4981 #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ 4982 4983 #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ 4984 #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ 4985 4986 #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ 4987 #define SPI_MODE_gp 2 /* SPI Mode group position. */ 4988 #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ 4989 #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ 4990 #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ 4991 #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ 4992 4993 #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ 4994 #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ 4995 #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ 4996 #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ 4997 #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ 4998 #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ 4999 5000 /* SPI.INTCTRL bit masks and bit positions */ 5001 #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ 5002 #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ 5003 #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 5004 #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 5005 #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 5006 #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 5007 5008 /* SPI.STATUS bit masks and bit positions */ 5009 #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ 5010 #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ 5011 5012 #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ 5013 #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ 5014 5015 /* IRCOM - IR Communication Module */ 5016 /* IRCOM.CTRL bit masks and bit positions */ 5017 #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ 5018 #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ 5019 #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ 5020 #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ 5021 #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ 5022 #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ 5023 #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ 5024 #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ 5025 #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ 5026 #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ 5027 5028 /* FUSE - Fuses and Lockbits */ 5029 /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ 5030 #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ 5031 #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ 5032 #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ 5033 #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ 5034 #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ 5035 #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ 5036 #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ 5037 #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ 5038 #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ 5039 #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ 5040 5041 #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ 5042 #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ 5043 #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ 5044 #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ 5045 #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ 5046 #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ 5047 #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ 5048 #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ 5049 #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ 5050 #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ 5051 5052 /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ 5053 #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ 5054 #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ 5055 5056 #define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ 5057 #define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ 5058 5059 #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ 5060 #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ 5061 #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ 5062 #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ 5063 #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ 5064 #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ 5065 5066 /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ 5067 #define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ 5068 #define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ 5069 5070 #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ 5071 #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ 5072 #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ 5073 #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ 5074 #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ 5075 #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ 5076 5077 #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ 5078 #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ 5079 5080 /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ 5081 #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ 5082 #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ 5083 #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ 5084 #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ 5085 #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ 5086 #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ 5087 5088 #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ 5089 #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ 5090 5091 #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ 5092 #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ 5093 #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ 5094 #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ 5095 #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ 5096 #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ 5097 #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ 5098 #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ 5099 5100 /* LOCKBIT - Fuses and Lockbits */ 5101 /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ 5102 #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 5103 #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 5104 #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 5105 #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 5106 #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 5107 #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 5108 5109 #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 5110 #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 5111 #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 5112 #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 5113 #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 5114 #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 5115 5116 #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 5117 #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 5118 #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 5119 #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 5120 #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 5121 #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 5122 5123 #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ 5124 #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ 5125 #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 5126 #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ 5127 #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 5128 #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ 5129 5130 5131 5132 // Generic Port Pins 5133 5134 #define PIN0_bm 0x01 5135 #define PIN0_bp 0 5136 #define PIN1_bm 0x02 5137 #define PIN1_bp 1 5138 #define PIN2_bm 0x04 5139 #define PIN2_bp 2 5140 #define PIN3_bm 0x08 5141 #define PIN3_bp 3 5142 #define PIN4_bm 0x10 5143 #define PIN4_bp 4 5144 #define PIN5_bm 0x20 5145 #define PIN5_bp 5 5146 #define PIN6_bm 0x40 5147 #define PIN6_bp 6 5148 #define PIN7_bm 0x80 5149 #define PIN7_bp 7 5150 5151 /* ========== Interrupt Vector Definitions ========== */ 5152 /* Vector 0 is the reset vector */ 5153 5154 /* OSC interrupt vectors */ 5155 #define OSC_OSCF_vect_num 1 5156 #define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ 5157 5158 /* PORTC interrupt vectors */ 5159 #define PORTC_INT0_vect_num 2 5160 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ 5161 #define PORTC_INT1_vect_num 3 5162 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ 5163 5164 /* PORTR interrupt vectors */ 5165 #define PORTR_INT0_vect_num 4 5166 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ 5167 #define PORTR_INT1_vect_num 5 5168 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ 5169 5170 /* RTC interrupt vectors */ 5171 #define RTC_OVF_vect_num 10 5172 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ 5173 #define RTC_COMP_vect_num 11 5174 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ 5175 5176 /* TWIC interrupt vectors */ 5177 #define TWIC_TWIS_vect_num 12 5178 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ 5179 #define TWIC_TWIM_vect_num 13 5180 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ 5181 5182 /* TCC0 interrupt vectors */ 5183 #define TCC0_OVF_vect_num 14 5184 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ 5185 5186 /* TCC2 interrupt vectors */ 5187 #define TCC2_LUNF_vect_num 14 5188 #define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ 5189 5190 /* TCC0 interrupt vectors */ 5191 #define TCC0_ERR_vect_num 15 5192 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ 5193 5194 /* TCC2 interrupt vectors */ 5195 #define TCC2_HUNF_vect_num 15 5196 #define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ 5197 5198 /* TCC0 interrupt vectors */ 5199 #define TCC0_CCA_vect_num 16 5200 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ 5201 5202 /* TCC2 interrupt vectors */ 5203 #define TCC2_LCMPA_vect_num 16 5204 #define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ 5205 5206 /* TCC0 interrupt vectors */ 5207 #define TCC0_CCB_vect_num 17 5208 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ 5209 5210 /* TCC2 interrupt vectors */ 5211 #define TCC2_LCMPB_vect_num 17 5212 #define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ 5213 5214 /* TCC0 interrupt vectors */ 5215 #define TCC0_CCC_vect_num 18 5216 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ 5217 5218 /* TCC2 interrupt vectors */ 5219 #define TCC2_LCMPC_vect_num 18 5220 #define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ 5221 5222 /* TCC0 interrupt vectors */ 5223 #define TCC0_CCD_vect_num 19 5224 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ 5225 5226 /* TCC2 interrupt vectors */ 5227 #define TCC2_LCMPD_vect_num 19 5228 #define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ 5229 5230 /* TCC1 interrupt vectors */ 5231 #define TCC1_OVF_vect_num 20 5232 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ 5233 #define TCC1_ERR_vect_num 21 5234 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ 5235 #define TCC1_CCA_vect_num 22 5236 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ 5237 #define TCC1_CCB_vect_num 23 5238 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ 5239 5240 /* SPIC interrupt vectors */ 5241 #define SPIC_INT_vect_num 24 5242 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ 5243 5244 /* USARTC0 interrupt vectors */ 5245 #define USARTC0_RXC_vect_num 25 5246 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ 5247 #define USARTC0_DRE_vect_num 26 5248 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ 5249 #define USARTC0_TXC_vect_num 27 5250 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ 5251 5252 /* NVM interrupt vectors */ 5253 #define NVM_EE_vect_num 32 5254 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ 5255 #define NVM_SPM_vect_num 33 5256 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ 5257 5258 /* PORTB interrupt vectors */ 5259 #define PORTB_INT0_vect_num 34 5260 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ 5261 #define PORTB_INT1_vect_num 35 5262 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ 5263 5264 /* PORTE interrupt vectors */ 5265 #define PORTE_INT0_vect_num 43 5266 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ 5267 #define PORTE_INT1_vect_num 44 5268 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ 5269 5270 /* TWIE interrupt vectors */ 5271 #define TWIE_TWIS_vect_num 45 5272 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ 5273 #define TWIE_TWIM_vect_num 46 5274 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ 5275 5276 /* TCE0 interrupt vectors */ 5277 #define TCE0_OVF_vect_num 47 5278 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ 5279 #define TCE0_ERR_vect_num 48 5280 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ 5281 #define TCE0_CCA_vect_num 49 5282 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ 5283 #define TCE0_CCB_vect_num 50 5284 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ 5285 #define TCE0_CCC_vect_num 51 5286 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ 5287 #define TCE0_CCD_vect_num 52 5288 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ 5289 5290 /* USARTE0 interrupt vectors */ 5291 #define USARTE0_RXC_vect_num 58 5292 #define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ 5293 #define USARTE0_DRE_vect_num 59 5294 #define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ 5295 #define USARTE0_TXC_vect_num 60 5296 #define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ 5297 5298 /* PORTD interrupt vectors */ 5299 #define PORTD_INT0_vect_num 64 5300 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ 5301 #define PORTD_INT1_vect_num 65 5302 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ 5303 5304 /* PORTA interrupt vectors */ 5305 #define PORTA_INT0_vect_num 66 5306 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ 5307 #define PORTA_INT1_vect_num 67 5308 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ 5309 5310 /* ACA interrupt vectors */ 5311 #define ACA_AC0_vect_num 68 5312 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ 5313 #define ACA_AC1_vect_num 69 5314 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ 5315 #define ACA_ACW_vect_num 70 5316 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ 5317 5318 /* ADCA interrupt vectors */ 5319 #define ADCA_CH0_vect_num 71 5320 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ 5321 5322 /* TCD0 interrupt vectors */ 5323 #define TCD0_OVF_vect_num 77 5324 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ 5325 5326 /* TCD2 interrupt vectors */ 5327 #define TCD2_LUNF_vect_num 77 5328 #define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ 5329 5330 /* TCD0 interrupt vectors */ 5331 #define TCD0_ERR_vect_num 78 5332 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ 5333 5334 /* TCD2 interrupt vectors */ 5335 #define TCD2_HUNF_vect_num 78 5336 #define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ 5337 5338 /* TCD0 interrupt vectors */ 5339 #define TCD0_CCA_vect_num 79 5340 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ 5341 5342 /* TCD2 interrupt vectors */ 5343 #define TCD2_LCMPA_vect_num 79 5344 #define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ 5345 5346 /* TCD0 interrupt vectors */ 5347 #define TCD0_CCB_vect_num 80 5348 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ 5349 5350 /* TCD2 interrupt vectors */ 5351 #define TCD2_LCMPB_vect_num 80 5352 #define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ 5353 5354 /* TCD0 interrupt vectors */ 5355 #define TCD0_CCC_vect_num 81 5356 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ 5357 5358 /* TCD2 interrupt vectors */ 5359 #define TCD2_LCMPC_vect_num 81 5360 #define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ 5361 5362 /* TCD0 interrupt vectors */ 5363 #define TCD0_CCD_vect_num 82 5364 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ 5365 5366 /* TCD2 interrupt vectors */ 5367 #define TCD2_LCMPD_vect_num 82 5368 #define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ 5369 5370 /* SPID interrupt vectors */ 5371 #define SPID_INT_vect_num 87 5372 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ 5373 5374 /* USARTD0 interrupt vectors */ 5375 #define USARTD0_RXC_vect_num 88 5376 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ 5377 #define USARTD0_DRE_vect_num 89 5378 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ 5379 #define USARTD0_TXC_vect_num 90 5380 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ 5381 5382 #define _VECTOR_SIZE 4 /* Size of individual vector. */ 5383 #define _VECTORS_SIZE (91 * _VECTOR_SIZE) 5384 5385 5386 /* ========== Constants ========== */ 5387 5388 #define PROGMEM_START (0x0000) 5389 #define PROGMEM_SIZE (139264) 5390 #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) 5391 5392 #define APP_SECTION_START (0x0000) 5393 #define APP_SECTION_SIZE (131072) 5394 #define APP_SECTION_PAGE_SIZE (256) 5395 #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) 5396 5397 #define APPTABLE_SECTION_START (0x1E000) 5398 #define APPTABLE_SECTION_SIZE (8192) 5399 #define APPTABLE_SECTION_PAGE_SIZE (256) 5400 #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) 5401 5402 #define BOOT_SECTION_START (0x20000) 5403 #define BOOT_SECTION_SIZE (8192) 5404 #define BOOT_SECTION_PAGE_SIZE (256) 5405 #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) 5406 5407 #define DATAMEM_START (0x0000) 5408 #define DATAMEM_SIZE (16384) 5409 #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) 5410 5411 #define IO_START (0x0000) 5412 #define IO_SIZE (4096) 5413 #define IO_PAGE_SIZE (0) 5414 #define IO_END (IO_START + IO_SIZE - 1) 5415 5416 #define MAPPED_EEPROM_START (0x1000) 5417 #define MAPPED_EEPROM_SIZE (2048) 5418 #define MAPPED_EEPROM_PAGE_SIZE (0) 5419 #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) 5420 5421 #define INTERNAL_SRAM_START (0x2000) 5422 #define INTERNAL_SRAM_SIZE (8192) 5423 #define INTERNAL_SRAM_PAGE_SIZE (0) 5424 #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) 5425 5426 #define EEPROM_START (0x0000) 5427 #define EEPROM_SIZE (2048) 5428 #define EEPROM_PAGE_SIZE (32) 5429 #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) 5430 5431 #define SIGNATURES_START (0x0000) 5432 #define SIGNATURES_SIZE (3) 5433 #define SIGNATURES_PAGE_SIZE (0) 5434 #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) 5435 5436 #define FUSES_START (0x0000) 5437 #define FUSES_SIZE (6) 5438 #define FUSES_PAGE_SIZE (0) 5439 #define FUSES_END (FUSES_START + FUSES_SIZE - 1) 5440 5441 #define LOCKBITS_START (0x0000) 5442 #define LOCKBITS_SIZE (1) 5443 #define LOCKBITS_PAGE_SIZE (0) 5444 #define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) 5445 5446 #define USER_SIGNATURES_START (0x0000) 5447 #define USER_SIGNATURES_SIZE (256) 5448 #define USER_SIGNATURES_PAGE_SIZE (256) 5449 #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) 5450 5451 #define PROD_SIGNATURES_START (0x0000) 5452 #define PROD_SIGNATURES_SIZE (64) 5453 #define PROD_SIGNATURES_PAGE_SIZE (256) 5454 #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) 5455 5456 #define FLASHSTART PROGMEM_START 5457 #define FLASHEND PROGMEM_END 5458 #define SPM_PAGESIZE 256 5459 #define RAMSTART INTERNAL_SRAM_START 5460 #define RAMSIZE INTERNAL_SRAM_SIZE 5461 #define RAMEND INTERNAL_SRAM_END 5462 #define E2END EEPROM_END 5463 #define E2PAGESIZE EEPROM_PAGE_SIZE 5464 5465 5466 /* ========== Fuses ========== */ 5467 #define FUSE_MEMORY_SIZE 6 5468 5469 /* Fuse Byte 0 Reserved */ 5470 5471 /* Fuse Byte 1 */ 5472 #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ 5473 #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ 5474 #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ 5475 #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ 5476 #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ 5477 #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ 5478 #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ 5479 #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ 5480 #define FUSE1_DEFAULT (0xFF) 5481 5482 /* Fuse Byte 2 */ 5483 #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ 5484 #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ 5485 #define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ 5486 #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ 5487 #define FUSE2_DEFAULT (0xFF) 5488 5489 /* Fuse Byte 3 Reserved */ 5490 5491 /* Fuse Byte 4 */ 5492 #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ 5493 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ 5494 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ 5495 #define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ 5496 #define FUSE4_DEFAULT (0xFF) 5497 5498 /* Fuse Byte 5 */ 5499 #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ 5500 #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ 5501 #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ 5502 #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ 5503 #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ 5504 #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ 5505 #define FUSE5_DEFAULT (0xFF) 5506 5507 /* ========== Lock Bits ========== */ 5508 #define __LOCK_BITS_EXIST 5509 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST 5510 #define __BOOT_LOCK_APPLICATION_BITS_EXIST 5511 #define __BOOT_LOCK_BOOT_BITS_EXIST 5512 5513 /* ========== Signature ========== */ 5514 #define SIGNATURE_0 0x1E 5515 #define SIGNATURE_1 0x97 5516 #define SIGNATURE_2 0x47 5517 5518 /* ========== Power Reduction Condition Definitions ========== */ 5519 5520 /* PR.PRGEN */ 5521 #define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) 5522 #define __AVR_HAVE_PRGEN_RTC 5523 #define __AVR_HAVE_PRGEN_EVSYS 5524 5525 /* PR.PRPA */ 5526 #define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) 5527 #define __AVR_HAVE_PRPA_ADC 5528 #define __AVR_HAVE_PRPA_AC 5529 5530 /* PR.PRPC */ 5531 #define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 5532 #define __AVR_HAVE_PRPC_TWI 5533 #define __AVR_HAVE_PRPC_USART0 5534 #define __AVR_HAVE_PRPC_SPI 5535 #define __AVR_HAVE_PRPC_HIRES 5536 #define __AVR_HAVE_PRPC_TC1 5537 #define __AVR_HAVE_PRPC_TC0 5538 5539 /* PR.PRPD */ 5540 #define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) 5541 #define __AVR_HAVE_PRPD_USART0 5542 #define __AVR_HAVE_PRPD_SPI 5543 #define __AVR_HAVE_PRPD_TC0 5544 5545 /* PR.PRPE */ 5546 #define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) 5547 #define __AVR_HAVE_PRPE_TWI 5548 #define __AVR_HAVE_PRPE_USART0 5549 #define __AVR_HAVE_PRPE_TC0 5550 5551 /* PR.PRPF */ 5552 #define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) 5553 #define __AVR_HAVE_PRPF_USART0 5554 #define __AVR_HAVE_PRPF_TC0 5555 5556 5557 #endif /* #ifdef _AVR_ATXMEGA128D4_H_INCLUDED */ 5558 5559