1;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
2;***** Created: 2005-01-11 10:30 ******* Source: ATmega161.xml ***********
3;*************************************************************************
4;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
5;*
6;* Number            : AVR000
7;* File Name         : "m161def.inc"
8;* Title             : Register/Bit Definitions for the ATmega161
9;* Date              : 2005-01-11
10;* Version           : 2.14
11;* Support E-mail    : avr@atmel.com
12;* Target MCU        : ATmega161
13;*
14;* DESCRIPTION
15;* When including this file in the assembly program file, all I/O register
16;* names and I/O register bit names appearing in the data book can be used.
17;* In addition, the six registers forming the three data pointers X, Y and
18;* Z have been assigned names XL - ZH. Highest RAM address for Internal
19;* SRAM is also defined
20;*
21;* The Register names are represented by their hexadecimal address.
22;*
23;* The Register Bit names are represented by their bit number (0-7).
24;*
25;* Please observe the difference in using the bit names with instructions
26;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
27;* (skip if bit in register set/cleared). The following example illustrates
28;* this:
29;*
30;* in    r16,PORTB             ;read PORTB latch
31;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
32;* out   PORTB,r16             ;output to PORTB
33;*
34;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
35;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
36;* rjmp  TOV0_is_set           ;jump if set
37;* ...                         ;otherwise do something else
38;*************************************************************************
39
40#ifndef _M161DEF_INC_
41#define _M161DEF_INC_
42
43
44#pragma partinc 0
45
46; ***** SPECIFY DEVICE ***************************************************
47.device ATmega161
48#pragma AVRPART ADMIN PART_NAME ATmega161
49.equ	SIGNATURE_000	= 0x1e
50.equ	SIGNATURE_001	= 0x94
51.equ	SIGNATURE_002	= 0x01
52
53#pragma AVRPART CORE CORE_VERSION V2E
54
55
56; ***** I/O REGISTER DEFINITIONS *****************************************
57; NOTE:
58; Definitions marked "MEMORY MAPPED"are extended I/O ports
59; and cannot be used with IN/OUT instructions
60.equ	SREG	= 0x3f
61.equ	SPH	= 0x3e
62.equ	SPL	= 0x3d
63.equ	GIMSK	= 0x3b
64.equ	GIFR	= 0x3a
65.equ	TIMSK	= 0x39
66.equ	TIFR	= 0x38
67.equ	SPMCR	= 0x37
68.equ	EMCUCR	= 0x36
69.equ	MCUCR	= 0x35
70.equ	MCUSR	= 0x34
71.equ	TCCR0	= 0x33
72.equ	TCNT0	= 0x32
73.equ	OCR0	= 0x31
74.equ	SFIOR	= 0x30
75.equ	TCCR1A	= 0x2f
76.equ	TCCR1B	= 0x2e
77.equ	TCNT1H	= 0x2d
78.equ	TCNT1L	= 0x2c
79.equ	OCR1AH	= 0x2b
80.equ	OCR1AL	= 0x2a
81.equ	OCR1BH	= 0x29
82.equ	OCR1BL	= 0x28
83.equ	TCCR2	= 0x27
84.equ	ASSR	= 0x26
85.equ	ICR1H	= 0x25
86.equ	ICR1L	= 0x24
87.equ	TCNT2	= 0x23
88.equ	OCR2	= 0x22
89.equ	WDTCR	= 0x21
90.equ	UBRRHI	= 0x20
91.equ	EEARH	= 0x1f
92.equ	EEARL	= 0x1e
93.equ	EEDR	= 0x1d
94.equ	EECR	= 0x1c
95.equ	PORTA	= 0x1b
96.equ	DDRA	= 0x1a
97.equ	PINA	= 0x19
98.equ	PORTB	= 0x18
99.equ	DDRB	= 0x17
100.equ	PINB	= 0x16
101.equ	PORTC	= 0x15
102.equ	DDRC	= 0x14
103.equ	PINC	= 0x13
104.equ	PORTD	= 0x12
105.equ	DDRD	= 0x11
106.equ	PIND	= 0x10
107.equ	SPDR	= 0x0f
108.equ	SPSR	= 0x0e
109.equ	SPCR	= 0x0d
110.equ	UDR0	= 0x0c
111.equ	UCSR0A	= 0x0b
112.equ	UCSR0B	= 0x0a
113.equ	UBRR0	= 0x09
114.equ	ACSR	= 0x08
115.equ	PORTE	= 0x07
116.equ	DDRE	= 0x06
117.equ	PINE	= 0x05
118.equ	UDR1	= 0x03
119.equ	UCSR1A	= 0x02
120.equ	UCSR1B	= 0x01
121.equ	UBRR1	= 0x00
122
123
124; ***** BIT DEFINITIONS **************************************************
125
126; ***** ANALOG_COMPARATOR ************
127; ACSR - Analog Comparator Control And Status Register
128.equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
129.equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
130.equ	ACIC	= 2	; Analog Comparator Input Capture Enable
131.equ	ACIE	= 3	; Analog Comparator Interrupt Enable
132.equ	ACI	= 4	; Analog Comparator Interrupt Flag
133.equ	ACO	= 5	; Analog Compare Output
134.equ	AINBG	= 6	; Analog Comparator Bandgap Select
135.equ	ACD	= 7	; Analog Comparator Disable
136
137
138; ***** SPI **************************
139; SPDR - SPI Data Register
140.equ	SPDR0	= 0	; SPI Data Register bit 0
141.equ	SPDR1	= 1	; SPI Data Register bit 1
142.equ	SPDR2	= 2	; SPI Data Register bit 2
143.equ	SPDR3	= 3	; SPI Data Register bit 3
144.equ	SPDR4	= 4	; SPI Data Register bit 4
145.equ	SPDR5	= 5	; SPI Data Register bit 5
146.equ	SPDR6	= 6	; SPI Data Register bit 6
147.equ	SPDR7	= 7	; SPI Data Register bit 7
148
149; SPSR - SPI Status Register
150.equ	SPI2X	= 0	; Double SPI Speed Bit
151.equ	WCOL	= 6	; Write Collision Flag
152.equ	SPIF	= 7	; SPI Interrupt Flag
153
154; SPCR - SPI Control Register
155.equ	SPR0	= 0	; SPI Clock Rate Select 0
156.equ	SPR1	= 1	; SPI Clock Rate Select 1
157.equ	CPHA	= 2	; Clock Phase
158.equ	CPOL	= 3	; Clock polarity
159.equ	MSTR	= 4	; Master/Slave Select
160.equ	DORD	= 5	; Data Order
161.equ	SPE	= 6	; SPI Enable
162.equ	SPIE	= 7	; SPI Interrupt Enable
163
164
165; ***** USART0 ***********************
166; UDR0 - USART I/O Data Register
167.equ	UDR00	= 0	; USART I/O Data Register bit 0
168.equ	UDR01	= 1	; USART I/O Data Register bit 1
169.equ	UDR02	= 2	; USART I/O Data Register bit 2
170.equ	UDR03	= 3	; USART I/O Data Register bit 3
171.equ	UDR04	= 4	; USART I/O Data Register bit 4
172.equ	UDR05	= 5	; USART I/O Data Register bit 5
173.equ	UDR06	= 6	; USART I/O Data Register bit 6
174.equ	UDR07	= 7	; USART I/O Data Register bit 7
175
176; UCSR0A - USART Control and Status Register A
177.equ	MPCM0	= 0	; Multi-processor Communication Mode
178.equ	U2X0	= 1	; Double the USART transmission speed
179.equ	OR0	= 3	; Data overRun
180.equ	FE0	= 4	; Framing Error
181.equ	UDRE0	= 5	; USART Data Register Empty
182.equ	TXC0	= 6	; USART Transmitt Complete
183.equ	RXC0	= 7	; USART Receive Complete
184
185; UCSR0B - USART Control and Status Register B
186.equ	TXB80	= 0	; Transmit Data Bit 8
187.equ	RXB80	= 1	; Receive Data Bit 8
188.equ	CHR90	= 2	; 9-Bit Character
189.equ	TXEN0	= 3	; Transmitter Enable
190.equ	RXEN0	= 4	; Receiver Enable
191.equ	UDR0IE0	= 5	; USART Data register Empty Interrupt Enable
192.equ	TXCIE0	= 6	; TX Complete Interrupt Enable
193.equ	RXCIE0	= 7	; RX Complete Interrupt Enable
194
195; UBRR0 - USART Baud Rate Register Byte
196.equ	UBRR00	= 0	; USART Baud Rate Register bit 0
197.equ	UBRR01	= 1	; USART Baud Rate Register bit 1
198.equ	UBRR02	= 2	; USART Baud Rate Register bit 2
199.equ	UBRR03	= 3	; USART Baud Rate Register bit 3
200.equ	UBRR04	= 4	; USART Baud Rate Register bit 4
201.equ	UBRR05	= 5	; USART Baud Rate Register bit 5
202.equ	UBRR06	= 6	; USART Baud Rate Register bit 6
203.equ	UBRR07	= 7	; USART Baud Rate Register bit 7
204
205; UBRRHI - High Byte Baud Rate Register
206.equ	UBRRHI00	= 0	; High Byte Baud Rate Register Port 0 Bit 0
207.equ	UBRRHI01	= 1	; High Byte Baud Rate Register Port 0 Bit 1
208.equ	UBRRHI02	= 2	; High Byte Baud Rate Register Port 0 Bit 2
209.equ	UBRRHI03	= 3	; High Byte Baud Rate Register Port 0 Bit 3
210
211
212; ***** USART1 ***********************
213; UDR1 - USART I/O Data Register
214.equ	UDR10	= 0	; USART I/O Data Register bit 0
215.equ	UDR11	= 1	; USART I/O Data Register bit 1
216.equ	UDR12	= 2	; USART I/O Data Register bit 2
217.equ	UDR13	= 3	; USART I/O Data Register bit 3
218.equ	UDR14	= 4	; USART I/O Data Register bit 4
219.equ	UDR15	= 5	; USART I/O Data Register bit 5
220.equ	UDR16	= 6	; USART I/O Data Register bit 6
221.equ	UDR17	= 7	; USART I/O Data Register bit 7
222
223; UCSR1A - USART Control and Status Register A
224.equ	MPCM1	= 0	; Multi-processor Communication Mode
225.equ	U2X1	= 1	; Double the USART transmission speed
226.equ	OR1	= 3	; Data overRun
227.equ	FE1	= 4	; Framing Error
228.equ	UDRE1	= 5	; USART Data Register Empty
229.equ	TXC1	= 6	; USART Transmitt Complete
230.equ	RXC1	= 7	; USART Receive Complete
231
232; UCSR1B - USART Control and Status Register B
233.equ	TXB81	= 0	; Transmit Data Bit 8
234.equ	RXB81	= 1	; Receive Data Bit 8
235.equ	CHR91	= 2	; 9-Bit Character
236.equ	TXEN1	= 3	; Transmitter Enable
237.equ	RXEN1	= 4	; Receiver Enable
238.equ	UDR1IE1	= 5	; USART Data register Empty Interrupt Enable
239.equ	TXCIE1	= 6	; TX Complete Interrupt Enable
240.equ	RXCIE1	= 7	; RX Complete Interrupt Enable
241
242; UBRR1 - USART Baud Rate Register Byte
243.equ	UBRR10	= 0	; USART Baud Rate Register bit 0
244.equ	UBRR11	= 1	; USART Baud Rate Register bit 1
245.equ	UBRR12	= 2	; USART Baud Rate Register bit 2
246.equ	UBRR13	= 3	; USART Baud Rate Register bit 3
247.equ	UBRR14	= 4	; USART Baud Rate Register bit 4
248.equ	UBRR15	= 5	; USART Baud Rate Register bit 5
249.equ	UBRR16	= 6	; USART Baud Rate Register bit 6
250.equ	UBRR17	= 7	; USART Baud Rate Register bit 7
251
252; UBRRHI - high Byte Baud Rate Register
253.equ	UBRRHI10	= 4	; High Byte Baud Rate Register Port 0 Bit 0
254.equ	UBRRHI11	= 5	; High Byte Baud Rate Register Port 0 Bit 1
255.equ	UBRRHI12	= 6	; High Byte Baud Rate Register Port 0 Bit 2
256.equ	UBRRHI13	= 7	; High Byte Baud Rate Register Port 0 Bit 3
257
258
259; ***** PORTA ************************
260; PORTA - Port A Data Register
261.equ	PORTA0	= 0	; Port A Data Register bit 0
262.equ	PA0	= 0	; For compatibility
263.equ	PORTA1	= 1	; Port A Data Register bit 1
264.equ	PA1	= 1	; For compatibility
265.equ	PORTA2	= 2	; Port A Data Register bit 2
266.equ	PA2	= 2	; For compatibility
267.equ	PORTA3	= 3	; Port A Data Register bit 3
268.equ	PA3	= 3	; For compatibility
269.equ	PORTA4	= 4	; Port A Data Register bit 4
270.equ	PA4	= 4	; For compatibility
271.equ	PORTA5	= 5	; Port A Data Register bit 5
272.equ	PA5	= 5	; For compatibility
273.equ	PORTA6	= 6	; Port A Data Register bit 6
274.equ	PA6	= 6	; For compatibility
275.equ	PORTA7	= 7	; Port A Data Register bit 7
276.equ	PA7	= 7	; For compatibility
277
278; DDRA - Port A Data Direction Register
279.equ	DDA0	= 0	; Data Direction Register, Port A, bit 0
280.equ	DDA1	= 1	; Data Direction Register, Port A, bit 1
281.equ	DDA2	= 2	; Data Direction Register, Port A, bit 2
282.equ	DDA3	= 3	; Data Direction Register, Port A, bit 3
283.equ	DDA4	= 4	; Data Direction Register, Port A, bit 4
284.equ	DDA5	= 5	; Data Direction Register, Port A, bit 5
285.equ	DDA6	= 6	; Data Direction Register, Port A, bit 6
286.equ	DDA7	= 7	; Data Direction Register, Port A, bit 7
287
288; PINA - Port A Input Pins
289.equ	PINA0	= 0	; Input Pins, Port A bit 0
290.equ	PINA1	= 1	; Input Pins, Port A bit 1
291.equ	PINA2	= 2	; Input Pins, Port A bit 2
292.equ	PINA3	= 3	; Input Pins, Port A bit 3
293.equ	PINA4	= 4	; Input Pins, Port A bit 4
294.equ	PINA5	= 5	; Input Pins, Port A bit 5
295.equ	PINA6	= 6	; Input Pins, Port A bit 6
296.equ	PINA7	= 7	; Input Pins, Port A bit 7
297
298
299; ***** PORTB ************************
300; PORTB - Port B Data Register
301.equ	PORTB0	= 0	; Port B Data Register bit 0
302.equ	PB0	= 0	; For compatibility
303.equ	PORTB1	= 1	; Port B Data Register bit 1
304.equ	PB1	= 1	; For compatibility
305.equ	PORTB2	= 2	; Port B Data Register bit 2
306.equ	PB2	= 2	; For compatibility
307.equ	PORTB3	= 3	; Port B Data Register bit 3
308.equ	PB3	= 3	; For compatibility
309.equ	PORTB4	= 4	; Port B Data Register bit 4
310.equ	PB4	= 4	; For compatibility
311.equ	PORTB5	= 5	; Port B Data Register bit 5
312.equ	PB5	= 5	; For compatibility
313.equ	PORTB6	= 6	; Port B Data Register bit 6
314.equ	PB6	= 6	; For compatibility
315.equ	PORTB7	= 7	; Port B Data Register bit 7
316.equ	PB7	= 7	; For compatibility
317
318; DDRB - Port B Data Direction Register
319.equ	DDB0	= 0	; Port B Data Direction Register bit 0
320.equ	DDB1	= 1	; Port B Data Direction Register bit 1
321.equ	DDB2	= 2	; Port B Data Direction Register bit 2
322.equ	DDB3	= 3	; Port B Data Direction Register bit 3
323.equ	DDB4	= 4	; Port B Data Direction Register bit 4
324.equ	DDB5	= 5	; Port B Data Direction Register bit 5
325.equ	DDB6	= 6	; Port B Data Direction Register bit 6
326.equ	DDB7	= 7	; Port B Data Direction Register bit 7
327
328; PINB - Port B Input Pins
329.equ	PINB0	= 0	; Port B Input Pins bit 0
330.equ	PINB1	= 1	; Port B Input Pins bit 1
331.equ	PINB2	= 2	; Port B Input Pins bit 2
332.equ	PINB3	= 3	; Port B Input Pins bit 3
333.equ	PINB4	= 4	; Port B Input Pins bit 4
334.equ	PINB5	= 5	; Port B Input Pins bit 5
335.equ	PINB6	= 6	; Port B Input Pins bit 6
336.equ	PINB7	= 7	; Port B Input Pins bit 7
337
338
339; ***** PORTC ************************
340; PORTC - Port C Data Register
341.equ	PORTC0	= 0	; Port C Data Register bit 0
342.equ	PC0	= 0	; For compatibility
343.equ	PORTC1	= 1	; Port C Data Register bit 1
344.equ	PC1	= 1	; For compatibility
345.equ	PORTC2	= 2	; Port C Data Register bit 2
346.equ	PC2	= 2	; For compatibility
347.equ	PORTC3	= 3	; Port C Data Register bit 3
348.equ	PC3	= 3	; For compatibility
349.equ	PORTC4	= 4	; Port C Data Register bit 4
350.equ	PC4	= 4	; For compatibility
351.equ	PORTC5	= 5	; Port C Data Register bit 5
352.equ	PC5	= 5	; For compatibility
353.equ	PORTC6	= 6	; Port C Data Register bit 6
354.equ	PC6	= 6	; For compatibility
355.equ	PORTC7	= 7	; Port C Data Register bit 7
356.equ	PC7	= 7	; For compatibility
357
358; DDRC - Port C Data Direction Register
359.equ	DDC0	= 0	; Port C Data Direction Register bit 0
360.equ	DDC1	= 1	; Port C Data Direction Register bit 1
361.equ	DDC2	= 2	; Port C Data Direction Register bit 2
362.equ	DDC3	= 3	; Port C Data Direction Register bit 3
363.equ	DDC4	= 4	; Port C Data Direction Register bit 4
364.equ	DDC5	= 5	; Port C Data Direction Register bit 5
365.equ	DDC6	= 6	; Port C Data Direction Register bit 6
366.equ	DDC7	= 7	; Port C Data Direction Register bit 7
367
368; PINC - Port C Input Pins
369.equ	PINC0	= 0	; Port C Input Pins bit 0
370.equ	PINC1	= 1	; Port C Input Pins bit 1
371.equ	PINC2	= 2	; Port C Input Pins bit 2
372.equ	PINC3	= 3	; Port C Input Pins bit 3
373.equ	PINC4	= 4	; Port C Input Pins bit 4
374.equ	PINC5	= 5	; Port C Input Pins bit 5
375.equ	PINC6	= 6	; Port C Input Pins bit 6
376.equ	PINC7	= 7	; Port C Input Pins bit 7
377
378
379; ***** PORTD ************************
380; PORTD - Port D Data Register
381.equ	PORTD0	= 0	; Port D Data Register bit 0
382.equ	PD0	= 0	; For compatibility
383.equ	PORTD1	= 1	; Port D Data Register bit 1
384.equ	PD1	= 1	; For compatibility
385.equ	PORTD2	= 2	; Port D Data Register bit 2
386.equ	PD2	= 2	; For compatibility
387.equ	PORTD3	= 3	; Port D Data Register bit 3
388.equ	PD3	= 3	; For compatibility
389.equ	PORTD4	= 4	; Port D Data Register bit 4
390.equ	PD4	= 4	; For compatibility
391.equ	PORTD5	= 5	; Port D Data Register bit 5
392.equ	PD5	= 5	; For compatibility
393.equ	PORTD6	= 6	; Port D Data Register bit 6
394.equ	PD6	= 6	; For compatibility
395.equ	PORTD7	= 7	; Port D Data Register bit 7
396.equ	PD7	= 7	; For compatibility
397
398; DDRD - Port D Data Direction Register
399.equ	DDD0	= 0	; Port D Data Direction Register bit 0
400.equ	DDD1	= 1	; Port D Data Direction Register bit 1
401.equ	DDD2	= 2	; Port D Data Direction Register bit 2
402.equ	DDD3	= 3	; Port D Data Direction Register bit 3
403.equ	DDD4	= 4	; Port D Data Direction Register bit 4
404.equ	DDD5	= 5	; Port D Data Direction Register bit 5
405.equ	DDD6	= 6	; Port D Data Direction Register bit 6
406.equ	DDD7	= 7	; Port D Data Direction Register bit 7
407
408; PIND - Port D Input Pins
409.equ	PIND0	= 0	; Port D Input Pins bit 0
410.equ	PIND1	= 1	; Port D Input Pins bit 1
411.equ	PIND2	= 2	; Port D Input Pins bit 2
412.equ	PIND3	= 3	; Port D Input Pins bit 3
413.equ	PIND4	= 4	; Port D Input Pins bit 4
414.equ	PIND5	= 5	; Port D Input Pins bit 5
415.equ	PIND6	= 6	; Port D Input Pins bit 6
416.equ	PIND7	= 7	; Port D Input Pins bit 7
417
418
419; ***** PORTE ************************
420; PORTE - Port E Data Register
421.equ	PORTE0	= 0	;
422.equ	PE0	= 0	; For compatibility
423.equ	PORTE1	= 1	;
424.equ	PE1	= 1	; For compatibility
425.equ	PORTE2	= 2	;
426.equ	PE2	= 2	; For compatibility
427
428; DDRE - Port E Data Direction Register
429.equ	DDE0	= 0	;
430.equ	DDE1	= 1	;
431.equ	DDE2	= 2	;
432
433; PINE - Port E Input Pins
434.equ	PINE0	= 0	;
435.equ	PINE1	= 1	;
436.equ	PINE2	= 2	;
437
438
439; ***** EEPROM ***********************
440; EEDR - EEPROM Data Register
441.equ	EEDR0	= 0	; EEPROM Data Register bit 0
442.equ	EEDR1	= 1	; EEPROM Data Register bit 1
443.equ	EEDR2	= 2	; EEPROM Data Register bit 2
444.equ	EEDR3	= 3	; EEPROM Data Register bit 3
445.equ	EEDR4	= 4	; EEPROM Data Register bit 4
446.equ	EEDR5	= 5	; EEPROM Data Register bit 5
447.equ	EEDR6	= 6	; EEPROM Data Register bit 6
448.equ	EEDR7	= 7	; EEPROM Data Register bit 7
449
450; EECR - EEPROM Control Register
451.equ	EERE	= 0	; EEPROM Read Enable
452.equ	EEWE	= 1	; EEPROM Write Enable
453.equ	EEMWE	= 2	; EEPROM Master Write Enable
454.equ	EEWEE	= EEMWE	; For compatibility
455.equ	EERIE	= 3	; EEPROM Ready Interrupt Enable
456
457
458; ***** EXTERNAL_INTERRUPT ***********
459; GIMSK - General Interrupt Mask Register
460.equ	INT2	= 5	; External Interrupt Request 2 Enable
461.equ	INT0	= 6	; External Interrupt Request 0 Enable
462.equ	INT1	= 7	; External Interrupt Request 1 Enable
463
464; GIFR - General Interrupt Flag Register
465.equ	INTF2	= 5	; External Interrupt Flag 2
466.equ	INTF0	= 6	; External Interrupt Flag 0
467.equ	INTF1	= 7	; External Interrupt Flag 1
468
469
470; ***** CPU **************************
471; SREG - Status Register
472.equ	SREG_C	= 0	; Carry Flag
473.equ	SREG_Z	= 1	; Zero Flag
474.equ	SREG_N	= 2	; Negative Flag
475.equ	SREG_V	= 3	; Two's Complement Overflow Flag
476.equ	SREG_S	= 4	; Sign Bit
477.equ	SREG_H	= 5	; Half Carry Flag
478.equ	SREG_T	= 6	; Bit Copy Storage
479.equ	SREG_I	= 7	; Global Interrupt Enable
480
481; MCUCR - MCU Control Register
482.equ	ISC00	= 0	; Interrupt Sense Control 0 bit 0
483.equ	ISC01	= 1	; Interrupt Sense Control 0 bit 1
484.equ	ISC10	= 2	; Interrupt Sense Control 1 bit 1
485.equ	ISC11	= 3	; Interrupt Sense Control 1 bit 1
486.equ	SM1	= 4	; Sleep Mode Select
487.equ	SE	= 5	; Sleep Enable
488.equ	SRW10	= 6	; External SRAM Wait State Select
489.equ	SRE	= 7	; External SRAM Enable
490
491; MCUSR - MCU Status Register
492.equ	PORF	= 0	; Power-on reset flag
493.equ	EXTRF	= 1	; External Reset Flag
494.equ	BORF	= 2	; Brown-out Reset Flag
495.equ	WDRF	= 3	; Watchdog Reset Flag
496
497; EMCUCR - Extended MCU Control Register
498.equ	ISC2	= 0	; Interrupt Sense Control 2
499.equ	SRW11	= 1	; Wait State Select Bit 1 for Upper Sector
500.equ	SRW00	= 2	; Wait State Select Bit 0 for Lower Sector
501.equ	SRW01	= 3	; Wait State Select Bit 1 for Lower Sector
502.equ	SRL0	= 4	; Wait State Sector Limit Bit 0
503.equ	SRL1	= 5	; Wait State Sector Limit Bit 1
504.equ	SRL2	= 6	; Wait State Sector Limit Bit 2
505.equ	SM0	= 7	; Sleep mode Select Bit 0
506
507; SPMCR - Store Program Memory Control Register
508.equ	SPMEN	= 0	; Store Program Memory Enable
509.equ	PGERS	= 1	; Page Erase
510.equ	PGWRT	= 2	; Page Write
511.equ	BLBSET	= 3	; Boot Lock Bit Set
512
513
514; ***** TIMER_COUNTER_0 **************
515; TCCR0 - Timer/Counter Control Register
516.equ	CS00	= 0	; Clock Select 1
517.equ	CS01	= 1	; Clock Select 1
518.equ	CS02	= 2	; Clock Select 2
519.equ	WGM01	= 3	; Waveform Generation Mode 1
520.equ	COM00	= 4	; Compare match Output Mode 0
521.equ	COM01	= 5	; Compare Match Output Mode 1
522.equ	WGM00	= 6	; Waveform Generation Mode 0
523.equ	FOC0	= 7	; Force Output Compare
524
525; TCNT0 - Timer/Counter Register
526.equ	TCNT0_0	= 0	;
527.equ	TCNT0_1	= 1	;
528.equ	TCNT0_2	= 2	;
529.equ	TCNT0_3	= 3	;
530.equ	TCNT0_4	= 4	;
531.equ	TCNT0_5	= 5	;
532.equ	TCNT0_6	= 6	;
533.equ	TCNT0_7	= 7	;
534
535; OCR0 - Output Compare Register
536.equ	OCR0_0	= 0	;
537.equ	OCR0_1	= 1	;
538.equ	OCR0_2	= 2	;
539.equ	OCR0_3	= 3	;
540.equ	OCR0_4	= 4	;
541.equ	OCR0_5	= 5	;
542.equ	OCR0_6	= 6	;
543.equ	OCR0_7	= 7	;
544
545; TIMSK - Timer/Counter Interrupt Mask Register
546.equ	OCIE0	= 0	; Timer/Counter0 Output Compare Match Interrupt register
547.equ	TOIE0	= 1	; Timer/Counter0 Overflow Interrupt Enable
548
549; TIFR - Timer/Counter Interrupt Flag register
550.equ	OCF0	= 0	; Output Compare Flag 0
551.equ	TOV0	= 1	; Timer/Counter0 Overflow Flag
552
553; SFIOR - Special Function IO Register
554.equ	PSR10	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
555
556
557; ***** TIMER_COUNTER_2 **************
558; TIMSK - Timer/Counter Interrupt Mask register
559.equ	OCIE2	= 2	; Timer/Counter2 Output Compare Match Interrupt Enable
560.equ	TOIE2	= 4	; Timer/Counter2 Overflow Interrupt Enable
561
562; TIFR - Timer/Counter Interrupt Flag Register
563.equ	OCF2	= 2	; Output Compare Flag 2
564.equ	TOV2	= 4	; Timer/Counter2 Overflow Flag
565
566; TCCR2 - Timer/Counter2 Control Register
567.equ	CS20	= 0	; Clock Select bit 0
568.equ	CS21	= 1	; Clock Select bit 1
569.equ	CS22	= 2	; Clock Select bit 2
570.equ	CTC2	= 3	; Clear Timer/Counter2 on Compare Match
571.equ	COM20	= 4	; Compare Output Mode bit 0
572.equ	COM21	= 5	; Compare Output Mode bit 1
573.equ	PWM2	= 6	; Pulse Width Modulator Enable
574.equ	FOC2	= 7	; Force Output Compare
575
576; TCNT2 - Timer/Counter2
577.equ	TCNT2_0	= 0	; Timer/Counter 2 bit 0
578.equ	TCNT2_1	= 1	; Timer/Counter 2 bit 1
579.equ	TCNT2_2	= 2	; Timer/Counter 2 bit 2
580.equ	TCNT2_3	= 3	; Timer/Counter 2 bit 3
581.equ	TCNT2_4	= 4	; Timer/Counter 2 bit 4
582.equ	TCNT2_5	= 5	; Timer/Counter 2 bit 5
583.equ	TCNT2_6	= 6	; Timer/Counter 2 bit 6
584.equ	TCNT2_7	= 7	; Timer/Counter 2 bit 7
585
586; OCR2 - Timer/Counter2 Output Compare Register
587.equ	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
588.equ	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
589.equ	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
590.equ	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
591.equ	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
592.equ	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
593.equ	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
594.equ	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
595
596; ASSR - Asynchronous Status Register
597.equ	TCR2UB	= 0	; Timer/counter Control Register2 Update Busy
598.equ	OCR2UB	= 1	; Output Compare Register2 Update Busy
599.equ	TCN2UB	= 2	; Timer/Counter2 Update Busy
600.equ	AS2	= 3	; Asynchronous Timer/counter2
601
602; SFIOR - Specil Function IO Register
603.equ	PSR2	= 1	; Prescaler Reset Timer/Counter2
604
605
606; ***** TIMER_COUNTER_1 **************
607; TIMSK - Timer/Counter Interrupt Mask Register
608.equ	TICIE1	= 3	; Timer/Counter1 Input Capture Interrupt Enable
609.equ	OCIE1B	= 5	; Timer/Counter1 Output CompareB Match Interrupt Enable
610.equ	OCIE1A	= 6	; Timer/Counter1 Output CompareA Match Interrupt Enable
611.equ	TOIE1	= 7	; Timer/Counter1 Overflow Interrupt Enable
612
613; TIFR - Timer/Counter Interrupt Flag register
614.equ	ICF1	= 3	; Input Capture Flag 1
615.equ	OCF1B	= 5	; Output Compare Flag 1B
616.equ	OCF1A	= 6	; Output Compare Flag 1A
617.equ	TOV1	= 7	; Timer/Counter1 Overflow Flag
618
619; TCCR1A - Timer/Counter1 Control Register A
620.equ	WGM10	= 0	; Waveform Generation Mode
621.equ	WGM11	= 1	; Waveform Generation Mode
622.equ	FOC1B	= 2	; Force Output Compare 1B
623.equ	FOC1A	= 3	; Force Output Compare 1A
624.equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0
625.equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
626.equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
627.equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
628
629; TCCR1B - Timer/Counter1 Control Register B
630.equ	CS10	= 0	; Prescaler source of Timer/Counter 1
631.equ	CS11	= 1	; Prescaler source of Timer/Counter 1
632.equ	CS12	= 2	; Prescaler source of Timer/Counter 1
633.equ	CTC1	= 3	; Clear Timer/Counter1 on Compare Match
634.equ	ICES1	= 6	; Input Capture 1 Edge Select
635.equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
636
637
638; ***** WATCHDOG *********************
639; WDTCR - Watchdog Timer Control Register
640.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
641.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
642.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
643.equ	WDE	= 3	; Watch Dog Enable
644.equ	WDTOE	= 4	; RW
645.equ	WDDE	= WDTOE	; For compatibility
646
647
648
649; ***** LOCKSBITS ********************************************************
650.equ	LB1	= 0	; Lock bit
651.equ	LB2	= 1	; Lock bit
652.equ	BLB01	= 2	; Boot Lock bit
653.equ	BLB02	= 3	; Boot Lock bit
654.equ	BLB11	= 4	; Boot lock bit
655.equ	BLB12	= 5	; Boot lock bit
656
657
658; ***** FUSES ************************************************************
659; LOW fuse bits
660.equ	CKSEL0	= 0	; Select Clock Source
661.equ	CKSEL1	= 1	; Select Clock Source
662.equ	CKSEL2	= 2	; Select Clock Source
663.equ	SUT	= 3	; Start-up time
664.equ	SPIEN	= 4	; Serial program downloading (SPI) enabled
665.equ	BOOTRST	= 5	; Boot Reset Vector Enabled
666
667; HIGH fuse bits
668
669; EXTENDED fuse bits
670
671
672
673; ***** CPU REGISTER DEFINITIONS *****************************************
674.def	XH	= r27
675.def	XL	= r26
676.def	YH	= r29
677.def	YL	= r28
678.def	ZH	= r31
679.def	ZL	= r30
680
681
682
683; ***** DATA MEMORY DECLARATIONS *****************************************
684.equ	FLASHEND	= 0x1fff	; Note: Word address
685.equ	IOEND	= 0x003f
686.equ	SRAM_START	= 0x0060
687.equ	SRAM_SIZE	= 1024
688.equ	RAMEND	= 0x045f
689.equ	XRAMEND	= 0xfbff
690.equ	E2END	= 0x01ff
691.equ	EEPROMEND	= 0x01ff
692.equ	EEADRBITS	= 9
693#pragma AVRPART MEMORY PROG_FLASH 16384
694#pragma AVRPART MEMORY EEPROM 512
695#pragma AVRPART MEMORY INT_SRAM SIZE 1024
696#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
697
698
699
700; ***** BOOTLOADER DECLARATIONS ******************************************
701.equ	NRWW_START_ADDR	= 0x0
702.equ	NRWW_STOP_ADDR	= 0x1fff
703.equ	PAGESIZE	= 64
704.equ	FIRSTBOOTSTART	= 0x1e00
705
706
707
708; ***** INTERRUPT VECTORS ************************************************
709.equ	INT0addr	= 0x0002	; External Interrupt 0
710.equ	INT1addr	= 0x0004	; External Interrupt 1
711.equ	INT2addr	= 0x0006	; External Interrupt 2
712.equ	OC2addr	= 0x0008	; Timer/Counter2 Compare Match
713.equ	OVF2addr	= 0x000a	; Timer/Counter2 Overflow
714.equ	ICP1addr	= 0x000c	; Timer/Counter1 Capture Event
715.equ	OC1Aaddr	= 0x000e	; Timer/Counter1 Compare Match A
716.equ	OC1Baddr	= 0x0010	; Timer/Counter1 Compare Match B
717.equ	OVF1addr	= 0x0012	; Timer/Counter1 Overflow
718.equ	OC0addr	= 0x0014	; Timer/Counter0 Compare Match
719.equ	OVF0addr	= 0x0016	; Timer/Counter0 Overflow
720.equ	SPIaddr	= 0x0018	; Serial Transfer Complete
721.equ	URXC0addr	= 0x001a	; UART0, Rx Complete
722.equ	URXC1addr	= 0x001c	; UART1, Rx Complete
723.equ	UDRE0addr	= 0x001e	; UART0 Data Register Empty
724.equ	UDRE1addr	= 0x0020	; UART1 Data Register Empty
725.equ	UTXC0addr	= 0x0022	; UART0, Tx Complete
726.equ	UTXC1addr	= 0x0024	; UART1, Tx Complete
727.equ	ERDYaddr	= 0x0026	; EEPROM Ready
728.equ	ACIaddr	= 0x0028	; Analog Comparator
729
730.equ	INT_VECTORS_SIZE	= 42	; size in words
731
732#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
733
734#endif  /* _M161DEF_INC_ */
735
736; ***** END OF FILE ******************************************************
737