1@c Copyright (C) 1991-2021 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@c man end 5 6@ifset GENERIC 7@page 8@node i386-Dependent 9@chapter 80386 Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter 80386 Dependent Features 14@end ifclear 15 16@cindex i386 support 17@cindex i80386 support 18@cindex x86-64 support 19 20The i386 version @code{@value{AS}} supports both the original Intel 386 21architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture 22extending the Intel architecture to 64-bits. 23 24@menu 25* i386-Options:: Options 26* i386-Directives:: X86 specific directives 27* i386-Syntax:: Syntactical considerations 28* i386-Mnemonics:: Instruction Naming 29* i386-Regs:: Register Naming 30* i386-Prefixes:: Instruction Prefixes 31* i386-Memory:: Memory References 32* i386-Jumps:: Handling of Jump Instructions 33* i386-Float:: Floating Point 34* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 35* i386-LWP:: AMD's Lightweight Profiling Instructions 36* i386-BMI:: Bit Manipulation Instruction 37* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 38* i386-16bit:: Writing 16-bit Code 39* i386-Arch:: Specifying an x86 CPU architecture 40* i386-ISA:: AMD64 ISA vs. Intel64 ISA 41* i386-Bugs:: AT&T Syntax bugs 42* i386-Notes:: Notes 43@end menu 44 45@node i386-Options 46@section Options 47 48@cindex options for i386 49@cindex options for x86-64 50@cindex i386 options 51@cindex x86-64 options 52 53The i386 version of @code{@value{AS}} has a few machine 54dependent options: 55 56@c man begin OPTIONS 57@table @gcctabopt 58@cindex @samp{--32} option, i386 59@cindex @samp{--32} option, x86-64 60@cindex @samp{--x32} option, i386 61@cindex @samp{--x32} option, x86-64 62@cindex @samp{--64} option, i386 63@cindex @samp{--64} option, x86-64 64@item --32 | --x32 | --64 65Select the word size, either 32 bits or 64 bits. @samp{--32} 66implies Intel i386 architecture, while @samp{--x32} and @samp{--64} 67imply AMD x86-64 architecture with 32-bit or 64-bit word-size 68respectively. 69 70These options are only available with the ELF object file format, and 71require that the necessary BFD support has been included (on a 32-bit 72platform you have to add --enable-64-bit-bfd to configure enable 64-bit 73usage and use x86-64 as target platform). 74 75@item -n 76By default, x86 GAS replaces multiple nop instructions used for 77alignment within code sections with multi-byte nop instructions such 78as leal 0(%esi,1),%esi. This switch disables the optimization if a single 79byte nop (0x90) is explicitly specified as the fill byte for alignment. 80 81@cindex @samp{--divide} option, i386 82@item --divide 83On SVR4-derived platforms, the character @samp{/} is treated as a comment 84character, which means that it cannot be used in expressions. The 85@samp{--divide} option turns @samp{/} into a normal character. This does 86not disable @samp{/} at the beginning of a line starting a comment, or 87affect using @samp{#} for starting a comment. 88 89@cindex @samp{-march=} option, i386 90@cindex @samp{-march=} option, x86-64 91@item -march=@var{CPU}[+@var{EXTENSION}@dots{}] 92This option specifies the target processor. The assembler will 93issue an error message if an attempt is made to assemble an instruction 94which will not execute on the target processor. The following 95processor names are recognized: 96@code{i8086}, 97@code{i186}, 98@code{i286}, 99@code{i386}, 100@code{i486}, 101@code{i586}, 102@code{i686}, 103@code{pentium}, 104@code{pentiumpro}, 105@code{pentiumii}, 106@code{pentiumiii}, 107@code{pentium4}, 108@code{prescott}, 109@code{nocona}, 110@code{core}, 111@code{core2}, 112@code{corei7}, 113@code{l1om}, 114@code{k1om}, 115@code{iamcu}, 116@code{k6}, 117@code{k6_2}, 118@code{athlon}, 119@code{opteron}, 120@code{k8}, 121@code{amdfam10}, 122@code{bdver1}, 123@code{bdver2}, 124@code{bdver3}, 125@code{bdver4}, 126@code{znver1}, 127@code{znver2}, 128@code{znver3}, 129@code{btver1}, 130@code{btver2}, 131@code{generic32} and 132@code{generic64}. 133 134In addition to the basic instruction set, the assembler can be told to 135accept various extension mnemonics. For example, 136@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and 137@var{vmx}. The following extensions are currently supported: 138@code{8087}, 139@code{287}, 140@code{387}, 141@code{687}, 142@code{no87}, 143@code{no287}, 144@code{no387}, 145@code{no687}, 146@code{cmov}, 147@code{nocmov}, 148@code{fxsr}, 149@code{nofxsr}, 150@code{mmx}, 151@code{nommx}, 152@code{sse}, 153@code{sse2}, 154@code{sse3}, 155@code{sse4a}, 156@code{ssse3}, 157@code{sse4.1}, 158@code{sse4.2}, 159@code{sse4}, 160@code{nosse}, 161@code{nosse2}, 162@code{nosse3}, 163@code{nosse4a}, 164@code{nossse3}, 165@code{nosse4.1}, 166@code{nosse4.2}, 167@code{nosse4}, 168@code{avx}, 169@code{avx2}, 170@code{noavx}, 171@code{noavx2}, 172@code{adx}, 173@code{rdseed}, 174@code{prfchw}, 175@code{smap}, 176@code{mpx}, 177@code{sha}, 178@code{rdpid}, 179@code{ptwrite}, 180@code{cet}, 181@code{gfni}, 182@code{vaes}, 183@code{vpclmulqdq}, 184@code{prefetchwt1}, 185@code{clflushopt}, 186@code{se1}, 187@code{clwb}, 188@code{movdiri}, 189@code{movdir64b}, 190@code{enqcmd}, 191@code{serialize}, 192@code{tsxldtrk}, 193@code{kl}, 194@code{nokl}, 195@code{widekl}, 196@code{nowidekl}, 197@code{hreset}, 198@code{avx512f}, 199@code{avx512cd}, 200@code{avx512er}, 201@code{avx512pf}, 202@code{avx512vl}, 203@code{avx512bw}, 204@code{avx512dq}, 205@code{avx512ifma}, 206@code{avx512vbmi}, 207@code{avx512_4fmaps}, 208@code{avx512_4vnniw}, 209@code{avx512_vpopcntdq}, 210@code{avx512_vbmi2}, 211@code{avx512_vnni}, 212@code{avx512_bitalg}, 213@code{avx512_vp2intersect}, 214@code{tdx}, 215@code{avx512_bf16}, 216@code{avx_vnni}, 217@code{noavx512f}, 218@code{noavx512cd}, 219@code{noavx512er}, 220@code{noavx512pf}, 221@code{noavx512vl}, 222@code{noavx512bw}, 223@code{noavx512dq}, 224@code{noavx512ifma}, 225@code{noavx512vbmi}, 226@code{noavx512_4fmaps}, 227@code{noavx512_4vnniw}, 228@code{noavx512_vpopcntdq}, 229@code{noavx512_vbmi2}, 230@code{noavx512_vnni}, 231@code{noavx512_bitalg}, 232@code{noavx512_vp2intersect}, 233@code{notdx}, 234@code{noavx512_bf16}, 235@code{noavx_vnni}, 236@code{noenqcmd}, 237@code{noserialize}, 238@code{notsxldtrk}, 239@code{amx_int8}, 240@code{noamx_int8}, 241@code{amx_bf16}, 242@code{noamx_bf16}, 243@code{amx_tile}, 244@code{noamx_tile}, 245@code{nouintr}, 246@code{nohreset}, 247@code{vmx}, 248@code{vmfunc}, 249@code{smx}, 250@code{xsave}, 251@code{xsaveopt}, 252@code{xsavec}, 253@code{xsaves}, 254@code{aes}, 255@code{pclmul}, 256@code{fsgsbase}, 257@code{rdrnd}, 258@code{f16c}, 259@code{bmi2}, 260@code{fma}, 261@code{movbe}, 262@code{ept}, 263@code{lzcnt}, 264@code{popcnt}, 265@code{hle}, 266@code{rtm}, 267@code{invpcid}, 268@code{clflush}, 269@code{mwaitx}, 270@code{clzero}, 271@code{wbnoinvd}, 272@code{pconfig}, 273@code{waitpkg}, 274@code{uintr}, 275@code{cldemote}, 276@code{rdpru}, 277@code{mcommit}, 278@code{sev_es}, 279@code{lwp}, 280@code{fma4}, 281@code{xop}, 282@code{cx16}, 283@code{syscall}, 284@code{rdtscp}, 285@code{3dnow}, 286@code{3dnowa}, 287@code{sse4a}, 288@code{sse5}, 289@code{snp}, 290@code{invlpgb}, 291@code{tlbsync}, 292@code{svme} and 293@code{padlock}. 294Note that rather than extending a basic instruction set, the extension 295mnemonics starting with @code{no} revoke the respective functionality. 296 297When the @code{.arch} directive is used with @option{-march}, the 298@code{.arch} directive will take precedent. 299 300@cindex @samp{-mtune=} option, i386 301@cindex @samp{-mtune=} option, x86-64 302@item -mtune=@var{CPU} 303This option specifies a processor to optimize for. When used in 304conjunction with the @option{-march} option, only instructions 305of the processor specified by the @option{-march} option will be 306generated. 307 308Valid @var{CPU} values are identical to the processor list of 309@option{-march=@var{CPU}}. 310 311@cindex @samp{-msse2avx} option, i386 312@cindex @samp{-msse2avx} option, x86-64 313@item -msse2avx 314This option specifies that the assembler should encode SSE instructions 315with VEX prefix. 316 317@cindex @samp{-msse-check=} option, i386 318@cindex @samp{-msse-check=} option, x86-64 319@item -msse-check=@var{none} 320@itemx -msse-check=@var{warning} 321@itemx -msse-check=@var{error} 322These options control if the assembler should check SSE instructions. 323@option{-msse-check=@var{none}} will make the assembler not to check SSE 324instructions, which is the default. @option{-msse-check=@var{warning}} 325will make the assembler issue a warning for any SSE instruction. 326@option{-msse-check=@var{error}} will make the assembler issue an error 327for any SSE instruction. 328 329@cindex @samp{-mavxscalar=} option, i386 330@cindex @samp{-mavxscalar=} option, x86-64 331@item -mavxscalar=@var{128} 332@itemx -mavxscalar=@var{256} 333These options control how the assembler should encode scalar AVX 334instructions. @option{-mavxscalar=@var{128}} will encode scalar 335AVX instructions with 128bit vector length, which is the default. 336@option{-mavxscalar=@var{256}} will encode scalar AVX instructions 337with 256bit vector length. 338 339WARNING: Don't use this for production code - due to CPU errata the 340resulting code may not work on certain models. 341 342@cindex @samp{-mvexwig=} option, i386 343@cindex @samp{-mvexwig=} option, x86-64 344@item -mvexwig=@var{0} 345@itemx -mvexwig=@var{1} 346These options control how the assembler should encode VEX.W-ignored (WIG) 347VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX 348instructions with vex.w = 0, which is the default. 349@option{-mvexwig=@var{1}} will encode WIG EVEX instructions with 350vex.w = 1. 351 352WARNING: Don't use this for production code - due to CPU errata the 353resulting code may not work on certain models. 354 355@cindex @samp{-mevexlig=} option, i386 356@cindex @samp{-mevexlig=} option, x86-64 357@item -mevexlig=@var{128} 358@itemx -mevexlig=@var{256} 359@itemx -mevexlig=@var{512} 360These options control how the assembler should encode length-ignored 361(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG 362EVEX instructions with 128bit vector length, which is the default. 363@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will 364encode LIG EVEX instructions with 256bit and 512bit vector length, 365respectively. 366 367@cindex @samp{-mevexwig=} option, i386 368@cindex @samp{-mevexwig=} option, x86-64 369@item -mevexwig=@var{0} 370@itemx -mevexwig=@var{1} 371These options control how the assembler should encode w-ignored (WIG) 372EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG 373EVEX instructions with evex.w = 0, which is the default. 374@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with 375evex.w = 1. 376 377@cindex @samp{-mmnemonic=} option, i386 378@cindex @samp{-mmnemonic=} option, x86-64 379@item -mmnemonic=@var{att} 380@itemx -mmnemonic=@var{intel} 381This option specifies instruction mnemonic for matching instructions. 382The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will 383take precedent. 384 385@cindex @samp{-msyntax=} option, i386 386@cindex @samp{-msyntax=} option, x86-64 387@item -msyntax=@var{att} 388@itemx -msyntax=@var{intel} 389This option specifies instruction syntax when processing instructions. 390The @code{.att_syntax} and @code{.intel_syntax} directives will 391take precedent. 392 393@cindex @samp{-mnaked-reg} option, i386 394@cindex @samp{-mnaked-reg} option, x86-64 395@item -mnaked-reg 396This option specifies that registers don't require a @samp{%} prefix. 397The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. 398 399@cindex @samp{-madd-bnd-prefix} option, i386 400@cindex @samp{-madd-bnd-prefix} option, x86-64 401@item -madd-bnd-prefix 402This option forces the assembler to add BND prefix to all branches, even 403if such prefix was not explicitly specified in the source code. 404 405@cindex @samp{-mshared} option, i386 406@cindex @samp{-mshared} option, x86-64 407@item -mno-shared 408On ELF target, the assembler normally optimizes out non-PLT relocations 409against defined non-weak global branch targets with default visibility. 410The @samp{-mshared} option tells the assembler to generate code which 411may go into a shared library where all non-weak global branch targets 412with default visibility can be preempted. The resulting code is 413slightly bigger. This option only affects the handling of branch 414instructions. 415 416@cindex @samp{-mbig-obj} option, i386 417@cindex @samp{-mbig-obj} option, x86-64 418@item -mbig-obj 419On PE/COFF target this option forces the use of big object file 420format, which allows more than 32768 sections. 421 422@cindex @samp{-momit-lock-prefix=} option, i386 423@cindex @samp{-momit-lock-prefix=} option, x86-64 424@item -momit-lock-prefix=@var{no} 425@itemx -momit-lock-prefix=@var{yes} 426These options control how the assembler should encode lock prefix. 427This option is intended as a workaround for processors, that fail on 428lock prefix. This option can only be safely used with single-core, 429single-thread computers 430@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. 431@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, 432which is the default. 433 434@cindex @samp{-mfence-as-lock-add=} option, i386 435@cindex @samp{-mfence-as-lock-add=} option, x86-64 436@item -mfence-as-lock-add=@var{no} 437@itemx -mfence-as-lock-add=@var{yes} 438These options control how the assembler should encode lfence, mfence and 439sfence. 440@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and 441sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and 442@samp{lock addl $0x0, (%esp)} in 32-bit mode. 443@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and 444sfence as usual, which is the default. 445 446@cindex @samp{-mrelax-relocations=} option, i386 447@cindex @samp{-mrelax-relocations=} option, x86-64 448@item -mrelax-relocations=@var{no} 449@itemx -mrelax-relocations=@var{yes} 450These options control whether the assembler should generate relax 451relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and 452R_X86_64_REX_GOTPCRELX, in 64-bit mode. 453@option{-mrelax-relocations=@var{yes}} will generate relax relocations. 454@option{-mrelax-relocations=@var{no}} will not generate relax 455relocations. The default can be controlled by a configure option 456@option{--enable-x86-relax-relocations}. 457 458@cindex @samp{-malign-branch-boundary=} option, i386 459@cindex @samp{-malign-branch-boundary=} option, x86-64 460@item -malign-branch-boundary=@var{NUM} 461This option controls how the assembler should align branches with segment 462prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or 463no less than 16. Branches will be aligned within @var{NUM} byte 464boundary. @option{-malign-branch-boundary=0}, which is the default, 465doesn't align branches. 466 467@cindex @samp{-malign-branch=} option, i386 468@cindex @samp{-malign-branch=} option, x86-64 469@item -malign-branch=@var{TYPE}[+@var{TYPE}...] 470This option specifies types of branches to align. @var{TYPE} is 471combination of @samp{jcc}, which aligns conditional jumps, 472@samp{fused}, which aligns fused conditional jumps, @samp{jmp}, 473which aligns unconditional jumps, @samp{call} which aligns calls, 474@samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect 475jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}. 476 477@cindex @samp{-malign-branch-prefix-size=} option, i386 478@cindex @samp{-malign-branch-prefix-size=} option, x86-64 479@item -malign-branch-prefix-size=@var{NUM} 480This option specifies the maximum number of prefixes on an instruction 481to align branches. @var{NUM} should be between 0 and 5. The default 482@var{NUM} is 5. 483 484@cindex @samp{-mbranches-within-32B-boundaries} option, i386 485@cindex @samp{-mbranches-within-32B-boundaries} option, x86-64 486@item -mbranches-within-32B-boundaries 487This option aligns conditional jumps, fused conditional jumps and 488unconditional jumps within 32 byte boundary with up to 5 segment prefixes 489on an instruction. It is equivalent to 490@option{-malign-branch-boundary=32} 491@option{-malign-branch=jcc+fused+jmp} 492@option{-malign-branch-prefix-size=5}. 493The default doesn't align branches. 494 495@cindex @samp{-mlfence-after-load=} option, i386 496@cindex @samp{-mlfence-after-load=} option, x86-64 497@item -mlfence-after-load=@var{no} 498@itemx -mlfence-after-load=@var{yes} 499These options control whether the assembler should generate lfence 500after load instructions. @option{-mlfence-after-load=@var{yes}} will 501generate lfence. @option{-mlfence-after-load=@var{no}} will not generate 502lfence, which is the default. 503 504@cindex @samp{-mlfence-before-indirect-branch=} option, i386 505@cindex @samp{-mlfence-before-indirect-branch=} option, x86-64 506@item -mlfence-before-indirect-branch=@var{none} 507@item -mlfence-before-indirect-branch=@var{all} 508@item -mlfence-before-indirect-branch=@var{register} 509@itemx -mlfence-before-indirect-branch=@var{memory} 510These options control whether the assembler should generate lfence 511before indirect near branch instructions. 512@option{-mlfence-before-indirect-branch=@var{all}} will generate lfence 513before indirect near branch via register and issue a warning before 514indirect near branch via memory. 515It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when 516there's no explicit @option{-mlfence-before-ret=}. 517@option{-mlfence-before-indirect-branch=@var{register}} will generate 518lfence before indirect near branch via register. 519@option{-mlfence-before-indirect-branch=@var{memory}} will issue a 520warning before indirect near branch via memory. 521@option{-mlfence-before-indirect-branch=@var{none}} will not generate 522lfence nor issue warning, which is the default. Note that lfence won't 523be generated before indirect near branch via register with 524@option{-mlfence-after-load=@var{yes}} since lfence will be generated 525after loading branch target register. 526 527@cindex @samp{-mlfence-before-ret=} option, i386 528@cindex @samp{-mlfence-before-ret=} option, x86-64 529@item -mlfence-before-ret=@var{none} 530@item -mlfence-before-ret=@var{shl} 531@item -mlfence-before-ret=@var{or} 532@item -mlfence-before-ret=@var{yes} 533@itemx -mlfence-before-ret=@var{not} 534These options control whether the assembler should generate lfence 535before ret. @option{-mlfence-before-ret=@var{or}} will generate 536generate or instruction with lfence. 537@option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction 538with lfence. @option{-mlfence-before-ret=@var{not}} will generate not 539instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not 540generate lfence, which is the default. 541 542@cindex @samp{-mx86-used-note=} option, i386 543@cindex @samp{-mx86-used-note=} option, x86-64 544@item -mx86-used-note=@var{no} 545@itemx -mx86-used-note=@var{yes} 546These options control whether the assembler should generate 547GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED 548GNU property notes. The default can be controlled by the 549@option{--enable-x86-used-note} configure option. 550 551@cindex @samp{-mevexrcig=} option, i386 552@cindex @samp{-mevexrcig=} option, x86-64 553@item -mevexrcig=@var{rne} 554@itemx -mevexrcig=@var{rd} 555@itemx -mevexrcig=@var{ru} 556@itemx -mevexrcig=@var{rz} 557These options control how the assembler should encode SAE-only 558EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits 559of EVEX instruction with 00, which is the default. 560@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} 561and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions 562with 01, 10 and 11 RC bits, respectively. 563 564@cindex @samp{-mamd64} option, x86-64 565@cindex @samp{-mintel64} option, x86-64 566@item -mamd64 567@itemx -mintel64 568This option specifies that the assembler should accept only AMD64 or 569Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 570only and AMD64 ISAs. 571 572@cindex @samp{-O0} option, i386 573@cindex @samp{-O0} option, x86-64 574@cindex @samp{-O} option, i386 575@cindex @samp{-O} option, x86-64 576@cindex @samp{-O1} option, i386 577@cindex @samp{-O1} option, x86-64 578@cindex @samp{-O2} option, i386 579@cindex @samp{-O2} option, x86-64 580@cindex @samp{-Os} option, i386 581@cindex @samp{-Os} option, x86-64 582@item -O0 | -O | -O1 | -O2 | -Os 583Optimize instruction encoding with smaller instruction size. @samp{-O} 584and @samp{-O1} encode 64-bit register load instructions with 64-bit 585immediate as 32-bit register load instructions with 31-bit or 32-bits 586immediates, encode 64-bit register clearing instructions with 32-bit 587register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector 588register clearing instructions with 128-bit VEX vector register 589clearing instructions, encode 128-bit/256-bit EVEX vector 590register load/store instructions with VEX vector register load/store 591instructions, and encode 128-bit/256-bit EVEX packed integer logical 592instructions with 128-bit/256-bit VEX packed integer logical. 593 594@samp{-O2} includes @samp{-O1} optimization plus encodes 595256-bit/512-bit EVEX vector register clearing instructions with 128-bit 596EVEX vector register clearing instructions. In 64-bit mode VEX encoded 597instructions with commutative source operands will also have their 598source operands swapped if this allows using the 2-byte VEX prefix form 599instead of the 3-byte one. Certain forms of AND as well as OR with the 600same (register) operand specified twice will also be changed to TEST. 601 602@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit 603and 64-bit register tests with immediate as 8-bit register test with 604immediate. @samp{-O0} turns off this optimization. 605 606@end table 607@c man end 608 609@node i386-Directives 610@section x86 specific Directives 611 612@cindex machine directives, x86 613@cindex x86 machine directives 614@table @code 615 616@cindex @code{lcomm} directive, COFF 617@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] 618Reserve @var{length} (an absolute expression) bytes for a local common 619denoted by @var{symbol}. The section and value of @var{symbol} are 620those of the new local common. The addresses are allocated in the bss 621section, so that at run-time the bytes start off zeroed. Since 622@var{symbol} is not declared global, it is normally not visible to 623@code{@value{LD}}. The optional third parameter, @var{alignment}, 624specifies the desired alignment of the symbol in the bss section. 625 626This directive is only available for COFF based x86 targets. 627 628@cindex @code{largecomm} directive, ELF 629@item .largecomm @var{symbol} , @var{length}[, @var{alignment}] 630This directive behaves in the same way as the @code{comm} directive 631except that the data is placed into the @var{.lbss} section instead of 632the @var{.bss} section @ref{Comm}. 633 634The directive is intended to be used for data which requires a large 635amount of space, and it is only available for ELF based x86_64 636targets. 637 638@cindex @code{value} directive 639@item .value @var{expression} [, @var{expression}] 640This directive behaves in the same way as the @code{.short} directive, 641taking a series of comma separated expressions and storing them as 642two-byte wide values into the current section. 643 644@c FIXME: Document other x86 specific directives ? Eg: .code16gcc, 645 646@end table 647 648@node i386-Syntax 649@section i386 Syntactical Considerations 650@menu 651* i386-Variations:: AT&T Syntax versus Intel Syntax 652* i386-Chars:: Special Characters 653@end menu 654 655@node i386-Variations 656@subsection AT&T Syntax versus Intel Syntax 657 658@cindex i386 intel_syntax pseudo op 659@cindex intel_syntax pseudo op, i386 660@cindex i386 att_syntax pseudo op 661@cindex att_syntax pseudo op, i386 662@cindex i386 syntax compatibility 663@cindex syntax compatibility, i386 664@cindex x86-64 intel_syntax pseudo op 665@cindex intel_syntax pseudo op, x86-64 666@cindex x86-64 att_syntax pseudo op 667@cindex att_syntax pseudo op, x86-64 668@cindex x86-64 syntax compatibility 669@cindex syntax compatibility, x86-64 670 671@code{@value{AS}} now supports assembly using Intel assembler syntax. 672@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches 673back to the usual AT&T mode for compatibility with the output of 674@code{@value{GCC}}. Either of these directives may have an optional 675argument, @code{prefix}, or @code{noprefix} specifying whether registers 676require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite 677different from Intel syntax. We mention these differences because 678almost all 80386 documents use Intel syntax. Notable differences 679between the two syntaxes are: 680 681@cindex immediate operands, i386 682@cindex i386 immediate operands 683@cindex register operands, i386 684@cindex i386 register operands 685@cindex jump/call operands, i386 686@cindex i386 jump/call operands 687@cindex operand delimiters, i386 688 689@cindex immediate operands, x86-64 690@cindex x86-64 immediate operands 691@cindex register operands, x86-64 692@cindex x86-64 register operands 693@cindex jump/call operands, x86-64 694@cindex x86-64 jump/call operands 695@cindex operand delimiters, x86-64 696@itemize @bullet 697@item 698AT&T immediate operands are preceded by @samp{$}; Intel immediate 699operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 700AT&T register operands are preceded by @samp{%}; Intel register operands 701are undelimited. AT&T absolute (as opposed to PC relative) jump/call 702operands are prefixed by @samp{*}; they are undelimited in Intel syntax. 703 704@cindex i386 source, destination operands 705@cindex source, destination operands; i386 706@cindex x86-64 source, destination operands 707@cindex source, destination operands; x86-64 708@item 709AT&T and Intel syntax use the opposite order for source and destination 710operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 711@samp{source, dest} convention is maintained for compatibility with 712previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and 713instructions with 2 immediate operands, such as the @samp{enter} 714instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. 715 716@cindex mnemonic suffixes, i386 717@cindex sizes operands, i386 718@cindex i386 size suffixes 719@cindex mnemonic suffixes, x86-64 720@cindex sizes operands, x86-64 721@cindex x86-64 size suffixes 722@item 723In AT&T syntax the size of memory operands is determined from the last 724character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 725@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long 726(32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes 727of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm 728(256-bit vector) and zmm (512-bit vector) memory references, only when there's 729no other way to disambiguate an instruction. Intel syntax accomplishes this by 730prefixing memory operands (@emph{not} the instruction mnemonics) with 731@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr}, 732@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel 733syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T 734syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and 735@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references. 736 737In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} 738instruction with the 64-bit displacement or immediate operand. 739 740@cindex return instructions, i386 741@cindex i386 jump, call, return 742@cindex return instructions, x86-64 743@cindex x86-64 jump, call, return 744@item 745Immediate form long jumps and calls are 746@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 747Intel syntax is 748@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 749instruction 750is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 751@samp{ret far @var{stack-adjust}}. 752 753@cindex sections, i386 754@cindex i386 sections 755@cindex sections, x86-64 756@cindex x86-64 sections 757@item 758The AT&T assembler does not provide support for multiple section 759programs. Unix style systems expect all programs to be single sections. 760@end itemize 761 762@node i386-Chars 763@subsection Special Characters 764 765@cindex line comment character, i386 766@cindex i386 line comment character 767The presence of a @samp{#} appearing anywhere on a line indicates the 768start of a comment that extends to the end of that line. 769 770If a @samp{#} appears as the first character of a line then the whole 771line is treated as a comment, but in this case the line can also be a 772logical line number directive (@pxref{Comments}) or a preprocessor 773control command (@pxref{Preprocessing}). 774 775If the @option{--divide} command-line option has not been specified 776then the @samp{/} character appearing anywhere on a line also 777introduces a line comment. 778 779@cindex line separator, i386 780@cindex statement separator, i386 781@cindex i386 line separator 782The @samp{;} character can be used to separate statements on the same 783line. 784 785@node i386-Mnemonics 786@section i386-Mnemonics 787@subsection Instruction Naming 788 789@cindex i386 instruction naming 790@cindex instruction naming, i386 791@cindex x86-64 instruction naming 792@cindex instruction naming, x86-64 793 794Instruction mnemonics are suffixed with one character modifiers which 795specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} 796and @samp{q} specify byte, word, long and quadruple word operands. If 797no suffix is specified by an instruction then @code{@value{AS}} tries to 798fill in the missing suffix based on the destination register operand 799(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent 800to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to 801@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix 802assembler which assumes that a missing mnemonic suffix implies long 803operand size. (This incompatibility does not affect compiler output 804since compilers always explicitly specify the mnemonic suffix.) 805 806When there is no sizing suffix and no (suitable) register operands to 807deduce the size of memory operands, with a few exceptions and where long 808operand size is possible in the first place, operand size will default 809to long in 32- and 64-bit modes. Similarly it will default to short in 81016-bit mode. Noteworthy exceptions are 811 812@itemize @bullet 813@item 814Instructions with an implicit on-stack operand as well as branches, 815which default to quad in 64-bit mode. 816 817@item 818Sign- and zero-extending moves, which default to byte size source 819operands. 820 821@item 822Floating point insns with integer operands, which default to short (for 823perhaps historical reasons). 824 825@item 826CRC32 with a 64-bit destination, which defaults to a quad source 827operand. 828 829@end itemize 830 831@cindex encoding options, i386 832@cindex encoding options, x86-64 833 834Different encoding options can be specified via pseudo prefixes: 835 836@itemize @bullet 837@item 838@samp{@{disp8@}} -- prefer 8-bit displacement. 839 840@item 841@samp{@{disp32@}} -- prefer 32-bit displacement. 842 843@item 844@samp{@{disp16@}} -- prefer 16-bit displacement. 845 846@item 847@samp{@{load@}} -- prefer load-form instruction. 848 849@item 850@samp{@{store@}} -- prefer store-form instruction. 851 852@item 853@samp{@{vex@}} -- encode with VEX prefix. 854 855@item 856@samp{@{vex3@}} -- encode with 3-byte VEX prefix. 857 858@item 859@samp{@{evex@}} -- encode with EVEX prefix. 860 861@item 862@samp{@{rex@}} -- prefer REX prefix for integer and legacy vector 863instructions (x86-64 only). Note that this differs from the @samp{rex} 864prefix which generates REX prefix unconditionally. 865 866@item 867@samp{@{nooptimize@}} -- disable instruction size optimization. 868@end itemize 869 870Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix 871by default. The pseudo @samp{@{vex@}} prefix can be used to encode 872mnemonics of Intel VNNI instructions with the VEX prefix. 873 874@cindex conversion instructions, i386 875@cindex i386 conversion instructions 876@cindex conversion instructions, x86-64 877@cindex x86-64 conversion instructions 878The Intel-syntax conversion instructions 879 880@itemize @bullet 881@item 882@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 883 884@item 885@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 886 887@item 888@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 889 890@item 891@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 892 893@item 894@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} 895(x86-64 only), 896 897@item 898@samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in 899@samp{%rdx:%rax} (x86-64 only), 900@end itemize 901 902@noindent 903are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and 904@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these 905instructions. 906 907@cindex extension instructions, i386 908@cindex i386 extension instructions 909@cindex extension instructions, x86-64 910@cindex x86-64 extension instructions 911The Intel-syntax extension instructions 912 913@itemize @bullet 914@item 915@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}. 916 917@item 918@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}. 919 920@item 921@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64} 922(x86-64 only). 923 924@item 925@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32} 926 927@item 928@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64} 929(x86-64 only). 930 931@item 932@samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64} 933(x86-64 only). 934 935@item 936@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}. 937 938@item 939@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}. 940 941@item 942@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64} 943(x86-64 only). 944 945@item 946@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32} 947 948@item 949@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64} 950(x86-64 only). 951@end itemize 952 953@noindent 954are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx}, 955@samp{movsbq/movsxb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw}, 956@samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx}, 957@samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx}, 958@samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax. 959 960@cindex jump instructions, i386 961@cindex call instructions, i386 962@cindex jump instructions, x86-64 963@cindex call instructions, x86-64 964Far call/jump instructions are @samp{lcall} and @samp{ljmp} in 965AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 966convention. 967 968@subsection AT&T Mnemonic versus Intel Mnemonic 969 970@cindex i386 mnemonic compatibility 971@cindex mnemonic compatibility, i386 972 973@code{@value{AS}} supports assembly using Intel mnemonic. 974@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and 975@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T 976syntax for compatibility with the output of @code{@value{GCC}}. 977Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, 978@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, 979@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 980assembler with different mnemonics from those in Intel IA32 specification. 981@code{@value{GCC}} generates those instructions with AT&T mnemonic. 982 983@itemize @bullet 984@item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination 985register. @samp{movsxd} should be used to encode 16-bit or 32-bit 986destination register with both AT&T and Intel mnemonics. 987@end itemize 988 989@node i386-Regs 990@section Register Naming 991 992@cindex i386 registers 993@cindex registers, i386 994@cindex x86-64 registers 995@cindex registers, x86-64 996Register operands are always prefixed with @samp{%}. The 80386 registers 997consist of 998 999@itemize @bullet 1000@item 1001the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 1002@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 1003frame pointer), and @samp{%esp} (the stack pointer). 1004 1005@item 1006the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 1007@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 1008 1009@item 1010the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 1011@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 1012are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 1013@samp{%cx}, and @samp{%dx}) 1014 1015@item 1016the 6 section registers @samp{%cs} (code section), @samp{%ds} 1017(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 1018and @samp{%gs}. 1019 1020@item 1021the 5 processor control registers @samp{%cr0}, @samp{%cr2}, 1022@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. 1023 1024@item 1025the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 1026@samp{%db3}, @samp{%db6}, and @samp{%db7}. 1027 1028@item 1029the 2 test registers @samp{%tr6} and @samp{%tr7}. 1030 1031@item 1032the 8 floating point register stack @samp{%st} or equivalently 1033@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 1034@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 1035These registers are overloaded by 8 MMX registers @samp{%mm0}, 1036@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, 1037@samp{%mm6} and @samp{%mm7}. 1038 1039@item 1040the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, 1041@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. 1042@end itemize 1043 1044The AMD x86-64 architecture extends the register set by: 1045 1046@itemize @bullet 1047@item 1048enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the 1049accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, 1050@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack 1051pointer) 1052 1053@item 1054the 8 extended registers @samp{%r8}--@samp{%r15}. 1055 1056@item 1057the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. 1058 1059@item 1060the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. 1061 1062@item 1063the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. 1064 1065@item 1066the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. 1067 1068@item 1069the 8 debug registers: @samp{%db8}--@samp{%db15}. 1070 1071@item 1072the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. 1073@end itemize 1074 1075With the AVX extensions more registers were made available: 1076 1077@itemize @bullet 1078 1079@item 1080the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 1081available in 32-bit mode). The bottom 128 bits are overlaid with the 1082@samp{xmm0}--@samp{xmm15} registers. 1083 1084@end itemize 1085 1086The AVX512 extensions added the following registers: 1087 1088@itemize @bullet 1089 1090@item 1091the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 1092available in 32-bit mode). The bottom 128 bits are overlaid with the 1093@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are 1094overlaid with the @samp{%ymm0}--@samp{%ymm31} registers. 1095 1096@item 1097the 8 mask registers @samp{%k0}--@samp{%k7}. 1098 1099@end itemize 1100 1101@node i386-Prefixes 1102@section Instruction Prefixes 1103 1104@cindex i386 instruction prefixes 1105@cindex instruction prefixes, i386 1106@cindex prefixes, i386 1107Instruction prefixes are used to modify the following instruction. They 1108are used to repeat string instructions, to provide section overrides, to 1109perform bus lock operations, and to change operand and address sizes. 1110(Most instructions that normally operate on 32-bit operands will use 111116-bit operands if the instruction has an ``operand size'' prefix.) 1112Instruction prefixes are best written on the same line as the instruction 1113they act upon. For example, the @samp{scas} (scan string) instruction is 1114repeated with: 1115 1116@smallexample 1117 repne scas %es:(%edi),%al 1118@end smallexample 1119 1120You may also place prefixes on the lines immediately preceding the 1121instruction, but this circumvents checks that @code{@value{AS}} does 1122with prefixes, and will not work with all prefixes. 1123 1124Here is a list of instruction prefixes: 1125 1126@cindex section override prefixes, i386 1127@itemize @bullet 1128@item 1129Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 1130@samp{fs}, @samp{gs}. These are automatically added by specifying 1131using the @var{section}:@var{memory-operand} form for memory references. 1132 1133@cindex size prefixes, i386 1134@item 1135Operand/Address size prefixes @samp{data16} and @samp{addr16} 1136change 32-bit operands/addresses into 16-bit operands/addresses, 1137while @samp{data32} and @samp{addr32} change 16-bit ones (in a 1138@code{.code16} section) into 32-bit operands/addresses. These prefixes 1139@emph{must} appear on the same line of code as the instruction they 1140modify. For example, in a 16-bit @code{.code16} section, you might 1141write: 1142 1143@smallexample 1144 addr32 jmpl *(%ebx) 1145@end smallexample 1146 1147@cindex bus lock prefixes, i386 1148@cindex inhibiting interrupts, i386 1149@item 1150The bus lock prefix @samp{lock} inhibits interrupts during execution of 1151the instruction it precedes. (This is only valid with certain 1152instructions; see a 80386 manual for details). 1153 1154@cindex coprocessor wait, i386 1155@item 1156The wait for coprocessor prefix @samp{wait} waits for the coprocessor to 1157complete the current instruction. This should never be needed for the 115880386/80387 combination. 1159 1160@cindex repeat prefixes, i386 1161@item 1162The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 1163to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 1164times if the current address size is 16-bits). 1165@cindex REX prefixes, i386 1166@item 1167The @samp{rex} family of prefixes is used by x86-64 to encode 1168extensions to i386 instruction set. The @samp{rex} prefix has four 1169bits --- an operand size overwrite (@code{64}) used to change operand size 1170from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 1171register set. 1172 1173You may write the @samp{rex} prefixes directly. The @samp{rex64xyz} 1174instruction emits @samp{rex} prefix with all the bits set. By omitting 1175the @code{64}, @code{x}, @code{y} or @code{z} you may write other 1176prefixes as well. Normally, there is no need to write the prefixes 1177explicitly, since gas will automatically generate them based on the 1178instruction operands. 1179@end itemize 1180 1181@node i386-Memory 1182@section Memory References 1183 1184@cindex i386 memory references 1185@cindex memory references, i386 1186@cindex x86-64 memory references 1187@cindex memory references, x86-64 1188An Intel syntax indirect memory reference of the form 1189 1190@smallexample 1191@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 1192@end smallexample 1193 1194@noindent 1195is translated into the AT&T syntax 1196 1197@smallexample 1198@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 1199@end smallexample 1200 1201@noindent 1202where @var{base} and @var{index} are the optional 32-bit base and 1203index registers, @var{disp} is the optional displacement, and 1204@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 1205to calculate the address of the operand. If no @var{scale} is 1206specified, @var{scale} is taken to be 1. @var{section} specifies the 1207optional section register for the memory operand, and may override the 1208default section register (see a 80386 manual for section register 1209defaults). Note that section overrides in AT&T syntax @emph{must} 1210be preceded by a @samp{%}. If you specify a section override which 1211coincides with the default section register, @code{@value{AS}} does @emph{not} 1212output any section register override prefixes to assemble the given 1213instruction. Thus, section overrides can be specified to emphasize which 1214section register is used for a given memory operand. 1215 1216Here are some examples of Intel and AT&T style memory references: 1217 1218@table @asis 1219@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 1220@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 1221missing, and the default section is used (@samp{%ss} for addressing with 1222@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 1223 1224@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 1225@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 1226@samp{foo}. All other fields are missing. The section register here 1227defaults to @samp{%ds}. 1228 1229@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 1230This uses the value pointed to by @samp{foo} as a memory operand. 1231Note that @var{base} and @var{index} are both missing, but there is only 1232@emph{one} @samp{,}. This is a syntactic exception. 1233 1234@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 1235This selects the contents of the variable @samp{foo} with section 1236register @var{section} being @samp{%gs}. 1237@end table 1238 1239Absolute (as opposed to PC relative) call and jump operands must be 1240prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 1241always chooses PC relative addressing for jump/call labels. 1242 1243Any instruction that has a memory operand, but no register operand, 1244@emph{must} specify its size (byte, word, long, or quadruple) with an 1245instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, 1246respectively). 1247 1248The x86-64 architecture adds an RIP (instruction pointer relative) 1249addressing. This addressing mode is specified by using @samp{rip} as a 1250base register. Only constant offsets are valid. For example: 1251 1252@table @asis 1253@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} 1254Points to the address 1234 bytes past the end of the current 1255instruction. 1256 1257@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} 1258Points to the @code{symbol} in RIP relative way, this is shorter than 1259the default absolute addressing. 1260@end table 1261 1262Other addressing modes remain unchanged in x86-64 architecture, except 1263registers used are 64-bit instead of 32-bit. 1264 1265@node i386-Jumps 1266@section Handling of Jump Instructions 1267 1268@cindex jump optimization, i386 1269@cindex i386 jump optimization 1270@cindex jump optimization, x86-64 1271@cindex x86-64 jump optimization 1272Jump instructions are always optimized to use the smallest possible 1273displacements. This is accomplished by using byte (8-bit) displacement 1274jumps whenever the target is sufficiently close. If a byte displacement 1275is insufficient a long displacement is used. We do not support 1276word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 1277instruction with the @samp{data16} instruction prefix), since the 80386 1278insists upon masking @samp{%eip} to 16 bits after the word displacement 1279is added. (See also @pxref{i386-Arch}) 1280 1281Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 1282@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 1283displacements, so that if you use these instructions (@code{@value{GCC}} does 1284not use them) you may get an error message (and incorrect code). The AT&T 128580386 assembler tries to get around this problem by expanding @samp{jcxz foo} 1286to 1287 1288@smallexample 1289 jcxz cx_zero 1290 jmp cx_nonzero 1291cx_zero: jmp foo 1292cx_nonzero: 1293@end smallexample 1294 1295@node i386-Float 1296@section Floating Point 1297 1298@cindex i386 floating point 1299@cindex floating point, i386 1300@cindex x86-64 floating point 1301@cindex floating point, x86-64 1302All 80387 floating point types except packed BCD are supported. 1303(BCD support may be added without much difficulty). These data 1304types are 16-, 32-, and 64- bit integers, and single (32-bit), 1305double (64-bit), and extended (80-bit) precision floating point. 1306Each supported type has an instruction mnemonic suffix and a constructor 1307associated with it. Instruction mnemonic suffixes specify the operand's 1308data type. Constructors build these data types into memory. 1309 1310@cindex @code{float} directive, i386 1311@cindex @code{single} directive, i386 1312@cindex @code{double} directive, i386 1313@cindex @code{tfloat} directive, i386 1314@cindex @code{float} directive, x86-64 1315@cindex @code{single} directive, x86-64 1316@cindex @code{double} directive, x86-64 1317@cindex @code{tfloat} directive, x86-64 1318@itemize @bullet 1319@item 1320Floating point constructors are @samp{.float} or @samp{.single}, 1321@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 1322These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 1323and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 1324only supports this format via the @samp{fldt} (load 80-bit real to stack 1325top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 1326 1327@cindex @code{word} directive, i386 1328@cindex @code{long} directive, i386 1329@cindex @code{int} directive, i386 1330@cindex @code{quad} directive, i386 1331@cindex @code{word} directive, x86-64 1332@cindex @code{long} directive, x86-64 1333@cindex @code{int} directive, x86-64 1334@cindex @code{quad} directive, x86-64 1335@item 1336Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 1337@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 1338corresponding instruction mnemonic suffixes are @samp{s} (short), 1339@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 1340the 64-bit @samp{q} format is only present in the @samp{fildq} (load 1341quad integer to stack top) and @samp{fistpq} (store quad integer and pop 1342stack) instructions. 1343@end itemize 1344 1345Register to register operations should not use instruction mnemonic suffixes. 1346@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 1347wrote @samp{fst %st, %st(1)}, since all register to register operations 1348use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 1349which converts @samp{%st} from 80-bit to 64-bit floating point format, 1350then stores the result in the 4 byte location @samp{mem}) 1351 1352@node i386-SIMD 1353@section Intel's MMX and AMD's 3DNow! SIMD Operations 1354 1355@cindex MMX, i386 1356@cindex 3DNow!, i386 1357@cindex SIMD, i386 1358@cindex MMX, x86-64 1359@cindex 3DNow!, x86-64 1360@cindex SIMD, x86-64 1361 1362@code{@value{AS}} supports Intel's MMX instruction set (SIMD 1363instructions for integer data), available on Intel's Pentium MMX 1364processors and Pentium II processors, AMD's K6 and K6-2 processors, 1365Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: 1366instruction set (SIMD instructions for 32-bit floating point data) 1367available on AMD's K6-2 processor and possibly others in the future. 1368 1369Currently, @code{@value{AS}} does not support Intel's floating point 1370SIMD, Katmai (KNI). 1371 1372The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 1373@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 137416-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 1375floating point values. The MMX registers cannot be used at the same time 1376as the floating point stack. 1377 1378See Intel and AMD documentation, keeping in mind that the operand order in 1379instructions is reversed from the Intel syntax. 1380 1381@node i386-LWP 1382@section AMD's Lightweight Profiling Instructions 1383 1384@cindex LWP, i386 1385@cindex LWP, x86-64 1386 1387@code{@value{AS}} supports AMD's Lightweight Profiling (LWP) 1388instruction set, available on AMD's Family 15h (Orochi) processors. 1389 1390LWP enables applications to collect and manage performance data, and 1391react to performance events. The collection of performance data 1392requires no context switches. LWP runs in the context of a thread and 1393so several counters can be used independently across multiple threads. 1394LWP can be used in both 64-bit and legacy 32-bit modes. 1395 1396For detailed information on the LWP instruction set, see the 1397@cite{AMD Lightweight Profiling Specification} available at 1398@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. 1399 1400@node i386-BMI 1401@section Bit Manipulation Instructions 1402 1403@cindex BMI, i386 1404@cindex BMI, x86-64 1405 1406@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. 1407 1408BMI instructions provide several instructions implementing individual 1409bit manipulation operations such as isolation, masking, setting, or 1410resetting. 1411 1412@c Need to add a specification citation here when available. 1413 1414@node i386-TBM 1415@section AMD's Trailing Bit Manipulation Instructions 1416 1417@cindex TBM, i386 1418@cindex TBM, x86-64 1419 1420@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) 1421instruction set, available on AMD's BDVER2 processors (Trinity and 1422Viperfish). 1423 1424TBM instructions provide instructions implementing individual bit 1425manipulation operations such as isolating, masking, setting, resetting, 1426complementing, and operations on trailing zeros and ones. 1427 1428@c Need to add a specification citation here when available. 1429 1430@node i386-16bit 1431@section Writing 16-bit Code 1432 1433@cindex i386 16-bit code 1434@cindex 16-bit code, i386 1435@cindex real-mode code, i386 1436@cindex @code{code16gcc} directive, i386 1437@cindex @code{code16} directive, i386 1438@cindex @code{code32} directive, i386 1439@cindex @code{code64} directive, i386 1440@cindex @code{code64} directive, x86-64 1441While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code 1442or 64-bit x86-64 code depending on the default configuration, 1443it also supports writing code to run in real mode or in 16-bit protected 1444mode code segments. To do this, put a @samp{.code16} or 1445@samp{.code16gcc} directive before the assembly language instructions to 1446be run in 16-bit mode. You can switch @code{@value{AS}} to writing 144732-bit code with the @samp{.code32} directive or 64-bit code with the 1448@samp{.code64} directive. 1449 1450@samp{.code16gcc} provides experimental support for generating 16-bit 1451code from gcc, and differs from @samp{.code16} in that @samp{call}, 1452@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 1453@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 1454default to 32-bit size. This is so that the stack pointer is 1455manipulated in the same way over function calls, allowing access to 1456function parameters at the same stack offsets as in 32-bit mode. 1457@samp{.code16gcc} also automatically adds address size prefixes where 1458necessary to use the 32-bit addressing modes that gcc generates. 1459 1460The code which @code{@value{AS}} generates in 16-bit mode will not 1461necessarily run on a 16-bit pre-80386 processor. To write code that 1462runs on such a processor, you must refrain from using @emph{any} 32-bit 1463constructs which require @code{@value{AS}} to output address or operand 1464size prefixes. 1465 1466Note that writing 16-bit code instructions by explicitly specifying a 1467prefix or an instruction mnemonic suffix within a 32-bit code section 1468generates different machine instructions than those generated for a 146916-bit code segment. In a 32-bit code section, the following code 1470generates the machine opcode bytes @samp{66 6a 04}, which pushes the 1471value @samp{4} onto the stack, decrementing @samp{%esp} by 2. 1472 1473@smallexample 1474 pushw $4 1475@end smallexample 1476 1477The same code in a 16-bit code section would generate the machine 1478opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which 1479is correct since the processor default operand size is assumed to be 16 1480bits in a 16-bit code section. 1481 1482@node i386-Arch 1483@section Specifying CPU Architecture 1484 1485@cindex arch directive, i386 1486@cindex i386 arch directive 1487@cindex arch directive, x86-64 1488@cindex x86-64 arch directive 1489 1490@code{@value{AS}} may be told to assemble for a particular CPU 1491(sub-)architecture with the @code{.arch @var{cpu_type}} directive. This 1492directive enables a warning when gas detects an instruction that is not 1493supported on the CPU specified. The choices for @var{cpu_type} are: 1494 1495@multitable @columnfractions .20 .20 .20 .20 1496@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} 1497@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} 1498@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} 1499@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} 1500@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu} 1501@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} 1502@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} 1503@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3} 1504@item @samp{btver1} @tab @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} 1505@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} 1506@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a} 1507@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} 1508@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} 1509@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} 1510@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} 1511@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} 1512@item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} 1513@item @samp{.hle} 1514@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} 1515@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} 1516@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} 1517@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} 1518@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} 1519@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} 1520@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} 1521@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} 1522@item @samp{.tdx} @tab @samp{.avx_vnni} 1523@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt} 1524@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} 1525@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} 1526@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} 1527@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile} 1528@item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset} 1529@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} 1530@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} 1531@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} 1532@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} 1533@item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb} 1534@item @samp{.tlbsync} 1535@end multitable 1536 1537Apart from the warning, there are only two other effects on 1538@code{@value{AS}} operation; Firstly, if you specify a CPU other than 1539@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} 1540will automatically use a two byte opcode sequence. The larger three 1541byte opcode sequence is used on the 486 (and when no architecture is 1542specified) because it executes faster on the 486. Note that you can 1543explicitly request the two byte opcode by writing @samp{sarl %eax}. 1544Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, 1545@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset 1546conditional jumps will be promoted when necessary to a two instruction 1547sequence consisting of a conditional jump of the opposite sense around 1548an unconditional jump to the target. 1549 1550Following the CPU architecture (but not a sub-architecture, which are those 1551starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to 1552control automatic promotion of conditional jumps. @samp{jumps} is the 1553default, and enables jump promotion; All external jumps will be of the long 1554variety, and file-local jumps will be promoted as necessary. 1555(@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as 1556byte offset jumps, and warns about file-local conditional jumps that 1557@code{@value{AS}} promotes. 1558Unconditional jumps are treated as for @samp{jumps}. 1559 1560For example 1561 1562@smallexample 1563 .arch i8086,nojumps 1564@end smallexample 1565 1566@node i386-ISA 1567@section AMD64 ISA vs. Intel64 ISA 1568 1569There are some discrepancies between AMD64 and Intel64 ISAs. 1570 1571@itemize @bullet 1572@item For @samp{movsxd} with 16-bit destination register, AMD64 1573supports 32-bit source operand and Intel64 supports 16-bit source 1574operand. 1575 1576@item For far branches (with explicit memory operand), both ISAs support 157732- and 16-bit operand size. Intel64 additionally supports 64-bit 1578operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax 1579and with an explicit @samp{tbyte ptr} operand size specifier in Intel 1580syntax. 1581 1582@item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16- 1583and 32-bit operand size (32- and 48-bit memory operand) in both ISAs, 1584while Intel64 additionally supports 64-bit operand sise (80-bit memory 1585operands). 1586 1587@end itemize 1588 1589@node i386-Bugs 1590@section AT&T Syntax bugs 1591 1592The UnixWare assembler, and probably other AT&T derived ix86 Unix 1593assemblers, generate floating point instructions with reversed source 1594and destination registers in certain cases. Unfortunately, gcc and 1595possibly many other programs use this reversed syntax, so we're stuck 1596with it. 1597 1598For example 1599 1600@smallexample 1601 fsub %st,%st(3) 1602@end smallexample 1603@noindent 1604results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 1605than the expected @samp{%st(3) - %st}. This happens with all the 1606non-commutative arithmetic floating point operations with two register 1607operands where the source register is @samp{%st} and the destination 1608register is @samp{%st(i)}. 1609 1610@node i386-Notes 1611@section Notes 1612 1613@cindex i386 @code{mul}, @code{imul} instructions 1614@cindex @code{mul} instruction, i386 1615@cindex @code{imul} instruction, i386 1616@cindex @code{mul} instruction, x86-64 1617@cindex @code{imul} instruction, x86-64 1618There is some trickery concerning the @samp{mul} and @samp{imul} 1619instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding 1620multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 1621for @samp{imul}) can be output only in the one operand form. Thus, 1622@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 1623the expanding multiply would clobber the @samp{%edx} register, and this 1624would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 162564-bit product in @samp{%edx:%eax}. 1626 1627We have added a two operand form of @samp{imul} when the first operand 1628is an immediate mode expression and the second operand is a register. 1629This is just a shorthand, so that, multiplying @samp{%eax} by 69, for 1630example, can be done with @samp{imul $69, %eax} rather than @samp{imul 1631$69, %eax, %eax}. 1632 1633