1 #objdump: -dr --prefix-addresses 2 #name: MIPS macro drol/dror 3 4 # Test the drol and dror macros. 5 6 .*: +file format .*mips.* 7 8 Disassembly of section .text: 9 0+0000 <[^>]*> dnegu at,a1 10 0+0004 <[^>]*> dsrlv at,a0,at 11 0+0008 <[^>]*> dsllv a0,a0,a1 12 0+000c <[^>]*> or a0,a0,at 13 0+0010 <[^>]*> dnegu at,a2 14 0+0014 <[^>]*> dsrlv at,a1,at 15 0+0018 <[^>]*> dsllv a0,a1,a2 16 0+001c <[^>]*> or a0,a0,at 17 0+0020 <[^>]*> dsll at,a0,0x1 18 0+0024 <[^>]*> dsrl32 a0,a0,0x1f 19 0+0028 <[^>]*> or a0,a0,at 20 0+002c <[^>]*> dsrl a0,a1,0x0 21 0+0030 <[^>]*> dsll at,a1,0x1 22 0+0034 <[^>]*> dsrl32 a0,a1,0x1f 23 0+0038 <[^>]*> or a0,a0,at 24 0+003c <[^>]*> dsll at,a1,0x1f 25 0+0040 <[^>]*> dsrl32 a0,a1,0x1 26 0+0044 <[^>]*> or a0,a0,at 27 0+0048 <[^>]*> dsll32 at,a1,0x0 28 0+004c <[^>]*> dsrl32 a0,a1,0x0 29 0+0050 <[^>]*> or a0,a0,at 30 0+0054 <[^>]*> dsll32 at,a1,0x1 31 0+0058 <[^>]*> dsrl a0,a1,0x1f 32 0+005c <[^>]*> or a0,a0,at 33 0+0060 <[^>]*> dsll32 at,a1,0x1f 34 0+0064 <[^>]*> dsrl a0,a1,0x1 35 0+0068 <[^>]*> or a0,a0,at 36 0+006c <[^>]*> dsrl a0,a1,0x0 37 0+0070 <[^>]*> dnegu at,a1 38 0+0074 <[^>]*> dsllv at,a0,at 39 0+0078 <[^>]*> dsrlv a0,a0,a1 40 0+007c <[^>]*> or a0,a0,at 41 0+0080 <[^>]*> dnegu at,a2 42 0+0084 <[^>]*> dsllv at,a1,at 43 0+0088 <[^>]*> dsrlv a0,a1,a2 44 0+008c <[^>]*> or a0,a0,at 45 0+0090 <[^>]*> dsrl at,a0,0x1 46 0+0094 <[^>]*> dsll32 a0,a0,0x1f 47 0+0098 <[^>]*> or a0,a0,at 48 0+009c <[^>]*> dsrl a0,a1,0x0 49 0+00a0 <[^>]*> dsrl at,a1,0x1 50 0+00a4 <[^>]*> dsll32 a0,a1,0x1f 51 0+00a8 <[^>]*> or a0,a0,at 52 0+00ac <[^>]*> dsrl at,a1,0x1f 53 0+00b0 <[^>]*> dsll32 a0,a1,0x1 54 0+00b4 <[^>]*> or a0,a0,at 55 0+00b8 <[^>]*> dsrl32 at,a1,0x0 56 0+00bc <[^>]*> dsll32 a0,a1,0x0 57 0+00c0 <[^>]*> or a0,a0,at 58 0+00c4 <[^>]*> dsrl32 at,a1,0x1 59 0+00c8 <[^>]*> dsll a0,a1,0x1f 60 0+00cc <[^>]*> or a0,a0,at 61 0+00d0 <[^>]*> dsrl32 at,a1,0x1f 62 0+00d4 <[^>]*> dsll a0,a1,0x1 63 0+00d8 <[^>]*> or a0,a0,at 64 0+00dc <[^>]*> dsrl a0,a1,0x0 65 0+00e0 <[^>]*> dsll at,a1,0x1 66 0+00e4 <[^>]*> dsrl32 a0,a1,0x1f 67 0+00e8 <[^>]*> or a0,a0,at 68 0+00ec <[^>]*> dsll at,a1,0x1f 69 0+00f0 <[^>]*> dsrl32 a0,a1,0x1 70 0+00f4 <[^>]*> or a0,a0,at 71 0+00f8 <[^>]*> dsll32 at,a1,0x0 72 0+00fc <[^>]*> dsrl32 a0,a1,0x0 73 0+0100 <[^>]*> or a0,a0,at 74 0+0104 <[^>]*> dsll32 at,a1,0x1 75 0+0108 <[^>]*> dsrl a0,a1,0x1f 76 0+010c <[^>]*> or a0,a0,at 77 0+0110 <[^>]*> dsll32 at,a1,0x1f 78 0+0114 <[^>]*> dsrl a0,a1,0x1 79 0+0118 <[^>]*> or a0,a0,at 80 0+011c <[^>]*> dsrl at,a1,0x1 81 0+0120 <[^>]*> dsll32 a0,a1,0x1f 82 0+0124 <[^>]*> or a0,a0,at 83 0+0128 <[^>]*> dsrl at,a1,0x1f 84 0+012c <[^>]*> dsll32 a0,a1,0x1 85 0+0130 <[^>]*> or a0,a0,at 86 0+0134 <[^>]*> dsrl32 at,a1,0x0 87 0+0138 <[^>]*> dsll32 a0,a1,0x0 88 0+013c <[^>]*> or a0,a0,at 89 0+0140 <[^>]*> dsrl32 at,a1,0x1 90 0+0144 <[^>]*> dsll a0,a1,0x1f 91 0+0148 <[^>]*> or a0,a0,at 92 0+014c <[^>]*> dsrl32 at,a1,0x1f 93 0+0150 <[^>]*> dsll a0,a1,0x1 94 0+0154 <[^>]*> or a0,a0,at 95 ... 96