1 .macro check2 insn 2 mflo $2 3 \insn $3,$3 4 .endm 5 6 .macro check3 insn 7 mfhi $2 8 \insn $0,$3,$3 9 .endm 10 11 .macro main func 12 13 .ent \func 14 .type \func,@function 15\func: 16 17 # PART A 18 # 19 # Check that mfhis and mflos in .set noreorder blocks are not 20 # considered. 21 22 .set noreorder 23 mfhi $2 24 .set reorder 25 mult $3,$3 26 27 .set noreorder 28 mflo $2 29 .set reorder 30 mult $3,$3 31 32 # PART B 33 # 34 # Check for simple instances. 35 36 mfhi $2 37 mult $3,$3 # 4 nops 38 39 mfhi $2 40 addiu $3,1 41 mult $4,$4 # 3 nops 42 43 mfhi $2 44 addiu $3,1 45 addiu $4,1 46 mult $5,$5 # 2 nops 47 48 mfhi $2 49 addiu $3,1 50 addiu $4,1 51 addiu $5,1 52 mult $6,$6 # 1 nop 53 54 mfhi $2 55 addiu $3,1 56 addiu $4,1 57 addiu $5,1 58 addiu $6,1 59 mult $7,$7 # 0 nops 60 61 # PART C 62 # 63 # Check that no nops are inserted after the result has been read. 64 65 mfhi $2 66 addiu $2,1 67 addiu $3,1 68 addiu $4,1 69 mult $5,$5 70 71 mfhi $2 72 addiu $3,1 73 addiu $2,1 74 addiu $4,1 75 mult $5,$5 76 77 mfhi $2 78 addiu $3,1 79 addiu $4,1 80 addiu $2,1 81 mult $5,$5 82 83 mfhi $2 84 addiu $3,1 85 addiu $4,1 86 addiu $5,1 87 mult $2,$2 88 89 # PART D 90 # 91 # Check that we still insert the usual interlocking nops in cases 92 # where the VR4130 errata doesn't apply. 93 94 mfhi $2 95 mult $2,$2 # 2 nops 96 97 mfhi $2 98 addiu $2,1 99 mult $3,$3 # 1 nop 100 101 mfhi $2 102 addiu $3,1 103 mult $2,$2 # 1 nop 104 105 # PART E 106 # 107 # Check for branches whose targets might be affected. 108 109 mfhi $2 110 bnez $3,1f # 2 nops for normal mode, 3 for mips16 111 112 mfhi $2 113 addiu $3,1 114 bnez $3,1f # 1 nop for normal mode, 2 for mips16 115 116 mfhi $2 117 addiu $3,1 118 addiu $3,1 119 bnez $3,1f # 0 nops for normal mode, 1 for mips16 120 121 mfhi $2 122 addiu $3,1 123 addiu $3,1 124 addiu $3,1 125 bnez $3,1f # 0 nops 126 127 # PART F 128 # 129 # As above, but with no dependencies between the branch and 130 # the previous instruction. The final branch can use the 131 # preceding addiu as its delay slot. 132 133 mfhi $2 134 addiu $3,1 135 bnez $4,1f # 1 nop for normal mode, 2 for mips16 136 137 mfhi $2 138 addiu $3,1 139 addiu $4,1 140 bnez $5,1f # 0 nops for normal mode, 1 for mips16 141 142 mfhi $2 143 addiu $3,1 144 addiu $4,1 145 addiu $5,1 146 bnez $6,1f # 0 nops, fill delay slot in normal mode 1471: 148 149 # PART G 150 # 151 # Like part B, but check that intervening .set noreorders don't 152 # affect the number of nops. 153 154 mfhi $2 155 .set noreorder 156 addiu $3,1 157 .set reorder 158 mult $4,$4 # 3 nops 159 160 mfhi $2 161 .set noreorder 162 addiu $3,1 163 .set reorder 164 addiu $4,1 165 mult $5,$5 # 2 nops 166 167 mfhi $2 168 addiu $3,1 169 .set noreorder 170 addiu $4,1 171 .set reorder 172 mult $5,$5 # 2 nops 173 174 mfhi $2 175 .set noreorder 176 addiu $3,1 177 addiu $4,1 178 .set reorder 179 mult $5,$5 # 2 nops 180 181 mfhi $2 182 addiu $3,1 183 .set noreorder 184 addiu $4,1 185 .set reorder 186 addiu $5,1 187 mult $6,$6 # 1 nop 188 189 mfhi $2 190 .set noreorder 191 addiu $3,1 192 addiu $4,1 193 addiu $5,1 194 .set reorder 195 mult $6,$6 # 1 nop 196 197 mfhi $2 198 .set noreorder 199 addiu $3,1 200 addiu $4,1 201 addiu $5,1 202 addiu $6,1 203 .set reorder 204 mult $7,$7 # 0 nops 205 206 # PART H 207 # 208 # Like part B, but the mult occurs in a .set noreorder block. 209 210 mfhi $2 211 .set noreorder 212 mult $3,$3 # 4 nops 213 .set reorder 214 215 mfhi $2 216 .set noreorder 217 addiu $3,1 218 mult $4,$4 # 3 nops 219 .set reorder 220 221 mfhi $2 222 addiu $3,1 223 .set noreorder 224 addiu $4,1 225 mult $5,$5 # 2 nops 226 .set reorder 227 228 mfhi $2 229 .set noreorder 230 addiu $3,1 231 addiu $4,1 232 addiu $5,1 233 mult $6,$6 # 1 nop 234 .set reorder 235 236 mfhi $2 237 .set noreorder 238 addiu $3,1 239 addiu $4,1 240 addiu $5,1 241 addiu $6,1 242 mult $7,$7 # 0 nops 243 .set reorder 244 245 # PART I 246 # 247 # Check every affected multiplication and division instruction. 248 249 check2 mult 250 check2 multu 251 check2 dmult 252 check2 dmultu 253 254 check3 div 255 check3 divu 256 check3 ddiv 257 check3 ddivu 258 259 .end \func 260 .endm 261 262 .set nomips16 263 main foo 264 265 # PART J 266 # 267 # Check every affected multiply-accumulate instruction. 268 269 check3 macc 270 check3 macchi 271 check3 macchis 272 check3 macchiu 273 check3 macchius 274 check3 maccs 275 check3 maccu 276 check3 maccus 277 278 check3 dmacc 279 check3 dmacchi 280 check3 dmacchis 281 check3 dmacchiu 282 check3 dmacchius 283 check3 dmaccs 284 check3 dmaccu 285 check3 dmaccus 286 287 # PART K 288 # 289 # Check that mtlo and mthi are exempt from the VR4130 errata, 290 # although the usual interlocking delay applies. 291 292 mflo $2 293 mtlo $3 294 295 mflo $2 296 mthi $3 297 298 mfhi $2 299 mtlo $3 300 301 mfhi $2 302 mthi $3 303 304 .set mips16 305 main bar 306