1 /* Print i386 instructions for GDB, the GNU debugger.
2    Copyright (C) 1988-2021 Free Software Foundation, Inc.
3 
4    This file is part of the GNU opcodes library.
5 
6    This library is free software; you can redistribute it and/or modify
7    it under the terms of the GNU General Public License as published by
8    the Free Software Foundation; either version 3, or (at your option)
9    any later version.
10 
11    It is distributed in the hope that it will be useful, but WITHOUT
12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14    License for more details.
15 
16    You should have received a copy of the GNU General Public License
17    along with this program; if not, write to the Free Software
18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19    MA 02110-1301, USA.  */
20 
21 
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23    July 1988
24     modified by John Hassey (hassey@dg-rtp.dg.com)
25     x86-64 support added by Jan Hubicka (jh@suse.cz)
26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
27 
28 /* The main tables describing the instructions is essentially a copy
29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30    Programmers Manual.  Usually, there is a capital letter, followed
31    by a small letter.  The capital letter tell the addressing mode,
32    and the small letter tells about the operand size.  Refer to
33    the Intel manual for details.  */
34 
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41 
42 #include <setjmp.h>
43 
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
116 
117 static void MOVSXD_Fixup (int, int);
118 
119 static void OP_Mask (int, int);
120 
121 struct dis_private {
122   /* Points to first byte not fetched.  */
123   bfd_byte *max_fetched;
124   bfd_byte the_buffer[MAX_MNEM_SIZE];
125   bfd_vma insn_start;
126   int orig_sizeflag;
127   OPCODES_SIGJMP_BUF bailout;
128 };
129 
130 enum address_mode
131 {
132   mode_16bit,
133   mode_32bit,
134   mode_64bit
135 };
136 
137 enum address_mode address_mode;
138 
139 /* Flags for the prefixes for the current instruction.  See below.  */
140 static int prefixes;
141 
142 /* REX prefix the current instruction.  See below.  */
143 static int rex;
144 /* Bits of REX we've already used.  */
145 static int rex_used;
146 /* Mark parts used in the REX prefix.  When we are testing for
147    empty prefix (for 8bit register REX extension), just mask it
148    out.  Otherwise test for REX bit is excuse for existence of REX
149    only in case value is nonzero.  */
150 #define USED_REX(value)					\
151   {							\
152     if (value)						\
153       {							\
154 	if ((rex & value))				\
155 	  rex_used |= (value) | REX_OPCODE;		\
156       }							\
157     else						\
158       rex_used |= REX_OPCODE;				\
159   }
160 
161 /* Flags for prefixes which we somehow handled when printing the
162    current instruction.  */
163 static int used_prefixes;
164 
165 /* Flags stored in PREFIXES.  */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
169 #define PREFIX_CS 8
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
178 
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
181    on error.  */
182 #define FETCH_DATA(info, addr) \
183   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184    ? 1 : fetch_data ((info), (addr)))
185 
186 static int
fetch_data(struct disassemble_info * info,bfd_byte * addr)187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
188 {
189   int status;
190   struct dis_private *priv = (struct dis_private *) info->private_data;
191   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
192 
193   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
194     status = (*info->read_memory_func) (start,
195 					priv->max_fetched,
196 					addr - priv->max_fetched,
197 					info);
198   else
199     status = -1;
200   if (status != 0)
201     {
202       /* If we did manage to read at least one byte, then
203 	 print_insn_i386 will do something sensible.  Otherwise, print
204 	 an error.  We do that here because this is where we know
205 	 STATUS.  */
206       if (priv->max_fetched == priv->the_buffer)
207 	(*info->memory_error_func) (status, start, info);
208       OPCODES_SIGLONGJMP (priv->bailout, 1);
209     }
210   else
211     priv->max_fetched = addr;
212   return 1;
213 }
214 
215 /* Possible values for prefix requirement.  */
216 #define PREFIX_IGNORED_SHIFT	16
217 #define PREFIX_IGNORED_REPZ	(PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ	(PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA	(PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR	(PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK	(PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
222 
223 /* Opcode prefixes.  */
224 #define PREFIX_OPCODE		(PREFIX_REPZ \
225 				 | PREFIX_REPNZ \
226 				 | PREFIX_DATA)
227 
228 /* Prefixes ignored.  */
229 #define PREFIX_IGNORED		(PREFIX_IGNORED_REPZ \
230 				 | PREFIX_IGNORED_REPNZ \
231 				 | PREFIX_IGNORED_DATA)
232 
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
235 
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 }		/* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode }		/* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode }	/* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
292 
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
319 
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
325 
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
337 
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
344 
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
350 #define XMM { OP_XMM, xmm_mode }
351 #define TMM { OP_XMM, tmm_mode }
352 #define XMxmmq { OP_XMM, xmmq_mode }
353 #define EM { OP_EM, v_mode }
354 #define EMS { OP_EM, v_swap_mode }
355 #define EMd { OP_EM, d_mode }
356 #define EMx { OP_EM, x_mode }
357 #define EXbwUnit { OP_EX, bw_unit_mode }
358 #define EXw { OP_EX, w_mode }
359 #define EXd { OP_EX, d_mode }
360 #define EXdS { OP_EX, d_swap_mode }
361 #define EXq { OP_EX, q_mode }
362 #define EXqS { OP_EX, q_swap_mode }
363 #define EXx { OP_EX, x_mode }
364 #define EXxS { OP_EX, x_swap_mode }
365 #define EXxmm { OP_EX, xmm_mode }
366 #define EXymm { OP_EX, ymm_mode }
367 #define EXtmm { OP_EX, tmm_mode }
368 #define EXxmmq { OP_EX, xmmq_mode }
369 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
370 #define EXxmm_mb { OP_EX, xmm_mb_mode }
371 #define EXxmm_mw { OP_EX, xmm_mw_mode }
372 #define EXxmm_md { OP_EX, xmm_md_mode }
373 #define EXxmm_mq { OP_EX, xmm_mq_mode }
374 #define EXxmmdw { OP_EX, xmmdw_mode }
375 #define EXxmmqd { OP_EX, xmmqd_mode }
376 #define EXymmq { OP_EX, ymmq_mode }
377 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
378 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
379 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
380 #define MS { OP_MS, v_mode }
381 #define XS { OP_XS, v_mode }
382 #define EMCq { OP_EMC, q_mode }
383 #define MXC { OP_MXC, 0 }
384 #define OPSUF { OP_3DNowSuffix, 0 }
385 #define SEP { SEP_Fixup, 0 }
386 #define CMP { CMP_Fixup, 0 }
387 #define XMM0 { XMM_Fixup, 0 }
388 #define FXSAVE { FXSAVE_Fixup, 0 }
389 
390 #define Vex { OP_VEX, vex_mode }
391 #define VexW { OP_VexW, vex_mode }
392 #define VexScalar { OP_VEX, vex_scalar_mode }
393 #define VexScalarR { OP_VexR, vex_scalar_mode }
394 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
395 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
396 #define VexGdq { OP_VEX, dq_mode }
397 #define VexTmm { OP_VEX, tmm_mode }
398 #define XMVexI4 { OP_REG_VexI4, x_mode }
399 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
400 #define VexI4 { OP_VexI4, 0 }
401 #define PCLMUL { PCLMUL_Fixup, 0 }
402 #define VPCMP { VPCMP_Fixup, 0 }
403 #define VPCOM { VPCOM_Fixup, 0 }
404 
405 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
406 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
407 #define EXxEVexS { OP_Rounding, evex_sae_mode }
408 
409 #define XMask { OP_Mask, mask_mode }
410 #define MaskG { OP_G, mask_mode }
411 #define MaskE { OP_E, mask_mode }
412 #define MaskBDE { OP_E, mask_bd_mode }
413 #define MaskVex { OP_VEX, mask_mode }
414 
415 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
416 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
417 
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
419 
420 /* Used handle "rep" prefix for string instructions.  */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
429 
430 /* Used handle HLE prefix for lockable instructions.  */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
437 
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
440 
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
443 
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
446 #define AFLAG 2
447 #define DFLAG 1
448 
449 enum
450 {
451   /* byte operand */
452   b_mode = 1,
453   /* byte operand with operand swapped */
454   b_swap_mode,
455   /* byte operand, sign extend like 'T' suffix */
456   b_T_mode,
457   /* operand size depends on prefixes */
458   v_mode,
459   /* operand size depends on prefixes with operand swapped */
460   v_swap_mode,
461   /* operand size depends on address prefix */
462   va_mode,
463   /* word operand */
464   w_mode,
465   /* double word operand  */
466   d_mode,
467   /* double word operand with operand swapped */
468   d_swap_mode,
469   /* quad word operand */
470   q_mode,
471   /* quad word operand with operand swapped */
472   q_swap_mode,
473   /* ten-byte operand */
474   t_mode,
475   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
476      broadcast enabled.  */
477   x_mode,
478   /* Similar to x_mode, but with different EVEX mem shifts.  */
479   evex_x_gscat_mode,
480   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
481   bw_unit_mode,
482   /* Similar to x_mode, but with disabled broadcast.  */
483   evex_x_nobcst_mode,
484   /* Similar to x_mode, but with operands swapped and disabled broadcast
485      in EVEX.  */
486   x_swap_mode,
487   /* 16-byte XMM operand */
488   xmm_mode,
489   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490      memory operand (depending on vector length).  Broadcast isn't
491      allowed.  */
492   xmmq_mode,
493   /* Same as xmmq_mode, but broadcast is allowed.  */
494   evex_half_bcst_xmmq_mode,
495   /* XMM register or byte memory operand */
496   xmm_mb_mode,
497   /* XMM register or word memory operand */
498   xmm_mw_mode,
499   /* XMM register or double word memory operand */
500   xmm_md_mode,
501   /* XMM register or quad word memory operand */
502   xmm_mq_mode,
503   /* 16-byte XMM, word, double word or quad word operand.  */
504   xmmdw_mode,
505   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
506   xmmqd_mode,
507   /* 32-byte YMM operand */
508   ymm_mode,
509   /* quad word, ymmword or zmmword memory operand.  */
510   ymmq_mode,
511   /* 32-byte YMM or 16-byte word operand */
512   ymmxmm_mode,
513   /* TMM operand */
514   tmm_mode,
515   /* d_mode in 32bit, q_mode in 64bit mode.  */
516   m_mode,
517   /* pair of v_mode operands */
518   a_mode,
519   cond_jump_mode,
520   loop_jcxz_mode,
521   movsxd_mode,
522   v_bnd_mode,
523   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
524   v_bndmk_mode,
525   /* operand size depends on REX prefixes.  */
526   dq_mode,
527   /* registers like dq_mode, memory like w_mode, displacements like
528      v_mode without considering Intel64 ISA.  */
529   dqw_mode,
530   /* bounds operand */
531   bnd_mode,
532   /* bounds operand with operand swapped */
533   bnd_swap_mode,
534   /* 4- or 6-byte pointer operand */
535   f_mode,
536   const_1_mode,
537   /* v_mode for indirect branch opcodes.  */
538   indir_v_mode,
539   /* v_mode for stack-related opcodes.  */
540   stack_v_mode,
541   /* non-quad operand size depends on prefixes */
542   z_mode,
543   /* 16-byte operand */
544   o_mode,
545   /* registers like dq_mode, memory like b_mode.  */
546   dqb_mode,
547   /* registers like d_mode, memory like b_mode.  */
548   db_mode,
549   /* registers like d_mode, memory like w_mode.  */
550   dw_mode,
551   /* registers like dq_mode, memory like d_mode.  */
552   dqd_mode,
553   /* normal vex mode */
554   vex_mode,
555 
556   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
557   vex_vsib_d_w_dq_mode,
558   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
559   vex_vsib_q_w_dq_mode,
560   /* mandatory non-vector SIB.  */
561   vex_sibmem_mode,
562 
563   /* scalar, ignore vector length.  */
564   scalar_mode,
565   /* like vex_mode, ignore vector length.  */
566   vex_scalar_mode,
567   /* Operand size depends on the VEX.W bit, ignore vector length.  */
568   vex_scalar_w_dq_mode,
569 
570   /* Static rounding.  */
571   evex_rounding_mode,
572   /* Static rounding, 64-bit mode only.  */
573   evex_rounding_64_mode,
574   /* Supress all exceptions.  */
575   evex_sae_mode,
576 
577   /* Mask register operand.  */
578   mask_mode,
579   /* Mask register operand.  */
580   mask_bd_mode,
581 
582   es_reg,
583   cs_reg,
584   ss_reg,
585   ds_reg,
586   fs_reg,
587   gs_reg,
588 
589   eAX_reg,
590   eCX_reg,
591   eDX_reg,
592   eBX_reg,
593   eSP_reg,
594   eBP_reg,
595   eSI_reg,
596   eDI_reg,
597 
598   al_reg,
599   cl_reg,
600   dl_reg,
601   bl_reg,
602   ah_reg,
603   ch_reg,
604   dh_reg,
605   bh_reg,
606 
607   ax_reg,
608   cx_reg,
609   dx_reg,
610   bx_reg,
611   sp_reg,
612   bp_reg,
613   si_reg,
614   di_reg,
615 
616   rAX_reg,
617   rCX_reg,
618   rDX_reg,
619   rBX_reg,
620   rSP_reg,
621   rBP_reg,
622   rSI_reg,
623   rDI_reg,
624 
625   z_mode_ax_reg,
626   indir_dx_reg
627 };
628 
629 enum
630 {
631   FLOATCODE = 1,
632   USE_REG_TABLE,
633   USE_MOD_TABLE,
634   USE_RM_TABLE,
635   USE_PREFIX_TABLE,
636   USE_X86_64_TABLE,
637   USE_3BYTE_TABLE,
638   USE_XOP_8F_TABLE,
639   USE_VEX_C4_TABLE,
640   USE_VEX_C5_TABLE,
641   USE_VEX_LEN_TABLE,
642   USE_VEX_W_TABLE,
643   USE_EVEX_TABLE,
644   USE_EVEX_LEN_TABLE
645 };
646 
647 #define FLOAT			NULL, { { NULL, FLOATCODE } }, 0
648 
649 #define DIS386(T, I)		NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
650 #define DIS386_PREFIX(T, I, P)		NULL, { { NULL, (T)}, { NULL,  (I) } }, P
651 #define REG_TABLE(I)		DIS386 (USE_REG_TABLE, (I))
652 #define MOD_TABLE(I)		DIS386 (USE_MOD_TABLE, (I))
653 #define RM_TABLE(I)		DIS386 (USE_RM_TABLE, (I))
654 #define PREFIX_TABLE(I)		DIS386 (USE_PREFIX_TABLE, (I))
655 #define X86_64_TABLE(I)		DIS386 (USE_X86_64_TABLE, (I))
656 #define THREE_BYTE_TABLE(I)	DIS386 (USE_3BYTE_TABLE, (I))
657 #define THREE_BYTE_TABLE_PREFIX(I, P)	DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
658 #define XOP_8F_TABLE(I)		DIS386 (USE_XOP_8F_TABLE, (I))
659 #define VEX_C4_TABLE(I)		DIS386 (USE_VEX_C4_TABLE, (I))
660 #define VEX_C5_TABLE(I)		DIS386 (USE_VEX_C5_TABLE, (I))
661 #define VEX_LEN_TABLE(I)	DIS386 (USE_VEX_LEN_TABLE, (I))
662 #define VEX_W_TABLE(I)		DIS386 (USE_VEX_W_TABLE, (I))
663 #define EVEX_TABLE(I)		DIS386 (USE_EVEX_TABLE, (I))
664 #define EVEX_LEN_TABLE(I)	DIS386 (USE_EVEX_LEN_TABLE, (I))
665 
666 enum
667 {
668   REG_80 = 0,
669   REG_81,
670   REG_83,
671   REG_8F,
672   REG_C0,
673   REG_C1,
674   REG_C6,
675   REG_C7,
676   REG_D0,
677   REG_D1,
678   REG_D2,
679   REG_D3,
680   REG_F6,
681   REG_F7,
682   REG_FE,
683   REG_FF,
684   REG_0F00,
685   REG_0F01,
686   REG_0F0D,
687   REG_0F18,
688   REG_0F1C_P_0_MOD_0,
689   REG_0F1E_P_1_MOD_3,
690   REG_0F38D8_PREFIX_1,
691   REG_0F3A0F_PREFIX_1_MOD_3,
692   REG_0F71_MOD_0,
693   REG_0F72_MOD_0,
694   REG_0F73_MOD_0,
695   REG_0FA6,
696   REG_0FA7,
697   REG_0FAE,
698   REG_0FBA,
699   REG_0FC7,
700   REG_VEX_0F71_M_0,
701   REG_VEX_0F72_M_0,
702   REG_VEX_0F73_M_0,
703   REG_VEX_0FAE,
704   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
705   REG_VEX_0F38F3_L_0,
706 
707   REG_XOP_09_01_L_0,
708   REG_XOP_09_02_L_0,
709   REG_XOP_09_12_M_1_L_0,
710   REG_XOP_0A_12_L_0,
711 
712   REG_EVEX_0F71,
713   REG_EVEX_0F72,
714   REG_EVEX_0F73,
715   REG_EVEX_0F38C6_M_0_L_2,
716   REG_EVEX_0F38C7_M_0_L_2
717 };
718 
719 enum
720 {
721   MOD_62_32BIT = 0,
722   MOD_8D,
723   MOD_C4_32BIT,
724   MOD_C5_32BIT,
725   MOD_C6_REG_7,
726   MOD_C7_REG_7,
727   MOD_FF_REG_3,
728   MOD_FF_REG_5,
729   MOD_0F01_REG_0,
730   MOD_0F01_REG_1,
731   MOD_0F01_REG_2,
732   MOD_0F01_REG_3,
733   MOD_0F01_REG_5,
734   MOD_0F01_REG_7,
735   MOD_0F12_PREFIX_0,
736   MOD_0F12_PREFIX_2,
737   MOD_0F13,
738   MOD_0F16_PREFIX_0,
739   MOD_0F16_PREFIX_2,
740   MOD_0F17,
741   MOD_0F18_REG_0,
742   MOD_0F18_REG_1,
743   MOD_0F18_REG_2,
744   MOD_0F18_REG_3,
745   MOD_0F1A_PREFIX_0,
746   MOD_0F1B_PREFIX_0,
747   MOD_0F1B_PREFIX_1,
748   MOD_0F1C_PREFIX_0,
749   MOD_0F1E_PREFIX_1,
750   MOD_0F2B_PREFIX_0,
751   MOD_0F2B_PREFIX_1,
752   MOD_0F2B_PREFIX_2,
753   MOD_0F2B_PREFIX_3,
754   MOD_0F50,
755   MOD_0F71,
756   MOD_0F72,
757   MOD_0F73,
758   MOD_0FAE_REG_0,
759   MOD_0FAE_REG_1,
760   MOD_0FAE_REG_2,
761   MOD_0FAE_REG_3,
762   MOD_0FAE_REG_4,
763   MOD_0FAE_REG_5,
764   MOD_0FAE_REG_6,
765   MOD_0FAE_REG_7,
766   MOD_0FB2,
767   MOD_0FB4,
768   MOD_0FB5,
769   MOD_0FC3,
770   MOD_0FC7_REG_3,
771   MOD_0FC7_REG_4,
772   MOD_0FC7_REG_5,
773   MOD_0FC7_REG_6,
774   MOD_0FC7_REG_7,
775   MOD_0FD7,
776   MOD_0FE7_PREFIX_2,
777   MOD_0FF0_PREFIX_3,
778   MOD_0F382A,
779   MOD_0F38DC_PREFIX_1,
780   MOD_0F38DD_PREFIX_1,
781   MOD_0F38DE_PREFIX_1,
782   MOD_0F38DF_PREFIX_1,
783   MOD_0F38F5,
784   MOD_0F38F6_PREFIX_0,
785   MOD_0F38F8_PREFIX_1,
786   MOD_0F38F8_PREFIX_2,
787   MOD_0F38F8_PREFIX_3,
788   MOD_0F38F9,
789   MOD_0F38FA_PREFIX_1,
790   MOD_0F38FB_PREFIX_1,
791   MOD_0F3A0F_PREFIX_1,
792 
793   MOD_VEX_0F12_PREFIX_0,
794   MOD_VEX_0F12_PREFIX_2,
795   MOD_VEX_0F13,
796   MOD_VEX_0F16_PREFIX_0,
797   MOD_VEX_0F16_PREFIX_2,
798   MOD_VEX_0F17,
799   MOD_VEX_0F2B,
800   MOD_VEX_0F41_L_1,
801   MOD_VEX_0F42_L_1,
802   MOD_VEX_0F44_L_0,
803   MOD_VEX_0F45_L_1,
804   MOD_VEX_0F46_L_1,
805   MOD_VEX_0F47_L_1,
806   MOD_VEX_0F4A_L_1,
807   MOD_VEX_0F4B_L_1,
808   MOD_VEX_0F50,
809   MOD_VEX_0F71,
810   MOD_VEX_0F72,
811   MOD_VEX_0F73,
812   MOD_VEX_0F91_L_0,
813   MOD_VEX_0F92_L_0,
814   MOD_VEX_0F93_L_0,
815   MOD_VEX_0F98_L_0,
816   MOD_VEX_0F99_L_0,
817   MOD_VEX_0FAE_REG_2,
818   MOD_VEX_0FAE_REG_3,
819   MOD_VEX_0FD7,
820   MOD_VEX_0FE7,
821   MOD_VEX_0FF0_PREFIX_3,
822   MOD_VEX_0F381A,
823   MOD_VEX_0F382A,
824   MOD_VEX_0F382C,
825   MOD_VEX_0F382D,
826   MOD_VEX_0F382E,
827   MOD_VEX_0F382F,
828   MOD_VEX_0F3849_X86_64_P_0_W_0,
829   MOD_VEX_0F3849_X86_64_P_2_W_0,
830   MOD_VEX_0F3849_X86_64_P_3_W_0,
831   MOD_VEX_0F384B_X86_64_P_1_W_0,
832   MOD_VEX_0F384B_X86_64_P_2_W_0,
833   MOD_VEX_0F384B_X86_64_P_3_W_0,
834   MOD_VEX_0F385A,
835   MOD_VEX_0F385C_X86_64_P_1_W_0,
836   MOD_VEX_0F385E_X86_64_P_0_W_0,
837   MOD_VEX_0F385E_X86_64_P_1_W_0,
838   MOD_VEX_0F385E_X86_64_P_2_W_0,
839   MOD_VEX_0F385E_X86_64_P_3_W_0,
840   MOD_VEX_0F388C,
841   MOD_VEX_0F388E,
842   MOD_VEX_0F3A30_L_0,
843   MOD_VEX_0F3A31_L_0,
844   MOD_VEX_0F3A32_L_0,
845   MOD_VEX_0F3A33_L_0,
846 
847   MOD_XOP_09_12,
848 
849   MOD_EVEX_0F12_PREFIX_0,
850   MOD_EVEX_0F12_PREFIX_2,
851   MOD_EVEX_0F13,
852   MOD_EVEX_0F16_PREFIX_0,
853   MOD_EVEX_0F16_PREFIX_2,
854   MOD_EVEX_0F17,
855   MOD_EVEX_0F2B,
856   MOD_EVEX_0F381A,
857   MOD_EVEX_0F381B,
858   MOD_EVEX_0F3828_P_1,
859   MOD_EVEX_0F382A_P_1_W_1,
860   MOD_EVEX_0F3838_P_1,
861   MOD_EVEX_0F383A_P_1_W_0,
862   MOD_EVEX_0F385A,
863   MOD_EVEX_0F385B,
864   MOD_EVEX_0F387A_W_0,
865   MOD_EVEX_0F387B_W_0,
866   MOD_EVEX_0F387C,
867   MOD_EVEX_0F38C6,
868   MOD_EVEX_0F38C7
869 };
870 
871 enum
872 {
873   RM_C6_REG_7 = 0,
874   RM_C7_REG_7,
875   RM_0F01_REG_0,
876   RM_0F01_REG_1,
877   RM_0F01_REG_2,
878   RM_0F01_REG_3,
879   RM_0F01_REG_5_MOD_3,
880   RM_0F01_REG_7_MOD_3,
881   RM_0F1E_P_1_MOD_3_REG_7,
882   RM_0FAE_REG_6_MOD_3_P_0,
883   RM_0FAE_REG_7_MOD_3,
884   RM_0F3A0F_P_1_MOD_3_REG_0,
885 
886   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
887 };
888 
889 enum
890 {
891   PREFIX_90 = 0,
892   PREFIX_0F01_REG_1_RM_4,
893   PREFIX_0F01_REG_1_RM_5,
894   PREFIX_0F01_REG_1_RM_6,
895   PREFIX_0F01_REG_1_RM_7,
896   PREFIX_0F01_REG_3_RM_1,
897   PREFIX_0F01_REG_5_MOD_0,
898   PREFIX_0F01_REG_5_MOD_3_RM_0,
899   PREFIX_0F01_REG_5_MOD_3_RM_1,
900   PREFIX_0F01_REG_5_MOD_3_RM_2,
901   PREFIX_0F01_REG_5_MOD_3_RM_4,
902   PREFIX_0F01_REG_5_MOD_3_RM_5,
903   PREFIX_0F01_REG_5_MOD_3_RM_6,
904   PREFIX_0F01_REG_5_MOD_3_RM_7,
905   PREFIX_0F01_REG_7_MOD_3_RM_2,
906   PREFIX_0F01_REG_7_MOD_3_RM_6,
907   PREFIX_0F01_REG_7_MOD_3_RM_7,
908   PREFIX_0F09,
909   PREFIX_0F10,
910   PREFIX_0F11,
911   PREFIX_0F12,
912   PREFIX_0F16,
913   PREFIX_0F1A,
914   PREFIX_0F1B,
915   PREFIX_0F1C,
916   PREFIX_0F1E,
917   PREFIX_0F2A,
918   PREFIX_0F2B,
919   PREFIX_0F2C,
920   PREFIX_0F2D,
921   PREFIX_0F2E,
922   PREFIX_0F2F,
923   PREFIX_0F51,
924   PREFIX_0F52,
925   PREFIX_0F53,
926   PREFIX_0F58,
927   PREFIX_0F59,
928   PREFIX_0F5A,
929   PREFIX_0F5B,
930   PREFIX_0F5C,
931   PREFIX_0F5D,
932   PREFIX_0F5E,
933   PREFIX_0F5F,
934   PREFIX_0F60,
935   PREFIX_0F61,
936   PREFIX_0F62,
937   PREFIX_0F6F,
938   PREFIX_0F70,
939   PREFIX_0F78,
940   PREFIX_0F79,
941   PREFIX_0F7C,
942   PREFIX_0F7D,
943   PREFIX_0F7E,
944   PREFIX_0F7F,
945   PREFIX_0FAE_REG_0_MOD_3,
946   PREFIX_0FAE_REG_1_MOD_3,
947   PREFIX_0FAE_REG_2_MOD_3,
948   PREFIX_0FAE_REG_3_MOD_3,
949   PREFIX_0FAE_REG_4_MOD_0,
950   PREFIX_0FAE_REG_4_MOD_3,
951   PREFIX_0FAE_REG_5_MOD_3,
952   PREFIX_0FAE_REG_6_MOD_0,
953   PREFIX_0FAE_REG_6_MOD_3,
954   PREFIX_0FAE_REG_7_MOD_0,
955   PREFIX_0FB8,
956   PREFIX_0FBC,
957   PREFIX_0FBD,
958   PREFIX_0FC2,
959   PREFIX_0FC7_REG_6_MOD_0,
960   PREFIX_0FC7_REG_6_MOD_3,
961   PREFIX_0FC7_REG_7_MOD_3,
962   PREFIX_0FD0,
963   PREFIX_0FD6,
964   PREFIX_0FE6,
965   PREFIX_0FE7,
966   PREFIX_0FF0,
967   PREFIX_0FF7,
968   PREFIX_0F38D8,
969   PREFIX_0F38DC,
970   PREFIX_0F38DD,
971   PREFIX_0F38DE,
972   PREFIX_0F38DF,
973   PREFIX_0F38F0,
974   PREFIX_0F38F1,
975   PREFIX_0F38F6,
976   PREFIX_0F38F8,
977   PREFIX_0F38FA,
978   PREFIX_0F38FB,
979   PREFIX_0F3A0F,
980   PREFIX_VEX_0F10,
981   PREFIX_VEX_0F11,
982   PREFIX_VEX_0F12,
983   PREFIX_VEX_0F16,
984   PREFIX_VEX_0F2A,
985   PREFIX_VEX_0F2C,
986   PREFIX_VEX_0F2D,
987   PREFIX_VEX_0F2E,
988   PREFIX_VEX_0F2F,
989   PREFIX_VEX_0F41_L_1_M_1_W_0,
990   PREFIX_VEX_0F41_L_1_M_1_W_1,
991   PREFIX_VEX_0F42_L_1_M_1_W_0,
992   PREFIX_VEX_0F42_L_1_M_1_W_1,
993   PREFIX_VEX_0F44_L_0_M_1_W_0,
994   PREFIX_VEX_0F44_L_0_M_1_W_1,
995   PREFIX_VEX_0F45_L_1_M_1_W_0,
996   PREFIX_VEX_0F45_L_1_M_1_W_1,
997   PREFIX_VEX_0F46_L_1_M_1_W_0,
998   PREFIX_VEX_0F46_L_1_M_1_W_1,
999   PREFIX_VEX_0F47_L_1_M_1_W_0,
1000   PREFIX_VEX_0F47_L_1_M_1_W_1,
1001   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1002   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1003   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1004   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1005   PREFIX_VEX_0F51,
1006   PREFIX_VEX_0F52,
1007   PREFIX_VEX_0F53,
1008   PREFIX_VEX_0F58,
1009   PREFIX_VEX_0F59,
1010   PREFIX_VEX_0F5A,
1011   PREFIX_VEX_0F5B,
1012   PREFIX_VEX_0F5C,
1013   PREFIX_VEX_0F5D,
1014   PREFIX_VEX_0F5E,
1015   PREFIX_VEX_0F5F,
1016   PREFIX_VEX_0F6F,
1017   PREFIX_VEX_0F70,
1018   PREFIX_VEX_0F7C,
1019   PREFIX_VEX_0F7D,
1020   PREFIX_VEX_0F7E,
1021   PREFIX_VEX_0F7F,
1022   PREFIX_VEX_0F90_L_0_W_0,
1023   PREFIX_VEX_0F90_L_0_W_1,
1024   PREFIX_VEX_0F91_L_0_M_0_W_0,
1025   PREFIX_VEX_0F91_L_0_M_0_W_1,
1026   PREFIX_VEX_0F92_L_0_M_1_W_0,
1027   PREFIX_VEX_0F92_L_0_M_1_W_1,
1028   PREFIX_VEX_0F93_L_0_M_1_W_0,
1029   PREFIX_VEX_0F93_L_0_M_1_W_1,
1030   PREFIX_VEX_0F98_L_0_M_1_W_0,
1031   PREFIX_VEX_0F98_L_0_M_1_W_1,
1032   PREFIX_VEX_0F99_L_0_M_1_W_0,
1033   PREFIX_VEX_0F99_L_0_M_1_W_1,
1034   PREFIX_VEX_0FC2,
1035   PREFIX_VEX_0FD0,
1036   PREFIX_VEX_0FE6,
1037   PREFIX_VEX_0FF0,
1038   PREFIX_VEX_0F3849_X86_64,
1039   PREFIX_VEX_0F384B_X86_64,
1040   PREFIX_VEX_0F385C_X86_64,
1041   PREFIX_VEX_0F385E_X86_64,
1042   PREFIX_VEX_0F38F5_L_0,
1043   PREFIX_VEX_0F38F6_L_0,
1044   PREFIX_VEX_0F38F7_L_0,
1045   PREFIX_VEX_0F3AF0_L_0,
1046 
1047   PREFIX_EVEX_0F10,
1048   PREFIX_EVEX_0F11,
1049   PREFIX_EVEX_0F12,
1050   PREFIX_EVEX_0F16,
1051   PREFIX_EVEX_0F2A,
1052   PREFIX_EVEX_0F51,
1053   PREFIX_EVEX_0F58,
1054   PREFIX_EVEX_0F59,
1055   PREFIX_EVEX_0F5A,
1056   PREFIX_EVEX_0F5B,
1057   PREFIX_EVEX_0F5C,
1058   PREFIX_EVEX_0F5D,
1059   PREFIX_EVEX_0F5E,
1060   PREFIX_EVEX_0F5F,
1061   PREFIX_EVEX_0F6F,
1062   PREFIX_EVEX_0F70,
1063   PREFIX_EVEX_0F78,
1064   PREFIX_EVEX_0F79,
1065   PREFIX_EVEX_0F7A,
1066   PREFIX_EVEX_0F7B,
1067   PREFIX_EVEX_0F7E,
1068   PREFIX_EVEX_0F7F,
1069   PREFIX_EVEX_0FC2,
1070   PREFIX_EVEX_0FE6,
1071   PREFIX_EVEX_0F3810,
1072   PREFIX_EVEX_0F3811,
1073   PREFIX_EVEX_0F3812,
1074   PREFIX_EVEX_0F3813,
1075   PREFIX_EVEX_0F3814,
1076   PREFIX_EVEX_0F3815,
1077   PREFIX_EVEX_0F3820,
1078   PREFIX_EVEX_0F3821,
1079   PREFIX_EVEX_0F3822,
1080   PREFIX_EVEX_0F3823,
1081   PREFIX_EVEX_0F3824,
1082   PREFIX_EVEX_0F3825,
1083   PREFIX_EVEX_0F3826,
1084   PREFIX_EVEX_0F3827,
1085   PREFIX_EVEX_0F3828,
1086   PREFIX_EVEX_0F3829,
1087   PREFIX_EVEX_0F382A,
1088   PREFIX_EVEX_0F3830,
1089   PREFIX_EVEX_0F3831,
1090   PREFIX_EVEX_0F3832,
1091   PREFIX_EVEX_0F3833,
1092   PREFIX_EVEX_0F3834,
1093   PREFIX_EVEX_0F3835,
1094   PREFIX_EVEX_0F3838,
1095   PREFIX_EVEX_0F3839,
1096   PREFIX_EVEX_0F383A,
1097   PREFIX_EVEX_0F3852,
1098   PREFIX_EVEX_0F3853,
1099   PREFIX_EVEX_0F3868,
1100   PREFIX_EVEX_0F3872,
1101   PREFIX_EVEX_0F389A,
1102   PREFIX_EVEX_0F389B,
1103   PREFIX_EVEX_0F38AA,
1104   PREFIX_EVEX_0F38AB,
1105 };
1106 
1107 enum
1108 {
1109   X86_64_06 = 0,
1110   X86_64_07,
1111   X86_64_0E,
1112   X86_64_16,
1113   X86_64_17,
1114   X86_64_1E,
1115   X86_64_1F,
1116   X86_64_27,
1117   X86_64_2F,
1118   X86_64_37,
1119   X86_64_3F,
1120   X86_64_60,
1121   X86_64_61,
1122   X86_64_62,
1123   X86_64_63,
1124   X86_64_6D,
1125   X86_64_6F,
1126   X86_64_82,
1127   X86_64_9A,
1128   X86_64_C2,
1129   X86_64_C3,
1130   X86_64_C4,
1131   X86_64_C5,
1132   X86_64_CE,
1133   X86_64_D4,
1134   X86_64_D5,
1135   X86_64_E8,
1136   X86_64_E9,
1137   X86_64_EA,
1138   X86_64_0F01_REG_0,
1139   X86_64_0F01_REG_1,
1140   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1141   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1142   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1143   X86_64_0F01_REG_2,
1144   X86_64_0F01_REG_3,
1145   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1146   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1147   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1148   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1149   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1150   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1151   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1152   X86_64_0F24,
1153   X86_64_0F26,
1154   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1155 
1156   X86_64_VEX_0F3849,
1157   X86_64_VEX_0F384B,
1158   X86_64_VEX_0F385C,
1159   X86_64_VEX_0F385E
1160 };
1161 
1162 enum
1163 {
1164   THREE_BYTE_0F38 = 0,
1165   THREE_BYTE_0F3A
1166 };
1167 
1168 enum
1169 {
1170   XOP_08 = 0,
1171   XOP_09,
1172   XOP_0A
1173 };
1174 
1175 enum
1176 {
1177   VEX_0F = 0,
1178   VEX_0F38,
1179   VEX_0F3A
1180 };
1181 
1182 enum
1183 {
1184   EVEX_0F = 0,
1185   EVEX_0F38,
1186   EVEX_0F3A
1187 };
1188 
1189 enum
1190 {
1191   VEX_LEN_0F12_P_0_M_0 = 0,
1192   VEX_LEN_0F12_P_0_M_1,
1193 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1194   VEX_LEN_0F13_M_0,
1195   VEX_LEN_0F16_P_0_M_0,
1196   VEX_LEN_0F16_P_0_M_1,
1197 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1198   VEX_LEN_0F17_M_0,
1199   VEX_LEN_0F41,
1200   VEX_LEN_0F42,
1201   VEX_LEN_0F44,
1202   VEX_LEN_0F45,
1203   VEX_LEN_0F46,
1204   VEX_LEN_0F47,
1205   VEX_LEN_0F4A,
1206   VEX_LEN_0F4B,
1207   VEX_LEN_0F6E,
1208   VEX_LEN_0F77,
1209   VEX_LEN_0F7E_P_1,
1210   VEX_LEN_0F7E_P_2,
1211   VEX_LEN_0F90,
1212   VEX_LEN_0F91,
1213   VEX_LEN_0F92,
1214   VEX_LEN_0F93,
1215   VEX_LEN_0F98,
1216   VEX_LEN_0F99,
1217   VEX_LEN_0FAE_R_2_M_0,
1218   VEX_LEN_0FAE_R_3_M_0,
1219   VEX_LEN_0FC4,
1220   VEX_LEN_0FC5,
1221   VEX_LEN_0FD6,
1222   VEX_LEN_0FF7,
1223   VEX_LEN_0F3816,
1224   VEX_LEN_0F3819,
1225   VEX_LEN_0F381A_M_0,
1226   VEX_LEN_0F3836,
1227   VEX_LEN_0F3841,
1228   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1229   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1230   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1231   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1232   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1233   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1234   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1235   VEX_LEN_0F385A_M_0,
1236   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1237   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1238   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1239   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1240   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1241   VEX_LEN_0F38DB,
1242   VEX_LEN_0F38F2,
1243   VEX_LEN_0F38F3,
1244   VEX_LEN_0F38F5,
1245   VEX_LEN_0F38F6,
1246   VEX_LEN_0F38F7,
1247   VEX_LEN_0F3A00,
1248   VEX_LEN_0F3A01,
1249   VEX_LEN_0F3A06,
1250   VEX_LEN_0F3A14,
1251   VEX_LEN_0F3A15,
1252   VEX_LEN_0F3A16,
1253   VEX_LEN_0F3A17,
1254   VEX_LEN_0F3A18,
1255   VEX_LEN_0F3A19,
1256   VEX_LEN_0F3A20,
1257   VEX_LEN_0F3A21,
1258   VEX_LEN_0F3A22,
1259   VEX_LEN_0F3A30,
1260   VEX_LEN_0F3A31,
1261   VEX_LEN_0F3A32,
1262   VEX_LEN_0F3A33,
1263   VEX_LEN_0F3A38,
1264   VEX_LEN_0F3A39,
1265   VEX_LEN_0F3A41,
1266   VEX_LEN_0F3A46,
1267   VEX_LEN_0F3A60,
1268   VEX_LEN_0F3A61,
1269   VEX_LEN_0F3A62,
1270   VEX_LEN_0F3A63,
1271   VEX_LEN_0F3ADF,
1272   VEX_LEN_0F3AF0,
1273   VEX_LEN_0FXOP_08_85,
1274   VEX_LEN_0FXOP_08_86,
1275   VEX_LEN_0FXOP_08_87,
1276   VEX_LEN_0FXOP_08_8E,
1277   VEX_LEN_0FXOP_08_8F,
1278   VEX_LEN_0FXOP_08_95,
1279   VEX_LEN_0FXOP_08_96,
1280   VEX_LEN_0FXOP_08_97,
1281   VEX_LEN_0FXOP_08_9E,
1282   VEX_LEN_0FXOP_08_9F,
1283   VEX_LEN_0FXOP_08_A3,
1284   VEX_LEN_0FXOP_08_A6,
1285   VEX_LEN_0FXOP_08_B6,
1286   VEX_LEN_0FXOP_08_C0,
1287   VEX_LEN_0FXOP_08_C1,
1288   VEX_LEN_0FXOP_08_C2,
1289   VEX_LEN_0FXOP_08_C3,
1290   VEX_LEN_0FXOP_08_CC,
1291   VEX_LEN_0FXOP_08_CD,
1292   VEX_LEN_0FXOP_08_CE,
1293   VEX_LEN_0FXOP_08_CF,
1294   VEX_LEN_0FXOP_08_EC,
1295   VEX_LEN_0FXOP_08_ED,
1296   VEX_LEN_0FXOP_08_EE,
1297   VEX_LEN_0FXOP_08_EF,
1298   VEX_LEN_0FXOP_09_01,
1299   VEX_LEN_0FXOP_09_02,
1300   VEX_LEN_0FXOP_09_12_M_1,
1301   VEX_LEN_0FXOP_09_82_W_0,
1302   VEX_LEN_0FXOP_09_83_W_0,
1303   VEX_LEN_0FXOP_09_90,
1304   VEX_LEN_0FXOP_09_91,
1305   VEX_LEN_0FXOP_09_92,
1306   VEX_LEN_0FXOP_09_93,
1307   VEX_LEN_0FXOP_09_94,
1308   VEX_LEN_0FXOP_09_95,
1309   VEX_LEN_0FXOP_09_96,
1310   VEX_LEN_0FXOP_09_97,
1311   VEX_LEN_0FXOP_09_98,
1312   VEX_LEN_0FXOP_09_99,
1313   VEX_LEN_0FXOP_09_9A,
1314   VEX_LEN_0FXOP_09_9B,
1315   VEX_LEN_0FXOP_09_C1,
1316   VEX_LEN_0FXOP_09_C2,
1317   VEX_LEN_0FXOP_09_C3,
1318   VEX_LEN_0FXOP_09_C6,
1319   VEX_LEN_0FXOP_09_C7,
1320   VEX_LEN_0FXOP_09_CB,
1321   VEX_LEN_0FXOP_09_D1,
1322   VEX_LEN_0FXOP_09_D2,
1323   VEX_LEN_0FXOP_09_D3,
1324   VEX_LEN_0FXOP_09_D6,
1325   VEX_LEN_0FXOP_09_D7,
1326   VEX_LEN_0FXOP_09_DB,
1327   VEX_LEN_0FXOP_09_E1,
1328   VEX_LEN_0FXOP_09_E2,
1329   VEX_LEN_0FXOP_09_E3,
1330   VEX_LEN_0FXOP_0A_12,
1331 };
1332 
1333 enum
1334 {
1335   EVEX_LEN_0F3816 = 0,
1336   EVEX_LEN_0F3819,
1337   EVEX_LEN_0F381A_M_0,
1338   EVEX_LEN_0F381B_M_0,
1339   EVEX_LEN_0F3836,
1340   EVEX_LEN_0F385A_M_0,
1341   EVEX_LEN_0F385B_M_0,
1342   EVEX_LEN_0F38C6_M_0,
1343   EVEX_LEN_0F38C7_M_0,
1344   EVEX_LEN_0F3A00,
1345   EVEX_LEN_0F3A01,
1346   EVEX_LEN_0F3A18,
1347   EVEX_LEN_0F3A19,
1348   EVEX_LEN_0F3A1A,
1349   EVEX_LEN_0F3A1B,
1350   EVEX_LEN_0F3A23,
1351   EVEX_LEN_0F3A38,
1352   EVEX_LEN_0F3A39,
1353   EVEX_LEN_0F3A3A,
1354   EVEX_LEN_0F3A3B,
1355   EVEX_LEN_0F3A43
1356 };
1357 
1358 enum
1359 {
1360   VEX_W_0F41_L_1_M_1 = 0,
1361   VEX_W_0F42_L_1_M_1,
1362   VEX_W_0F44_L_0_M_1,
1363   VEX_W_0F45_L_1_M_1,
1364   VEX_W_0F46_L_1_M_1,
1365   VEX_W_0F47_L_1_M_1,
1366   VEX_W_0F4A_L_1_M_1,
1367   VEX_W_0F4B_L_1_M_1,
1368   VEX_W_0F90_L_0,
1369   VEX_W_0F91_L_0_M_0,
1370   VEX_W_0F92_L_0_M_1,
1371   VEX_W_0F93_L_0_M_1,
1372   VEX_W_0F98_L_0_M_1,
1373   VEX_W_0F99_L_0_M_1,
1374   VEX_W_0F380C,
1375   VEX_W_0F380D,
1376   VEX_W_0F380E,
1377   VEX_W_0F380F,
1378   VEX_W_0F3813,
1379   VEX_W_0F3816_L_1,
1380   VEX_W_0F3818,
1381   VEX_W_0F3819_L_1,
1382   VEX_W_0F381A_M_0_L_1,
1383   VEX_W_0F382C_M_0,
1384   VEX_W_0F382D_M_0,
1385   VEX_W_0F382E_M_0,
1386   VEX_W_0F382F_M_0,
1387   VEX_W_0F3836,
1388   VEX_W_0F3846,
1389   VEX_W_0F3849_X86_64_P_0,
1390   VEX_W_0F3849_X86_64_P_2,
1391   VEX_W_0F3849_X86_64_P_3,
1392   VEX_W_0F384B_X86_64_P_1,
1393   VEX_W_0F384B_X86_64_P_2,
1394   VEX_W_0F384B_X86_64_P_3,
1395   VEX_W_0F3850,
1396   VEX_W_0F3851,
1397   VEX_W_0F3852,
1398   VEX_W_0F3853,
1399   VEX_W_0F3858,
1400   VEX_W_0F3859,
1401   VEX_W_0F385A_M_0_L_0,
1402   VEX_W_0F385C_X86_64_P_1,
1403   VEX_W_0F385E_X86_64_P_0,
1404   VEX_W_0F385E_X86_64_P_1,
1405   VEX_W_0F385E_X86_64_P_2,
1406   VEX_W_0F385E_X86_64_P_3,
1407   VEX_W_0F3878,
1408   VEX_W_0F3879,
1409   VEX_W_0F38CF,
1410   VEX_W_0F3A00_L_1,
1411   VEX_W_0F3A01_L_1,
1412   VEX_W_0F3A02,
1413   VEX_W_0F3A04,
1414   VEX_W_0F3A05,
1415   VEX_W_0F3A06_L_1,
1416   VEX_W_0F3A18_L_1,
1417   VEX_W_0F3A19_L_1,
1418   VEX_W_0F3A1D,
1419   VEX_W_0F3A38_L_1,
1420   VEX_W_0F3A39_L_1,
1421   VEX_W_0F3A46_L_1,
1422   VEX_W_0F3A4A,
1423   VEX_W_0F3A4B,
1424   VEX_W_0F3A4C,
1425   VEX_W_0F3ACE,
1426   VEX_W_0F3ACF,
1427 
1428   VEX_W_0FXOP_08_85_L_0,
1429   VEX_W_0FXOP_08_86_L_0,
1430   VEX_W_0FXOP_08_87_L_0,
1431   VEX_W_0FXOP_08_8E_L_0,
1432   VEX_W_0FXOP_08_8F_L_0,
1433   VEX_W_0FXOP_08_95_L_0,
1434   VEX_W_0FXOP_08_96_L_0,
1435   VEX_W_0FXOP_08_97_L_0,
1436   VEX_W_0FXOP_08_9E_L_0,
1437   VEX_W_0FXOP_08_9F_L_0,
1438   VEX_W_0FXOP_08_A6_L_0,
1439   VEX_W_0FXOP_08_B6_L_0,
1440   VEX_W_0FXOP_08_C0_L_0,
1441   VEX_W_0FXOP_08_C1_L_0,
1442   VEX_W_0FXOP_08_C2_L_0,
1443   VEX_W_0FXOP_08_C3_L_0,
1444   VEX_W_0FXOP_08_CC_L_0,
1445   VEX_W_0FXOP_08_CD_L_0,
1446   VEX_W_0FXOP_08_CE_L_0,
1447   VEX_W_0FXOP_08_CF_L_0,
1448   VEX_W_0FXOP_08_EC_L_0,
1449   VEX_W_0FXOP_08_ED_L_0,
1450   VEX_W_0FXOP_08_EE_L_0,
1451   VEX_W_0FXOP_08_EF_L_0,
1452 
1453   VEX_W_0FXOP_09_80,
1454   VEX_W_0FXOP_09_81,
1455   VEX_W_0FXOP_09_82,
1456   VEX_W_0FXOP_09_83,
1457   VEX_W_0FXOP_09_C1_L_0,
1458   VEX_W_0FXOP_09_C2_L_0,
1459   VEX_W_0FXOP_09_C3_L_0,
1460   VEX_W_0FXOP_09_C6_L_0,
1461   VEX_W_0FXOP_09_C7_L_0,
1462   VEX_W_0FXOP_09_CB_L_0,
1463   VEX_W_0FXOP_09_D1_L_0,
1464   VEX_W_0FXOP_09_D2_L_0,
1465   VEX_W_0FXOP_09_D3_L_0,
1466   VEX_W_0FXOP_09_D6_L_0,
1467   VEX_W_0FXOP_09_D7_L_0,
1468   VEX_W_0FXOP_09_DB_L_0,
1469   VEX_W_0FXOP_09_E1_L_0,
1470   VEX_W_0FXOP_09_E2_L_0,
1471   VEX_W_0FXOP_09_E3_L_0,
1472 
1473   EVEX_W_0F10_P_1,
1474   EVEX_W_0F10_P_3,
1475   EVEX_W_0F11_P_1,
1476   EVEX_W_0F11_P_3,
1477   EVEX_W_0F12_P_0_M_1,
1478   EVEX_W_0F12_P_1,
1479   EVEX_W_0F12_P_3,
1480   EVEX_W_0F16_P_0_M_1,
1481   EVEX_W_0F16_P_1,
1482   EVEX_W_0F2A_P_3,
1483   EVEX_W_0F51_P_1,
1484   EVEX_W_0F51_P_3,
1485   EVEX_W_0F58_P_1,
1486   EVEX_W_0F58_P_3,
1487   EVEX_W_0F59_P_1,
1488   EVEX_W_0F59_P_3,
1489   EVEX_W_0F5A_P_0,
1490   EVEX_W_0F5A_P_1,
1491   EVEX_W_0F5A_P_2,
1492   EVEX_W_0F5A_P_3,
1493   EVEX_W_0F5B_P_0,
1494   EVEX_W_0F5B_P_1,
1495   EVEX_W_0F5B_P_2,
1496   EVEX_W_0F5C_P_1,
1497   EVEX_W_0F5C_P_3,
1498   EVEX_W_0F5D_P_1,
1499   EVEX_W_0F5D_P_3,
1500   EVEX_W_0F5E_P_1,
1501   EVEX_W_0F5E_P_3,
1502   EVEX_W_0F5F_P_1,
1503   EVEX_W_0F5F_P_3,
1504   EVEX_W_0F62,
1505   EVEX_W_0F66,
1506   EVEX_W_0F6A,
1507   EVEX_W_0F6B,
1508   EVEX_W_0F6C,
1509   EVEX_W_0F6D,
1510   EVEX_W_0F6F_P_1,
1511   EVEX_W_0F6F_P_2,
1512   EVEX_W_0F6F_P_3,
1513   EVEX_W_0F70_P_2,
1514   EVEX_W_0F72_R_2,
1515   EVEX_W_0F72_R_6,
1516   EVEX_W_0F73_R_2,
1517   EVEX_W_0F73_R_6,
1518   EVEX_W_0F76,
1519   EVEX_W_0F78_P_0,
1520   EVEX_W_0F78_P_2,
1521   EVEX_W_0F79_P_0,
1522   EVEX_W_0F79_P_2,
1523   EVEX_W_0F7A_P_1,
1524   EVEX_W_0F7A_P_2,
1525   EVEX_W_0F7A_P_3,
1526   EVEX_W_0F7B_P_2,
1527   EVEX_W_0F7B_P_3,
1528   EVEX_W_0F7E_P_1,
1529   EVEX_W_0F7F_P_1,
1530   EVEX_W_0F7F_P_2,
1531   EVEX_W_0F7F_P_3,
1532   EVEX_W_0FC2_P_1,
1533   EVEX_W_0FC2_P_3,
1534   EVEX_W_0FD2,
1535   EVEX_W_0FD3,
1536   EVEX_W_0FD4,
1537   EVEX_W_0FD6,
1538   EVEX_W_0FE6_P_1,
1539   EVEX_W_0FE6_P_2,
1540   EVEX_W_0FE6_P_3,
1541   EVEX_W_0FE7,
1542   EVEX_W_0FF2,
1543   EVEX_W_0FF3,
1544   EVEX_W_0FF4,
1545   EVEX_W_0FFA,
1546   EVEX_W_0FFB,
1547   EVEX_W_0FFE,
1548   EVEX_W_0F380D,
1549   EVEX_W_0F3810_P_1,
1550   EVEX_W_0F3810_P_2,
1551   EVEX_W_0F3811_P_1,
1552   EVEX_W_0F3811_P_2,
1553   EVEX_W_0F3812_P_1,
1554   EVEX_W_0F3812_P_2,
1555   EVEX_W_0F3813_P_1,
1556   EVEX_W_0F3813_P_2,
1557   EVEX_W_0F3814_P_1,
1558   EVEX_W_0F3815_P_1,
1559   EVEX_W_0F3819_L_n,
1560   EVEX_W_0F381A_M_0_L_n,
1561   EVEX_W_0F381B_M_0_L_2,
1562   EVEX_W_0F381E,
1563   EVEX_W_0F381F,
1564   EVEX_W_0F3820_P_1,
1565   EVEX_W_0F3821_P_1,
1566   EVEX_W_0F3822_P_1,
1567   EVEX_W_0F3823_P_1,
1568   EVEX_W_0F3824_P_1,
1569   EVEX_W_0F3825_P_1,
1570   EVEX_W_0F3825_P_2,
1571   EVEX_W_0F3828_P_2,
1572   EVEX_W_0F3829_P_2,
1573   EVEX_W_0F382A_P_1,
1574   EVEX_W_0F382A_P_2,
1575   EVEX_W_0F382B,
1576   EVEX_W_0F3830_P_1,
1577   EVEX_W_0F3831_P_1,
1578   EVEX_W_0F3832_P_1,
1579   EVEX_W_0F3833_P_1,
1580   EVEX_W_0F3834_P_1,
1581   EVEX_W_0F3835_P_1,
1582   EVEX_W_0F3835_P_2,
1583   EVEX_W_0F3837,
1584   EVEX_W_0F383A_P_1,
1585   EVEX_W_0F3852_P_1,
1586   EVEX_W_0F3859,
1587   EVEX_W_0F385A_M_0_L_n,
1588   EVEX_W_0F385B_M_0_L_2,
1589   EVEX_W_0F3870,
1590   EVEX_W_0F3872_P_1,
1591   EVEX_W_0F3872_P_2,
1592   EVEX_W_0F3872_P_3,
1593   EVEX_W_0F387A,
1594   EVEX_W_0F387B,
1595   EVEX_W_0F3883,
1596 
1597   EVEX_W_0F3A05,
1598   EVEX_W_0F3A08,
1599   EVEX_W_0F3A09,
1600   EVEX_W_0F3A0A,
1601   EVEX_W_0F3A0B,
1602   EVEX_W_0F3A18_L_n,
1603   EVEX_W_0F3A19_L_n,
1604   EVEX_W_0F3A1A_L_2,
1605   EVEX_W_0F3A1B_L_2,
1606   EVEX_W_0F3A21,
1607   EVEX_W_0F3A23_L_n,
1608   EVEX_W_0F3A38_L_n,
1609   EVEX_W_0F3A39_L_n,
1610   EVEX_W_0F3A3A_L_2,
1611   EVEX_W_0F3A3B_L_2,
1612   EVEX_W_0F3A42,
1613   EVEX_W_0F3A43_L_n,
1614   EVEX_W_0F3A70,
1615   EVEX_W_0F3A72,
1616 };
1617 
1618 typedef void (*op_rtn) (int bytemode, int sizeflag);
1619 
1620 struct dis386 {
1621   const char *name;
1622   struct
1623     {
1624       op_rtn rtn;
1625       int bytemode;
1626     } op[MAX_OPERANDS];
1627   unsigned int prefix_requirement;
1628 };
1629 
1630 /* Upper case letters in the instruction names here are macros.
1631    'A' => print 'b' if no register operands or suffix_always is true
1632    'B' => print 'b' if suffix_always is true
1633    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1634 	  size prefix
1635    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1636 	  suffix_always is true
1637    'E' => print 'e' if 32-bit form of jcxz
1638    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1639    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1640    'H' => print ",pt" or ",pn" branch hint
1641    'I' unused.
1642    'J' unused.
1643    'K' => print 'd' or 'q' if rex prefix is present.
1644    'L' unused.
1645    'M' => print 'r' if intel_mnemonic is false.
1646    'N' => print 'n' if instruction has no wait "prefix"
1647    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1648    'P' => behave as 'T' except with register operand outside of suffix_always
1649 	  mode
1650    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1651 	  is true
1652    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1653    'S' => print 'w', 'l' or 'q' if suffix_always is true
1654    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1655 	  prefix or if suffix_always is true.
1656    'U' unused.
1657    'V' unused.
1658    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1659    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1660    'Y' unused.
1661    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1662    '!' => change condition from true to false or from false to true.
1663    '%' => add 1 upper case letter to the macro.
1664    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1665 	  prefix or suffix_always is true (lcall/ljmp).
1666    '@' => in 64bit mode for Intel64 ISA or if instruction
1667 	  has no operand sizing prefix, print 'q' if suffix_always is true or
1668 	  nothing otherwise; behave as 'P' in all other cases
1669 
1670    2 upper case letter macros:
1671    "XY" => print 'x' or 'y' if suffix_always is true or no register
1672 	   operands and no broadcast.
1673    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1674 	   register operands and no broadcast.
1675    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1676    "XV" => print "{vex3}" pseudo prefix
1677    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1678 	   being false, or no operand at all in 64bit mode, or if suffix_always
1679 	   is true.
1680    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1681    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1682    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1683    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1684    "BW" => print 'b' or 'w' depending on the VEX.W bit
1685    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1686 	   an operand size prefix, or suffix_always is true.  print
1687 	   'q' if rex prefix is present.
1688 
1689    Many of the above letters print nothing in Intel mode.  See "putop"
1690    for the details.
1691 
1692    Braces '{' and '}', and vertical bars '|', indicate alternative
1693    mnemonic strings for AT&T and Intel.  */
1694 
1695 static const struct dis386 dis386[] = {
1696   /* 00 */
1697   { "addB",		{ Ebh1, Gb }, 0 },
1698   { "addS",		{ Evh1, Gv }, 0 },
1699   { "addB",		{ Gb, EbS }, 0 },
1700   { "addS",		{ Gv, EvS }, 0 },
1701   { "addB",		{ AL, Ib }, 0 },
1702   { "addS",		{ eAX, Iv }, 0 },
1703   { X86_64_TABLE (X86_64_06) },
1704   { X86_64_TABLE (X86_64_07) },
1705   /* 08 */
1706   { "orB",		{ Ebh1, Gb }, 0 },
1707   { "orS",		{ Evh1, Gv }, 0 },
1708   { "orB",		{ Gb, EbS }, 0 },
1709   { "orS",		{ Gv, EvS }, 0 },
1710   { "orB",		{ AL, Ib }, 0 },
1711   { "orS",		{ eAX, Iv }, 0 },
1712   { X86_64_TABLE (X86_64_0E) },
1713   { Bad_Opcode },	/* 0x0f extended opcode escape */
1714   /* 10 */
1715   { "adcB",		{ Ebh1, Gb }, 0 },
1716   { "adcS",		{ Evh1, Gv }, 0 },
1717   { "adcB",		{ Gb, EbS }, 0 },
1718   { "adcS",		{ Gv, EvS }, 0 },
1719   { "adcB",		{ AL, Ib }, 0 },
1720   { "adcS",		{ eAX, Iv }, 0 },
1721   { X86_64_TABLE (X86_64_16) },
1722   { X86_64_TABLE (X86_64_17) },
1723   /* 18 */
1724   { "sbbB",		{ Ebh1, Gb }, 0 },
1725   { "sbbS",		{ Evh1, Gv }, 0 },
1726   { "sbbB",		{ Gb, EbS }, 0 },
1727   { "sbbS",		{ Gv, EvS }, 0 },
1728   { "sbbB",		{ AL, Ib }, 0 },
1729   { "sbbS",		{ eAX, Iv }, 0 },
1730   { X86_64_TABLE (X86_64_1E) },
1731   { X86_64_TABLE (X86_64_1F) },
1732   /* 20 */
1733   { "andB",		{ Ebh1, Gb }, 0 },
1734   { "andS",		{ Evh1, Gv }, 0 },
1735   { "andB",		{ Gb, EbS }, 0 },
1736   { "andS",		{ Gv, EvS }, 0 },
1737   { "andB",		{ AL, Ib }, 0 },
1738   { "andS",		{ eAX, Iv }, 0 },
1739   { Bad_Opcode },	/* SEG ES prefix */
1740   { X86_64_TABLE (X86_64_27) },
1741   /* 28 */
1742   { "subB",		{ Ebh1, Gb }, 0 },
1743   { "subS",		{ Evh1, Gv }, 0 },
1744   { "subB",		{ Gb, EbS }, 0 },
1745   { "subS",		{ Gv, EvS }, 0 },
1746   { "subB",		{ AL, Ib }, 0 },
1747   { "subS",		{ eAX, Iv }, 0 },
1748   { Bad_Opcode },	/* SEG CS prefix */
1749   { X86_64_TABLE (X86_64_2F) },
1750   /* 30 */
1751   { "xorB",		{ Ebh1, Gb }, 0 },
1752   { "xorS",		{ Evh1, Gv }, 0 },
1753   { "xorB",		{ Gb, EbS }, 0 },
1754   { "xorS",		{ Gv, EvS }, 0 },
1755   { "xorB",		{ AL, Ib }, 0 },
1756   { "xorS",		{ eAX, Iv }, 0 },
1757   { Bad_Opcode },	/* SEG SS prefix */
1758   { X86_64_TABLE (X86_64_37) },
1759   /* 38 */
1760   { "cmpB",		{ Eb, Gb }, 0 },
1761   { "cmpS",		{ Ev, Gv }, 0 },
1762   { "cmpB",		{ Gb, EbS }, 0 },
1763   { "cmpS",		{ Gv, EvS }, 0 },
1764   { "cmpB",		{ AL, Ib }, 0 },
1765   { "cmpS",		{ eAX, Iv }, 0 },
1766   { Bad_Opcode },	/* SEG DS prefix */
1767   { X86_64_TABLE (X86_64_3F) },
1768   /* 40 */
1769   { "inc{S|}",		{ RMeAX }, 0 },
1770   { "inc{S|}",		{ RMeCX }, 0 },
1771   { "inc{S|}",		{ RMeDX }, 0 },
1772   { "inc{S|}",		{ RMeBX }, 0 },
1773   { "inc{S|}",		{ RMeSP }, 0 },
1774   { "inc{S|}",		{ RMeBP }, 0 },
1775   { "inc{S|}",		{ RMeSI }, 0 },
1776   { "inc{S|}",		{ RMeDI }, 0 },
1777   /* 48 */
1778   { "dec{S|}",		{ RMeAX }, 0 },
1779   { "dec{S|}",		{ RMeCX }, 0 },
1780   { "dec{S|}",		{ RMeDX }, 0 },
1781   { "dec{S|}",		{ RMeBX }, 0 },
1782   { "dec{S|}",		{ RMeSP }, 0 },
1783   { "dec{S|}",		{ RMeBP }, 0 },
1784   { "dec{S|}",		{ RMeSI }, 0 },
1785   { "dec{S|}",		{ RMeDI }, 0 },
1786   /* 50 */
1787   { "push{!P|}",		{ RMrAX }, 0 },
1788   { "push{!P|}",		{ RMrCX }, 0 },
1789   { "push{!P|}",		{ RMrDX }, 0 },
1790   { "push{!P|}",		{ RMrBX }, 0 },
1791   { "push{!P|}",		{ RMrSP }, 0 },
1792   { "push{!P|}",		{ RMrBP }, 0 },
1793   { "push{!P|}",		{ RMrSI }, 0 },
1794   { "push{!P|}",		{ RMrDI }, 0 },
1795   /* 58 */
1796   { "pop{!P|}",		{ RMrAX }, 0 },
1797   { "pop{!P|}",		{ RMrCX }, 0 },
1798   { "pop{!P|}",		{ RMrDX }, 0 },
1799   { "pop{!P|}",		{ RMrBX }, 0 },
1800   { "pop{!P|}",		{ RMrSP }, 0 },
1801   { "pop{!P|}",		{ RMrBP }, 0 },
1802   { "pop{!P|}",		{ RMrSI }, 0 },
1803   { "pop{!P|}",		{ RMrDI }, 0 },
1804   /* 60 */
1805   { X86_64_TABLE (X86_64_60) },
1806   { X86_64_TABLE (X86_64_61) },
1807   { X86_64_TABLE (X86_64_62) },
1808   { X86_64_TABLE (X86_64_63) },
1809   { Bad_Opcode },	/* seg fs */
1810   { Bad_Opcode },	/* seg gs */
1811   { Bad_Opcode },	/* op size prefix */
1812   { Bad_Opcode },	/* adr size prefix */
1813   /* 68 */
1814   { "pushP",		{ sIv }, 0 },
1815   { "imulS",		{ Gv, Ev, Iv }, 0 },
1816   { "pushP",		{ sIbT }, 0 },
1817   { "imulS",		{ Gv, Ev, sIb }, 0 },
1818   { "ins{b|}",		{ Ybr, indirDX }, 0 },
1819   { X86_64_TABLE (X86_64_6D) },
1820   { "outs{b|}",		{ indirDXr, Xb }, 0 },
1821   { X86_64_TABLE (X86_64_6F) },
1822   /* 70 */
1823   { "joH",		{ Jb, BND, cond_jump_flag }, 0 },
1824   { "jnoH",		{ Jb, BND, cond_jump_flag }, 0 },
1825   { "jbH",		{ Jb, BND, cond_jump_flag }, 0 },
1826   { "jaeH",		{ Jb, BND, cond_jump_flag }, 0 },
1827   { "jeH",		{ Jb, BND, cond_jump_flag }, 0 },
1828   { "jneH",		{ Jb, BND, cond_jump_flag }, 0 },
1829   { "jbeH",		{ Jb, BND, cond_jump_flag }, 0 },
1830   { "jaH",		{ Jb, BND, cond_jump_flag }, 0 },
1831   /* 78 */
1832   { "jsH",		{ Jb, BND, cond_jump_flag }, 0 },
1833   { "jnsH",		{ Jb, BND, cond_jump_flag }, 0 },
1834   { "jpH",		{ Jb, BND, cond_jump_flag }, 0 },
1835   { "jnpH",		{ Jb, BND, cond_jump_flag }, 0 },
1836   { "jlH",		{ Jb, BND, cond_jump_flag }, 0 },
1837   { "jgeH",		{ Jb, BND, cond_jump_flag }, 0 },
1838   { "jleH",		{ Jb, BND, cond_jump_flag }, 0 },
1839   { "jgH",		{ Jb, BND, cond_jump_flag }, 0 },
1840   /* 80 */
1841   { REG_TABLE (REG_80) },
1842   { REG_TABLE (REG_81) },
1843   { X86_64_TABLE (X86_64_82) },
1844   { REG_TABLE (REG_83) },
1845   { "testB",		{ Eb, Gb }, 0 },
1846   { "testS",		{ Ev, Gv }, 0 },
1847   { "xchgB",		{ Ebh2, Gb }, 0 },
1848   { "xchgS",		{ Evh2, Gv }, 0 },
1849   /* 88 */
1850   { "movB",		{ Ebh3, Gb }, 0 },
1851   { "movS",		{ Evh3, Gv }, 0 },
1852   { "movB",		{ Gb, EbS }, 0 },
1853   { "movS",		{ Gv, EvS }, 0 },
1854   { "movD",		{ Sv, Sw }, 0 },
1855   { MOD_TABLE (MOD_8D) },
1856   { "movD",		{ Sw, Sv }, 0 },
1857   { REG_TABLE (REG_8F) },
1858   /* 90 */
1859   { PREFIX_TABLE (PREFIX_90) },
1860   { "xchgS",		{ RMeCX, eAX }, 0 },
1861   { "xchgS",		{ RMeDX, eAX }, 0 },
1862   { "xchgS",		{ RMeBX, eAX }, 0 },
1863   { "xchgS",		{ RMeSP, eAX }, 0 },
1864   { "xchgS",		{ RMeBP, eAX }, 0 },
1865   { "xchgS",		{ RMeSI, eAX }, 0 },
1866   { "xchgS",		{ RMeDI, eAX }, 0 },
1867   /* 98 */
1868   { "cW{t|}R",		{ XX }, 0 },
1869   { "cR{t|}O",		{ XX }, 0 },
1870   { X86_64_TABLE (X86_64_9A) },
1871   { Bad_Opcode },	/* fwait */
1872   { "pushfP",		{ XX }, 0 },
1873   { "popfP",		{ XX }, 0 },
1874   { "sahf",		{ XX }, 0 },
1875   { "lahf",		{ XX }, 0 },
1876   /* a0 */
1877   { "mov%LB",		{ AL, Ob }, 0 },
1878   { "mov%LS",		{ eAX, Ov }, 0 },
1879   { "mov%LB",		{ Ob, AL }, 0 },
1880   { "mov%LS",		{ Ov, eAX }, 0 },
1881   { "movs{b|}",		{ Ybr, Xb }, 0 },
1882   { "movs{R|}",		{ Yvr, Xv }, 0 },
1883   { "cmps{b|}",		{ Xb, Yb }, 0 },
1884   { "cmps{R|}",		{ Xv, Yv }, 0 },
1885   /* a8 */
1886   { "testB",		{ AL, Ib }, 0 },
1887   { "testS",		{ eAX, Iv }, 0 },
1888   { "stosB",		{ Ybr, AL }, 0 },
1889   { "stosS",		{ Yvr, eAX }, 0 },
1890   { "lodsB",		{ ALr, Xb }, 0 },
1891   { "lodsS",		{ eAXr, Xv }, 0 },
1892   { "scasB",		{ AL, Yb }, 0 },
1893   { "scasS",		{ eAX, Yv }, 0 },
1894   /* b0 */
1895   { "movB",		{ RMAL, Ib }, 0 },
1896   { "movB",		{ RMCL, Ib }, 0 },
1897   { "movB",		{ RMDL, Ib }, 0 },
1898   { "movB",		{ RMBL, Ib }, 0 },
1899   { "movB",		{ RMAH, Ib }, 0 },
1900   { "movB",		{ RMCH, Ib }, 0 },
1901   { "movB",		{ RMDH, Ib }, 0 },
1902   { "movB",		{ RMBH, Ib }, 0 },
1903   /* b8 */
1904   { "mov%LV",		{ RMeAX, Iv64 }, 0 },
1905   { "mov%LV",		{ RMeCX, Iv64 }, 0 },
1906   { "mov%LV",		{ RMeDX, Iv64 }, 0 },
1907   { "mov%LV",		{ RMeBX, Iv64 }, 0 },
1908   { "mov%LV",		{ RMeSP, Iv64 }, 0 },
1909   { "mov%LV",		{ RMeBP, Iv64 }, 0 },
1910   { "mov%LV",		{ RMeSI, Iv64 }, 0 },
1911   { "mov%LV",		{ RMeDI, Iv64 }, 0 },
1912   /* c0 */
1913   { REG_TABLE (REG_C0) },
1914   { REG_TABLE (REG_C1) },
1915   { X86_64_TABLE (X86_64_C2) },
1916   { X86_64_TABLE (X86_64_C3) },
1917   { X86_64_TABLE (X86_64_C4) },
1918   { X86_64_TABLE (X86_64_C5) },
1919   { REG_TABLE (REG_C6) },
1920   { REG_TABLE (REG_C7) },
1921   /* c8 */
1922   { "enterP",		{ Iw, Ib }, 0 },
1923   { "leaveP",		{ XX }, 0 },
1924   { "{l|}ret{|f}%LP",	{ Iw }, 0 },
1925   { "{l|}ret{|f}%LP",	{ XX }, 0 },
1926   { "int3",		{ XX }, 0 },
1927   { "int",		{ Ib }, 0 },
1928   { X86_64_TABLE (X86_64_CE) },
1929   { "iret%LP",		{ XX }, 0 },
1930   /* d0 */
1931   { REG_TABLE (REG_D0) },
1932   { REG_TABLE (REG_D1) },
1933   { REG_TABLE (REG_D2) },
1934   { REG_TABLE (REG_D3) },
1935   { X86_64_TABLE (X86_64_D4) },
1936   { X86_64_TABLE (X86_64_D5) },
1937   { Bad_Opcode },
1938   { "xlat",		{ DSBX }, 0 },
1939   /* d8 */
1940   { FLOAT },
1941   { FLOAT },
1942   { FLOAT },
1943   { FLOAT },
1944   { FLOAT },
1945   { FLOAT },
1946   { FLOAT },
1947   { FLOAT },
1948   /* e0 */
1949   { "loopneFH",		{ Jb, XX, loop_jcxz_flag }, 0 },
1950   { "loopeFH",		{ Jb, XX, loop_jcxz_flag }, 0 },
1951   { "loopFH",		{ Jb, XX, loop_jcxz_flag }, 0 },
1952   { "jEcxzH",		{ Jb, XX, loop_jcxz_flag }, 0 },
1953   { "inB",		{ AL, Ib }, 0 },
1954   { "inG",		{ zAX, Ib }, 0 },
1955   { "outB",		{ Ib, AL }, 0 },
1956   { "outG",		{ Ib, zAX }, 0 },
1957   /* e8 */
1958   { X86_64_TABLE (X86_64_E8) },
1959   { X86_64_TABLE (X86_64_E9) },
1960   { X86_64_TABLE (X86_64_EA) },
1961   { "jmp",		{ Jb, BND }, 0 },
1962   { "inB",		{ AL, indirDX }, 0 },
1963   { "inG",		{ zAX, indirDX }, 0 },
1964   { "outB",		{ indirDX, AL }, 0 },
1965   { "outG",		{ indirDX, zAX }, 0 },
1966   /* f0 */
1967   { Bad_Opcode },	/* lock prefix */
1968   { "icebp",		{ XX }, 0 },
1969   { Bad_Opcode },	/* repne */
1970   { Bad_Opcode },	/* repz */
1971   { "hlt",		{ XX }, 0 },
1972   { "cmc",		{ XX }, 0 },
1973   { REG_TABLE (REG_F6) },
1974   { REG_TABLE (REG_F7) },
1975   /* f8 */
1976   { "clc",		{ XX }, 0 },
1977   { "stc",		{ XX }, 0 },
1978   { "cli",		{ XX }, 0 },
1979   { "sti",		{ XX }, 0 },
1980   { "cld",		{ XX }, 0 },
1981   { "std",		{ XX }, 0 },
1982   { REG_TABLE (REG_FE) },
1983   { REG_TABLE (REG_FF) },
1984 };
1985 
1986 static const struct dis386 dis386_twobyte[] = {
1987   /* 00 */
1988   { REG_TABLE (REG_0F00 ) },
1989   { REG_TABLE (REG_0F01 ) },
1990   { "larS",		{ Gv, Ew }, 0 },
1991   { "lslS",		{ Gv, Ew }, 0 },
1992   { Bad_Opcode },
1993   { "syscall",		{ XX }, 0 },
1994   { "clts",		{ XX }, 0 },
1995   { "sysret%LQ",		{ XX }, 0 },
1996   /* 08 */
1997   { "invd",		{ XX }, 0 },
1998   { PREFIX_TABLE (PREFIX_0F09) },
1999   { Bad_Opcode },
2000   { "ud2",		{ XX }, 0 },
2001   { Bad_Opcode },
2002   { REG_TABLE (REG_0F0D) },
2003   { "femms",		{ XX }, 0 },
2004   { "",			{ MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2005   /* 10 */
2006   { PREFIX_TABLE (PREFIX_0F10) },
2007   { PREFIX_TABLE (PREFIX_0F11) },
2008   { PREFIX_TABLE (PREFIX_0F12) },
2009   { MOD_TABLE (MOD_0F13) },
2010   { "unpcklpX",		{ XM, EXx }, PREFIX_OPCODE },
2011   { "unpckhpX",		{ XM, EXx }, PREFIX_OPCODE },
2012   { PREFIX_TABLE (PREFIX_0F16) },
2013   { MOD_TABLE (MOD_0F17) },
2014   /* 18 */
2015   { REG_TABLE (REG_0F18) },
2016   { "nopQ",		{ Ev }, 0 },
2017   { PREFIX_TABLE (PREFIX_0F1A) },
2018   { PREFIX_TABLE (PREFIX_0F1B) },
2019   { PREFIX_TABLE (PREFIX_0F1C) },
2020   { "nopQ",		{ Ev }, 0 },
2021   { PREFIX_TABLE (PREFIX_0F1E) },
2022   { "nopQ",		{ Ev }, 0 },
2023   /* 20 */
2024   { "movZ",		{ Em, Cm }, 0 },
2025   { "movZ",		{ Em, Dm }, 0 },
2026   { "movZ",		{ Cm, Em }, 0 },
2027   { "movZ",		{ Dm, Em }, 0 },
2028   { X86_64_TABLE (X86_64_0F24) },
2029   { Bad_Opcode },
2030   { X86_64_TABLE (X86_64_0F26) },
2031   { Bad_Opcode },
2032   /* 28 */
2033   { "movapX",		{ XM, EXx }, PREFIX_OPCODE },
2034   { "movapX",		{ EXxS, XM }, PREFIX_OPCODE },
2035   { PREFIX_TABLE (PREFIX_0F2A) },
2036   { PREFIX_TABLE (PREFIX_0F2B) },
2037   { PREFIX_TABLE (PREFIX_0F2C) },
2038   { PREFIX_TABLE (PREFIX_0F2D) },
2039   { PREFIX_TABLE (PREFIX_0F2E) },
2040   { PREFIX_TABLE (PREFIX_0F2F) },
2041   /* 30 */
2042   { "wrmsr",		{ XX }, 0 },
2043   { "rdtsc",		{ XX }, 0 },
2044   { "rdmsr",		{ XX }, 0 },
2045   { "rdpmc",		{ XX }, 0 },
2046   { "sysenter",		{ SEP }, 0 },
2047   { "sysexit%LQ",	{ SEP }, 0 },
2048   { Bad_Opcode },
2049   { "getsec",		{ XX }, 0 },
2050   /* 38 */
2051   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2052   { Bad_Opcode },
2053   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2054   { Bad_Opcode },
2055   { Bad_Opcode },
2056   { Bad_Opcode },
2057   { Bad_Opcode },
2058   { Bad_Opcode },
2059   /* 40 */
2060   { "cmovoS",		{ Gv, Ev }, 0 },
2061   { "cmovnoS",		{ Gv, Ev }, 0 },
2062   { "cmovbS",		{ Gv, Ev }, 0 },
2063   { "cmovaeS",		{ Gv, Ev }, 0 },
2064   { "cmoveS",		{ Gv, Ev }, 0 },
2065   { "cmovneS",		{ Gv, Ev }, 0 },
2066   { "cmovbeS",		{ Gv, Ev }, 0 },
2067   { "cmovaS",		{ Gv, Ev }, 0 },
2068   /* 48 */
2069   { "cmovsS",		{ Gv, Ev }, 0 },
2070   { "cmovnsS",		{ Gv, Ev }, 0 },
2071   { "cmovpS",		{ Gv, Ev }, 0 },
2072   { "cmovnpS",		{ Gv, Ev }, 0 },
2073   { "cmovlS",		{ Gv, Ev }, 0 },
2074   { "cmovgeS",		{ Gv, Ev }, 0 },
2075   { "cmovleS",		{ Gv, Ev }, 0 },
2076   { "cmovgS",		{ Gv, Ev }, 0 },
2077   /* 50 */
2078   { MOD_TABLE (MOD_0F50) },
2079   { PREFIX_TABLE (PREFIX_0F51) },
2080   { PREFIX_TABLE (PREFIX_0F52) },
2081   { PREFIX_TABLE (PREFIX_0F53) },
2082   { "andpX",		{ XM, EXx }, PREFIX_OPCODE },
2083   { "andnpX",		{ XM, EXx }, PREFIX_OPCODE },
2084   { "orpX",		{ XM, EXx }, PREFIX_OPCODE },
2085   { "xorpX",		{ XM, EXx }, PREFIX_OPCODE },
2086   /* 58 */
2087   { PREFIX_TABLE (PREFIX_0F58) },
2088   { PREFIX_TABLE (PREFIX_0F59) },
2089   { PREFIX_TABLE (PREFIX_0F5A) },
2090   { PREFIX_TABLE (PREFIX_0F5B) },
2091   { PREFIX_TABLE (PREFIX_0F5C) },
2092   { PREFIX_TABLE (PREFIX_0F5D) },
2093   { PREFIX_TABLE (PREFIX_0F5E) },
2094   { PREFIX_TABLE (PREFIX_0F5F) },
2095   /* 60 */
2096   { PREFIX_TABLE (PREFIX_0F60) },
2097   { PREFIX_TABLE (PREFIX_0F61) },
2098   { PREFIX_TABLE (PREFIX_0F62) },
2099   { "packsswb",		{ MX, EM }, PREFIX_OPCODE },
2100   { "pcmpgtb",		{ MX, EM }, PREFIX_OPCODE },
2101   { "pcmpgtw",		{ MX, EM }, PREFIX_OPCODE },
2102   { "pcmpgtd",		{ MX, EM }, PREFIX_OPCODE },
2103   { "packuswb",		{ MX, EM }, PREFIX_OPCODE },
2104   /* 68 */
2105   { "punpckhbw",	{ MX, EM }, PREFIX_OPCODE },
2106   { "punpckhwd",	{ MX, EM }, PREFIX_OPCODE },
2107   { "punpckhdq",	{ MX, EM }, PREFIX_OPCODE },
2108   { "packssdw",		{ MX, EM }, PREFIX_OPCODE },
2109   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2110   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2111   { "movK",		{ MX, Edq }, PREFIX_OPCODE },
2112   { PREFIX_TABLE (PREFIX_0F6F) },
2113   /* 70 */
2114   { PREFIX_TABLE (PREFIX_0F70) },
2115   { MOD_TABLE (MOD_0F71) },
2116   { MOD_TABLE (MOD_0F72) },
2117   { MOD_TABLE (MOD_0F73) },
2118   { "pcmpeqb",		{ MX, EM }, PREFIX_OPCODE },
2119   { "pcmpeqw",		{ MX, EM }, PREFIX_OPCODE },
2120   { "pcmpeqd",		{ MX, EM }, PREFIX_OPCODE },
2121   { "emms",		{ XX }, PREFIX_OPCODE },
2122   /* 78 */
2123   { PREFIX_TABLE (PREFIX_0F78) },
2124   { PREFIX_TABLE (PREFIX_0F79) },
2125   { Bad_Opcode },
2126   { Bad_Opcode },
2127   { PREFIX_TABLE (PREFIX_0F7C) },
2128   { PREFIX_TABLE (PREFIX_0F7D) },
2129   { PREFIX_TABLE (PREFIX_0F7E) },
2130   { PREFIX_TABLE (PREFIX_0F7F) },
2131   /* 80 */
2132   { "joH",		{ Jv, BND, cond_jump_flag }, 0 },
2133   { "jnoH",		{ Jv, BND, cond_jump_flag }, 0 },
2134   { "jbH",		{ Jv, BND, cond_jump_flag }, 0 },
2135   { "jaeH",		{ Jv, BND, cond_jump_flag }, 0 },
2136   { "jeH",		{ Jv, BND, cond_jump_flag }, 0 },
2137   { "jneH",		{ Jv, BND, cond_jump_flag }, 0 },
2138   { "jbeH",		{ Jv, BND, cond_jump_flag }, 0 },
2139   { "jaH",		{ Jv, BND, cond_jump_flag }, 0 },
2140   /* 88 */
2141   { "jsH",		{ Jv, BND, cond_jump_flag }, 0 },
2142   { "jnsH",		{ Jv, BND, cond_jump_flag }, 0 },
2143   { "jpH",		{ Jv, BND, cond_jump_flag }, 0 },
2144   { "jnpH",		{ Jv, BND, cond_jump_flag }, 0 },
2145   { "jlH",		{ Jv, BND, cond_jump_flag }, 0 },
2146   { "jgeH",		{ Jv, BND, cond_jump_flag }, 0 },
2147   { "jleH",		{ Jv, BND, cond_jump_flag }, 0 },
2148   { "jgH",		{ Jv, BND, cond_jump_flag }, 0 },
2149   /* 90 */
2150   { "seto",		{ Eb }, 0 },
2151   { "setno",		{ Eb }, 0 },
2152   { "setb",		{ Eb }, 0 },
2153   { "setae",		{ Eb }, 0 },
2154   { "sete",		{ Eb }, 0 },
2155   { "setne",		{ Eb }, 0 },
2156   { "setbe",		{ Eb }, 0 },
2157   { "seta",		{ Eb }, 0 },
2158   /* 98 */
2159   { "sets",		{ Eb }, 0 },
2160   { "setns",		{ Eb }, 0 },
2161   { "setp",		{ Eb }, 0 },
2162   { "setnp",		{ Eb }, 0 },
2163   { "setl",		{ Eb }, 0 },
2164   { "setge",		{ Eb }, 0 },
2165   { "setle",		{ Eb }, 0 },
2166   { "setg",		{ Eb }, 0 },
2167   /* a0 */
2168   { "pushP",		{ fs }, 0 },
2169   { "popP",		{ fs }, 0 },
2170   { "cpuid",		{ XX }, 0 },
2171   { "btS",		{ Ev, Gv }, 0 },
2172   { "shldS",		{ Ev, Gv, Ib }, 0 },
2173   { "shldS",		{ Ev, Gv, CL }, 0 },
2174   { REG_TABLE (REG_0FA6) },
2175   { REG_TABLE (REG_0FA7) },
2176   /* a8 */
2177   { "pushP",		{ gs }, 0 },
2178   { "popP",		{ gs }, 0 },
2179   { "rsm",		{ XX }, 0 },
2180   { "btsS",		{ Evh1, Gv }, 0 },
2181   { "shrdS",		{ Ev, Gv, Ib }, 0 },
2182   { "shrdS",		{ Ev, Gv, CL }, 0 },
2183   { REG_TABLE (REG_0FAE) },
2184   { "imulS",		{ Gv, Ev }, 0 },
2185   /* b0 */
2186   { "cmpxchgB",		{ Ebh1, Gb }, 0 },
2187   { "cmpxchgS",		{ Evh1, Gv }, 0 },
2188   { MOD_TABLE (MOD_0FB2) },
2189   { "btrS",		{ Evh1, Gv }, 0 },
2190   { MOD_TABLE (MOD_0FB4) },
2191   { MOD_TABLE (MOD_0FB5) },
2192   { "movz{bR|x}",	{ Gv, Eb }, 0 },
2193   { "movz{wR|x}",	{ Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2194   /* b8 */
2195   { PREFIX_TABLE (PREFIX_0FB8) },
2196   { "ud1S",		{ Gv, Ev }, 0 },
2197   { REG_TABLE (REG_0FBA) },
2198   { "btcS",		{ Evh1, Gv }, 0 },
2199   { PREFIX_TABLE (PREFIX_0FBC) },
2200   { PREFIX_TABLE (PREFIX_0FBD) },
2201   { "movs{bR|x}",	{ Gv, Eb }, 0 },
2202   { "movs{wR|x}",	{ Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2203   /* c0 */
2204   { "xaddB",		{ Ebh1, Gb }, 0 },
2205   { "xaddS",		{ Evh1, Gv }, 0 },
2206   { PREFIX_TABLE (PREFIX_0FC2) },
2207   { MOD_TABLE (MOD_0FC3) },
2208   { "pinsrw",		{ MX, Edqw, Ib }, PREFIX_OPCODE },
2209   { "pextrw",		{ Gdq, MS, Ib }, PREFIX_OPCODE },
2210   { "shufpX",		{ XM, EXx, Ib }, PREFIX_OPCODE },
2211   { REG_TABLE (REG_0FC7) },
2212   /* c8 */
2213   { "bswap",		{ RMeAX }, 0 },
2214   { "bswap",		{ RMeCX }, 0 },
2215   { "bswap",		{ RMeDX }, 0 },
2216   { "bswap",		{ RMeBX }, 0 },
2217   { "bswap",		{ RMeSP }, 0 },
2218   { "bswap",		{ RMeBP }, 0 },
2219   { "bswap",		{ RMeSI }, 0 },
2220   { "bswap",		{ RMeDI }, 0 },
2221   /* d0 */
2222   { PREFIX_TABLE (PREFIX_0FD0) },
2223   { "psrlw",		{ MX, EM }, PREFIX_OPCODE },
2224   { "psrld",		{ MX, EM }, PREFIX_OPCODE },
2225   { "psrlq",		{ MX, EM }, PREFIX_OPCODE },
2226   { "paddq",		{ MX, EM }, PREFIX_OPCODE },
2227   { "pmullw",		{ MX, EM }, PREFIX_OPCODE },
2228   { PREFIX_TABLE (PREFIX_0FD6) },
2229   { MOD_TABLE (MOD_0FD7) },
2230   /* d8 */
2231   { "psubusb",		{ MX, EM }, PREFIX_OPCODE },
2232   { "psubusw",		{ MX, EM }, PREFIX_OPCODE },
2233   { "pminub",		{ MX, EM }, PREFIX_OPCODE },
2234   { "pand",		{ MX, EM }, PREFIX_OPCODE },
2235   { "paddusb",		{ MX, EM }, PREFIX_OPCODE },
2236   { "paddusw",		{ MX, EM }, PREFIX_OPCODE },
2237   { "pmaxub",		{ MX, EM }, PREFIX_OPCODE },
2238   { "pandn",		{ MX, EM }, PREFIX_OPCODE },
2239   /* e0 */
2240   { "pavgb",		{ MX, EM }, PREFIX_OPCODE },
2241   { "psraw",		{ MX, EM }, PREFIX_OPCODE },
2242   { "psrad",		{ MX, EM }, PREFIX_OPCODE },
2243   { "pavgw",		{ MX, EM }, PREFIX_OPCODE },
2244   { "pmulhuw",		{ MX, EM }, PREFIX_OPCODE },
2245   { "pmulhw",		{ MX, EM }, PREFIX_OPCODE },
2246   { PREFIX_TABLE (PREFIX_0FE6) },
2247   { PREFIX_TABLE (PREFIX_0FE7) },
2248   /* e8 */
2249   { "psubsb",		{ MX, EM }, PREFIX_OPCODE },
2250   { "psubsw",		{ MX, EM }, PREFIX_OPCODE },
2251   { "pminsw",		{ MX, EM }, PREFIX_OPCODE },
2252   { "por",		{ MX, EM }, PREFIX_OPCODE },
2253   { "paddsb",		{ MX, EM }, PREFIX_OPCODE },
2254   { "paddsw",		{ MX, EM }, PREFIX_OPCODE },
2255   { "pmaxsw",		{ MX, EM }, PREFIX_OPCODE },
2256   { "pxor",		{ MX, EM }, PREFIX_OPCODE },
2257   /* f0 */
2258   { PREFIX_TABLE (PREFIX_0FF0) },
2259   { "psllw",		{ MX, EM }, PREFIX_OPCODE },
2260   { "pslld",		{ MX, EM }, PREFIX_OPCODE },
2261   { "psllq",		{ MX, EM }, PREFIX_OPCODE },
2262   { "pmuludq",		{ MX, EM }, PREFIX_OPCODE },
2263   { "pmaddwd",		{ MX, EM }, PREFIX_OPCODE },
2264   { "psadbw",		{ MX, EM }, PREFIX_OPCODE },
2265   { PREFIX_TABLE (PREFIX_0FF7) },
2266   /* f8 */
2267   { "psubb",		{ MX, EM }, PREFIX_OPCODE },
2268   { "psubw",		{ MX, EM }, PREFIX_OPCODE },
2269   { "psubd",		{ MX, EM }, PREFIX_OPCODE },
2270   { "psubq",		{ MX, EM }, PREFIX_OPCODE },
2271   { "paddb",		{ MX, EM }, PREFIX_OPCODE },
2272   { "paddw",		{ MX, EM }, PREFIX_OPCODE },
2273   { "paddd",		{ MX, EM }, PREFIX_OPCODE },
2274   { "ud0S",		{ Gv, Ev }, 0 },
2275 };
2276 
2277 static const unsigned char onebyte_has_modrm[256] = {
2278   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2279   /*       -------------------------------        */
2280   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2281   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2282   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2283   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2284   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2285   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2286   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2287   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2288   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2289   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2290   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2291   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2292   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2293   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2294   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2295   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2296   /*       -------------------------------        */
2297   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2298 };
2299 
2300 static const unsigned char twobyte_has_modrm[256] = {
2301   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2302   /*       -------------------------------        */
2303   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2304   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2305   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2306   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2307   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2308   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2309   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2310   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2311   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2312   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2313   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2314   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2315   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2316   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2317   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2318   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2319   /*       -------------------------------        */
2320   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2321 };
2322 
2323 static char obuf[100];
2324 static char *obufp;
2325 static char *mnemonicendp;
2326 static char scratchbuf[100];
2327 static unsigned char *start_codep;
2328 static unsigned char *insn_codep;
2329 static unsigned char *codep;
2330 static unsigned char *end_codep;
2331 static int last_lock_prefix;
2332 static int last_repz_prefix;
2333 static int last_repnz_prefix;
2334 static int last_data_prefix;
2335 static int last_addr_prefix;
2336 static int last_rex_prefix;
2337 static int last_seg_prefix;
2338 static int fwait_prefix;
2339 /* The active segment register prefix.  */
2340 static int active_seg_prefix;
2341 #define MAX_CODE_LENGTH 15
2342 /* We can up to 14 prefixes since the maximum instruction length is
2343    15bytes.  */
2344 static int all_prefixes[MAX_CODE_LENGTH - 1];
2345 static disassemble_info *the_info;
2346 static struct
2347   {
2348     int mod;
2349     int reg;
2350     int rm;
2351   }
2352 modrm;
2353 static unsigned char need_modrm;
2354 static struct
2355   {
2356     int scale;
2357     int index;
2358     int base;
2359   }
2360 sib;
2361 static struct
2362   {
2363     int register_specifier;
2364     int length;
2365     int prefix;
2366     int w;
2367     int evex;
2368     int r;
2369     int v;
2370     int mask_register_specifier;
2371     int zeroing;
2372     int ll;
2373     int b;
2374   }
2375 vex;
2376 static unsigned char need_vex;
2377 
2378 struct op
2379   {
2380     const char *name;
2381     unsigned int len;
2382   };
2383 
2384 /* If we are accessing mod/rm/reg without need_modrm set, then the
2385    values are stale.  Hitting this abort likely indicates that you
2386    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2387 #define MODRM_CHECK  if (!need_modrm) abort ()
2388 
2389 static const char **names64;
2390 static const char **names32;
2391 static const char **names16;
2392 static const char **names8;
2393 static const char **names8rex;
2394 static const char **names_seg;
2395 static const char *index64;
2396 static const char *index32;
2397 static const char **index16;
2398 static const char **names_bnd;
2399 
2400 static const char *intel_names64[] = {
2401   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2402   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2403 };
2404 static const char *intel_names32[] = {
2405   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2406   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2407 };
2408 static const char *intel_names16[] = {
2409   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2410   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2411 };
2412 static const char *intel_names8[] = {
2413   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2414 };
2415 static const char *intel_names8rex[] = {
2416   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2417   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2418 };
2419 static const char *intel_names_seg[] = {
2420   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2421 };
2422 static const char *intel_index64 = "riz";
2423 static const char *intel_index32 = "eiz";
2424 static const char *intel_index16[] = {
2425   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2426 };
2427 
2428 static const char *att_names64[] = {
2429   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2430   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2431 };
2432 static const char *att_names32[] = {
2433   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2434   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2435 };
2436 static const char *att_names16[] = {
2437   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2438   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2439 };
2440 static const char *att_names8[] = {
2441   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2442 };
2443 static const char *att_names8rex[] = {
2444   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2445   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2446 };
2447 static const char *att_names_seg[] = {
2448   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2449 };
2450 static const char *att_index64 = "%riz";
2451 static const char *att_index32 = "%eiz";
2452 static const char *att_index16[] = {
2453   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2454 };
2455 
2456 static const char **names_mm;
2457 static const char *intel_names_mm[] = {
2458   "mm0", "mm1", "mm2", "mm3",
2459   "mm4", "mm5", "mm6", "mm7"
2460 };
2461 static const char *att_names_mm[] = {
2462   "%mm0", "%mm1", "%mm2", "%mm3",
2463   "%mm4", "%mm5", "%mm6", "%mm7"
2464 };
2465 
2466 static const char *intel_names_bnd[] = {
2467   "bnd0", "bnd1", "bnd2", "bnd3"
2468 };
2469 
2470 static const char *att_names_bnd[] = {
2471   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2472 };
2473 
2474 static const char **names_xmm;
2475 static const char *intel_names_xmm[] = {
2476   "xmm0", "xmm1", "xmm2", "xmm3",
2477   "xmm4", "xmm5", "xmm6", "xmm7",
2478   "xmm8", "xmm9", "xmm10", "xmm11",
2479   "xmm12", "xmm13", "xmm14", "xmm15",
2480   "xmm16", "xmm17", "xmm18", "xmm19",
2481   "xmm20", "xmm21", "xmm22", "xmm23",
2482   "xmm24", "xmm25", "xmm26", "xmm27",
2483   "xmm28", "xmm29", "xmm30", "xmm31"
2484 };
2485 static const char *att_names_xmm[] = {
2486   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2487   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2488   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2489   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2490   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2491   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2492   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2493   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2494 };
2495 
2496 static const char **names_ymm;
2497 static const char *intel_names_ymm[] = {
2498   "ymm0", "ymm1", "ymm2", "ymm3",
2499   "ymm4", "ymm5", "ymm6", "ymm7",
2500   "ymm8", "ymm9", "ymm10", "ymm11",
2501   "ymm12", "ymm13", "ymm14", "ymm15",
2502   "ymm16", "ymm17", "ymm18", "ymm19",
2503   "ymm20", "ymm21", "ymm22", "ymm23",
2504   "ymm24", "ymm25", "ymm26", "ymm27",
2505   "ymm28", "ymm29", "ymm30", "ymm31"
2506 };
2507 static const char *att_names_ymm[] = {
2508   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2509   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2510   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2511   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2512   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2513   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2514   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2515   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2516 };
2517 
2518 static const char **names_zmm;
2519 static const char *intel_names_zmm[] = {
2520   "zmm0", "zmm1", "zmm2", "zmm3",
2521   "zmm4", "zmm5", "zmm6", "zmm7",
2522   "zmm8", "zmm9", "zmm10", "zmm11",
2523   "zmm12", "zmm13", "zmm14", "zmm15",
2524   "zmm16", "zmm17", "zmm18", "zmm19",
2525   "zmm20", "zmm21", "zmm22", "zmm23",
2526   "zmm24", "zmm25", "zmm26", "zmm27",
2527   "zmm28", "zmm29", "zmm30", "zmm31"
2528 };
2529 static const char *att_names_zmm[] = {
2530   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2531   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2532   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2533   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2534   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2535   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2536   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2537   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2538 };
2539 
2540 static const char **names_tmm;
2541 static const char *intel_names_tmm[] = {
2542   "tmm0", "tmm1", "tmm2", "tmm3",
2543   "tmm4", "tmm5", "tmm6", "tmm7"
2544 };
2545 static const char *att_names_tmm[] = {
2546   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2547   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2548 };
2549 
2550 static const char **names_mask;
2551 static const char *intel_names_mask[] = {
2552   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2553 };
2554 static const char *att_names_mask[] = {
2555   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2556 };
2557 
2558 static const char *names_rounding[] =
2559 {
2560   "{rn-sae}",
2561   "{rd-sae}",
2562   "{ru-sae}",
2563   "{rz-sae}"
2564 };
2565 
2566 static const struct dis386 reg_table[][8] = {
2567   /* REG_80 */
2568   {
2569     { "addA",	{ Ebh1, Ib }, 0 },
2570     { "orA",	{ Ebh1, Ib }, 0 },
2571     { "adcA",	{ Ebh1, Ib }, 0 },
2572     { "sbbA",	{ Ebh1, Ib }, 0 },
2573     { "andA",	{ Ebh1, Ib }, 0 },
2574     { "subA",	{ Ebh1, Ib }, 0 },
2575     { "xorA",	{ Ebh1, Ib }, 0 },
2576     { "cmpA",	{ Eb, Ib }, 0 },
2577   },
2578   /* REG_81 */
2579   {
2580     { "addQ",	{ Evh1, Iv }, 0 },
2581     { "orQ",	{ Evh1, Iv }, 0 },
2582     { "adcQ",	{ Evh1, Iv }, 0 },
2583     { "sbbQ",	{ Evh1, Iv }, 0 },
2584     { "andQ",	{ Evh1, Iv }, 0 },
2585     { "subQ",	{ Evh1, Iv }, 0 },
2586     { "xorQ",	{ Evh1, Iv }, 0 },
2587     { "cmpQ",	{ Ev, Iv }, 0 },
2588   },
2589   /* REG_83 */
2590   {
2591     { "addQ",	{ Evh1, sIb }, 0 },
2592     { "orQ",	{ Evh1, sIb }, 0 },
2593     { "adcQ",	{ Evh1, sIb }, 0 },
2594     { "sbbQ",	{ Evh1, sIb }, 0 },
2595     { "andQ",	{ Evh1, sIb }, 0 },
2596     { "subQ",	{ Evh1, sIb }, 0 },
2597     { "xorQ",	{ Evh1, sIb }, 0 },
2598     { "cmpQ",	{ Ev, sIb }, 0 },
2599   },
2600   /* REG_8F */
2601   {
2602     { "pop{P|}", { stackEv }, 0 },
2603     { XOP_8F_TABLE (XOP_09) },
2604     { Bad_Opcode },
2605     { Bad_Opcode },
2606     { Bad_Opcode },
2607     { XOP_8F_TABLE (XOP_09) },
2608   },
2609   /* REG_C0 */
2610   {
2611     { "rolA",	{ Eb, Ib }, 0 },
2612     { "rorA",	{ Eb, Ib }, 0 },
2613     { "rclA",	{ Eb, Ib }, 0 },
2614     { "rcrA",	{ Eb, Ib }, 0 },
2615     { "shlA",	{ Eb, Ib }, 0 },
2616     { "shrA",	{ Eb, Ib }, 0 },
2617     { "shlA",	{ Eb, Ib }, 0 },
2618     { "sarA",	{ Eb, Ib }, 0 },
2619   },
2620   /* REG_C1 */
2621   {
2622     { "rolQ",	{ Ev, Ib }, 0 },
2623     { "rorQ",	{ Ev, Ib }, 0 },
2624     { "rclQ",	{ Ev, Ib }, 0 },
2625     { "rcrQ",	{ Ev, Ib }, 0 },
2626     { "shlQ",	{ Ev, Ib }, 0 },
2627     { "shrQ",	{ Ev, Ib }, 0 },
2628     { "shlQ",	{ Ev, Ib }, 0 },
2629     { "sarQ",	{ Ev, Ib }, 0 },
2630   },
2631   /* REG_C6 */
2632   {
2633     { "movA",	{ Ebh3, Ib }, 0 },
2634     { Bad_Opcode },
2635     { Bad_Opcode },
2636     { Bad_Opcode },
2637     { Bad_Opcode },
2638     { Bad_Opcode },
2639     { Bad_Opcode },
2640     { MOD_TABLE (MOD_C6_REG_7) },
2641   },
2642   /* REG_C7 */
2643   {
2644     { "movQ",	{ Evh3, Iv }, 0 },
2645     { Bad_Opcode },
2646     { Bad_Opcode },
2647     { Bad_Opcode },
2648     { Bad_Opcode },
2649     { Bad_Opcode },
2650     { Bad_Opcode },
2651     { MOD_TABLE (MOD_C7_REG_7) },
2652   },
2653   /* REG_D0 */
2654   {
2655     { "rolA",	{ Eb, I1 }, 0 },
2656     { "rorA",	{ Eb, I1 }, 0 },
2657     { "rclA",	{ Eb, I1 }, 0 },
2658     { "rcrA",	{ Eb, I1 }, 0 },
2659     { "shlA",	{ Eb, I1 }, 0 },
2660     { "shrA",	{ Eb, I1 }, 0 },
2661     { "shlA",	{ Eb, I1 }, 0 },
2662     { "sarA",	{ Eb, I1 }, 0 },
2663   },
2664   /* REG_D1 */
2665   {
2666     { "rolQ",	{ Ev, I1 }, 0 },
2667     { "rorQ",	{ Ev, I1 }, 0 },
2668     { "rclQ",	{ Ev, I1 }, 0 },
2669     { "rcrQ",	{ Ev, I1 }, 0 },
2670     { "shlQ",	{ Ev, I1 }, 0 },
2671     { "shrQ",	{ Ev, I1 }, 0 },
2672     { "shlQ",	{ Ev, I1 }, 0 },
2673     { "sarQ",	{ Ev, I1 }, 0 },
2674   },
2675   /* REG_D2 */
2676   {
2677     { "rolA",	{ Eb, CL }, 0 },
2678     { "rorA",	{ Eb, CL }, 0 },
2679     { "rclA",	{ Eb, CL }, 0 },
2680     { "rcrA",	{ Eb, CL }, 0 },
2681     { "shlA",	{ Eb, CL }, 0 },
2682     { "shrA",	{ Eb, CL }, 0 },
2683     { "shlA",	{ Eb, CL }, 0 },
2684     { "sarA",	{ Eb, CL }, 0 },
2685   },
2686   /* REG_D3 */
2687   {
2688     { "rolQ",	{ Ev, CL }, 0 },
2689     { "rorQ",	{ Ev, CL }, 0 },
2690     { "rclQ",	{ Ev, CL }, 0 },
2691     { "rcrQ",	{ Ev, CL }, 0 },
2692     { "shlQ",	{ Ev, CL }, 0 },
2693     { "shrQ",	{ Ev, CL }, 0 },
2694     { "shlQ",	{ Ev, CL }, 0 },
2695     { "sarQ",	{ Ev, CL }, 0 },
2696   },
2697   /* REG_F6 */
2698   {
2699     { "testA",	{ Eb, Ib }, 0 },
2700     { "testA",	{ Eb, Ib }, 0 },
2701     { "notA",	{ Ebh1 }, 0 },
2702     { "negA",	{ Ebh1 }, 0 },
2703     { "mulA",	{ Eb }, 0 },	/* Don't print the implicit %al register,  */
2704     { "imulA",	{ Eb }, 0 },	/* to distinguish these opcodes from other */
2705     { "divA",	{ Eb }, 0 },	/* mul/imul opcodes.  Do the same for div  */
2706     { "idivA",	{ Eb }, 0 },	/* and idiv for consistency.		   */
2707   },
2708   /* REG_F7 */
2709   {
2710     { "testQ",	{ Ev, Iv }, 0 },
2711     { "testQ",	{ Ev, Iv }, 0 },
2712     { "notQ",	{ Evh1 }, 0 },
2713     { "negQ",	{ Evh1 }, 0 },
2714     { "mulQ",	{ Ev }, 0 },	/* Don't print the implicit register.  */
2715     { "imulQ",	{ Ev }, 0 },
2716     { "divQ",	{ Ev }, 0 },
2717     { "idivQ",	{ Ev }, 0 },
2718   },
2719   /* REG_FE */
2720   {
2721     { "incA",	{ Ebh1 }, 0 },
2722     { "decA",	{ Ebh1 }, 0 },
2723   },
2724   /* REG_FF */
2725   {
2726     { "incQ",	{ Evh1 }, 0 },
2727     { "decQ",	{ Evh1 }, 0 },
2728     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2729     { MOD_TABLE (MOD_FF_REG_3) },
2730     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2731     { MOD_TABLE (MOD_FF_REG_5) },
2732     { "push{P|}", { stackEv }, 0 },
2733     { Bad_Opcode },
2734   },
2735   /* REG_0F00 */
2736   {
2737     { "sldtD",	{ Sv }, 0 },
2738     { "strD",	{ Sv }, 0 },
2739     { "lldt",	{ Ew }, 0 },
2740     { "ltr",	{ Ew }, 0 },
2741     { "verr",	{ Ew }, 0 },
2742     { "verw",	{ Ew }, 0 },
2743     { Bad_Opcode },
2744     { Bad_Opcode },
2745   },
2746   /* REG_0F01 */
2747   {
2748     { MOD_TABLE (MOD_0F01_REG_0) },
2749     { MOD_TABLE (MOD_0F01_REG_1) },
2750     { MOD_TABLE (MOD_0F01_REG_2) },
2751     { MOD_TABLE (MOD_0F01_REG_3) },
2752     { "smswD",	{ Sv }, 0 },
2753     { MOD_TABLE (MOD_0F01_REG_5) },
2754     { "lmsw",	{ Ew }, 0 },
2755     { MOD_TABLE (MOD_0F01_REG_7) },
2756   },
2757   /* REG_0F0D */
2758   {
2759     { "prefetch",	{ Mb }, 0 },
2760     { "prefetchw",	{ Mb }, 0 },
2761     { "prefetchwt1",	{ Mb }, 0 },
2762     { "prefetch",	{ Mb }, 0 },
2763     { "prefetch",	{ Mb }, 0 },
2764     { "prefetch",	{ Mb }, 0 },
2765     { "prefetch",	{ Mb }, 0 },
2766     { "prefetch",	{ Mb }, 0 },
2767   },
2768   /* REG_0F18 */
2769   {
2770     { MOD_TABLE (MOD_0F18_REG_0) },
2771     { MOD_TABLE (MOD_0F18_REG_1) },
2772     { MOD_TABLE (MOD_0F18_REG_2) },
2773     { MOD_TABLE (MOD_0F18_REG_3) },
2774     { "nopQ",		{ Ev }, 0 },
2775     { "nopQ",		{ Ev }, 0 },
2776     { "nopQ",		{ Ev }, 0 },
2777     { "nopQ",		{ Ev }, 0 },
2778   },
2779   /* REG_0F1C_P_0_MOD_0 */
2780   {
2781     { "cldemote",	{ Mb }, 0 },
2782     { "nopQ",		{ Ev }, 0 },
2783     { "nopQ",		{ Ev }, 0 },
2784     { "nopQ",		{ Ev }, 0 },
2785     { "nopQ",		{ Ev }, 0 },
2786     { "nopQ",		{ Ev }, 0 },
2787     { "nopQ",		{ Ev }, 0 },
2788     { "nopQ",		{ Ev }, 0 },
2789   },
2790   /* REG_0F1E_P_1_MOD_3 */
2791   {
2792     { "nopQ",		{ Ev }, PREFIX_IGNORED },
2793     { "rdsspK",		{ Edq }, 0 },
2794     { "nopQ",		{ Ev }, PREFIX_IGNORED },
2795     { "nopQ",		{ Ev }, PREFIX_IGNORED },
2796     { "nopQ",		{ Ev }, PREFIX_IGNORED },
2797     { "nopQ",		{ Ev }, PREFIX_IGNORED },
2798     { "nopQ",		{ Ev }, PREFIX_IGNORED },
2799     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2800   },
2801   /* REG_0F38D8_PREFIX_1 */
2802   {
2803     { "aesencwide128kl",	{ M }, 0 },
2804     { "aesdecwide128kl",	{ M }, 0 },
2805     { "aesencwide256kl",	{ M }, 0 },
2806     { "aesdecwide256kl",	{ M }, 0 },
2807   },
2808   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2809   {
2810     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2811   },
2812   /* REG_0F71_MOD_0 */
2813   {
2814     { Bad_Opcode },
2815     { Bad_Opcode },
2816     { "psrlw",		{ MS, Ib }, PREFIX_OPCODE },
2817     { Bad_Opcode },
2818     { "psraw",		{ MS, Ib }, PREFIX_OPCODE },
2819     { Bad_Opcode },
2820     { "psllw",		{ MS, Ib }, PREFIX_OPCODE },
2821   },
2822   /* REG_0F72_MOD_0 */
2823   {
2824     { Bad_Opcode },
2825     { Bad_Opcode },
2826     { "psrld",		{ MS, Ib }, PREFIX_OPCODE },
2827     { Bad_Opcode },
2828     { "psrad",		{ MS, Ib }, PREFIX_OPCODE },
2829     { Bad_Opcode },
2830     { "pslld",		{ MS, Ib }, PREFIX_OPCODE },
2831   },
2832   /* REG_0F73_MOD_0 */
2833   {
2834     { Bad_Opcode },
2835     { Bad_Opcode },
2836     { "psrlq",		{ MS, Ib }, PREFIX_OPCODE },
2837     { "psrldq",		{ XS, Ib }, PREFIX_DATA },
2838     { Bad_Opcode },
2839     { Bad_Opcode },
2840     { "psllq",		{ MS, Ib }, PREFIX_OPCODE },
2841     { "pslldq",		{ XS, Ib }, PREFIX_DATA },
2842   },
2843   /* REG_0FA6 */
2844   {
2845     { "montmul",	{ { OP_0f07, 0 } }, 0 },
2846     { "xsha1",		{ { OP_0f07, 0 } }, 0 },
2847     { "xsha256",	{ { OP_0f07, 0 } }, 0 },
2848   },
2849   /* REG_0FA7 */
2850   {
2851     { "xstore-rng",	{ { OP_0f07, 0 } }, 0 },
2852     { "xcrypt-ecb",	{ { OP_0f07, 0 } }, 0 },
2853     { "xcrypt-cbc",	{ { OP_0f07, 0 } }, 0 },
2854     { "xcrypt-ctr",	{ { OP_0f07, 0 } }, 0 },
2855     { "xcrypt-cfb",	{ { OP_0f07, 0 } }, 0 },
2856     { "xcrypt-ofb",	{ { OP_0f07, 0 } }, 0 },
2857   },
2858   /* REG_0FAE */
2859   {
2860     { MOD_TABLE (MOD_0FAE_REG_0) },
2861     { MOD_TABLE (MOD_0FAE_REG_1) },
2862     { MOD_TABLE (MOD_0FAE_REG_2) },
2863     { MOD_TABLE (MOD_0FAE_REG_3) },
2864     { MOD_TABLE (MOD_0FAE_REG_4) },
2865     { MOD_TABLE (MOD_0FAE_REG_5) },
2866     { MOD_TABLE (MOD_0FAE_REG_6) },
2867     { MOD_TABLE (MOD_0FAE_REG_7) },
2868   },
2869   /* REG_0FBA */
2870   {
2871     { Bad_Opcode },
2872     { Bad_Opcode },
2873     { Bad_Opcode },
2874     { Bad_Opcode },
2875     { "btQ",	{ Ev, Ib }, 0 },
2876     { "btsQ",	{ Evh1, Ib }, 0 },
2877     { "btrQ",	{ Evh1, Ib }, 0 },
2878     { "btcQ",	{ Evh1, Ib }, 0 },
2879   },
2880   /* REG_0FC7 */
2881   {
2882     { Bad_Opcode },
2883     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2884     { Bad_Opcode },
2885     { MOD_TABLE (MOD_0FC7_REG_3) },
2886     { MOD_TABLE (MOD_0FC7_REG_4) },
2887     { MOD_TABLE (MOD_0FC7_REG_5) },
2888     { MOD_TABLE (MOD_0FC7_REG_6) },
2889     { MOD_TABLE (MOD_0FC7_REG_7) },
2890   },
2891   /* REG_VEX_0F71_M_0 */
2892   {
2893     { Bad_Opcode },
2894     { Bad_Opcode },
2895     { "vpsrlw",		{ Vex, XS, Ib }, PREFIX_DATA },
2896     { Bad_Opcode },
2897     { "vpsraw",		{ Vex, XS, Ib }, PREFIX_DATA },
2898     { Bad_Opcode },
2899     { "vpsllw",		{ Vex, XS, Ib }, PREFIX_DATA },
2900   },
2901   /* REG_VEX_0F72_M_0 */
2902   {
2903     { Bad_Opcode },
2904     { Bad_Opcode },
2905     { "vpsrld",		{ Vex, XS, Ib }, PREFIX_DATA },
2906     { Bad_Opcode },
2907     { "vpsrad",		{ Vex, XS, Ib }, PREFIX_DATA },
2908     { Bad_Opcode },
2909     { "vpslld",		{ Vex, XS, Ib }, PREFIX_DATA },
2910   },
2911   /* REG_VEX_0F73_M_0 */
2912   {
2913     { Bad_Opcode },
2914     { Bad_Opcode },
2915     { "vpsrlq",		{ Vex, XS, Ib }, PREFIX_DATA },
2916     { "vpsrldq",	{ Vex, XS, Ib }, PREFIX_DATA },
2917     { Bad_Opcode },
2918     { Bad_Opcode },
2919     { "vpsllq",		{ Vex, XS, Ib }, PREFIX_DATA },
2920     { "vpslldq",	{ Vex, XS, Ib }, PREFIX_DATA },
2921   },
2922   /* REG_VEX_0FAE */
2923   {
2924     { Bad_Opcode },
2925     { Bad_Opcode },
2926     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2927     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2928   },
2929   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2930   {
2931     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2932   },
2933   /* REG_VEX_0F38F3_L_0 */
2934   {
2935     { Bad_Opcode },
2936     { "blsrS",		{ VexGdq, Edq }, PREFIX_OPCODE },
2937     { "blsmskS",	{ VexGdq, Edq }, PREFIX_OPCODE },
2938     { "blsiS",		{ VexGdq, Edq }, PREFIX_OPCODE },
2939   },
2940   /* REG_XOP_09_01_L_0 */
2941   {
2942     { Bad_Opcode },
2943     { "blcfill",	{ VexGdq, Edq }, 0 },
2944     { "blsfill",	{ VexGdq, Edq }, 0 },
2945     { "blcs",	{ VexGdq, Edq }, 0 },
2946     { "tzmsk",	{ VexGdq, Edq }, 0 },
2947     { "blcic",	{ VexGdq, Edq }, 0 },
2948     { "blsic",	{ VexGdq, Edq }, 0 },
2949     { "t1mskc",	{ VexGdq, Edq }, 0 },
2950   },
2951   /* REG_XOP_09_02_L_0 */
2952   {
2953     { Bad_Opcode },
2954     { "blcmsk",	{ VexGdq, Edq }, 0 },
2955     { Bad_Opcode },
2956     { Bad_Opcode },
2957     { Bad_Opcode },
2958     { Bad_Opcode },
2959     { "blci",	{ VexGdq, Edq }, 0 },
2960   },
2961   /* REG_XOP_09_12_M_1_L_0 */
2962   {
2963     { "llwpcb",	{ Edq }, 0 },
2964     { "slwpcb",	{ Edq }, 0 },
2965   },
2966   /* REG_XOP_0A_12_L_0 */
2967   {
2968     { "lwpins",	{ VexGdq, Ed, Id }, 0 },
2969     { "lwpval",	{ VexGdq, Ed, Id }, 0 },
2970   },
2971 
2972 #include "i386-dis-evex-reg.h"
2973 };
2974 
2975 static const struct dis386 prefix_table[][4] = {
2976   /* PREFIX_90 */
2977   {
2978     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
2979     { "pause", { XX }, 0 },
2980     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
2981     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2982   },
2983 
2984   /* PREFIX_0F01_REG_1_RM_4 */
2985   {
2986     { Bad_Opcode },
2987     { Bad_Opcode },
2988     { "tdcall", 	{ Skip_MODRM }, 0 },
2989     { Bad_Opcode },
2990   },
2991 
2992   /* PREFIX_0F01_REG_1_RM_5 */
2993   {
2994     { Bad_Opcode },
2995     { Bad_Opcode },
2996     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
2997     { Bad_Opcode },
2998   },
2999 
3000   /* PREFIX_0F01_REG_1_RM_6 */
3001   {
3002     { Bad_Opcode },
3003     { Bad_Opcode },
3004     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3005     { Bad_Opcode },
3006   },
3007 
3008   /* PREFIX_0F01_REG_1_RM_7 */
3009   {
3010     { "encls",		{ Skip_MODRM }, 0 },
3011     { Bad_Opcode },
3012     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3013     { Bad_Opcode },
3014   },
3015 
3016   /* PREFIX_0F01_REG_3_RM_1 */
3017   {
3018     { "vmmcall",	{ Skip_MODRM }, 0 },
3019     { "vmgexit",	{ Skip_MODRM }, 0 },
3020     { Bad_Opcode },
3021     { "vmgexit",	{ Skip_MODRM }, 0 },
3022   },
3023 
3024   /* PREFIX_0F01_REG_5_MOD_0 */
3025   {
3026     { Bad_Opcode },
3027     { "rstorssp",	{ Mq }, PREFIX_OPCODE },
3028   },
3029 
3030   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3031   {
3032     { "serialize",	{ Skip_MODRM }, PREFIX_OPCODE },
3033     { "setssbsy",	{ Skip_MODRM }, PREFIX_OPCODE },
3034     { Bad_Opcode },
3035     { "xsusldtrk",	{ Skip_MODRM }, PREFIX_OPCODE },
3036   },
3037 
3038   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3039   {
3040     { Bad_Opcode },
3041     { Bad_Opcode },
3042     { Bad_Opcode },
3043     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3044   },
3045 
3046   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3047   {
3048     { Bad_Opcode },
3049     { "saveprevssp",	{ Skip_MODRM }, PREFIX_OPCODE },
3050   },
3051 
3052   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3053   {
3054     { Bad_Opcode },
3055     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3056   },
3057 
3058   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3059   {
3060     { Bad_Opcode },
3061     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3062   },
3063 
3064   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3065   {
3066     { "rdpkru", { Skip_MODRM }, 0 },
3067     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3068   },
3069 
3070   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3071   {
3072     { "wrpkru",	{ Skip_MODRM }, 0 },
3073     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3074   },
3075 
3076   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3077   {
3078     { "monitorx",	{ { OP_Monitor, 0 } }, 0  },
3079     { "mcommit",	{ Skip_MODRM }, 0 },
3080   },
3081 
3082   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3083   {
3084     { "invlpgb",        { Skip_MODRM }, 0 },
3085     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3086     { Bad_Opcode },
3087     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3088   },
3089 
3090   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3091   {
3092     { "tlbsync",        { Skip_MODRM }, 0 },
3093     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3094     { Bad_Opcode },
3095     { "pvalidate",      { Skip_MODRM }, 0 },
3096   },
3097 
3098   /* PREFIX_0F09 */
3099   {
3100     { "wbinvd",   { XX }, 0 },
3101     { "wbnoinvd", { XX }, 0 },
3102   },
3103 
3104   /* PREFIX_0F10 */
3105   {
3106     { "movups",	{ XM, EXx }, PREFIX_OPCODE },
3107     { "movss",	{ XM, EXd }, PREFIX_OPCODE },
3108     { "movupd",	{ XM, EXx }, PREFIX_OPCODE },
3109     { "movsd",	{ XM, EXq }, PREFIX_OPCODE },
3110   },
3111 
3112   /* PREFIX_0F11 */
3113   {
3114     { "movups",	{ EXxS, XM }, PREFIX_OPCODE },
3115     { "movss",	{ EXdS, XM }, PREFIX_OPCODE },
3116     { "movupd",	{ EXxS, XM }, PREFIX_OPCODE },
3117     { "movsd",	{ EXqS, XM }, PREFIX_OPCODE },
3118   },
3119 
3120   /* PREFIX_0F12 */
3121   {
3122     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3123     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3124     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3125     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3126   },
3127 
3128   /* PREFIX_0F16 */
3129   {
3130     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3131     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3132     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3133   },
3134 
3135   /* PREFIX_0F1A */
3136   {
3137     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3138     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3139     { "bndmov", { Gbnd, Ebnd }, 0 },
3140     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3141   },
3142 
3143   /* PREFIX_0F1B */
3144   {
3145     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3146     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3147     { "bndmov", { EbndS, Gbnd }, 0 },
3148     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3149   },
3150 
3151   /* PREFIX_0F1C */
3152   {
3153     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3154     { "nopQ",	{ Ev }, PREFIX_IGNORED },
3155     { "nopQ",	{ Ev }, 0 },
3156     { "nopQ",	{ Ev }, PREFIX_IGNORED },
3157   },
3158 
3159   /* PREFIX_0F1E */
3160   {
3161     { "nopQ",	{ Ev }, 0 },
3162     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3163     { "nopQ",	{ Ev }, 0 },
3164     { NULL,	{ XX }, PREFIX_IGNORED },
3165   },
3166 
3167   /* PREFIX_0F2A */
3168   {
3169     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3170     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3171     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3172     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3173   },
3174 
3175   /* PREFIX_0F2B */
3176   {
3177     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3178     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3179     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3180     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3181   },
3182 
3183   /* PREFIX_0F2C */
3184   {
3185     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3186     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3187     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3188     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3189   },
3190 
3191   /* PREFIX_0F2D */
3192   {
3193     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3194     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3195     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3196     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3197   },
3198 
3199   /* PREFIX_0F2E */
3200   {
3201     { "ucomiss",{ XM, EXd }, 0 },
3202     { Bad_Opcode },
3203     { "ucomisd",{ XM, EXq }, 0 },
3204   },
3205 
3206   /* PREFIX_0F2F */
3207   {
3208     { "comiss",	{ XM, EXd }, 0 },
3209     { Bad_Opcode },
3210     { "comisd",	{ XM, EXq }, 0 },
3211   },
3212 
3213   /* PREFIX_0F51 */
3214   {
3215     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3216     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3217     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3218     { "sqrtsd",	{ XM, EXq }, PREFIX_OPCODE },
3219   },
3220 
3221   /* PREFIX_0F52 */
3222   {
3223     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3224     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3225   },
3226 
3227   /* PREFIX_0F53 */
3228   {
3229     { "rcpps",	{ XM, EXx }, PREFIX_OPCODE },
3230     { "rcpss",	{ XM, EXd }, PREFIX_OPCODE },
3231   },
3232 
3233   /* PREFIX_0F58 */
3234   {
3235     { "addps", { XM, EXx }, PREFIX_OPCODE },
3236     { "addss", { XM, EXd }, PREFIX_OPCODE },
3237     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3238     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3239   },
3240 
3241   /* PREFIX_0F59 */
3242   {
3243     { "mulps",	{ XM, EXx }, PREFIX_OPCODE },
3244     { "mulss",	{ XM, EXd }, PREFIX_OPCODE },
3245     { "mulpd",	{ XM, EXx }, PREFIX_OPCODE },
3246     { "mulsd",	{ XM, EXq }, PREFIX_OPCODE },
3247   },
3248 
3249   /* PREFIX_0F5A */
3250   {
3251     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3252     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3253     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3254     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3255   },
3256 
3257   /* PREFIX_0F5B */
3258   {
3259     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3260     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3261     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3262   },
3263 
3264   /* PREFIX_0F5C */
3265   {
3266     { "subps",	{ XM, EXx }, PREFIX_OPCODE },
3267     { "subss",	{ XM, EXd }, PREFIX_OPCODE },
3268     { "subpd",	{ XM, EXx }, PREFIX_OPCODE },
3269     { "subsd",	{ XM, EXq }, PREFIX_OPCODE },
3270   },
3271 
3272   /* PREFIX_0F5D */
3273   {
3274     { "minps",	{ XM, EXx }, PREFIX_OPCODE },
3275     { "minss",	{ XM, EXd }, PREFIX_OPCODE },
3276     { "minpd",	{ XM, EXx }, PREFIX_OPCODE },
3277     { "minsd",	{ XM, EXq }, PREFIX_OPCODE },
3278   },
3279 
3280   /* PREFIX_0F5E */
3281   {
3282     { "divps",	{ XM, EXx }, PREFIX_OPCODE },
3283     { "divss",	{ XM, EXd }, PREFIX_OPCODE },
3284     { "divpd",	{ XM, EXx }, PREFIX_OPCODE },
3285     { "divsd",	{ XM, EXq }, PREFIX_OPCODE },
3286   },
3287 
3288   /* PREFIX_0F5F */
3289   {
3290     { "maxps",	{ XM, EXx }, PREFIX_OPCODE },
3291     { "maxss",	{ XM, EXd }, PREFIX_OPCODE },
3292     { "maxpd",	{ XM, EXx }, PREFIX_OPCODE },
3293     { "maxsd",	{ XM, EXq }, PREFIX_OPCODE },
3294   },
3295 
3296   /* PREFIX_0F60 */
3297   {
3298     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3299     { Bad_Opcode },
3300     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3301   },
3302 
3303   /* PREFIX_0F61 */
3304   {
3305     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3306     { Bad_Opcode },
3307     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3308   },
3309 
3310   /* PREFIX_0F62 */
3311   {
3312     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3313     { Bad_Opcode },
3314     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3315   },
3316 
3317   /* PREFIX_0F6F */
3318   {
3319     { "movq",	{ MX, EM }, PREFIX_OPCODE },
3320     { "movdqu",	{ XM, EXx }, PREFIX_OPCODE },
3321     { "movdqa",	{ XM, EXx }, PREFIX_OPCODE },
3322   },
3323 
3324   /* PREFIX_0F70 */
3325   {
3326     { "pshufw",	{ MX, EM, Ib }, PREFIX_OPCODE },
3327     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3328     { "pshufd",	{ XM, EXx, Ib }, PREFIX_OPCODE },
3329     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3330   },
3331 
3332   /* PREFIX_0F78 */
3333   {
3334     {"vmread",	{ Em, Gm }, 0 },
3335     { Bad_Opcode },
3336     {"extrq",	{ XS, Ib, Ib }, 0 },
3337     {"insertq",	{ XM, XS, Ib, Ib }, 0 },
3338   },
3339 
3340   /* PREFIX_0F79 */
3341   {
3342     {"vmwrite",	{ Gm, Em }, 0 },
3343     { Bad_Opcode },
3344     {"extrq",	{ XM, XS }, 0 },
3345     {"insertq",	{ XM, XS }, 0 },
3346   },
3347 
3348   /* PREFIX_0F7C */
3349   {
3350     { Bad_Opcode },
3351     { Bad_Opcode },
3352     { "haddpd",	{ XM, EXx }, PREFIX_OPCODE },
3353     { "haddps",	{ XM, EXx }, PREFIX_OPCODE },
3354   },
3355 
3356   /* PREFIX_0F7D */
3357   {
3358     { Bad_Opcode },
3359     { Bad_Opcode },
3360     { "hsubpd",	{ XM, EXx }, PREFIX_OPCODE },
3361     { "hsubps",	{ XM, EXx }, PREFIX_OPCODE },
3362   },
3363 
3364   /* PREFIX_0F7E */
3365   {
3366     { "movK",	{ Edq, MX }, PREFIX_OPCODE },
3367     { "movq",	{ XM, EXq }, PREFIX_OPCODE },
3368     { "movK",	{ Edq, XM }, PREFIX_OPCODE },
3369   },
3370 
3371   /* PREFIX_0F7F */
3372   {
3373     { "movq",	{ EMS, MX }, PREFIX_OPCODE },
3374     { "movdqu",	{ EXxS, XM }, PREFIX_OPCODE },
3375     { "movdqa",	{ EXxS, XM }, PREFIX_OPCODE },
3376   },
3377 
3378   /* PREFIX_0FAE_REG_0_MOD_3 */
3379   {
3380     { Bad_Opcode },
3381     { "rdfsbase", { Ev }, 0 },
3382   },
3383 
3384   /* PREFIX_0FAE_REG_1_MOD_3 */
3385   {
3386     { Bad_Opcode },
3387     { "rdgsbase", { Ev }, 0 },
3388   },
3389 
3390   /* PREFIX_0FAE_REG_2_MOD_3 */
3391   {
3392     { Bad_Opcode },
3393     { "wrfsbase", { Ev }, 0 },
3394   },
3395 
3396   /* PREFIX_0FAE_REG_3_MOD_3 */
3397   {
3398     { Bad_Opcode },
3399     { "wrgsbase", { Ev }, 0 },
3400   },
3401 
3402   /* PREFIX_0FAE_REG_4_MOD_0 */
3403   {
3404     { "xsave",	{ FXSAVE }, 0 },
3405     { "ptwrite{%LQ|}", { Edq }, 0 },
3406   },
3407 
3408   /* PREFIX_0FAE_REG_4_MOD_3 */
3409   {
3410     { Bad_Opcode },
3411     { "ptwrite{%LQ|}", { Edq }, 0 },
3412   },
3413 
3414   /* PREFIX_0FAE_REG_5_MOD_3 */
3415   {
3416     { "lfence",		{ Skip_MODRM }, 0 },
3417     { "incsspK",	{ Edq }, PREFIX_OPCODE },
3418   },
3419 
3420   /* PREFIX_0FAE_REG_6_MOD_0 */
3421   {
3422     { "xsaveopt",	{ FXSAVE }, PREFIX_OPCODE },
3423     { "clrssbsy",	{ Mq }, PREFIX_OPCODE },
3424     { "clwb",	{ Mb }, PREFIX_OPCODE },
3425   },
3426 
3427   /* PREFIX_0FAE_REG_6_MOD_3 */
3428   {
3429     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3430     { "umonitor",	{ Eva }, PREFIX_OPCODE },
3431     { "tpause",	{ Edq }, PREFIX_OPCODE },
3432     { "umwait",	{ Edq }, PREFIX_OPCODE },
3433   },
3434 
3435   /* PREFIX_0FAE_REG_7_MOD_0 */
3436   {
3437     { "clflush",	{ Mb }, 0 },
3438     { Bad_Opcode },
3439     { "clflushopt",	{ Mb }, 0 },
3440   },
3441 
3442   /* PREFIX_0FB8 */
3443   {
3444     { Bad_Opcode },
3445     { "popcntS", { Gv, Ev }, 0 },
3446   },
3447 
3448   /* PREFIX_0FBC */
3449   {
3450     { "bsfS",	{ Gv, Ev }, 0 },
3451     { "tzcntS",	{ Gv, Ev }, 0 },
3452     { "bsfS",	{ Gv, Ev }, 0 },
3453   },
3454 
3455   /* PREFIX_0FBD */
3456   {
3457     { "bsrS",	{ Gv, Ev }, 0 },
3458     { "lzcntS",	{ Gv, Ev }, 0 },
3459     { "bsrS",	{ Gv, Ev }, 0 },
3460   },
3461 
3462   /* PREFIX_0FC2 */
3463   {
3464     { "cmpps",	{ XM, EXx, CMP }, PREFIX_OPCODE },
3465     { "cmpss",	{ XM, EXd, CMP }, PREFIX_OPCODE },
3466     { "cmppd",	{ XM, EXx, CMP }, PREFIX_OPCODE },
3467     { "cmpsd",	{ XM, EXq, CMP }, PREFIX_OPCODE },
3468   },
3469 
3470   /* PREFIX_0FC7_REG_6_MOD_0 */
3471   {
3472     { "vmptrld",{ Mq }, 0 },
3473     { "vmxon",	{ Mq }, 0 },
3474     { "vmclear",{ Mq }, 0 },
3475   },
3476 
3477   /* PREFIX_0FC7_REG_6_MOD_3 */
3478   {
3479     { "rdrand",	{ Ev }, 0 },
3480     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3481     { "rdrand",	{ Ev }, 0 }
3482   },
3483 
3484   /* PREFIX_0FC7_REG_7_MOD_3 */
3485   {
3486     { "rdseed",	{ Ev }, 0 },
3487     { "rdpid",	{ Em }, 0 },
3488     { "rdseed",	{ Ev }, 0 },
3489   },
3490 
3491   /* PREFIX_0FD0 */
3492   {
3493     { Bad_Opcode },
3494     { Bad_Opcode },
3495     { "addsubpd", { XM, EXx }, 0 },
3496     { "addsubps", { XM, EXx }, 0 },
3497   },
3498 
3499   /* PREFIX_0FD6 */
3500   {
3501     { Bad_Opcode },
3502     { "movq2dq",{ XM, MS }, 0 },
3503     { "movq",	{ EXqS, XM }, 0 },
3504     { "movdq2q",{ MX, XS }, 0 },
3505   },
3506 
3507   /* PREFIX_0FE6 */
3508   {
3509     { Bad_Opcode },
3510     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3511     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3512     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3513   },
3514 
3515   /* PREFIX_0FE7 */
3516   {
3517     { "movntq",	{ Mq, MX }, PREFIX_OPCODE },
3518     { Bad_Opcode },
3519     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3520   },
3521 
3522   /* PREFIX_0FF0 */
3523   {
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3528   },
3529 
3530   /* PREFIX_0FF7 */
3531   {
3532     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3533     { Bad_Opcode },
3534     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3535   },
3536 
3537   /* PREFIX_0F38D8 */
3538   {
3539     { Bad_Opcode },
3540     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3541   },
3542 
3543   /* PREFIX_0F38DC */
3544   {
3545     { Bad_Opcode },
3546     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3547     { "aesenc", { XM, EXx }, 0 },
3548   },
3549 
3550   /* PREFIX_0F38DD */
3551   {
3552     { Bad_Opcode },
3553     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3554     { "aesenclast", { XM, EXx }, 0 },
3555   },
3556 
3557   /* PREFIX_0F38DE */
3558   {
3559     { Bad_Opcode },
3560     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3561     { "aesdec", { XM, EXx }, 0 },
3562   },
3563 
3564   /* PREFIX_0F38DF */
3565   {
3566     { Bad_Opcode },
3567     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3568     { "aesdeclast", { XM, EXx }, 0 },
3569   },
3570 
3571   /* PREFIX_0F38F0 */
3572   {
3573     { "movbeS",	{ Gv, Mv }, PREFIX_OPCODE },
3574     { Bad_Opcode },
3575     { "movbeS",	{ Gv, Mv }, PREFIX_OPCODE },
3576     { "crc32A",	{ Gdq, Eb }, PREFIX_OPCODE },
3577   },
3578 
3579   /* PREFIX_0F38F1 */
3580   {
3581     { "movbeS",	{ Mv, Gv }, PREFIX_OPCODE },
3582     { Bad_Opcode },
3583     { "movbeS",	{ Mv, Gv }, PREFIX_OPCODE },
3584     { "crc32Q",	{ Gdq, Ev }, PREFIX_OPCODE },
3585   },
3586 
3587   /* PREFIX_0F38F6 */
3588   {
3589     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3590     { "adoxS",	{ Gdq, Edq}, PREFIX_OPCODE },
3591     { "adcxS",	{ Gdq, Edq}, PREFIX_OPCODE },
3592     { Bad_Opcode },
3593   },
3594 
3595   /* PREFIX_0F38F8 */
3596   {
3597     { Bad_Opcode },
3598     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3599     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3600     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3601   },
3602   /* PREFIX_0F38FA */
3603   {
3604     { Bad_Opcode },
3605     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3606   },
3607 
3608   /* PREFIX_0F38FB */
3609   {
3610     { Bad_Opcode },
3611     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3612   },
3613 
3614   /* PREFIX_0F3A0F */
3615   {
3616     { Bad_Opcode },
3617     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3618   },
3619 
3620   /* PREFIX_VEX_0F10 */
3621   {
3622     { "vmovups",	{ XM, EXx }, 0 },
3623     { "vmovss",		{ XMScalar, VexScalarR, EXxmm_md }, 0 },
3624     { "vmovupd",	{ XM, EXx }, 0 },
3625     { "vmovsd",		{ XMScalar, VexScalarR, EXxmm_mq }, 0 },
3626   },
3627 
3628   /* PREFIX_VEX_0F11 */
3629   {
3630     { "vmovups",	{ EXxS, XM }, 0 },
3631     { "vmovss",		{ EXdS, VexScalarR, XMScalar }, 0 },
3632     { "vmovupd",	{ EXxS, XM }, 0 },
3633     { "vmovsd",		{ EXqS, VexScalarR, XMScalar }, 0 },
3634   },
3635 
3636   /* PREFIX_VEX_0F12 */
3637   {
3638     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3639     { "vmovsldup",	{ XM, EXx }, 0 },
3640     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3641     { "vmovddup",	{ XM, EXymmq }, 0 },
3642   },
3643 
3644   /* PREFIX_VEX_0F16 */
3645   {
3646     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3647     { "vmovshdup",	{ XM, EXx }, 0 },
3648     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3649   },
3650 
3651   /* PREFIX_VEX_0F2A */
3652   {
3653     { Bad_Opcode },
3654     { "vcvtsi2ss{%LQ|}",	{ XMScalar, VexScalar, Edq }, 0 },
3655     { Bad_Opcode },
3656     { "vcvtsi2sd{%LQ|}",	{ XMScalar, VexScalar, Edq }, 0 },
3657   },
3658 
3659   /* PREFIX_VEX_0F2C */
3660   {
3661     { Bad_Opcode },
3662     { "vcvttss2si",	{ Gdq, EXxmm_md, EXxEVexS }, 0 },
3663     { Bad_Opcode },
3664     { "vcvttsd2si",	{ Gdq, EXxmm_mq, EXxEVexS }, 0 },
3665   },
3666 
3667   /* PREFIX_VEX_0F2D */
3668   {
3669     { Bad_Opcode },
3670     { "vcvtss2si",	{ Gdq, EXxmm_md, EXxEVexR }, 0 },
3671     { Bad_Opcode },
3672     { "vcvtsd2si",	{ Gdq, EXxmm_mq, EXxEVexR }, 0 },
3673   },
3674 
3675   /* PREFIX_VEX_0F2E */
3676   {
3677     { "vucomisX",	{ XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3678     { Bad_Opcode },
3679     { "vucomisX",	{ XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3680   },
3681 
3682   /* PREFIX_VEX_0F2F */
3683   {
3684     { "vcomisX",	{ XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3685     { Bad_Opcode },
3686     { "vcomisX",	{ XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3687   },
3688 
3689   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3690   {
3691     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3692     { Bad_Opcode },
3693     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3694   },
3695 
3696   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3697   {
3698     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3699     { Bad_Opcode },
3700     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3701   },
3702 
3703   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3704   {
3705     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3706     { Bad_Opcode },
3707     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3708   },
3709 
3710   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3711   {
3712     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3713     { Bad_Opcode },
3714     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3715   },
3716 
3717   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3718   {
3719     { "knotw",          { MaskG, MaskE }, 0 },
3720     { Bad_Opcode },
3721     { "knotb",          { MaskG, MaskE }, 0 },
3722   },
3723 
3724   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3725   {
3726     { "knotq",          { MaskG, MaskE }, 0 },
3727     { Bad_Opcode },
3728     { "knotd",          { MaskG, MaskE }, 0 },
3729   },
3730 
3731   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3732   {
3733     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3734     { Bad_Opcode },
3735     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3736   },
3737 
3738   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3739   {
3740     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3741     { Bad_Opcode },
3742     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3743   },
3744 
3745   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3746   {
3747     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3748     { Bad_Opcode },
3749     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3750   },
3751 
3752   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3753   {
3754     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3755     { Bad_Opcode },
3756     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3757   },
3758 
3759   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3760   {
3761     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3762     { Bad_Opcode },
3763     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3764   },
3765 
3766   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3767   {
3768     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3769     { Bad_Opcode },
3770     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3771   },
3772 
3773   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3774   {
3775     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3776     { Bad_Opcode },
3777     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3778   },
3779 
3780   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3781   {
3782     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3783     { Bad_Opcode },
3784     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3785   },
3786 
3787   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3788   {
3789     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3790     { Bad_Opcode },
3791     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3792   },
3793 
3794   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3795   {
3796     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3797   },
3798 
3799   /* PREFIX_VEX_0F51 */
3800   {
3801     { "vsqrtps",	{ XM, EXx }, 0 },
3802     { "vsqrtss",	{ XMScalar, VexScalar, EXxmm_md }, 0 },
3803     { "vsqrtpd",	{ XM, EXx }, 0 },
3804     { "vsqrtsd",	{ XMScalar, VexScalar, EXxmm_mq }, 0 },
3805   },
3806 
3807   /* PREFIX_VEX_0F52 */
3808   {
3809     { "vrsqrtps",	{ XM, EXx }, 0 },
3810     { "vrsqrtss",	{ XMScalar, VexScalar, EXxmm_md }, 0 },
3811   },
3812 
3813   /* PREFIX_VEX_0F53 */
3814   {
3815     { "vrcpps",		{ XM, EXx }, 0 },
3816     { "vrcpss",		{ XMScalar, VexScalar, EXxmm_md }, 0 },
3817   },
3818 
3819   /* PREFIX_VEX_0F58 */
3820   {
3821     { "vaddps",		{ XM, Vex, EXx }, 0 },
3822     { "vaddss",		{ XMScalar, VexScalar, EXxmm_md }, 0 },
3823     { "vaddpd",		{ XM, Vex, EXx }, 0 },
3824     { "vaddsd",		{ XMScalar, VexScalar, EXxmm_mq }, 0 },
3825   },
3826 
3827   /* PREFIX_VEX_0F59 */
3828   {
3829     { "vmulps",		{ XM, Vex, EXx }, 0 },
3830     { "vmulss",		{ XMScalar, VexScalar, EXxmm_md }, 0 },
3831     { "vmulpd",		{ XM, Vex, EXx }, 0 },
3832     { "vmulsd",		{ XMScalar, VexScalar, EXxmm_mq }, 0 },
3833   },
3834 
3835   /* PREFIX_VEX_0F5A */
3836   {
3837     { "vcvtps2pd",	{ XM, EXxmmq }, 0 },
3838     { "vcvtss2sd",	{ XMScalar, VexScalar, EXxmm_md }, 0 },
3839     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3840     { "vcvtsd2ss",	{ XMScalar, VexScalar, EXxmm_mq }, 0 },
3841   },
3842 
3843   /* PREFIX_VEX_0F5B */
3844   {
3845     { "vcvtdq2ps",	{ XM, EXx }, 0 },
3846     { "vcvttps2dq",	{ XM, EXx }, 0 },
3847     { "vcvtps2dq",	{ XM, EXx }, 0 },
3848   },
3849 
3850   /* PREFIX_VEX_0F5C */
3851   {
3852     { "vsubps",		{ XM, Vex, EXx }, 0 },
3853     { "vsubss",		{ XMScalar, VexScalar, EXxmm_md }, 0 },
3854     { "vsubpd",		{ XM, Vex, EXx }, 0 },
3855     { "vsubsd",		{ XMScalar, VexScalar, EXxmm_mq }, 0 },
3856   },
3857 
3858   /* PREFIX_VEX_0F5D */
3859   {
3860     { "vminps",		{ XM, Vex, EXx }, 0 },
3861     { "vminss",		{ XMScalar, VexScalar, EXxmm_md }, 0 },
3862     { "vminpd",		{ XM, Vex, EXx }, 0 },
3863     { "vminsd",		{ XMScalar, VexScalar, EXxmm_mq }, 0 },
3864   },
3865 
3866   /* PREFIX_VEX_0F5E */
3867   {
3868     { "vdivps",		{ XM, Vex, EXx }, 0 },
3869     { "vdivss",		{ XMScalar, VexScalar, EXxmm_md }, 0 },
3870     { "vdivpd",		{ XM, Vex, EXx }, 0 },
3871     { "vdivsd",		{ XMScalar, VexScalar, EXxmm_mq }, 0 },
3872   },
3873 
3874   /* PREFIX_VEX_0F5F */
3875   {
3876     { "vmaxps",		{ XM, Vex, EXx }, 0 },
3877     { "vmaxss",		{ XMScalar, VexScalar, EXxmm_md }, 0 },
3878     { "vmaxpd",		{ XM, Vex, EXx }, 0 },
3879     { "vmaxsd",		{ XMScalar, VexScalar, EXxmm_mq }, 0 },
3880   },
3881 
3882   /* PREFIX_VEX_0F6F */
3883   {
3884     { Bad_Opcode },
3885     { "vmovdqu",	{ XM, EXx }, 0 },
3886     { "vmovdqa",	{ XM, EXx }, 0 },
3887   },
3888 
3889   /* PREFIX_VEX_0F70 */
3890   {
3891     { Bad_Opcode },
3892     { "vpshufhw",	{ XM, EXx, Ib }, 0 },
3893     { "vpshufd",	{ XM, EXx, Ib }, 0 },
3894     { "vpshuflw",	{ XM, EXx, Ib }, 0 },
3895   },
3896 
3897   /* PREFIX_VEX_0F7C */
3898   {
3899     { Bad_Opcode },
3900     { Bad_Opcode },
3901     { "vhaddpd",	{ XM, Vex, EXx }, 0 },
3902     { "vhaddps",	{ XM, Vex, EXx }, 0 },
3903   },
3904 
3905   /* PREFIX_VEX_0F7D */
3906   {
3907     { Bad_Opcode },
3908     { Bad_Opcode },
3909     { "vhsubpd",	{ XM, Vex, EXx }, 0 },
3910     { "vhsubps",	{ XM, Vex, EXx }, 0 },
3911   },
3912 
3913   /* PREFIX_VEX_0F7E */
3914   {
3915     { Bad_Opcode },
3916     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3917     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3918   },
3919 
3920   /* PREFIX_VEX_0F7F */
3921   {
3922     { Bad_Opcode },
3923     { "vmovdqu",	{ EXxS, XM }, 0 },
3924     { "vmovdqa",	{ EXxS, XM }, 0 },
3925   },
3926 
3927   /* PREFIX_VEX_0F90_L_0_W_0 */
3928   {
3929     { "kmovw",		{ MaskG, MaskE }, 0 },
3930     { Bad_Opcode },
3931     { "kmovb",		{ MaskG, MaskBDE }, 0 },
3932   },
3933 
3934   /* PREFIX_VEX_0F90_L_0_W_1 */
3935   {
3936     { "kmovq",		{ MaskG, MaskE }, 0 },
3937     { Bad_Opcode },
3938     { "kmovd",		{ MaskG, MaskBDE }, 0 },
3939   },
3940 
3941   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3942   {
3943     { "kmovw",		{ Ew, MaskG }, 0 },
3944     { Bad_Opcode },
3945     { "kmovb",		{ Eb, MaskG }, 0 },
3946   },
3947 
3948   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3949   {
3950     { "kmovq",		{ Eq, MaskG }, 0 },
3951     { Bad_Opcode },
3952     { "kmovd",		{ Ed, MaskG }, 0 },
3953   },
3954 
3955   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3956   {
3957     { "kmovw",		{ MaskG, Edq }, 0 },
3958     { Bad_Opcode },
3959     { "kmovb",		{ MaskG, Edq }, 0 },
3960     { "kmovd",		{ MaskG, Edq }, 0 },
3961   },
3962 
3963   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3964   {
3965     { Bad_Opcode },
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { "kmovK",		{ MaskG, Edq }, 0 },
3969   },
3970 
3971   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3972   {
3973     { "kmovw",		{ Gdq, MaskE }, 0 },
3974     { Bad_Opcode },
3975     { "kmovb",		{ Gdq, MaskE }, 0 },
3976     { "kmovd",		{ Gdq, MaskE }, 0 },
3977   },
3978 
3979   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3980   {
3981     { Bad_Opcode },
3982     { Bad_Opcode },
3983     { Bad_Opcode },
3984     { "kmovK",		{ Gdq, MaskE }, 0 },
3985   },
3986 
3987   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3988   {
3989     { "kortestw", { MaskG, MaskE }, 0 },
3990     { Bad_Opcode },
3991     { "kortestb", { MaskG, MaskE }, 0 },
3992   },
3993 
3994   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3995   {
3996     { "kortestq", { MaskG, MaskE }, 0 },
3997     { Bad_Opcode },
3998     { "kortestd", { MaskG, MaskE }, 0 },
3999   },
4000 
4001   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4002   {
4003     { "ktestw", { MaskG, MaskE }, 0 },
4004     { Bad_Opcode },
4005     { "ktestb", { MaskG, MaskE }, 0 },
4006   },
4007 
4008   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4009   {
4010     { "ktestq", { MaskG, MaskE }, 0 },
4011     { Bad_Opcode },
4012     { "ktestd", { MaskG, MaskE }, 0 },
4013   },
4014 
4015   /* PREFIX_VEX_0FC2 */
4016   {
4017     { "vcmpps",		{ XM, Vex, EXx, CMP }, 0 },
4018     { "vcmpss",		{ XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4019     { "vcmppd",		{ XM, Vex, EXx, CMP }, 0 },
4020     { "vcmpsd",		{ XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4021   },
4022 
4023   /* PREFIX_VEX_0FD0 */
4024   {
4025     { Bad_Opcode },
4026     { Bad_Opcode },
4027     { "vaddsubpd",	{ XM, Vex, EXx }, 0 },
4028     { "vaddsubps",	{ XM, Vex, EXx }, 0 },
4029   },
4030 
4031   /* PREFIX_VEX_0FE6 */
4032   {
4033     { Bad_Opcode },
4034     { "vcvtdq2pd",	{ XM, EXxmmq }, 0 },
4035     { "vcvttpd2dq%XY",	{ XMM, EXx }, 0 },
4036     { "vcvtpd2dq%XY",	{ XMM, EXx }, 0 },
4037   },
4038 
4039   /* PREFIX_VEX_0FF0 */
4040   {
4041     { Bad_Opcode },
4042     { Bad_Opcode },
4043     { Bad_Opcode },
4044     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4045   },
4046 
4047   /* PREFIX_VEX_0F3849_X86_64 */
4048   {
4049     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4050     { Bad_Opcode },
4051     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4052     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4053   },
4054 
4055   /* PREFIX_VEX_0F384B_X86_64 */
4056   {
4057     { Bad_Opcode },
4058     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4059     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4060     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4061   },
4062 
4063   /* PREFIX_VEX_0F385C_X86_64 */
4064   {
4065     { Bad_Opcode },
4066     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4067     { Bad_Opcode },
4068   },
4069 
4070   /* PREFIX_VEX_0F385E_X86_64 */
4071   {
4072     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4073     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4074     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4075     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4076   },
4077 
4078   /* PREFIX_VEX_0F38F5_L_0 */
4079   {
4080     { "bzhiS",		{ Gdq, Edq, VexGdq }, 0 },
4081     { "pextS",		{ Gdq, VexGdq, Edq }, 0 },
4082     { Bad_Opcode },
4083     { "pdepS",		{ Gdq, VexGdq, Edq }, 0 },
4084   },
4085 
4086   /* PREFIX_VEX_0F38F6_L_0 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { "mulxS",		{ Gdq, VexGdq, Edq }, 0 },
4092   },
4093 
4094   /* PREFIX_VEX_0F38F7_L_0 */
4095   {
4096     { "bextrS",		{ Gdq, Edq, VexGdq }, 0 },
4097     { "sarxS",		{ Gdq, Edq, VexGdq }, 0 },
4098     { "shlxS",		{ Gdq, Edq, VexGdq }, 0 },
4099     { "shrxS",		{ Gdq, Edq, VexGdq }, 0 },
4100   },
4101 
4102   /* PREFIX_VEX_0F3AF0_L_0 */
4103   {
4104     { Bad_Opcode },
4105     { Bad_Opcode },
4106     { Bad_Opcode },
4107     { "rorxS",		{ Gdq, Edq, Ib }, 0 },
4108   },
4109 
4110 #include "i386-dis-evex-prefix.h"
4111 };
4112 
4113 static const struct dis386 x86_64_table[][2] = {
4114   /* X86_64_06 */
4115   {
4116     { "pushP", { es }, 0 },
4117   },
4118 
4119   /* X86_64_07 */
4120   {
4121     { "popP", { es }, 0 },
4122   },
4123 
4124   /* X86_64_0E */
4125   {
4126     { "pushP", { cs }, 0 },
4127   },
4128 
4129   /* X86_64_16 */
4130   {
4131     { "pushP", { ss }, 0 },
4132   },
4133 
4134   /* X86_64_17 */
4135   {
4136     { "popP", { ss }, 0 },
4137   },
4138 
4139   /* X86_64_1E */
4140   {
4141     { "pushP", { ds }, 0 },
4142   },
4143 
4144   /* X86_64_1F */
4145   {
4146     { "popP", { ds }, 0 },
4147   },
4148 
4149   /* X86_64_27 */
4150   {
4151     { "daa", { XX }, 0 },
4152   },
4153 
4154   /* X86_64_2F */
4155   {
4156     { "das", { XX }, 0 },
4157   },
4158 
4159   /* X86_64_37 */
4160   {
4161     { "aaa", { XX }, 0 },
4162   },
4163 
4164   /* X86_64_3F */
4165   {
4166     { "aas", { XX }, 0 },
4167   },
4168 
4169   /* X86_64_60 */
4170   {
4171     { "pushaP", { XX }, 0 },
4172   },
4173 
4174   /* X86_64_61 */
4175   {
4176     { "popaP", { XX }, 0 },
4177   },
4178 
4179   /* X86_64_62 */
4180   {
4181     { MOD_TABLE (MOD_62_32BIT) },
4182     { EVEX_TABLE (EVEX_0F) },
4183   },
4184 
4185   /* X86_64_63 */
4186   {
4187     { "arpl", { Ew, Gw }, 0 },
4188     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4189   },
4190 
4191   /* X86_64_6D */
4192   {
4193     { "ins{R|}", { Yzr, indirDX }, 0 },
4194     { "ins{G|}", { Yzr, indirDX }, 0 },
4195   },
4196 
4197   /* X86_64_6F */
4198   {
4199     { "outs{R|}", { indirDXr, Xz }, 0 },
4200     { "outs{G|}", { indirDXr, Xz }, 0 },
4201   },
4202 
4203   /* X86_64_82 */
4204   {
4205     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4206     { REG_TABLE (REG_80) },
4207   },
4208 
4209   /* X86_64_9A */
4210   {
4211     { "{l|}call{P|}", { Ap }, 0 },
4212   },
4213 
4214   /* X86_64_C2 */
4215   {
4216     { "retP",		{ Iw, BND }, 0 },
4217     { "ret@",		{ Iw, BND }, 0 },
4218   },
4219 
4220   /* X86_64_C3 */
4221   {
4222     { "retP",		{ BND }, 0 },
4223     { "ret@",		{ BND }, 0 },
4224   },
4225 
4226   /* X86_64_C4 */
4227   {
4228     { MOD_TABLE (MOD_C4_32BIT) },
4229     { VEX_C4_TABLE (VEX_0F) },
4230   },
4231 
4232   /* X86_64_C5 */
4233   {
4234     { MOD_TABLE (MOD_C5_32BIT) },
4235     { VEX_C5_TABLE (VEX_0F) },
4236   },
4237 
4238   /* X86_64_CE */
4239   {
4240     { "into", { XX }, 0 },
4241   },
4242 
4243   /* X86_64_D4 */
4244   {
4245     { "aam", { Ib }, 0 },
4246   },
4247 
4248   /* X86_64_D5 */
4249   {
4250     { "aad", { Ib }, 0 },
4251   },
4252 
4253   /* X86_64_E8 */
4254   {
4255     { "callP",		{ Jv, BND }, 0 },
4256     { "call@",		{ Jv, BND }, 0 }
4257   },
4258 
4259   /* X86_64_E9 */
4260   {
4261     { "jmpP",		{ Jv, BND }, 0 },
4262     { "jmp@",		{ Jv, BND }, 0 }
4263   },
4264 
4265   /* X86_64_EA */
4266   {
4267     { "{l|}jmp{P|}", { Ap }, 0 },
4268   },
4269 
4270   /* X86_64_0F01_REG_0 */
4271   {
4272     { "sgdt{Q|Q}", { M }, 0 },
4273     { "sgdt", { M }, 0 },
4274   },
4275 
4276   /* X86_64_0F01_REG_1 */
4277   {
4278     { "sidt{Q|Q}", { M }, 0 },
4279     { "sidt", { M }, 0 },
4280   },
4281 
4282   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4283   {
4284     { Bad_Opcode },
4285     { "seamret",	{ Skip_MODRM }, 0 },
4286   },
4287 
4288   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4289   {
4290     { Bad_Opcode },
4291     { "seamops",	{ Skip_MODRM }, 0 },
4292   },
4293 
4294   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4295   {
4296     { Bad_Opcode },
4297     { "seamcall",	{ Skip_MODRM }, 0 },
4298   },
4299 
4300   /* X86_64_0F01_REG_2 */
4301   {
4302     { "lgdt{Q|Q}", { M }, 0 },
4303     { "lgdt", { M }, 0 },
4304   },
4305 
4306   /* X86_64_0F01_REG_3 */
4307   {
4308     { "lidt{Q|Q}", { M }, 0 },
4309     { "lidt", { M }, 0 },
4310   },
4311 
4312   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4313   {
4314     { Bad_Opcode },
4315     { "uiret",	{ Skip_MODRM }, 0 },
4316   },
4317 
4318   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4319   {
4320     { Bad_Opcode },
4321     { "testui",	{ Skip_MODRM }, 0 },
4322   },
4323 
4324   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4325   {
4326     { Bad_Opcode },
4327     { "clui",	{ Skip_MODRM }, 0 },
4328   },
4329 
4330   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4331   {
4332     { Bad_Opcode },
4333     { "stui",	{ Skip_MODRM }, 0 },
4334   },
4335 
4336   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4337   {
4338     { Bad_Opcode },
4339     { "rmpadjust",	{ Skip_MODRM }, 0 },
4340   },
4341 
4342   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4343   {
4344     { Bad_Opcode },
4345     { "rmpupdate",	{ Skip_MODRM }, 0 },
4346   },
4347 
4348   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4349   {
4350     { Bad_Opcode },
4351     { "psmash",	{ Skip_MODRM }, 0 },
4352   },
4353 
4354   {
4355     /* X86_64_0F24 */
4356     { "movZ",		{ Em, Td }, 0 },
4357   },
4358 
4359   {
4360     /* X86_64_0F26 */
4361     { "movZ",		{ Td, Em }, 0 },
4362   },
4363 
4364   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4365   {
4366     { Bad_Opcode },
4367     { "senduipi",	{ Eq }, 0 },
4368   },
4369 
4370   /* X86_64_VEX_0F3849 */
4371   {
4372     { Bad_Opcode },
4373     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4374   },
4375 
4376   /* X86_64_VEX_0F384B */
4377   {
4378     { Bad_Opcode },
4379     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4380   },
4381 
4382   /* X86_64_VEX_0F385C */
4383   {
4384     { Bad_Opcode },
4385     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4386   },
4387 
4388   /* X86_64_VEX_0F385E */
4389   {
4390     { Bad_Opcode },
4391     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4392   },
4393 };
4394 
4395 static const struct dis386 three_byte_table[][256] = {
4396 
4397   /* THREE_BYTE_0F38 */
4398   {
4399     /* 00 */
4400     { "pshufb",		{ MX, EM }, PREFIX_OPCODE },
4401     { "phaddw",		{ MX, EM }, PREFIX_OPCODE },
4402     { "phaddd",		{ MX, EM }, PREFIX_OPCODE },
4403     { "phaddsw",	{ MX, EM }, PREFIX_OPCODE },
4404     { "pmaddubsw",	{ MX, EM }, PREFIX_OPCODE },
4405     { "phsubw",		{ MX, EM }, PREFIX_OPCODE },
4406     { "phsubd",		{ MX, EM }, PREFIX_OPCODE },
4407     { "phsubsw",	{ MX, EM }, PREFIX_OPCODE },
4408     /* 08 */
4409     { "psignb",		{ MX, EM }, PREFIX_OPCODE },
4410     { "psignw",		{ MX, EM }, PREFIX_OPCODE },
4411     { "psignd",		{ MX, EM }, PREFIX_OPCODE },
4412     { "pmulhrsw",	{ MX, EM }, PREFIX_OPCODE },
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     /* 10 */
4418     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4423     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4424     { Bad_Opcode },
4425     { "ptest",  { XM, EXx }, PREFIX_DATA },
4426     /* 18 */
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "pabsb",		{ MX, EM }, PREFIX_OPCODE },
4432     { "pabsw",		{ MX, EM }, PREFIX_OPCODE },
4433     { "pabsd",		{ MX, EM }, PREFIX_OPCODE },
4434     { Bad_Opcode },
4435     /* 20 */
4436     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4437     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4438     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4439     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4440     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4441     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4442     { Bad_Opcode },
4443     { Bad_Opcode },
4444     /* 28 */
4445     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4446     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4447     { MOD_TABLE (MOD_0F382A) },
4448     { "packusdw", { XM, EXx }, PREFIX_DATA },
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     /* 30 */
4454     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4455     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4456     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4457     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4458     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4459     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4460     { Bad_Opcode },
4461     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4462     /* 38 */
4463     { "pminsb",	{ XM, EXx }, PREFIX_DATA },
4464     { "pminsd",	{ XM, EXx }, PREFIX_DATA },
4465     { "pminuw",	{ XM, EXx }, PREFIX_DATA },
4466     { "pminud",	{ XM, EXx }, PREFIX_DATA },
4467     { "pmaxsb",	{ XM, EXx }, PREFIX_DATA },
4468     { "pmaxsd",	{ XM, EXx }, PREFIX_DATA },
4469     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4470     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4471     /* 40 */
4472     { "pmulld", { XM, EXx }, PREFIX_DATA },
4473     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     /* 48 */
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     /* 50 */
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     /* 58 */
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     /* 60 */
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     /* 68 */
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     /* 70 */
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     /* 78 */
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     /* 80 */
4544     { "invept",	{ Gm, Mo }, PREFIX_DATA },
4545     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4546     { "invpcid", { Gm, M }, PREFIX_DATA },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     /* 88 */
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     /* 90 */
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     /* 98 */
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     /* a0 */
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     /* a8 */
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     /* b0 */
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     /* b8 */
4607     { Bad_Opcode },
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     /* c0 */
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     /* c8 */
4625     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4626     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4627     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4628     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4629     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4630     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4631     { Bad_Opcode },
4632     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4633     /* d0 */
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     /* d8 */
4643     { PREFIX_TABLE (PREFIX_0F38D8) },
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { "aesimc", { XM, EXx }, PREFIX_DATA },
4647     { PREFIX_TABLE (PREFIX_0F38DC) },
4648     { PREFIX_TABLE (PREFIX_0F38DD) },
4649     { PREFIX_TABLE (PREFIX_0F38DE) },
4650     { PREFIX_TABLE (PREFIX_0F38DF) },
4651     /* e0 */
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     /* e8 */
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     /* f0 */
4670     { PREFIX_TABLE (PREFIX_0F38F0) },
4671     { PREFIX_TABLE (PREFIX_0F38F1) },
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { MOD_TABLE (MOD_0F38F5) },
4676     { PREFIX_TABLE (PREFIX_0F38F6) },
4677     { Bad_Opcode },
4678     /* f8 */
4679     { PREFIX_TABLE (PREFIX_0F38F8) },
4680     { MOD_TABLE (MOD_0F38F9) },
4681     { PREFIX_TABLE (PREFIX_0F38FA) },
4682     { PREFIX_TABLE (PREFIX_0F38FB) },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687   },
4688   /* THREE_BYTE_0F3A */
4689   {
4690     /* 00 */
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     /* 08 */
4700     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4701     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4702     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4703     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4704     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4705     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4706     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4707     { "palignr",	{ MX, EM, Ib }, PREFIX_OPCODE },
4708     /* 10 */
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "pextrb",	{ Edqb, XM, Ib }, PREFIX_DATA },
4714     { "pextrw",	{ Edqw, XM, Ib }, PREFIX_DATA },
4715     { "pextrK",	{ Edq, XM, Ib }, PREFIX_DATA },
4716     { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4717     /* 18 */
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     /* 20 */
4727     { "pinsrb",	{ XM, Edqb, Ib }, PREFIX_DATA },
4728     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4729     { "pinsrK",	{ XM, Edq, Ib }, PREFIX_DATA },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     /* 28 */
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     /* 30 */
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     /* 38 */
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     /* 40 */
4763     { "dpps",	{ XM, EXx, Ib }, PREFIX_DATA },
4764     { "dppd",	{ XM, EXx, Ib }, PREFIX_DATA },
4765     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4766     { Bad_Opcode },
4767     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     /* 48 */
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     /* 50 */
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     /* 58 */
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     /* 60 */
4799     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4800     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4801     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4802     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     /* 68 */
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     /* 70 */
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     /* 78 */
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     /* 80 */
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     /* 88 */
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     /* 90 */
4853     { Bad_Opcode },
4854     { Bad_Opcode },
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     /* 98 */
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     /* a0 */
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     /* a8 */
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     /* b0 */
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     /* b8 */
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     /* c0 */
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     /* c8 */
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4921     { Bad_Opcode },
4922     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4923     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4924     /* d0 */
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     /* d8 */
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4942     /* e0 */
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     /* e8 */
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     /* f0 */
4961     { PREFIX_TABLE (PREFIX_0F3A0F) },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     /* f8 */
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978   },
4979 };
4980 
4981 static const struct dis386 xop_table[][256] = {
4982   /* XOP_08 */
4983   {
4984     /* 00 */
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     /* 08 */
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     /* 10 */
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     /* 18 */
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     /* 20 */
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     /* 28 */
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     /* 30 */
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     /* 38 */
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     /* 40 */
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     /* 48 */
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     /* 50 */
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     /* 58 */
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     /* 60 */
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     /* 68 */
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     /* 70 */
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     /* 78 */
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     /* 80 */
5129     { Bad_Opcode },
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5135     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5136     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5137     /* 88 */
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5145     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5146     /* 90 */
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5153     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5154     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5155     /* 98 */
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5163     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5164     /* a0 */
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { "vpcmov", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
5168     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5172     { Bad_Opcode },
5173     /* a8 */
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     /* b0 */
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5190     { Bad_Opcode },
5191     /* b8 */
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     /* c0 */
5201     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5202     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5203     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5204     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     /* c8 */
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5215     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5216     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5217     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5218     /* d0 */
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     /* d8 */
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     /* e0 */
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     /* e8 */
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5251     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5252     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5253     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5254     /* f0 */
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     /* f8 */
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272   },
5273   /* XOP_09 */
5274   {
5275     /* 00 */
5276     { Bad_Opcode },
5277     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5278     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     /* 08 */
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     /* 10 */
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { MOD_TABLE (MOD_XOP_09_12) },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     /* 18 */
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     /* 20 */
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     /* 28 */
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     /* 30 */
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     /* 38 */
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     /* 40 */
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     /* 48 */
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     /* 50 */
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     /* 58 */
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     /* 60 */
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     /* 68 */
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     /* 70 */
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     /* 78 */
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     /* 80 */
5420     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5421     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5422     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5423     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     /* 88 */
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     /* 90 */
5438     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5439     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5440     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5441     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5442     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5443     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5444     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5445     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5446     /* 98 */
5447     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5448     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5449     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5450     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     /* a0 */
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     /* a8 */
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     /* b0 */
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     /* b8 */
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     /* c0 */
5492     { Bad_Opcode },
5493     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5494     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5495     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5499     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5500     /* c8 */
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     /* d0 */
5510     { Bad_Opcode },
5511     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5512     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5513     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5517     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5518     /* d8 */
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     /* e0 */
5528     { Bad_Opcode },
5529     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5530     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5531     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     /* e8 */
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     /* f0 */
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     /* f8 */
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563   },
5564   /* XOP_0A */
5565   {
5566     /* 00 */
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     /* 08 */
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     /* 10 */
5585     { "bextrS",	{ Gdq, Edq, Id }, 0 },
5586     { Bad_Opcode },
5587     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     /* 18 */
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     /* 20 */
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     /* 28 */
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     /* 30 */
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     /* 38 */
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     /* 40 */
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     /* 48 */
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     /* 50 */
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     /* 58 */
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     /* 60 */
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     /* 68 */
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     /* 70 */
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     /* 78 */
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     /* 80 */
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     /* 88 */
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     /* 90 */
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     /* 98 */
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     /* a0 */
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     /* a8 */
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     /* b0 */
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     /* b8 */
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     /* c0 */
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     /* c8 */
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     /* d0 */
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     /* d8 */
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     /* e0 */
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     /* e8 */
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     /* f0 */
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     /* f8 */
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854   },
5855 };
5856 
5857 static const struct dis386 vex_table[][256] = {
5858   /* VEX_0F */
5859   {
5860     /* 00 */
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     /* 08 */
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     /* 10 */
5879     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5880     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5881     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5882     { MOD_TABLE (MOD_VEX_0F13) },
5883     { "vunpcklpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
5884     { "vunpckhpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
5885     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5886     { MOD_TABLE (MOD_VEX_0F17) },
5887     /* 18 */
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     /* 20 */
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     /* 28 */
5906     { "vmovapX",	{ XM, EXx }, PREFIX_OPCODE },
5907     { "vmovapX",	{ EXxS, XM }, PREFIX_OPCODE },
5908     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5909     { MOD_TABLE (MOD_VEX_0F2B) },
5910     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5911     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5912     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5913     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5914     /* 30 */
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     /* 38 */
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     /* 40 */
5933     { Bad_Opcode },
5934     { VEX_LEN_TABLE (VEX_LEN_0F41) },
5935     { VEX_LEN_TABLE (VEX_LEN_0F42) },
5936     { Bad_Opcode },
5937     { VEX_LEN_TABLE (VEX_LEN_0F44) },
5938     { VEX_LEN_TABLE (VEX_LEN_0F45) },
5939     { VEX_LEN_TABLE (VEX_LEN_0F46) },
5940     { VEX_LEN_TABLE (VEX_LEN_0F47) },
5941     /* 48 */
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5945     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     /* 50 */
5951     { MOD_TABLE (MOD_VEX_0F50) },
5952     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5953     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5954     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5955     { "vandpX",		{ XM, Vex, EXx }, PREFIX_OPCODE },
5956     { "vandnpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
5957     { "vorpX",		{ XM, Vex, EXx }, PREFIX_OPCODE },
5958     { "vxorpX",		{ XM, Vex, EXx }, PREFIX_OPCODE },
5959     /* 58 */
5960     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5961     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5962     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5963     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5964     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5965     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5966     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5967     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5968     /* 60 */
5969     { "vpunpcklbw",	{ XM, Vex, EXx }, PREFIX_DATA },
5970     { "vpunpcklwd",	{ XM, Vex, EXx }, PREFIX_DATA },
5971     { "vpunpckldq",	{ XM, Vex, EXx }, PREFIX_DATA },
5972     { "vpacksswb",	{ XM, Vex, EXx }, PREFIX_DATA },
5973     { "vpcmpgtb",	{ XM, Vex, EXx }, PREFIX_DATA },
5974     { "vpcmpgtw",	{ XM, Vex, EXx }, PREFIX_DATA },
5975     { "vpcmpgtd",	{ XM, Vex, EXx }, PREFIX_DATA },
5976     { "vpackuswb",	{ XM, Vex, EXx }, PREFIX_DATA },
5977     /* 68 */
5978     { "vpunpckhbw",	{ XM, Vex, EXx }, PREFIX_DATA },
5979     { "vpunpckhwd",	{ XM, Vex, EXx }, PREFIX_DATA },
5980     { "vpunpckhdq",	{ XM, Vex, EXx }, PREFIX_DATA },
5981     { "vpackssdw",	{ XM, Vex, EXx }, PREFIX_DATA },
5982     { "vpunpcklqdq",	{ XM, Vex, EXx }, PREFIX_DATA },
5983     { "vpunpckhqdq",	{ XM, Vex, EXx }, PREFIX_DATA },
5984     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
5985     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
5986     /* 70 */
5987     { PREFIX_TABLE (PREFIX_VEX_0F70) },
5988     { MOD_TABLE (MOD_VEX_0F71) },
5989     { MOD_TABLE (MOD_VEX_0F72) },
5990     { MOD_TABLE (MOD_VEX_0F73) },
5991     { "vpcmpeqb",	{ XM, Vex, EXx }, PREFIX_DATA },
5992     { "vpcmpeqw",	{ XM, Vex, EXx }, PREFIX_DATA },
5993     { "vpcmpeqd",	{ XM, Vex, EXx }, PREFIX_DATA },
5994     { VEX_LEN_TABLE (VEX_LEN_0F77) },
5995     /* 78 */
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6001     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6002     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6003     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6004     /* 80 */
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     /* 88 */
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     /* 90 */
6023     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6024     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6025     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6026     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     /* 98 */
6032     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6033     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     /* a0 */
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     /* a8 */
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { REG_TABLE (REG_VEX_0FAE) },
6057     { Bad_Opcode },
6058     /* b0 */
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     /* b8 */
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     /* c0 */
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6080     { Bad_Opcode },
6081     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6082     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6083     { "vshufpX",	{ XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6084     { Bad_Opcode },
6085     /* c8 */
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     /* d0 */
6095     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6096     { "vpsrlw",		{ XM, Vex, EXxmm }, PREFIX_DATA },
6097     { "vpsrld",		{ XM, Vex, EXxmm }, PREFIX_DATA },
6098     { "vpsrlq",		{ XM, Vex, EXxmm }, PREFIX_DATA },
6099     { "vpaddq",		{ XM, Vex, EXx }, PREFIX_DATA },
6100     { "vpmullw",	{ XM, Vex, EXx }, PREFIX_DATA },
6101     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6102     { MOD_TABLE (MOD_VEX_0FD7) },
6103     /* d8 */
6104     { "vpsubusb",	{ XM, Vex, EXx }, PREFIX_DATA },
6105     { "vpsubusw",	{ XM, Vex, EXx }, PREFIX_DATA },
6106     { "vpminub",	{ XM, Vex, EXx }, PREFIX_DATA },
6107     { "vpand",		{ XM, Vex, EXx }, PREFIX_DATA },
6108     { "vpaddusb",	{ XM, Vex, EXx }, PREFIX_DATA },
6109     { "vpaddusw",	{ XM, Vex, EXx }, PREFIX_DATA },
6110     { "vpmaxub",	{ XM, Vex, EXx }, PREFIX_DATA },
6111     { "vpandn",		{ XM, Vex, EXx }, PREFIX_DATA },
6112     /* e0 */
6113     { "vpavgb",		{ XM, Vex, EXx }, PREFIX_DATA },
6114     { "vpsraw",		{ XM, Vex, EXxmm }, PREFIX_DATA },
6115     { "vpsrad",		{ XM, Vex, EXxmm }, PREFIX_DATA },
6116     { "vpavgw",		{ XM, Vex, EXx }, PREFIX_DATA },
6117     { "vpmulhuw",	{ XM, Vex, EXx }, PREFIX_DATA },
6118     { "vpmulhw",	{ XM, Vex, EXx }, PREFIX_DATA },
6119     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6120     { MOD_TABLE (MOD_VEX_0FE7) },
6121     /* e8 */
6122     { "vpsubsb",	{ XM, Vex, EXx }, PREFIX_DATA },
6123     { "vpsubsw",	{ XM, Vex, EXx }, PREFIX_DATA },
6124     { "vpminsw",	{ XM, Vex, EXx }, PREFIX_DATA },
6125     { "vpor",		{ XM, Vex, EXx }, PREFIX_DATA },
6126     { "vpaddsb",	{ XM, Vex, EXx }, PREFIX_DATA },
6127     { "vpaddsw",	{ XM, Vex, EXx }, PREFIX_DATA },
6128     { "vpmaxsw",	{ XM, Vex, EXx }, PREFIX_DATA },
6129     { "vpxor",		{ XM, Vex, EXx }, PREFIX_DATA },
6130     /* f0 */
6131     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6132     { "vpsllw",		{ XM, Vex, EXxmm }, PREFIX_DATA },
6133     { "vpslld",		{ XM, Vex, EXxmm }, PREFIX_DATA },
6134     { "vpsllq",		{ XM, Vex, EXxmm }, PREFIX_DATA },
6135     { "vpmuludq",	{ XM, Vex, EXx }, PREFIX_DATA },
6136     { "vpmaddwd",	{ XM, Vex, EXx }, PREFIX_DATA },
6137     { "vpsadbw",	{ XM, Vex, EXx }, PREFIX_DATA },
6138     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6139     /* f8 */
6140     { "vpsubb",		{ XM, Vex, EXx }, PREFIX_DATA },
6141     { "vpsubw",		{ XM, Vex, EXx }, PREFIX_DATA },
6142     { "vpsubd",		{ XM, Vex, EXx }, PREFIX_DATA },
6143     { "vpsubq",		{ XM, Vex, EXx }, PREFIX_DATA },
6144     { "vpaddb",		{ XM, Vex, EXx }, PREFIX_DATA },
6145     { "vpaddw",		{ XM, Vex, EXx }, PREFIX_DATA },
6146     { "vpaddd",		{ XM, Vex, EXx }, PREFIX_DATA },
6147     { Bad_Opcode },
6148   },
6149   /* VEX_0F38 */
6150   {
6151     /* 00 */
6152     { "vpshufb",	{ XM, Vex, EXx }, PREFIX_DATA },
6153     { "vphaddw",	{ XM, Vex, EXx }, PREFIX_DATA },
6154     { "vphaddd",	{ XM, Vex, EXx }, PREFIX_DATA },
6155     { "vphaddsw",	{ XM, Vex, EXx }, PREFIX_DATA },
6156     { "vpmaddubsw",	{ XM, Vex, EXx }, PREFIX_DATA },
6157     { "vphsubw",	{ XM, Vex, EXx }, PREFIX_DATA },
6158     { "vphsubd",	{ XM, Vex, EXx }, PREFIX_DATA },
6159     { "vphsubsw",	{ XM, Vex, EXx }, PREFIX_DATA },
6160     /* 08 */
6161     { "vpsignb",	{ XM, Vex, EXx }, PREFIX_DATA },
6162     { "vpsignw",	{ XM, Vex, EXx }, PREFIX_DATA },
6163     { "vpsignd",	{ XM, Vex, EXx }, PREFIX_DATA },
6164     { "vpmulhrsw",	{ XM, Vex, EXx }, PREFIX_DATA },
6165     { VEX_W_TABLE (VEX_W_0F380C) },
6166     { VEX_W_TABLE (VEX_W_0F380D) },
6167     { VEX_W_TABLE (VEX_W_0F380E) },
6168     { VEX_W_TABLE (VEX_W_0F380F) },
6169     /* 10 */
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { VEX_W_TABLE (VEX_W_0F3813) },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6177     { "vptest",		{ XM, EXx }, PREFIX_DATA },
6178     /* 18 */
6179     { VEX_W_TABLE (VEX_W_0F3818) },
6180     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6181     { MOD_TABLE (MOD_VEX_0F381A) },
6182     { Bad_Opcode },
6183     { "vpabsb",		{ XM, EXx }, PREFIX_DATA },
6184     { "vpabsw",		{ XM, EXx }, PREFIX_DATA },
6185     { "vpabsd",		{ XM, EXx }, PREFIX_DATA },
6186     { Bad_Opcode },
6187     /* 20 */
6188     { "vpmovsxbw",	{ XM, EXxmmq }, PREFIX_DATA },
6189     { "vpmovsxbd",	{ XM, EXxmmqd }, PREFIX_DATA },
6190     { "vpmovsxbq",	{ XM, EXxmmdw }, PREFIX_DATA },
6191     { "vpmovsxwd",	{ XM, EXxmmq }, PREFIX_DATA },
6192     { "vpmovsxwq",	{ XM, EXxmmqd }, PREFIX_DATA },
6193     { "vpmovsxdq",	{ XM, EXxmmq }, PREFIX_DATA },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     /* 28 */
6197     { "vpmuldq",	{ XM, Vex, EXx }, PREFIX_DATA },
6198     { "vpcmpeqq",	{ XM, Vex, EXx }, PREFIX_DATA },
6199     { MOD_TABLE (MOD_VEX_0F382A) },
6200     { "vpackusdw",	{ XM, Vex, EXx }, PREFIX_DATA },
6201     { MOD_TABLE (MOD_VEX_0F382C) },
6202     { MOD_TABLE (MOD_VEX_0F382D) },
6203     { MOD_TABLE (MOD_VEX_0F382E) },
6204     { MOD_TABLE (MOD_VEX_0F382F) },
6205     /* 30 */
6206     { "vpmovzxbw",	{ XM, EXxmmq }, PREFIX_DATA },
6207     { "vpmovzxbd",	{ XM, EXxmmqd }, PREFIX_DATA },
6208     { "vpmovzxbq",	{ XM, EXxmmdw }, PREFIX_DATA },
6209     { "vpmovzxwd",	{ XM, EXxmmq }, PREFIX_DATA },
6210     { "vpmovzxwq",	{ XM, EXxmmqd }, PREFIX_DATA },
6211     { "vpmovzxdq",	{ XM, EXxmmq }, PREFIX_DATA },
6212     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6213     { "vpcmpgtq",	{ XM, Vex, EXx }, PREFIX_DATA },
6214     /* 38 */
6215     { "vpminsb",	{ XM, Vex, EXx }, PREFIX_DATA },
6216     { "vpminsd",	{ XM, Vex, EXx }, PREFIX_DATA },
6217     { "vpminuw",	{ XM, Vex, EXx }, PREFIX_DATA },
6218     { "vpminud",	{ XM, Vex, EXx }, PREFIX_DATA },
6219     { "vpmaxsb",	{ XM, Vex, EXx }, PREFIX_DATA },
6220     { "vpmaxsd",	{ XM, Vex, EXx }, PREFIX_DATA },
6221     { "vpmaxuw",	{ XM, Vex, EXx }, PREFIX_DATA },
6222     { "vpmaxud",	{ XM, Vex, EXx }, PREFIX_DATA },
6223     /* 40 */
6224     { "vpmulld",	{ XM, Vex, EXx }, PREFIX_DATA },
6225     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6230     { VEX_W_TABLE (VEX_W_0F3846) },
6231     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6232     /* 48 */
6233     { Bad_Opcode },
6234     { X86_64_TABLE (X86_64_VEX_0F3849) },
6235     { Bad_Opcode },
6236     { X86_64_TABLE (X86_64_VEX_0F384B) },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     /* 50 */
6242     { VEX_W_TABLE (VEX_W_0F3850) },
6243     { VEX_W_TABLE (VEX_W_0F3851) },
6244     { VEX_W_TABLE (VEX_W_0F3852) },
6245     { VEX_W_TABLE (VEX_W_0F3853) },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     /* 58 */
6251     { VEX_W_TABLE (VEX_W_0F3858) },
6252     { VEX_W_TABLE (VEX_W_0F3859) },
6253     { MOD_TABLE (MOD_VEX_0F385A) },
6254     { Bad_Opcode },
6255     { X86_64_TABLE (X86_64_VEX_0F385C) },
6256     { Bad_Opcode },
6257     { X86_64_TABLE (X86_64_VEX_0F385E) },
6258     { Bad_Opcode },
6259     /* 60 */
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     /* 68 */
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     /* 70 */
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     /* 78 */
6287     { VEX_W_TABLE (VEX_W_0F3878) },
6288     { VEX_W_TABLE (VEX_W_0F3879) },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     /* 80 */
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     /* 88 */
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { MOD_TABLE (MOD_VEX_0F388C) },
6310     { Bad_Opcode },
6311     { MOD_TABLE (MOD_VEX_0F388E) },
6312     { Bad_Opcode },
6313     /* 90 */
6314     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6315     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6316     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6317     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6321     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6322     /* 98 */
6323     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6324     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6325     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6326     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6327     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6328     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6329     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6330     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6331     /* a0 */
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6339     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6340     /* a8 */
6341     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6342     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6343     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6345     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6347     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6348     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6349     /* b0 */
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6357     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6358     /* b8 */
6359     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6360     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6361     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6362     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6363     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6364     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6365     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6366     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6367     /* c0 */
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     /* c8 */
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_W_TABLE (VEX_W_0F38CF) },
6385     /* d0 */
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     /* d8 */
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6399     { "vaesenc",	{ XM, Vex, EXx }, PREFIX_DATA },
6400     { "vaesenclast",	{ XM, Vex, EXx }, PREFIX_DATA },
6401     { "vaesdec",	{ XM, Vex, EXx }, PREFIX_DATA },
6402     { "vaesdeclast",	{ XM, Vex, EXx }, PREFIX_DATA },
6403     /* e0 */
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     /* e8 */
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     /* f0 */
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6425     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6426     { Bad_Opcode },
6427     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6428     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6429     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6430     /* f8 */
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439   },
6440   /* VEX_0F3A */
6441   {
6442     /* 00 */
6443     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6444     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6445     { VEX_W_TABLE (VEX_W_0F3A02) },
6446     { Bad_Opcode },
6447     { VEX_W_TABLE (VEX_W_0F3A04) },
6448     { VEX_W_TABLE (VEX_W_0F3A05) },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6450     { Bad_Opcode },
6451     /* 08 */
6452     { "vroundps",	{ XM, EXx, Ib }, PREFIX_DATA },
6453     { "vroundpd",	{ XM, EXx, Ib }, PREFIX_DATA },
6454     { "vroundss",	{ XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6455     { "vroundsd",	{ XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6456     { "vblendps",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
6457     { "vblendpd",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
6458     { "vpblendw",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
6459     { "vpalignr",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
6460     /* 10 */
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6469     /* 18 */
6470     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6471     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_W_TABLE (VEX_W_0F3A1D) },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     /* 20 */
6479     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     /* 28 */
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     /* 30 */
6497     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6498     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6499     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     /* 38 */
6506     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6507     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     /* 40 */
6515     { "vdpps",		{ XM, Vex, EXx, Ib }, PREFIX_DATA },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6517     { "vmpsadbw",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
6518     { Bad_Opcode },
6519     { "vpclmulqdq",	{ XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6522     { Bad_Opcode },
6523     /* 48 */
6524     { "vpermil2ps",	{ XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6525     { "vpermil2pd",	{ XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6526     { VEX_W_TABLE (VEX_W_0F3A4A) },
6527     { VEX_W_TABLE (VEX_W_0F3A4B) },
6528     { VEX_W_TABLE (VEX_W_0F3A4C) },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     /* 50 */
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     /* 58 */
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6547     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6548     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6549     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6550     /* 60 */
6551     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6552     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6553     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6554     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     /* 68 */
6560     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6561     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6562     { "vfmaddss",	{ XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6563     { "vfmaddsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6564     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6565     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6566     { "vfmsubss",	{ XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6567     { "vfmsubsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6568     /* 70 */
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     /* 78 */
6578     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6579     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6580     { "vfnmaddss",	{ XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6581     { "vfnmaddsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6582     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6583     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6584     { "vfnmsubss",	{ XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6585     { "vfnmsubsd",	{ XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6586     /* 80 */
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     /* 88 */
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     /* 90 */
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     /* 98 */
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     /* a0 */
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     /* a8 */
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     /* b0 */
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     /* b8 */
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     /* c0 */
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     /* c8 */
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { VEX_W_TABLE (VEX_W_0F3ACE) },
6675     { VEX_W_TABLE (VEX_W_0F3ACF) },
6676     /* d0 */
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     /* d8 */
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6694     /* e0 */
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     /* e8 */
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     /* f0 */
6713     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     /* f8 */
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730   },
6731 };
6732 
6733 #include "i386-dis-evex.h"
6734 
6735 static const struct dis386 vex_len_table[][2] = {
6736   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6737   {
6738     { "vmovlpX",	{ XM, Vex, EXq }, 0 },
6739   },
6740 
6741   /* VEX_LEN_0F12_P_0_M_1 */
6742   {
6743     { "vmovhlps",	{ XM, Vex, EXq }, 0 },
6744   },
6745 
6746   /* VEX_LEN_0F13_M_0 */
6747   {
6748     { "vmovlpX",	{ EXq, XM }, PREFIX_OPCODE },
6749   },
6750 
6751   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6752   {
6753     { "vmovhpX",	{ XM, Vex, EXq }, 0 },
6754   },
6755 
6756   /* VEX_LEN_0F16_P_0_M_1 */
6757   {
6758     { "vmovlhps",	{ XM, Vex, EXq }, 0 },
6759   },
6760 
6761   /* VEX_LEN_0F17_M_0 */
6762   {
6763     { "vmovhpX",	{ EXq, XM }, PREFIX_OPCODE },
6764   },
6765 
6766   /* VEX_LEN_0F41 */
6767   {
6768     { Bad_Opcode },
6769     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6770   },
6771 
6772   /* VEX_LEN_0F42 */
6773   {
6774     { Bad_Opcode },
6775     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6776   },
6777 
6778   /* VEX_LEN_0F44 */
6779   {
6780     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6781   },
6782 
6783   /* VEX_LEN_0F45 */
6784   {
6785     { Bad_Opcode },
6786     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6787   },
6788 
6789   /* VEX_LEN_0F46 */
6790   {
6791     { Bad_Opcode },
6792     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6793   },
6794 
6795   /* VEX_LEN_0F47 */
6796   {
6797     { Bad_Opcode },
6798     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6799   },
6800 
6801   /* VEX_LEN_0F4A */
6802   {
6803     { Bad_Opcode },
6804     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6805   },
6806 
6807   /* VEX_LEN_0F4B */
6808   {
6809     { Bad_Opcode },
6810     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6811   },
6812 
6813   /* VEX_LEN_0F6E */
6814   {
6815     { "vmovK",		{ XMScalar, Edq }, PREFIX_DATA },
6816   },
6817 
6818   /* VEX_LEN_0F77 */
6819   {
6820     { "vzeroupper",	{ XX }, 0 },
6821     { "vzeroall",	{ XX }, 0 },
6822   },
6823 
6824   /* VEX_LEN_0F7E_P_1 */
6825   {
6826     { "vmovq",		{ XMScalar, EXxmm_mq }, 0 },
6827   },
6828 
6829   /* VEX_LEN_0F7E_P_2 */
6830   {
6831     { "vmovK",		{ Edq, XMScalar }, 0 },
6832   },
6833 
6834   /* VEX_LEN_0F90 */
6835   {
6836     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6837   },
6838 
6839   /* VEX_LEN_0F91 */
6840   {
6841     { MOD_TABLE (MOD_VEX_0F91_L_0) },
6842   },
6843 
6844   /* VEX_LEN_0F92 */
6845   {
6846     { MOD_TABLE (MOD_VEX_0F92_L_0) },
6847   },
6848 
6849   /* VEX_LEN_0F93 */
6850   {
6851     { MOD_TABLE (MOD_VEX_0F93_L_0) },
6852   },
6853 
6854   /* VEX_LEN_0F98 */
6855   {
6856     { MOD_TABLE (MOD_VEX_0F98_L_0) },
6857   },
6858 
6859   /* VEX_LEN_0F99 */
6860   {
6861     { MOD_TABLE (MOD_VEX_0F99_L_0) },
6862   },
6863 
6864   /* VEX_LEN_0FAE_R_2_M_0 */
6865   {
6866     { "vldmxcsr",	{ Md }, 0 },
6867   },
6868 
6869   /* VEX_LEN_0FAE_R_3_M_0 */
6870   {
6871     { "vstmxcsr",	{ Md }, 0 },
6872   },
6873 
6874   /* VEX_LEN_0FC4 */
6875   {
6876     { "vpinsrw",	{ XM, Vex, Edqw, Ib }, PREFIX_DATA },
6877   },
6878 
6879   /* VEX_LEN_0FC5 */
6880   {
6881     { "vpextrw",	{ Gdq, XS, Ib }, PREFIX_DATA },
6882   },
6883 
6884   /* VEX_LEN_0FD6 */
6885   {
6886     { "vmovq",		{ EXqS, XMScalar }, PREFIX_DATA },
6887   },
6888 
6889   /* VEX_LEN_0FF7 */
6890   {
6891     { "vmaskmovdqu",	{ XM, XS }, PREFIX_DATA },
6892   },
6893 
6894   /* VEX_LEN_0F3816 */
6895   {
6896     { Bad_Opcode },
6897     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6898   },
6899 
6900   /* VEX_LEN_0F3819 */
6901   {
6902     { Bad_Opcode },
6903     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6904   },
6905 
6906   /* VEX_LEN_0F381A_M_0 */
6907   {
6908     { Bad_Opcode },
6909     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6910   },
6911 
6912   /* VEX_LEN_0F3836 */
6913   {
6914     { Bad_Opcode },
6915     { VEX_W_TABLE (VEX_W_0F3836) },
6916   },
6917 
6918   /* VEX_LEN_0F3841 */
6919   {
6920     { "vphminposuw",	{ XM, EXx }, PREFIX_DATA },
6921   },
6922 
6923    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6924   {
6925     { "ldtilecfg", { M }, 0 },
6926   },
6927 
6928   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6929   {
6930     { "tilerelease", { Skip_MODRM }, 0 },
6931   },
6932 
6933   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6934   {
6935     { "sttilecfg", { M }, 0 },
6936   },
6937 
6938   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6939   {
6940     { "tilezero", { TMM, Skip_MODRM }, 0 },
6941   },
6942 
6943   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6944   {
6945     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6946   },
6947   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6948   {
6949     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6950   },
6951 
6952   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6953   {
6954     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6955   },
6956 
6957   /* VEX_LEN_0F385A_M_0 */
6958   {
6959     { Bad_Opcode },
6960     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6961   },
6962 
6963   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6964   {
6965     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6966   },
6967 
6968   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6969   {
6970     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6971   },
6972 
6973   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6974   {
6975     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6976   },
6977 
6978   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6979   {
6980     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
6981   },
6982 
6983   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6984   {
6985     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
6986   },
6987 
6988   /* VEX_LEN_0F38DB */
6989   {
6990     { "vaesimc",	{ XM, EXx }, PREFIX_DATA },
6991   },
6992 
6993   /* VEX_LEN_0F38F2 */
6994   {
6995     { "andnS",		{ Gdq, VexGdq, Edq }, PREFIX_OPCODE },
6996   },
6997 
6998   /* VEX_LEN_0F38F3 */
6999   {
7000     { REG_TABLE(REG_VEX_0F38F3_L_0) },
7001   },
7002 
7003   /* VEX_LEN_0F38F5 */
7004   {
7005     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7006   },
7007 
7008   /* VEX_LEN_0F38F6 */
7009   {
7010     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7011   },
7012 
7013   /* VEX_LEN_0F38F7 */
7014   {
7015     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7016   },
7017 
7018   /* VEX_LEN_0F3A00 */
7019   {
7020     { Bad_Opcode },
7021     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7022   },
7023 
7024   /* VEX_LEN_0F3A01 */
7025   {
7026     { Bad_Opcode },
7027     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7028   },
7029 
7030   /* VEX_LEN_0F3A06 */
7031   {
7032     { Bad_Opcode },
7033     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7034   },
7035 
7036   /* VEX_LEN_0F3A14 */
7037   {
7038     { "vpextrb",	{ Edqb, XM, Ib }, PREFIX_DATA },
7039   },
7040 
7041   /* VEX_LEN_0F3A15 */
7042   {
7043     { "vpextrw",	{ Edqw, XM, Ib }, PREFIX_DATA },
7044   },
7045 
7046   /* VEX_LEN_0F3A16  */
7047   {
7048     { "vpextrK",	{ Edq, XM, Ib }, PREFIX_DATA },
7049   },
7050 
7051   /* VEX_LEN_0F3A17 */
7052   {
7053     { "vextractps",	{ Edqd, XM, Ib }, PREFIX_DATA },
7054   },
7055 
7056   /* VEX_LEN_0F3A18 */
7057   {
7058     { Bad_Opcode },
7059     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7060   },
7061 
7062   /* VEX_LEN_0F3A19 */
7063   {
7064     { Bad_Opcode },
7065     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7066   },
7067 
7068   /* VEX_LEN_0F3A20 */
7069   {
7070     { "vpinsrb",	{ XM, Vex, Edqb, Ib }, PREFIX_DATA },
7071   },
7072 
7073   /* VEX_LEN_0F3A21 */
7074   {
7075     { "vinsertps",	{ XM, Vex, EXd, Ib }, PREFIX_DATA },
7076   },
7077 
7078   /* VEX_LEN_0F3A22 */
7079   {
7080     { "vpinsrK",	{ XM, Vex, Edq, Ib }, PREFIX_DATA },
7081   },
7082 
7083   /* VEX_LEN_0F3A30 */
7084   {
7085     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7086   },
7087 
7088   /* VEX_LEN_0F3A31 */
7089   {
7090     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7091   },
7092 
7093   /* VEX_LEN_0F3A32 */
7094   {
7095     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7096   },
7097 
7098   /* VEX_LEN_0F3A33 */
7099   {
7100     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7101   },
7102 
7103   /* VEX_LEN_0F3A38 */
7104   {
7105     { Bad_Opcode },
7106     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7107   },
7108 
7109   /* VEX_LEN_0F3A39 */
7110   {
7111     { Bad_Opcode },
7112     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7113   },
7114 
7115   /* VEX_LEN_0F3A41 */
7116   {
7117     { "vdppd",		{ XM, Vex, EXx, Ib }, PREFIX_DATA },
7118   },
7119 
7120   /* VEX_LEN_0F3A46 */
7121   {
7122     { Bad_Opcode },
7123     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7124   },
7125 
7126   /* VEX_LEN_0F3A60 */
7127   {
7128     { "vpcmpestrm!%LQ",	{ XM, EXx, Ib }, PREFIX_DATA },
7129   },
7130 
7131   /* VEX_LEN_0F3A61 */
7132   {
7133     { "vpcmpestri!%LQ",	{ XM, EXx, Ib }, PREFIX_DATA },
7134   },
7135 
7136   /* VEX_LEN_0F3A62 */
7137   {
7138     { "vpcmpistrm",	{ XM, EXx, Ib }, PREFIX_DATA },
7139   },
7140 
7141   /* VEX_LEN_0F3A63 */
7142   {
7143     { "vpcmpistri",	{ XM, EXx, Ib }, PREFIX_DATA },
7144   },
7145 
7146   /* VEX_LEN_0F3ADF */
7147   {
7148     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7149   },
7150 
7151   /* VEX_LEN_0F3AF0 */
7152   {
7153     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7154   },
7155 
7156   /* VEX_LEN_0FXOP_08_85 */
7157   {
7158     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7159   },
7160 
7161   /* VEX_LEN_0FXOP_08_86 */
7162   {
7163     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7164   },
7165 
7166   /* VEX_LEN_0FXOP_08_87 */
7167   {
7168     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7169   },
7170 
7171   /* VEX_LEN_0FXOP_08_8E */
7172   {
7173     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7174   },
7175 
7176   /* VEX_LEN_0FXOP_08_8F */
7177   {
7178     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7179   },
7180 
7181   /* VEX_LEN_0FXOP_08_95 */
7182   {
7183     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7184   },
7185 
7186   /* VEX_LEN_0FXOP_08_96 */
7187   {
7188     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7189   },
7190 
7191   /* VEX_LEN_0FXOP_08_97 */
7192   {
7193     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7194   },
7195 
7196   /* VEX_LEN_0FXOP_08_9E */
7197   {
7198     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7199   },
7200 
7201   /* VEX_LEN_0FXOP_08_9F */
7202   {
7203     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7204   },
7205 
7206   /* VEX_LEN_0FXOP_08_A3 */
7207   {
7208     { "vpperm", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7209   },
7210 
7211   /* VEX_LEN_0FXOP_08_A6 */
7212   {
7213     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7214   },
7215 
7216   /* VEX_LEN_0FXOP_08_B6 */
7217   {
7218     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7219   },
7220 
7221   /* VEX_LEN_0FXOP_08_C0 */
7222   {
7223     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7224   },
7225 
7226   /* VEX_LEN_0FXOP_08_C1 */
7227   {
7228     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7229   },
7230 
7231   /* VEX_LEN_0FXOP_08_C2 */
7232   {
7233     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7234   },
7235 
7236   /* VEX_LEN_0FXOP_08_C3 */
7237   {
7238     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7239   },
7240 
7241   /* VEX_LEN_0FXOP_08_CC */
7242   {
7243     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7244   },
7245 
7246   /* VEX_LEN_0FXOP_08_CD */
7247   {
7248     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7249   },
7250 
7251   /* VEX_LEN_0FXOP_08_CE */
7252   {
7253     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7254   },
7255 
7256   /* VEX_LEN_0FXOP_08_CF */
7257   {
7258     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7259   },
7260 
7261   /* VEX_LEN_0FXOP_08_EC */
7262   {
7263     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7264   },
7265 
7266   /* VEX_LEN_0FXOP_08_ED */
7267   {
7268     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7269   },
7270 
7271   /* VEX_LEN_0FXOP_08_EE */
7272   {
7273     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7274   },
7275 
7276   /* VEX_LEN_0FXOP_08_EF */
7277   {
7278     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7279   },
7280 
7281   /* VEX_LEN_0FXOP_09_01 */
7282   {
7283     { REG_TABLE (REG_XOP_09_01_L_0) },
7284   },
7285 
7286   /* VEX_LEN_0FXOP_09_02 */
7287   {
7288     { REG_TABLE (REG_XOP_09_02_L_0) },
7289   },
7290 
7291   /* VEX_LEN_0FXOP_09_12_M_1 */
7292   {
7293     { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
7294   },
7295 
7296   /* VEX_LEN_0FXOP_09_82_W_0 */
7297   {
7298     { "vfrczss", 	{ XM, EXd }, 0 },
7299   },
7300 
7301   /* VEX_LEN_0FXOP_09_83_W_0 */
7302   {
7303     { "vfrczsd", 	{ XM, EXq }, 0 },
7304   },
7305 
7306   /* VEX_LEN_0FXOP_09_90 */
7307   {
7308     { "vprotb",		{ XM, EXx, VexW }, 0 },
7309   },
7310 
7311   /* VEX_LEN_0FXOP_09_91 */
7312   {
7313     { "vprotw",		{ XM, EXx, VexW }, 0 },
7314   },
7315 
7316   /* VEX_LEN_0FXOP_09_92 */
7317   {
7318     { "vprotd",		{ XM, EXx, VexW }, 0 },
7319   },
7320 
7321   /* VEX_LEN_0FXOP_09_93 */
7322   {
7323     { "vprotq",		{ XM, EXx, VexW }, 0 },
7324   },
7325 
7326   /* VEX_LEN_0FXOP_09_94 */
7327   {
7328     { "vpshlb",		{ XM, EXx, VexW }, 0 },
7329   },
7330 
7331   /* VEX_LEN_0FXOP_09_95 */
7332   {
7333     { "vpshlw",		{ XM, EXx, VexW }, 0 },
7334   },
7335 
7336   /* VEX_LEN_0FXOP_09_96 */
7337   {
7338     { "vpshld",		{ XM, EXx, VexW }, 0 },
7339   },
7340 
7341   /* VEX_LEN_0FXOP_09_97 */
7342   {
7343     { "vpshlq",		{ XM, EXx, VexW }, 0 },
7344   },
7345 
7346   /* VEX_LEN_0FXOP_09_98 */
7347   {
7348     { "vpshab",		{ XM, EXx, VexW }, 0 },
7349   },
7350 
7351   /* VEX_LEN_0FXOP_09_99 */
7352   {
7353     { "vpshaw",		{ XM, EXx, VexW }, 0 },
7354   },
7355 
7356   /* VEX_LEN_0FXOP_09_9A */
7357   {
7358     { "vpshad",		{ XM, EXx, VexW }, 0 },
7359   },
7360 
7361   /* VEX_LEN_0FXOP_09_9B */
7362   {
7363     { "vpshaq",		{ XM, EXx, VexW }, 0 },
7364   },
7365 
7366   /* VEX_LEN_0FXOP_09_C1 */
7367   {
7368     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7369   },
7370 
7371   /* VEX_LEN_0FXOP_09_C2 */
7372   {
7373     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7374   },
7375 
7376   /* VEX_LEN_0FXOP_09_C3 */
7377   {
7378     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7379   },
7380 
7381   /* VEX_LEN_0FXOP_09_C6 */
7382   {
7383     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7384   },
7385 
7386   /* VEX_LEN_0FXOP_09_C7 */
7387   {
7388     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7389   },
7390 
7391   /* VEX_LEN_0FXOP_09_CB */
7392   {
7393     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7394   },
7395 
7396   /* VEX_LEN_0FXOP_09_D1 */
7397   {
7398     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7399   },
7400 
7401   /* VEX_LEN_0FXOP_09_D2 */
7402   {
7403     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7404   },
7405 
7406   /* VEX_LEN_0FXOP_09_D3 */
7407   {
7408     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7409   },
7410 
7411   /* VEX_LEN_0FXOP_09_D6 */
7412   {
7413     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7414   },
7415 
7416   /* VEX_LEN_0FXOP_09_D7 */
7417   {
7418     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7419   },
7420 
7421   /* VEX_LEN_0FXOP_09_DB */
7422   {
7423     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7424   },
7425 
7426   /* VEX_LEN_0FXOP_09_E1 */
7427   {
7428     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7429   },
7430 
7431   /* VEX_LEN_0FXOP_09_E2 */
7432   {
7433     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7434   },
7435 
7436   /* VEX_LEN_0FXOP_09_E3 */
7437   {
7438     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7439   },
7440 
7441   /* VEX_LEN_0FXOP_0A_12 */
7442   {
7443     { REG_TABLE (REG_XOP_0A_12_L_0) },
7444   },
7445 };
7446 
7447 #include "i386-dis-evex-len.h"
7448 
7449 static const struct dis386 vex_w_table[][2] = {
7450   {
7451     /* VEX_W_0F41_L_1_M_1 */
7452     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7453     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7454   },
7455   {
7456     /* VEX_W_0F42_L_1_M_1 */
7457     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7458     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7459   },
7460   {
7461     /* VEX_W_0F44_L_0_M_1 */
7462     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7463     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7464   },
7465   {
7466     /* VEX_W_0F45_L_1_M_1 */
7467     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7468     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7469   },
7470   {
7471     /* VEX_W_0F46_L_1_M_1 */
7472     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7473     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7474   },
7475   {
7476     /* VEX_W_0F47_L_1_M_1 */
7477     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7478     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7479   },
7480   {
7481     /* VEX_W_0F4A_L_1_M_1 */
7482     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7483     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7484   },
7485   {
7486     /* VEX_W_0F4B_L_1_M_1 */
7487     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7488     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7489   },
7490   {
7491     /* VEX_W_0F90_L_0 */
7492     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7493     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7494   },
7495   {
7496     /* VEX_W_0F91_L_0_M_0 */
7497     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7498     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7499   },
7500   {
7501     /* VEX_W_0F92_L_0_M_1 */
7502     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7503     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7504   },
7505   {
7506     /* VEX_W_0F93_L_0_M_1 */
7507     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7508     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7509   },
7510   {
7511     /* VEX_W_0F98_L_0_M_1 */
7512     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7513     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7514   },
7515   {
7516     /* VEX_W_0F99_L_0_M_1 */
7517     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7518     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7519   },
7520   {
7521     /* VEX_W_0F380C  */
7522     { "vpermilps",	{ XM, Vex, EXx }, PREFIX_DATA },
7523   },
7524   {
7525     /* VEX_W_0F380D  */
7526     { "vpermilpd",	{ XM, Vex, EXx }, PREFIX_DATA },
7527   },
7528   {
7529     /* VEX_W_0F380E  */
7530     { "vtestps",	{ XM, EXx }, PREFIX_DATA },
7531   },
7532   {
7533     /* VEX_W_0F380F  */
7534     { "vtestpd",	{ XM, EXx }, PREFIX_DATA },
7535   },
7536   {
7537     /* VEX_W_0F3813 */
7538     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7539   },
7540   {
7541     /* VEX_W_0F3816_L_1  */
7542     { "vpermps",	{ XM, Vex, EXx }, PREFIX_DATA },
7543   },
7544   {
7545     /* VEX_W_0F3818 */
7546     { "vbroadcastss",	{ XM, EXxmm_md }, PREFIX_DATA },
7547   },
7548   {
7549     /* VEX_W_0F3819_L_1 */
7550     { "vbroadcastsd",	{ XM, EXxmm_mq }, PREFIX_DATA },
7551   },
7552   {
7553     /* VEX_W_0F381A_M_0_L_1 */
7554     { "vbroadcastf128",	{ XM, Mxmm }, PREFIX_DATA },
7555   },
7556   {
7557     /* VEX_W_0F382C_M_0 */
7558     { "vmaskmovps",	{ XM, Vex, Mx }, PREFIX_DATA },
7559   },
7560   {
7561     /* VEX_W_0F382D_M_0 */
7562     { "vmaskmovpd",	{ XM, Vex, Mx }, PREFIX_DATA },
7563   },
7564   {
7565     /* VEX_W_0F382E_M_0 */
7566     { "vmaskmovps",	{ Mx, Vex, XM }, PREFIX_DATA },
7567   },
7568   {
7569     /* VEX_W_0F382F_M_0 */
7570     { "vmaskmovpd",	{ Mx, Vex, XM }, PREFIX_DATA },
7571   },
7572   {
7573     /* VEX_W_0F3836  */
7574     { "vpermd",		{ XM, Vex, EXx }, PREFIX_DATA },
7575   },
7576   {
7577     /* VEX_W_0F3846 */
7578     { "vpsravd",	{ XM, Vex, EXx }, PREFIX_DATA },
7579   },
7580   {
7581     /* VEX_W_0F3849_X86_64_P_0 */
7582     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7583   },
7584   {
7585     /* VEX_W_0F3849_X86_64_P_2 */
7586     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7587   },
7588   {
7589     /* VEX_W_0F3849_X86_64_P_3 */
7590     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7591   },
7592   {
7593     /* VEX_W_0F384B_X86_64_P_1 */
7594     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7595   },
7596   {
7597     /* VEX_W_0F384B_X86_64_P_2 */
7598     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7599   },
7600   {
7601     /* VEX_W_0F384B_X86_64_P_3 */
7602     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7603   },
7604   {
7605     /* VEX_W_0F3850 */
7606     { "%XV vpdpbusd",	{ XM, Vex, EXx }, 0 },
7607   },
7608   {
7609     /* VEX_W_0F3851 */
7610     { "%XV vpdpbusds",	{ XM, Vex, EXx }, 0 },
7611   },
7612   {
7613     /* VEX_W_0F3852 */
7614     { "%XV vpdpwssd",	{ XM, Vex, EXx }, 0 },
7615   },
7616   {
7617     /* VEX_W_0F3853 */
7618     { "%XV vpdpwssds",	{ XM, Vex, EXx }, 0 },
7619   },
7620   {
7621     /* VEX_W_0F3858 */
7622     { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7623   },
7624   {
7625     /* VEX_W_0F3859 */
7626     { "vpbroadcastq",	{ XM, EXxmm_mq }, PREFIX_DATA },
7627   },
7628   {
7629     /* VEX_W_0F385A_M_0_L_0 */
7630     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7631   },
7632   {
7633     /* VEX_W_0F385C_X86_64_P_1 */
7634     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7635   },
7636   {
7637     /* VEX_W_0F385E_X86_64_P_0 */
7638     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7639   },
7640   {
7641     /* VEX_W_0F385E_X86_64_P_1 */
7642     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7643   },
7644   {
7645     /* VEX_W_0F385E_X86_64_P_2 */
7646     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7647   },
7648   {
7649     /* VEX_W_0F385E_X86_64_P_3 */
7650     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7651   },
7652   {
7653     /* VEX_W_0F3878 */
7654     { "vpbroadcastb",	{ XM, EXxmm_mb }, PREFIX_DATA },
7655   },
7656   {
7657     /* VEX_W_0F3879 */
7658     { "vpbroadcastw",	{ XM, EXxmm_mw }, PREFIX_DATA },
7659   },
7660   {
7661     /* VEX_W_0F38CF */
7662     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7663   },
7664   {
7665     /* VEX_W_0F3A00_L_1 */
7666     { Bad_Opcode },
7667     { "vpermq",		{ XM, EXx, Ib }, PREFIX_DATA },
7668   },
7669   {
7670     /* VEX_W_0F3A01_L_1 */
7671     { Bad_Opcode },
7672     { "vpermpd",	{ XM, EXx, Ib }, PREFIX_DATA },
7673   },
7674   {
7675     /* VEX_W_0F3A02 */
7676     { "vpblendd",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
7677   },
7678   {
7679     /* VEX_W_0F3A04 */
7680     { "vpermilps",	{ XM, EXx, Ib }, PREFIX_DATA },
7681   },
7682   {
7683     /* VEX_W_0F3A05 */
7684     { "vpermilpd",	{ XM, EXx, Ib }, PREFIX_DATA },
7685   },
7686   {
7687     /* VEX_W_0F3A06_L_1 */
7688     { "vperm2f128",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
7689   },
7690   {
7691     /* VEX_W_0F3A18_L_1 */
7692     { "vinsertf128",	{ XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7693   },
7694   {
7695     /* VEX_W_0F3A19_L_1 */
7696     { "vextractf128",	{ EXxmm, XM, Ib }, PREFIX_DATA },
7697   },
7698   {
7699     /* VEX_W_0F3A1D */
7700     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7701   },
7702   {
7703     /* VEX_W_0F3A38_L_1 */
7704     { "vinserti128",	{ XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7705   },
7706   {
7707     /* VEX_W_0F3A39_L_1 */
7708     { "vextracti128",	{ EXxmm, XM, Ib }, PREFIX_DATA },
7709   },
7710   {
7711     /* VEX_W_0F3A46_L_1 */
7712     { "vperm2i128",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
7713   },
7714   {
7715     /* VEX_W_0F3A4A */
7716     { "vblendvps",	{ XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7717   },
7718   {
7719     /* VEX_W_0F3A4B */
7720     { "vblendvpd",	{ XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7721   },
7722   {
7723     /* VEX_W_0F3A4C */
7724     { "vpblendvb",	{ XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7725   },
7726   {
7727     /* VEX_W_0F3ACE */
7728     { Bad_Opcode },
7729     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7730   },
7731   {
7732     /* VEX_W_0F3ACF */
7733     { Bad_Opcode },
7734     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7735   },
7736   /* VEX_W_0FXOP_08_85_L_0 */
7737   {
7738     { "vpmacssww", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7739   },
7740   /* VEX_W_0FXOP_08_86_L_0 */
7741   {
7742     { "vpmacsswd", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7743   },
7744   /* VEX_W_0FXOP_08_87_L_0 */
7745   {
7746     { "vpmacssdql", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7747   },
7748   /* VEX_W_0FXOP_08_8E_L_0 */
7749   {
7750     { "vpmacssdd", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7751   },
7752   /* VEX_W_0FXOP_08_8F_L_0 */
7753   {
7754     { "vpmacssdqh", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7755   },
7756   /* VEX_W_0FXOP_08_95_L_0 */
7757   {
7758     { "vpmacsww", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7759   },
7760   /* VEX_W_0FXOP_08_96_L_0 */
7761   {
7762     { "vpmacswd", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7763   },
7764   /* VEX_W_0FXOP_08_97_L_0 */
7765   {
7766     { "vpmacsdql", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7767   },
7768   /* VEX_W_0FXOP_08_9E_L_0 */
7769   {
7770     { "vpmacsdd", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7771   },
7772   /* VEX_W_0FXOP_08_9F_L_0 */
7773   {
7774     { "vpmacsdqh", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7775   },
7776   /* VEX_W_0FXOP_08_A6_L_0 */
7777   {
7778     { "vpmadcsswd", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7779   },
7780   /* VEX_W_0FXOP_08_B6_L_0 */
7781   {
7782     { "vpmadcswd", 	{ XM, Vex, EXx, XMVexI4 }, 0 },
7783   },
7784   /* VEX_W_0FXOP_08_C0_L_0 */
7785   {
7786     { "vprotb", 	{ XM, EXx, Ib }, 0 },
7787   },
7788   /* VEX_W_0FXOP_08_C1_L_0 */
7789   {
7790     { "vprotw", 	{ XM, EXx, Ib }, 0 },
7791   },
7792   /* VEX_W_0FXOP_08_C2_L_0 */
7793   {
7794     { "vprotd", 	{ XM, EXx, Ib }, 0 },
7795   },
7796   /* VEX_W_0FXOP_08_C3_L_0 */
7797   {
7798     { "vprotq", 	{ XM, EXx, Ib }, 0 },
7799   },
7800   /* VEX_W_0FXOP_08_CC_L_0 */
7801   {
7802      { "vpcomb",	{ XM, Vex, EXx, VPCOM }, 0 },
7803   },
7804   /* VEX_W_0FXOP_08_CD_L_0 */
7805   {
7806      { "vpcomw",	{ XM, Vex, EXx, VPCOM }, 0 },
7807   },
7808   /* VEX_W_0FXOP_08_CE_L_0 */
7809   {
7810      { "vpcomd",	{ XM, Vex, EXx, VPCOM }, 0 },
7811   },
7812   /* VEX_W_0FXOP_08_CF_L_0 */
7813   {
7814      { "vpcomq",	{ XM, Vex, EXx, VPCOM }, 0 },
7815   },
7816   /* VEX_W_0FXOP_08_EC_L_0 */
7817   {
7818      { "vpcomub",	{ XM, Vex, EXx, VPCOM }, 0 },
7819   },
7820   /* VEX_W_0FXOP_08_ED_L_0 */
7821   {
7822      { "vpcomuw",	{ XM, Vex, EXx, VPCOM }, 0 },
7823   },
7824   /* VEX_W_0FXOP_08_EE_L_0 */
7825   {
7826      { "vpcomud",	{ XM, Vex, EXx, VPCOM }, 0 },
7827   },
7828   /* VEX_W_0FXOP_08_EF_L_0 */
7829   {
7830      { "vpcomuq",	{ XM, Vex, EXx, VPCOM }, 0 },
7831   },
7832   /* VEX_W_0FXOP_09_80 */
7833   {
7834     { "vfrczps",	{ XM, EXx }, 0 },
7835   },
7836   /* VEX_W_0FXOP_09_81 */
7837   {
7838     { "vfrczpd",	{ XM, EXx }, 0 },
7839   },
7840   /* VEX_W_0FXOP_09_82 */
7841   {
7842     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7843   },
7844   /* VEX_W_0FXOP_09_83 */
7845   {
7846     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7847   },
7848   /* VEX_W_0FXOP_09_C1_L_0 */
7849   {
7850     { "vphaddbw",	{ XM, EXxmm }, 0 },
7851   },
7852   /* VEX_W_0FXOP_09_C2_L_0 */
7853   {
7854     { "vphaddbd",	{ XM, EXxmm }, 0 },
7855   },
7856   /* VEX_W_0FXOP_09_C3_L_0 */
7857   {
7858     { "vphaddbq",	{ XM, EXxmm }, 0 },
7859   },
7860   /* VEX_W_0FXOP_09_C6_L_0 */
7861   {
7862     { "vphaddwd",	{ XM, EXxmm }, 0 },
7863   },
7864   /* VEX_W_0FXOP_09_C7_L_0 */
7865   {
7866     { "vphaddwq",	{ XM, EXxmm }, 0 },
7867   },
7868   /* VEX_W_0FXOP_09_CB_L_0 */
7869   {
7870     { "vphadddq",	{ XM, EXxmm }, 0 },
7871   },
7872   /* VEX_W_0FXOP_09_D1_L_0 */
7873   {
7874     { "vphaddubw",	{ XM, EXxmm }, 0 },
7875   },
7876   /* VEX_W_0FXOP_09_D2_L_0 */
7877   {
7878     { "vphaddubd",	{ XM, EXxmm }, 0 },
7879   },
7880   /* VEX_W_0FXOP_09_D3_L_0 */
7881   {
7882     { "vphaddubq",	{ XM, EXxmm }, 0 },
7883   },
7884   /* VEX_W_0FXOP_09_D6_L_0 */
7885   {
7886     { "vphadduwd",	{ XM, EXxmm }, 0 },
7887   },
7888   /* VEX_W_0FXOP_09_D7_L_0 */
7889   {
7890     { "vphadduwq",	{ XM, EXxmm }, 0 },
7891   },
7892   /* VEX_W_0FXOP_09_DB_L_0 */
7893   {
7894     { "vphaddudq",	{ XM, EXxmm }, 0 },
7895   },
7896   /* VEX_W_0FXOP_09_E1_L_0 */
7897   {
7898     { "vphsubbw",	{ XM, EXxmm }, 0 },
7899   },
7900   /* VEX_W_0FXOP_09_E2_L_0 */
7901   {
7902     { "vphsubwd",	{ XM, EXxmm }, 0 },
7903   },
7904   /* VEX_W_0FXOP_09_E3_L_0 */
7905   {
7906     { "vphsubdq",	{ XM, EXxmm }, 0 },
7907   },
7908 
7909 #include "i386-dis-evex-w.h"
7910 };
7911 
7912 static const struct dis386 mod_table[][2] = {
7913   {
7914     /* MOD_62_32BIT */
7915     { "bound{S|}",	{ Gv, Ma }, 0 },
7916     { EVEX_TABLE (EVEX_0F) },
7917   },
7918   {
7919     /* MOD_8D */
7920     { "leaS",		{ Gv, M }, 0 },
7921   },
7922   {
7923     /* MOD_C4_32BIT */
7924     { "lesS",		{ Gv, Mp }, 0 },
7925     { VEX_C4_TABLE (VEX_0F) },
7926   },
7927   {
7928     /* MOD_C5_32BIT */
7929     { "ldsS",		{ Gv, Mp }, 0 },
7930     { VEX_C5_TABLE (VEX_0F) },
7931   },
7932   {
7933     /* MOD_C6_REG_7 */
7934     { Bad_Opcode },
7935     { RM_TABLE (RM_C6_REG_7) },
7936   },
7937   {
7938     /* MOD_C7_REG_7 */
7939     { Bad_Opcode },
7940     { RM_TABLE (RM_C7_REG_7) },
7941   },
7942   {
7943     /* MOD_FF_REG_3 */
7944     { "{l|}call^", { indirEp }, 0 },
7945   },
7946   {
7947     /* MOD_FF_REG_5 */
7948     { "{l|}jmp^", { indirEp }, 0 },
7949   },
7950   {
7951     /* MOD_0F01_REG_0 */
7952     { X86_64_TABLE (X86_64_0F01_REG_0) },
7953     { RM_TABLE (RM_0F01_REG_0) },
7954   },
7955   {
7956     /* MOD_0F01_REG_1 */
7957     { X86_64_TABLE (X86_64_0F01_REG_1) },
7958     { RM_TABLE (RM_0F01_REG_1) },
7959   },
7960   {
7961     /* MOD_0F01_REG_2 */
7962     { X86_64_TABLE (X86_64_0F01_REG_2) },
7963     { RM_TABLE (RM_0F01_REG_2) },
7964   },
7965   {
7966     /* MOD_0F01_REG_3 */
7967     { X86_64_TABLE (X86_64_0F01_REG_3) },
7968     { RM_TABLE (RM_0F01_REG_3) },
7969   },
7970   {
7971     /* MOD_0F01_REG_5 */
7972     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7973     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7974   },
7975   {
7976     /* MOD_0F01_REG_7 */
7977     { "invlpg",		{ Mb }, 0 },
7978     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7979   },
7980   {
7981     /* MOD_0F12_PREFIX_0 */
7982     { "movlpX",		{ XM, EXq }, 0 },
7983     { "movhlps",	{ XM, EXq }, 0 },
7984   },
7985   {
7986     /* MOD_0F12_PREFIX_2 */
7987     { "movlpX",	{ XM, EXq }, 0 },
7988   },
7989   {
7990     /* MOD_0F13 */
7991     { "movlpX",		{ EXq, XM }, PREFIX_OPCODE },
7992   },
7993   {
7994     /* MOD_0F16_PREFIX_0 */
7995     { "movhpX",		{ XM, EXq }, 0 },
7996     { "movlhps",	{ XM, EXq }, 0 },
7997   },
7998   {
7999     /* MOD_0F16_PREFIX_2 */
8000     { "movhpX",	{ XM, EXq }, 0 },
8001   },
8002   {
8003     /* MOD_0F17 */
8004     { "movhpX",		{ EXq, XM }, PREFIX_OPCODE },
8005   },
8006   {
8007     /* MOD_0F18_REG_0 */
8008     { "prefetchnta",	{ Mb }, 0 },
8009     { "nopQ",		{ Ev }, 0 },
8010   },
8011   {
8012     /* MOD_0F18_REG_1 */
8013     { "prefetcht0",	{ Mb }, 0 },
8014     { "nopQ",		{ Ev }, 0 },
8015   },
8016   {
8017     /* MOD_0F18_REG_2 */
8018     { "prefetcht1",	{ Mb }, 0 },
8019     { "nopQ",		{ Ev }, 0 },
8020   },
8021   {
8022     /* MOD_0F18_REG_3 */
8023     { "prefetcht2",	{ Mb }, 0 },
8024     { "nopQ",		{ Ev }, 0 },
8025   },
8026   {
8027     /* MOD_0F1A_PREFIX_0 */
8028     { "bndldx",		{ Gbnd, Mv_bnd }, 0 },
8029     { "nopQ",		{ Ev }, 0 },
8030   },
8031   {
8032     /* MOD_0F1B_PREFIX_0 */
8033     { "bndstx",		{ Mv_bnd, Gbnd }, 0 },
8034     { "nopQ",		{ Ev }, 0 },
8035   },
8036   {
8037     /* MOD_0F1B_PREFIX_1 */
8038     { "bndmk",		{ Gbnd, Mv_bnd }, 0 },
8039     { "nopQ",		{ Ev }, PREFIX_IGNORED },
8040   },
8041   {
8042     /* MOD_0F1C_PREFIX_0 */
8043     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8044     { "nopQ",		{ Ev }, 0 },
8045   },
8046   {
8047     /* MOD_0F1E_PREFIX_1 */
8048     { "nopQ",		{ Ev }, PREFIX_IGNORED },
8049     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8050   },
8051   {
8052     /* MOD_0F2B_PREFIX_0 */
8053     {"movntps",		{ Mx, XM }, PREFIX_OPCODE },
8054   },
8055   {
8056     /* MOD_0F2B_PREFIX_1 */
8057     {"movntss",		{ Md, XM }, PREFIX_OPCODE },
8058   },
8059   {
8060     /* MOD_0F2B_PREFIX_2 */
8061     {"movntpd",		{ Mx, XM }, PREFIX_OPCODE },
8062   },
8063   {
8064     /* MOD_0F2B_PREFIX_3 */
8065     {"movntsd",		{ Mq, XM }, PREFIX_OPCODE },
8066   },
8067   {
8068     /* MOD_0F50 */
8069     { Bad_Opcode },
8070     { "movmskpX",	{ Gdq, XS }, PREFIX_OPCODE },
8071   },
8072   {
8073     /* MOD_0F71 */
8074     { Bad_Opcode },
8075     { REG_TABLE (REG_0F71_MOD_0) },
8076   },
8077   {
8078     /* MOD_0F72 */
8079     { Bad_Opcode },
8080     { REG_TABLE (REG_0F72_MOD_0) },
8081   },
8082   {
8083     /* MOD_0F73 */
8084     { Bad_Opcode },
8085     { REG_TABLE (REG_0F73_MOD_0) },
8086   },
8087   {
8088     /* MOD_0FAE_REG_0 */
8089     { "fxsave",		{ FXSAVE }, 0 },
8090     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8091   },
8092   {
8093     /* MOD_0FAE_REG_1 */
8094     { "fxrstor",	{ FXSAVE }, 0 },
8095     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8096   },
8097   {
8098     /* MOD_0FAE_REG_2 */
8099     { "ldmxcsr",	{ Md }, 0 },
8100     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8101   },
8102   {
8103     /* MOD_0FAE_REG_3 */
8104     { "stmxcsr",	{ Md }, 0 },
8105     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8106   },
8107   {
8108     /* MOD_0FAE_REG_4 */
8109     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8110     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8111   },
8112   {
8113     /* MOD_0FAE_REG_5 */
8114     { "xrstor",		{ FXSAVE }, PREFIX_OPCODE },
8115     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8116   },
8117   {
8118     /* MOD_0FAE_REG_6 */
8119     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8120     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8121   },
8122   {
8123     /* MOD_0FAE_REG_7 */
8124     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8125     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8126   },
8127   {
8128     /* MOD_0FB2 */
8129     { "lssS",		{ Gv, Mp }, 0 },
8130   },
8131   {
8132     /* MOD_0FB4 */
8133     { "lfsS",		{ Gv, Mp }, 0 },
8134   },
8135   {
8136     /* MOD_0FB5 */
8137     { "lgsS",		{ Gv, Mp }, 0 },
8138   },
8139   {
8140     /* MOD_0FC3 */
8141     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8142   },
8143   {
8144     /* MOD_0FC7_REG_3 */
8145     { "xrstors",	{ FXSAVE }, 0 },
8146   },
8147   {
8148     /* MOD_0FC7_REG_4 */
8149     { "xsavec",		{ FXSAVE }, 0 },
8150   },
8151   {
8152     /* MOD_0FC7_REG_5 */
8153     { "xsaves",		{ FXSAVE }, 0 },
8154   },
8155   {
8156     /* MOD_0FC7_REG_6 */
8157     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8158     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8159   },
8160   {
8161     /* MOD_0FC7_REG_7 */
8162     { "vmptrst",	{ Mq }, 0 },
8163     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8164   },
8165   {
8166     /* MOD_0FD7 */
8167     { Bad_Opcode },
8168     { "pmovmskb",	{ Gdq, MS }, 0 },
8169   },
8170   {
8171     /* MOD_0FE7_PREFIX_2 */
8172     { "movntdq",	{ Mx, XM }, 0 },
8173   },
8174   {
8175     /* MOD_0FF0_PREFIX_3 */
8176     { "lddqu",		{ XM, M }, 0 },
8177   },
8178   {
8179     /* MOD_0F382A */
8180     { "movntdqa",	{ XM, Mx }, PREFIX_DATA },
8181   },
8182   {
8183     /* MOD_0F38DC_PREFIX_1 */
8184     { "aesenc128kl",    { XM, M }, 0 },
8185     { "loadiwkey",      { XM, EXx }, 0 },
8186   },
8187   {
8188     /* MOD_0F38DD_PREFIX_1 */
8189     { "aesdec128kl",    { XM, M }, 0 },
8190   },
8191   {
8192     /* MOD_0F38DE_PREFIX_1 */
8193     { "aesenc256kl",    { XM, M }, 0 },
8194   },
8195   {
8196     /* MOD_0F38DF_PREFIX_1 */
8197     { "aesdec256kl",    { XM, M }, 0 },
8198   },
8199   {
8200     /* MOD_0F38F5 */
8201     { "wrussK",		{ M, Gdq }, PREFIX_DATA },
8202   },
8203   {
8204     /* MOD_0F38F6_PREFIX_0 */
8205     { "wrssK",		{ M, Gdq }, PREFIX_OPCODE },
8206   },
8207   {
8208     /* MOD_0F38F8_PREFIX_1 */
8209     { "enqcmds",	{ Gva, M }, PREFIX_OPCODE },
8210   },
8211   {
8212     /* MOD_0F38F8_PREFIX_2 */
8213     { "movdir64b",	{ Gva, M }, PREFIX_OPCODE },
8214   },
8215   {
8216     /* MOD_0F38F8_PREFIX_3 */
8217     { "enqcmd",		{ Gva, M }, PREFIX_OPCODE },
8218   },
8219   {
8220     /* MOD_0F38F9 */
8221     { "movdiri",	{ Edq, Gdq }, PREFIX_OPCODE },
8222   },
8223   {
8224     /* MOD_0F38FA_PREFIX_1 */
8225     { Bad_Opcode },
8226     { "encodekey128", { Gd, Ed }, 0 },
8227   },
8228   {
8229     /* MOD_0F38FB_PREFIX_1 */
8230     { Bad_Opcode },
8231     { "encodekey256", { Gd, Ed }, 0 },
8232   },
8233   {
8234     /* MOD_0F3A0F_PREFIX_1 */
8235     { Bad_Opcode },
8236     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8237   },
8238   {
8239     /* MOD_VEX_0F12_PREFIX_0 */
8240     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8241     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8242   },
8243   {
8244     /* MOD_VEX_0F12_PREFIX_2 */
8245     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8246   },
8247   {
8248     /* MOD_VEX_0F13 */
8249     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8250   },
8251   {
8252     /* MOD_VEX_0F16_PREFIX_0 */
8253     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8254     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8255   },
8256   {
8257     /* MOD_VEX_0F16_PREFIX_2 */
8258     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8259   },
8260   {
8261     /* MOD_VEX_0F17 */
8262     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8263   },
8264   {
8265     /* MOD_VEX_0F2B */
8266     { "vmovntpX",	{ Mx, XM }, PREFIX_OPCODE },
8267   },
8268   {
8269     /* MOD_VEX_0F41_L_1 */
8270     { Bad_Opcode },
8271     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8272   },
8273   {
8274     /* MOD_VEX_0F42_L_1 */
8275     { Bad_Opcode },
8276     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8277   },
8278   {
8279     /* MOD_VEX_0F44_L_0 */
8280     { Bad_Opcode },
8281     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8282   },
8283   {
8284     /* MOD_VEX_0F45_L_1 */
8285     { Bad_Opcode },
8286     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8287   },
8288   {
8289     /* MOD_VEX_0F46_L_1 */
8290     { Bad_Opcode },
8291     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8292   },
8293   {
8294     /* MOD_VEX_0F47_L_1 */
8295     { Bad_Opcode },
8296     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8297   },
8298   {
8299     /* MOD_VEX_0F4A_L_1 */
8300     { Bad_Opcode },
8301     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8302   },
8303   {
8304     /* MOD_VEX_0F4B_L_1 */
8305     { Bad_Opcode },
8306     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8307   },
8308   {
8309     /* MOD_VEX_0F50 */
8310     { Bad_Opcode },
8311     { "vmovmskpX",	{ Gdq, XS }, PREFIX_OPCODE },
8312   },
8313   {
8314     /* MOD_VEX_0F71 */
8315     { Bad_Opcode },
8316     { REG_TABLE (REG_VEX_0F71_M_0) },
8317   },
8318   {
8319     /* MOD_VEX_0F72 */
8320     { Bad_Opcode },
8321     { REG_TABLE (REG_VEX_0F72_M_0) },
8322   },
8323   {
8324     /* MOD_VEX_0F73 */
8325     { Bad_Opcode },
8326     { REG_TABLE (REG_VEX_0F73_M_0) },
8327   },
8328   {
8329     /* MOD_VEX_0F91_L_0 */
8330     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8331   },
8332   {
8333     /* MOD_VEX_0F92_L_0 */
8334     { Bad_Opcode },
8335     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8336   },
8337   {
8338     /* MOD_VEX_0F93_L_0 */
8339     { Bad_Opcode },
8340     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8341   },
8342   {
8343     /* MOD_VEX_0F98_L_0 */
8344     { Bad_Opcode },
8345     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8346   },
8347   {
8348     /* MOD_VEX_0F99_L_0 */
8349     { Bad_Opcode },
8350     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8351   },
8352   {
8353     /* MOD_VEX_0FAE_REG_2 */
8354     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8355   },
8356   {
8357     /* MOD_VEX_0FAE_REG_3 */
8358     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8359   },
8360   {
8361     /* MOD_VEX_0FD7 */
8362     { Bad_Opcode },
8363     { "vpmovmskb",	{ Gdq, XS }, PREFIX_DATA },
8364   },
8365   {
8366     /* MOD_VEX_0FE7 */
8367     { "vmovntdq",	{ Mx, XM }, PREFIX_DATA },
8368   },
8369   {
8370     /* MOD_VEX_0FF0_PREFIX_3 */
8371     { "vlddqu",		{ XM, M }, 0 },
8372   },
8373   {
8374     /* MOD_VEX_0F381A */
8375     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8376   },
8377   {
8378     /* MOD_VEX_0F382A */
8379     { "vmovntdqa",	{ XM, Mx }, PREFIX_DATA },
8380   },
8381   {
8382     /* MOD_VEX_0F382C */
8383     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8384   },
8385   {
8386     /* MOD_VEX_0F382D */
8387     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8388   },
8389   {
8390     /* MOD_VEX_0F382E */
8391     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8392   },
8393   {
8394     /* MOD_VEX_0F382F */
8395     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8396   },
8397   {
8398     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8399     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8400     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8401   },
8402   {
8403     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8404     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8405   },
8406   {
8407     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8408     { Bad_Opcode },
8409     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8410   },
8411   {
8412     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8413     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8414   },
8415   {
8416     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8417     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8418   },
8419   {
8420     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8421     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8422   },
8423   {
8424     /* MOD_VEX_0F385A */
8425     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8426   },
8427   {
8428     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8429     { Bad_Opcode },
8430     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8431   },
8432   {
8433     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8434     { Bad_Opcode },
8435     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8436   },
8437   {
8438     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8439     { Bad_Opcode },
8440     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8441   },
8442   {
8443     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8444     { Bad_Opcode },
8445     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8446   },
8447   {
8448     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8449     { Bad_Opcode },
8450     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8451   },
8452   {
8453     /* MOD_VEX_0F388C */
8454     { "vpmaskmov%DQ",	{ XM, Vex, Mx }, PREFIX_DATA },
8455   },
8456   {
8457     /* MOD_VEX_0F388E */
8458     { "vpmaskmov%DQ",	{ Mx, Vex, XM }, PREFIX_DATA },
8459   },
8460   {
8461     /* MOD_VEX_0F3A30_L_0 */
8462     { Bad_Opcode },
8463     { "kshiftr%BW",	{ MaskG, MaskE, Ib }, PREFIX_DATA },
8464   },
8465   {
8466     /* MOD_VEX_0F3A31_L_0 */
8467     { Bad_Opcode },
8468     { "kshiftr%DQ",	{ MaskG, MaskE, Ib }, PREFIX_DATA },
8469   },
8470   {
8471     /* MOD_VEX_0F3A32_L_0 */
8472     { Bad_Opcode },
8473     { "kshiftl%BW",	{ MaskG, MaskE, Ib }, PREFIX_DATA },
8474   },
8475   {
8476     /* MOD_VEX_0F3A33_L_0 */
8477     { Bad_Opcode },
8478     { "kshiftl%DQ",	{ MaskG, MaskE, Ib }, PREFIX_DATA },
8479   },
8480   {
8481     /* MOD_XOP_09_12 */
8482     { Bad_Opcode },
8483     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8484   },
8485 
8486 #include "i386-dis-evex-mod.h"
8487 };
8488 
8489 static const struct dis386 rm_table[][8] = {
8490   {
8491     /* RM_C6_REG_7 */
8492     { "xabort",		{ Skip_MODRM, Ib }, 0 },
8493   },
8494   {
8495     /* RM_C7_REG_7 */
8496     { "xbeginT",	{ Skip_MODRM, Jdqw }, 0 },
8497   },
8498   {
8499     /* RM_0F01_REG_0 */
8500     { "enclv",		{ Skip_MODRM }, 0 },
8501     { "vmcall",		{ Skip_MODRM }, 0 },
8502     { "vmlaunch",	{ Skip_MODRM }, 0 },
8503     { "vmresume",	{ Skip_MODRM }, 0 },
8504     { "vmxoff",		{ Skip_MODRM }, 0 },
8505     { "pconfig",	{ Skip_MODRM }, 0 },
8506   },
8507   {
8508     /* RM_0F01_REG_1 */
8509     { "monitor",	{ { OP_Monitor, 0 } }, 0 },
8510     { "mwait",		{ { OP_Mwait, 0 } }, 0 },
8511     { "clac",		{ Skip_MODRM }, 0 },
8512     { "stac",		{ Skip_MODRM }, 0 },
8513     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8514     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8515     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8516     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8517   },
8518   {
8519     /* RM_0F01_REG_2 */
8520     { "xgetbv",		{ Skip_MODRM }, 0 },
8521     { "xsetbv",		{ Skip_MODRM }, 0 },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { "vmfunc",		{ Skip_MODRM }, 0 },
8525     { "xend",		{ Skip_MODRM }, 0 },
8526     { "xtest",		{ Skip_MODRM }, 0 },
8527     { "enclu",		{ Skip_MODRM }, 0 },
8528   },
8529   {
8530     /* RM_0F01_REG_3 */
8531     { "vmrun",		{ Skip_MODRM }, 0 },
8532     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8533     { "vmload",		{ Skip_MODRM }, 0 },
8534     { "vmsave",		{ Skip_MODRM }, 0 },
8535     { "stgi",		{ Skip_MODRM }, 0 },
8536     { "clgi",		{ Skip_MODRM }, 0 },
8537     { "skinit",		{ Skip_MODRM }, 0 },
8538     { "invlpga",	{ Skip_MODRM }, 0 },
8539   },
8540   {
8541     /* RM_0F01_REG_5_MOD_3 */
8542     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8543     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8544     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8545     { Bad_Opcode },
8546     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8547     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8548     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8549     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8550   },
8551   {
8552     /* RM_0F01_REG_7_MOD_3 */
8553     { "swapgs",		{ Skip_MODRM }, 0  },
8554     { "rdtscp",		{ Skip_MODRM }, 0  },
8555     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8556     { "mwaitx",		{ { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8557     { "clzero",		{ Skip_MODRM }, 0  },
8558     { "rdpru",		{ Skip_MODRM }, 0  },
8559     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8560     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8561   },
8562   {
8563     /* RM_0F1E_P_1_MOD_3_REG_7 */
8564     { "nopQ",		{ Ev }, PREFIX_IGNORED },
8565     { "nopQ",		{ Ev }, PREFIX_IGNORED },
8566     { "endbr64",	{ Skip_MODRM }, 0 },
8567     { "endbr32",	{ Skip_MODRM }, 0 },
8568     { "nopQ",		{ Ev }, PREFIX_IGNORED },
8569     { "nopQ",		{ Ev }, PREFIX_IGNORED },
8570     { "nopQ",		{ Ev }, PREFIX_IGNORED },
8571     { "nopQ",		{ Ev }, PREFIX_IGNORED },
8572   },
8573   {
8574     /* RM_0FAE_REG_6_MOD_3 */
8575     { "mfence",		{ Skip_MODRM }, 0 },
8576   },
8577   {
8578     /* RM_0FAE_REG_7_MOD_3 */
8579     { "sfence",		{ Skip_MODRM }, 0 },
8580   },
8581   {
8582     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8583     { "hreset",		{ Skip_MODRM, Ib }, 0 },
8584   },
8585   {
8586     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8587     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8588   },
8589 };
8590 
8591 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8592 
8593 /* We use the high bit to indicate different name for the same
8594    prefix.  */
8595 #define REP_PREFIX	(0xf3 | 0x100)
8596 #define XACQUIRE_PREFIX	(0xf2 | 0x200)
8597 #define XRELEASE_PREFIX	(0xf3 | 0x400)
8598 #define BND_PREFIX	(0xf2 | 0x400)
8599 #define NOTRACK_PREFIX	(0x3e | 0x100)
8600 
8601 /* Remember if the current op is a jump instruction.  */
8602 static bool op_is_jump = false;
8603 
8604 static int
ckprefix(void)8605 ckprefix (void)
8606 {
8607   int newrex, i, length;
8608   rex = 0;
8609   prefixes = 0;
8610   used_prefixes = 0;
8611   rex_used = 0;
8612   last_lock_prefix = -1;
8613   last_repz_prefix = -1;
8614   last_repnz_prefix = -1;
8615   last_data_prefix = -1;
8616   last_addr_prefix = -1;
8617   last_rex_prefix = -1;
8618   last_seg_prefix = -1;
8619   fwait_prefix = -1;
8620   active_seg_prefix = 0;
8621   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8622     all_prefixes[i] = 0;
8623   i = 0;
8624   length = 0;
8625   /* The maximum instruction length is 15bytes.  */
8626   while (length < MAX_CODE_LENGTH - 1)
8627     {
8628       FETCH_DATA (the_info, codep + 1);
8629       newrex = 0;
8630       switch (*codep)
8631 	{
8632 	/* REX prefixes family.  */
8633 	case 0x40:
8634 	case 0x41:
8635 	case 0x42:
8636 	case 0x43:
8637 	case 0x44:
8638 	case 0x45:
8639 	case 0x46:
8640 	case 0x47:
8641 	case 0x48:
8642 	case 0x49:
8643 	case 0x4a:
8644 	case 0x4b:
8645 	case 0x4c:
8646 	case 0x4d:
8647 	case 0x4e:
8648 	case 0x4f:
8649 	  if (address_mode == mode_64bit)
8650 	    newrex = *codep;
8651 	  else
8652 	    return 1;
8653 	  last_rex_prefix = i;
8654 	  break;
8655 	case 0xf3:
8656 	  prefixes |= PREFIX_REPZ;
8657 	  last_repz_prefix = i;
8658 	  break;
8659 	case 0xf2:
8660 	  prefixes |= PREFIX_REPNZ;
8661 	  last_repnz_prefix = i;
8662 	  break;
8663 	case 0xf0:
8664 	  prefixes |= PREFIX_LOCK;
8665 	  last_lock_prefix = i;
8666 	  break;
8667 	case 0x2e:
8668 	  prefixes |= PREFIX_CS;
8669 	  last_seg_prefix = i;
8670 
8671 	  if (address_mode != mode_64bit)
8672 	    active_seg_prefix = PREFIX_CS;
8673 
8674 	  break;
8675 	case 0x36:
8676 	  prefixes |= PREFIX_SS;
8677 	  last_seg_prefix = i;
8678 
8679 	  if (address_mode != mode_64bit)
8680 	    active_seg_prefix = PREFIX_SS;
8681 
8682 	  break;
8683 	case 0x3e:
8684 	  prefixes |= PREFIX_DS;
8685 	  last_seg_prefix = i;
8686 
8687 	  if (address_mode != mode_64bit)
8688 	    active_seg_prefix = PREFIX_DS;
8689 
8690 	  break;
8691 	case 0x26:
8692 	  prefixes |= PREFIX_ES;
8693 	  last_seg_prefix = i;
8694 
8695 	  if (address_mode != mode_64bit)
8696 	    active_seg_prefix = PREFIX_ES;
8697 
8698 	  break;
8699 	case 0x64:
8700 	  prefixes |= PREFIX_FS;
8701 	  last_seg_prefix = i;
8702 	  active_seg_prefix = PREFIX_FS;
8703 	  break;
8704 	case 0x65:
8705 	  prefixes |= PREFIX_GS;
8706 	  last_seg_prefix = i;
8707 	  active_seg_prefix = PREFIX_GS;
8708 	  break;
8709 	case 0x66:
8710 	  prefixes |= PREFIX_DATA;
8711 	  last_data_prefix = i;
8712 	  break;
8713 	case 0x67:
8714 	  prefixes |= PREFIX_ADDR;
8715 	  last_addr_prefix = i;
8716 	  break;
8717 	case FWAIT_OPCODE:
8718 	  /* fwait is really an instruction.  If there are prefixes
8719 	     before the fwait, they belong to the fwait, *not* to the
8720 	     following instruction.  */
8721 	  fwait_prefix = i;
8722 	  if (prefixes || rex)
8723 	    {
8724 	      prefixes |= PREFIX_FWAIT;
8725 	      codep++;
8726 	      /* This ensures that the previous REX prefixes are noticed
8727 		 as unused prefixes, as in the return case below.  */
8728 	      rex_used = rex;
8729 	      return 1;
8730 	    }
8731 	  prefixes = PREFIX_FWAIT;
8732 	  break;
8733 	default:
8734 	  return 1;
8735 	}
8736       /* Rex is ignored when followed by another prefix.  */
8737       if (rex)
8738 	{
8739 	  rex_used = rex;
8740 	  return 1;
8741 	}
8742       if (*codep != FWAIT_OPCODE)
8743 	all_prefixes[i++] = *codep;
8744       rex = newrex;
8745       codep++;
8746       length++;
8747     }
8748   return 0;
8749 }
8750 
8751 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8752    prefix byte.  */
8753 
8754 static const char *
prefix_name(int pref,int sizeflag)8755 prefix_name (int pref, int sizeflag)
8756 {
8757   static const char *rexes [16] =
8758     {
8759       "rex",		/* 0x40 */
8760       "rex.B",		/* 0x41 */
8761       "rex.X",		/* 0x42 */
8762       "rex.XB",		/* 0x43 */
8763       "rex.R",		/* 0x44 */
8764       "rex.RB",		/* 0x45 */
8765       "rex.RX",		/* 0x46 */
8766       "rex.RXB",	/* 0x47 */
8767       "rex.W",		/* 0x48 */
8768       "rex.WB",		/* 0x49 */
8769       "rex.WX",		/* 0x4a */
8770       "rex.WXB",	/* 0x4b */
8771       "rex.WR",		/* 0x4c */
8772       "rex.WRB",	/* 0x4d */
8773       "rex.WRX",	/* 0x4e */
8774       "rex.WRXB",	/* 0x4f */
8775     };
8776 
8777   switch (pref)
8778     {
8779     /* REX prefixes family.  */
8780     case 0x40:
8781     case 0x41:
8782     case 0x42:
8783     case 0x43:
8784     case 0x44:
8785     case 0x45:
8786     case 0x46:
8787     case 0x47:
8788     case 0x48:
8789     case 0x49:
8790     case 0x4a:
8791     case 0x4b:
8792     case 0x4c:
8793     case 0x4d:
8794     case 0x4e:
8795     case 0x4f:
8796       return rexes [pref - 0x40];
8797     case 0xf3:
8798       return "repz";
8799     case 0xf2:
8800       return "repnz";
8801     case 0xf0:
8802       return "lock";
8803     case 0x2e:
8804       return "cs";
8805     case 0x36:
8806       return "ss";
8807     case 0x3e:
8808       return "ds";
8809     case 0x26:
8810       return "es";
8811     case 0x64:
8812       return "fs";
8813     case 0x65:
8814       return "gs";
8815     case 0x66:
8816       return (sizeflag & DFLAG) ? "data16" : "data32";
8817     case 0x67:
8818       if (address_mode == mode_64bit)
8819 	return (sizeflag & AFLAG) ? "addr32" : "addr64";
8820       else
8821 	return (sizeflag & AFLAG) ? "addr16" : "addr32";
8822     case FWAIT_OPCODE:
8823       return "fwait";
8824     case REP_PREFIX:
8825       return "rep";
8826     case XACQUIRE_PREFIX:
8827       return "xacquire";
8828     case XRELEASE_PREFIX:
8829       return "xrelease";
8830     case BND_PREFIX:
8831       return "bnd";
8832     case NOTRACK_PREFIX:
8833       return "notrack";
8834     default:
8835       return NULL;
8836     }
8837 }
8838 
8839 static char op_out[MAX_OPERANDS][100];
8840 static int op_ad, op_index[MAX_OPERANDS];
8841 static int two_source_ops;
8842 static bfd_vma op_address[MAX_OPERANDS];
8843 static bfd_vma op_riprel[MAX_OPERANDS];
8844 static bfd_vma start_pc;
8845 
8846 /*
8847  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8848  *   (see topic "Redundant prefixes" in the "Differences from 8086"
8849  *   section of the "Virtual 8086 Mode" chapter.)
8850  * 'pc' should be the address of this instruction, it will
8851  *   be used to print the target address if this is a relative jump or call
8852  * The function returns the length of this instruction in bytes.
8853  */
8854 
8855 static char intel_syntax;
8856 static char intel_mnemonic = !SYSV386_COMPAT;
8857 static char open_char;
8858 static char close_char;
8859 static char separator_char;
8860 static char scale_char;
8861 
8862 enum x86_64_isa
8863 {
8864   amd64 = 1,
8865   intel64
8866 };
8867 
8868 static enum x86_64_isa isa64;
8869 
8870 /* Here for backwards compatibility.  When gdb stops using
8871    print_insn_i386_att and print_insn_i386_intel these functions can
8872    disappear, and print_insn_i386 be merged into print_insn.  */
8873 int
print_insn_i386_att(bfd_vma pc,disassemble_info * info)8874 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8875 {
8876   intel_syntax = 0;
8877 
8878   return print_insn (pc, info);
8879 }
8880 
8881 int
print_insn_i386_intel(bfd_vma pc,disassemble_info * info)8882 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8883 {
8884   intel_syntax = 1;
8885 
8886   return print_insn (pc, info);
8887 }
8888 
8889 int
print_insn_i386(bfd_vma pc,disassemble_info * info)8890 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8891 {
8892   intel_syntax = -1;
8893 
8894   return print_insn (pc, info);
8895 }
8896 
8897 void
print_i386_disassembler_options(FILE * stream)8898 print_i386_disassembler_options (FILE *stream)
8899 {
8900   fprintf (stream, _("\n\
8901 The following i386/x86-64 specific disassembler options are supported for use\n\
8902 with the -M switch (multiple options should be separated by commas):\n"));
8903 
8904   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8905   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8906   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8907   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8908   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8909   fprintf (stream, _("  att-mnemonic\n"
8910 		     "              Display instruction in AT&T mnemonic\n"));
8911   fprintf (stream, _("  intel-mnemonic\n"
8912 		     "              Display instruction in Intel mnemonic\n"));
8913   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8914   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8915   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8916   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8917   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8918   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8919   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8920   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8921 }
8922 
8923 /* Bad opcode.  */
8924 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8925 
8926 /* Get a pointer to struct dis386 with a valid name.  */
8927 
8928 static const struct dis386 *
get_valid_dis386(const struct dis386 * dp,disassemble_info * info)8929 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
8930 {
8931   int vindex, vex_table_index;
8932 
8933   if (dp->name != NULL)
8934     return dp;
8935 
8936   switch (dp->op[0].bytemode)
8937     {
8938     case USE_REG_TABLE:
8939       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
8940       break;
8941 
8942     case USE_MOD_TABLE:
8943       vindex = modrm.mod == 0x3 ? 1 : 0;
8944       dp = &mod_table[dp->op[1].bytemode][vindex];
8945       break;
8946 
8947     case USE_RM_TABLE:
8948       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
8949       break;
8950 
8951     case USE_PREFIX_TABLE:
8952       if (need_vex)
8953 	{
8954 	  /* The prefix in VEX is implicit.  */
8955 	  switch (vex.prefix)
8956 	    {
8957 	    case 0:
8958 	      vindex = 0;
8959 	      break;
8960 	    case REPE_PREFIX_OPCODE:
8961 	      vindex = 1;
8962 	      break;
8963 	    case DATA_PREFIX_OPCODE:
8964 	      vindex = 2;
8965 	      break;
8966 	    case REPNE_PREFIX_OPCODE:
8967 	      vindex = 3;
8968 	      break;
8969 	    default:
8970 	      abort ();
8971 	      break;
8972 	    }
8973 	}
8974       else
8975 	{
8976 	  int last_prefix = -1;
8977 	  int prefix = 0;
8978 	  vindex = 0;
8979 	  /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8980 	     When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8981 	     last one wins.  */
8982 	  if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8983 	    {
8984 	      if (last_repz_prefix > last_repnz_prefix)
8985 		{
8986 		  vindex = 1;
8987 		  prefix = PREFIX_REPZ;
8988 		  last_prefix = last_repz_prefix;
8989 		}
8990 	      else
8991 		{
8992 		  vindex = 3;
8993 		  prefix = PREFIX_REPNZ;
8994 		  last_prefix = last_repnz_prefix;
8995 		}
8996 
8997 	      /* Check if prefix should be ignored.  */
8998 	      if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8999 		     & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9000 		   & prefix) != 0
9001 		  && !prefix_table[dp->op[1].bytemode][vindex].name)
9002 		vindex = 0;
9003 	    }
9004 
9005 	  if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9006 	    {
9007 	      vindex = 2;
9008 	      prefix = PREFIX_DATA;
9009 	      last_prefix = last_data_prefix;
9010 	    }
9011 
9012 	  if (vindex != 0)
9013 	    {
9014 	      used_prefixes |= prefix;
9015 	      all_prefixes[last_prefix] = 0;
9016 	    }
9017 	}
9018       dp = &prefix_table[dp->op[1].bytemode][vindex];
9019       break;
9020 
9021     case USE_X86_64_TABLE:
9022       vindex = address_mode == mode_64bit ? 1 : 0;
9023       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9024       break;
9025 
9026     case USE_3BYTE_TABLE:
9027       FETCH_DATA (info, codep + 2);
9028       vindex = *codep++;
9029       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9030       end_codep = codep;
9031       modrm.mod = (*codep >> 6) & 3;
9032       modrm.reg = (*codep >> 3) & 7;
9033       modrm.rm = *codep & 7;
9034       break;
9035 
9036     case USE_VEX_LEN_TABLE:
9037       if (!need_vex)
9038 	abort ();
9039 
9040       switch (vex.length)
9041 	{
9042 	case 128:
9043 	  vindex = 0;
9044 	  break;
9045 	case 512:
9046 	  /* This allows re-using in particular table entries where only
9047 	     128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
9048 	  if (vex.evex)
9049 	    {
9050 	case 256:
9051 	      vindex = 1;
9052 	      break;
9053 	    }
9054 	/* Fall through.  */
9055 	default:
9056 	  abort ();
9057 	  break;
9058 	}
9059 
9060       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9061       break;
9062 
9063     case USE_EVEX_LEN_TABLE:
9064       if (!vex.evex)
9065 	abort ();
9066 
9067       switch (vex.length)
9068 	{
9069 	case 128:
9070 	  vindex = 0;
9071 	  break;
9072 	case 256:
9073 	  vindex = 1;
9074 	  break;
9075 	case 512:
9076 	  vindex = 2;
9077 	  break;
9078 	default:
9079 	  abort ();
9080 	  break;
9081 	}
9082 
9083       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9084       break;
9085 
9086     case USE_XOP_8F_TABLE:
9087       FETCH_DATA (info, codep + 3);
9088       rex = ~(*codep >> 5) & 0x7;
9089 
9090       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9091       switch ((*codep & 0x1f))
9092 	{
9093 	default:
9094 	  dp = &bad_opcode;
9095 	  return dp;
9096 	case 0x8:
9097 	  vex_table_index = XOP_08;
9098 	  break;
9099 	case 0x9:
9100 	  vex_table_index = XOP_09;
9101 	  break;
9102 	case 0xa:
9103 	  vex_table_index = XOP_0A;
9104 	  break;
9105 	}
9106       codep++;
9107       vex.w = *codep & 0x80;
9108       if (vex.w && address_mode == mode_64bit)
9109 	rex |= REX_W;
9110 
9111       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9112       if (address_mode != mode_64bit)
9113 	{
9114 	  /* In 16/32-bit mode REX_B is silently ignored.  */
9115 	  rex &= ~REX_B;
9116 	}
9117 
9118       vex.length = (*codep & 0x4) ? 256 : 128;
9119       switch ((*codep & 0x3))
9120 	{
9121 	case 0:
9122 	  break;
9123 	case 1:
9124 	  vex.prefix = DATA_PREFIX_OPCODE;
9125 	  break;
9126 	case 2:
9127 	  vex.prefix = REPE_PREFIX_OPCODE;
9128 	  break;
9129 	case 3:
9130 	  vex.prefix = REPNE_PREFIX_OPCODE;
9131 	  break;
9132 	}
9133       need_vex = 1;
9134       codep++;
9135       vindex = *codep++;
9136       dp = &xop_table[vex_table_index][vindex];
9137 
9138       end_codep = codep;
9139       FETCH_DATA (info, codep + 1);
9140       modrm.mod = (*codep >> 6) & 3;
9141       modrm.reg = (*codep >> 3) & 7;
9142       modrm.rm = *codep & 7;
9143 
9144       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9145 	 having to decode the bits for every otherwise valid encoding.  */
9146       if (vex.prefix)
9147 	return &bad_opcode;
9148       break;
9149 
9150     case USE_VEX_C4_TABLE:
9151       /* VEX prefix.  */
9152       FETCH_DATA (info, codep + 3);
9153       rex = ~(*codep >> 5) & 0x7;
9154       switch ((*codep & 0x1f))
9155 	{
9156 	default:
9157 	  dp = &bad_opcode;
9158 	  return dp;
9159 	case 0x1:
9160 	  vex_table_index = VEX_0F;
9161 	  break;
9162 	case 0x2:
9163 	  vex_table_index = VEX_0F38;
9164 	  break;
9165 	case 0x3:
9166 	  vex_table_index = VEX_0F3A;
9167 	  break;
9168 	}
9169       codep++;
9170       vex.w = *codep & 0x80;
9171       if (address_mode == mode_64bit)
9172 	{
9173 	  if (vex.w)
9174 	    rex |= REX_W;
9175 	}
9176       else
9177 	{
9178 	  /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9179 	     is ignored, other REX bits are 0 and the highest bit in
9180 	     VEX.vvvv is also ignored (but we mustn't clear it here).  */
9181 	  rex = 0;
9182 	}
9183       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9184       vex.length = (*codep & 0x4) ? 256 : 128;
9185       switch ((*codep & 0x3))
9186 	{
9187 	case 0:
9188 	  break;
9189 	case 1:
9190 	  vex.prefix = DATA_PREFIX_OPCODE;
9191 	  break;
9192 	case 2:
9193 	  vex.prefix = REPE_PREFIX_OPCODE;
9194 	  break;
9195 	case 3:
9196 	  vex.prefix = REPNE_PREFIX_OPCODE;
9197 	  break;
9198 	}
9199       need_vex = 1;
9200       codep++;
9201       vindex = *codep++;
9202       dp = &vex_table[vex_table_index][vindex];
9203       end_codep = codep;
9204       /* There is no MODRM byte for VEX0F 77.  */
9205       if (vex_table_index != VEX_0F || vindex != 0x77)
9206 	{
9207 	  FETCH_DATA (info, codep + 1);
9208 	  modrm.mod = (*codep >> 6) & 3;
9209 	  modrm.reg = (*codep >> 3) & 7;
9210 	  modrm.rm = *codep & 7;
9211 	}
9212       break;
9213 
9214     case USE_VEX_C5_TABLE:
9215       /* VEX prefix.  */
9216       FETCH_DATA (info, codep + 2);
9217       rex = (*codep & 0x80) ? 0 : REX_R;
9218 
9219       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9220 	 VEX.vvvv is 1.  */
9221       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9222       vex.length = (*codep & 0x4) ? 256 : 128;
9223       switch ((*codep & 0x3))
9224 	{
9225 	case 0:
9226 	  break;
9227 	case 1:
9228 	  vex.prefix = DATA_PREFIX_OPCODE;
9229 	  break;
9230 	case 2:
9231 	  vex.prefix = REPE_PREFIX_OPCODE;
9232 	  break;
9233 	case 3:
9234 	  vex.prefix = REPNE_PREFIX_OPCODE;
9235 	  break;
9236 	}
9237       need_vex = 1;
9238       codep++;
9239       vindex = *codep++;
9240       dp = &vex_table[dp->op[1].bytemode][vindex];
9241       end_codep = codep;
9242       /* There is no MODRM byte for VEX 77.  */
9243       if (vindex != 0x77)
9244 	{
9245 	  FETCH_DATA (info, codep + 1);
9246 	  modrm.mod = (*codep >> 6) & 3;
9247 	  modrm.reg = (*codep >> 3) & 7;
9248 	  modrm.rm = *codep & 7;
9249 	}
9250       break;
9251 
9252     case USE_VEX_W_TABLE:
9253       if (!need_vex)
9254 	abort ();
9255 
9256       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9257       break;
9258 
9259     case USE_EVEX_TABLE:
9260       two_source_ops = 0;
9261       /* EVEX prefix.  */
9262       vex.evex = 1;
9263       FETCH_DATA (info, codep + 4);
9264       /* The first byte after 0x62.  */
9265       rex = ~(*codep >> 5) & 0x7;
9266       vex.r = *codep & 0x10;
9267       switch ((*codep & 0xf))
9268 	{
9269 	default:
9270 	  return &bad_opcode;
9271 	case 0x1:
9272 	  vex_table_index = EVEX_0F;
9273 	  break;
9274 	case 0x2:
9275 	  vex_table_index = EVEX_0F38;
9276 	  break;
9277 	case 0x3:
9278 	  vex_table_index = EVEX_0F3A;
9279 	  break;
9280 	}
9281 
9282       /* The second byte after 0x62.  */
9283       codep++;
9284       vex.w = *codep & 0x80;
9285       if (vex.w && address_mode == mode_64bit)
9286 	rex |= REX_W;
9287 
9288       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9289 
9290       /* The U bit.  */
9291       if (!(*codep & 0x4))
9292 	return &bad_opcode;
9293 
9294       switch ((*codep & 0x3))
9295 	{
9296 	case 0:
9297 	  break;
9298 	case 1:
9299 	  vex.prefix = DATA_PREFIX_OPCODE;
9300 	  break;
9301 	case 2:
9302 	  vex.prefix = REPE_PREFIX_OPCODE;
9303 	  break;
9304 	case 3:
9305 	  vex.prefix = REPNE_PREFIX_OPCODE;
9306 	  break;
9307 	}
9308 
9309       /* The third byte after 0x62.  */
9310       codep++;
9311 
9312       /* Remember the static rounding bits.  */
9313       vex.ll = (*codep >> 5) & 3;
9314       vex.b = (*codep & 0x10) != 0;
9315 
9316       vex.v = *codep & 0x8;
9317       vex.mask_register_specifier = *codep & 0x7;
9318       vex.zeroing = *codep & 0x80;
9319 
9320       if (address_mode != mode_64bit)
9321 	{
9322 	  /* In 16/32-bit mode silently ignore following bits.  */
9323 	  rex &= ~REX_B;
9324 	  vex.r = 1;
9325 	  vex.v = 1;
9326 	}
9327 
9328       need_vex = 1;
9329       codep++;
9330       vindex = *codep++;
9331       dp = &evex_table[vex_table_index][vindex];
9332       end_codep = codep;
9333       FETCH_DATA (info, codep + 1);
9334       modrm.mod = (*codep >> 6) & 3;
9335       modrm.reg = (*codep >> 3) & 7;
9336       modrm.rm = *codep & 7;
9337 
9338       /* Set vector length.  */
9339       if (modrm.mod == 3 && vex.b)
9340 	vex.length = 512;
9341       else
9342 	{
9343 	  switch (vex.ll)
9344 	    {
9345 	    case 0x0:
9346 	      vex.length = 128;
9347 	      break;
9348 	    case 0x1:
9349 	      vex.length = 256;
9350 	      break;
9351 	    case 0x2:
9352 	      vex.length = 512;
9353 	      break;
9354 	    default:
9355 	      return &bad_opcode;
9356 	    }
9357 	}
9358       break;
9359 
9360     case 0:
9361       dp = &bad_opcode;
9362       break;
9363 
9364     default:
9365       abort ();
9366     }
9367 
9368   if (dp->name != NULL)
9369     return dp;
9370   else
9371     return get_valid_dis386 (dp, info);
9372 }
9373 
9374 static void
get_sib(disassemble_info * info,int sizeflag)9375 get_sib (disassemble_info *info, int sizeflag)
9376 {
9377   /* If modrm.mod == 3, operand must be register.  */
9378   if (need_modrm
9379       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9380       && modrm.mod != 3
9381       && modrm.rm == 4)
9382     {
9383       FETCH_DATA (info, codep + 2);
9384       sib.index = (codep [1] >> 3) & 7;
9385       sib.scale = (codep [1] >> 6) & 3;
9386       sib.base = codep [1] & 7;
9387     }
9388 }
9389 
9390 static int
print_insn(bfd_vma pc,disassemble_info * info)9391 print_insn (bfd_vma pc, disassemble_info *info)
9392 {
9393   const struct dis386 *dp;
9394   int i;
9395   char *op_txt[MAX_OPERANDS];
9396   int needcomma;
9397   int sizeflag, orig_sizeflag;
9398   const char *p;
9399   struct dis_private priv;
9400   int prefix_length;
9401 
9402   priv.orig_sizeflag = AFLAG | DFLAG;
9403   if ((info->mach & bfd_mach_i386_i386) != 0)
9404     address_mode = mode_32bit;
9405   else if (info->mach == bfd_mach_i386_i8086)
9406     {
9407       address_mode = mode_16bit;
9408       priv.orig_sizeflag = 0;
9409     }
9410   else
9411     address_mode = mode_64bit;
9412 
9413   if (intel_syntax == (char) -1)
9414     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9415 
9416   for (p = info->disassembler_options; p != NULL; )
9417     {
9418       if (startswith (p, "amd64"))
9419 	isa64 = amd64;
9420       else if (startswith (p, "intel64"))
9421 	isa64 = intel64;
9422       else if (startswith (p, "x86-64"))
9423 	{
9424 	  address_mode = mode_64bit;
9425 	  priv.orig_sizeflag |= AFLAG | DFLAG;
9426 	}
9427       else if (startswith (p, "i386"))
9428 	{
9429 	  address_mode = mode_32bit;
9430 	  priv.orig_sizeflag |= AFLAG | DFLAG;
9431 	}
9432       else if (startswith (p, "i8086"))
9433 	{
9434 	  address_mode = mode_16bit;
9435 	  priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9436 	}
9437       else if (startswith (p, "intel"))
9438 	{
9439 	  intel_syntax = 1;
9440 	  if (startswith (p + 5, "-mnemonic"))
9441 	    intel_mnemonic = 1;
9442 	}
9443       else if (startswith (p, "att"))
9444 	{
9445 	  intel_syntax = 0;
9446 	  if (startswith (p + 3, "-mnemonic"))
9447 	    intel_mnemonic = 0;
9448 	}
9449       else if (startswith (p, "addr"))
9450 	{
9451 	  if (address_mode == mode_64bit)
9452 	    {
9453 	      if (p[4] == '3' && p[5] == '2')
9454 		priv.orig_sizeflag &= ~AFLAG;
9455 	      else if (p[4] == '6' && p[5] == '4')
9456 		priv.orig_sizeflag |= AFLAG;
9457 	    }
9458 	  else
9459 	    {
9460 	      if (p[4] == '1' && p[5] == '6')
9461 		priv.orig_sizeflag &= ~AFLAG;
9462 	      else if (p[4] == '3' && p[5] == '2')
9463 		priv.orig_sizeflag |= AFLAG;
9464 	    }
9465 	}
9466       else if (startswith (p, "data"))
9467 	{
9468 	  if (p[4] == '1' && p[5] == '6')
9469 	    priv.orig_sizeflag &= ~DFLAG;
9470 	  else if (p[4] == '3' && p[5] == '2')
9471 	    priv.orig_sizeflag |= DFLAG;
9472 	}
9473       else if (startswith (p, "suffix"))
9474 	priv.orig_sizeflag |= SUFFIX_ALWAYS;
9475 
9476       p = strchr (p, ',');
9477       if (p != NULL)
9478 	p++;
9479     }
9480 
9481   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9482     {
9483       (*info->fprintf_func) (info->stream,
9484 			     _("64-bit address is disabled"));
9485       return -1;
9486     }
9487 
9488   if (intel_syntax)
9489     {
9490       names64 = intel_names64;
9491       names32 = intel_names32;
9492       names16 = intel_names16;
9493       names8 = intel_names8;
9494       names8rex = intel_names8rex;
9495       names_seg = intel_names_seg;
9496       names_mm = intel_names_mm;
9497       names_bnd = intel_names_bnd;
9498       names_xmm = intel_names_xmm;
9499       names_ymm = intel_names_ymm;
9500       names_zmm = intel_names_zmm;
9501       names_tmm = intel_names_tmm;
9502       index64 = intel_index64;
9503       index32 = intel_index32;
9504       names_mask = intel_names_mask;
9505       index16 = intel_index16;
9506       open_char = '[';
9507       close_char = ']';
9508       separator_char = '+';
9509       scale_char = '*';
9510     }
9511   else
9512     {
9513       names64 = att_names64;
9514       names32 = att_names32;
9515       names16 = att_names16;
9516       names8 = att_names8;
9517       names8rex = att_names8rex;
9518       names_seg = att_names_seg;
9519       names_mm = att_names_mm;
9520       names_bnd = att_names_bnd;
9521       names_xmm = att_names_xmm;
9522       names_ymm = att_names_ymm;
9523       names_zmm = att_names_zmm;
9524       names_tmm = att_names_tmm;
9525       index64 = att_index64;
9526       index32 = att_index32;
9527       names_mask = att_names_mask;
9528       index16 = att_index16;
9529       open_char = '(';
9530       close_char =  ')';
9531       separator_char = ',';
9532       scale_char = ',';
9533     }
9534 
9535   /* The output looks better if we put 7 bytes on a line, since that
9536      puts most long word instructions on a single line.  Use 8 bytes
9537      for Intel L1OM.  */
9538   if ((info->mach & bfd_mach_l1om) != 0)
9539     info->bytes_per_line = 8;
9540   else
9541     info->bytes_per_line = 7;
9542 
9543   info->private_data = &priv;
9544   priv.max_fetched = priv.the_buffer;
9545   priv.insn_start = pc;
9546 
9547   obuf[0] = 0;
9548   for (i = 0; i < MAX_OPERANDS; ++i)
9549     {
9550       op_out[i][0] = 0;
9551       op_index[i] = -1;
9552     }
9553 
9554   the_info = info;
9555   start_pc = pc;
9556   start_codep = priv.the_buffer;
9557   codep = priv.the_buffer;
9558 
9559   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9560     {
9561       const char *name;
9562 
9563       /* Getting here means we tried for data but didn't get it.  That
9564 	 means we have an incomplete instruction of some sort.  Just
9565 	 print the first byte as a prefix or a .byte pseudo-op.  */
9566       if (codep > priv.the_buffer)
9567 	{
9568 	  name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9569 	  if (name != NULL)
9570 	    (*info->fprintf_func) (info->stream, "%s", name);
9571 	  else
9572 	    {
9573 	      /* Just print the first byte as a .byte instruction.  */
9574 	      (*info->fprintf_func) (info->stream, ".byte 0x%x",
9575 				     (unsigned int) priv.the_buffer[0]);
9576 	    }
9577 
9578 	  return 1;
9579 	}
9580 
9581       return -1;
9582     }
9583 
9584   obufp = obuf;
9585   sizeflag = priv.orig_sizeflag;
9586 
9587   if (!ckprefix () || rex_used)
9588     {
9589       /* Too many prefixes or unused REX prefixes.  */
9590       for (i = 0;
9591 	   i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9592 	   i++)
9593 	(*info->fprintf_func) (info->stream, "%s%s",
9594 			       i == 0 ? "" : " ",
9595 			       prefix_name (all_prefixes[i], sizeflag));
9596       return i;
9597     }
9598 
9599   insn_codep = codep;
9600 
9601   FETCH_DATA (info, codep + 1);
9602   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9603 
9604   if (((prefixes & PREFIX_FWAIT)
9605        && ((*codep < 0xd8) || (*codep > 0xdf))))
9606     {
9607       /* Handle prefixes before fwait.  */
9608       for (i = 0; i < fwait_prefix && all_prefixes[i];
9609 	   i++)
9610 	(*info->fprintf_func) (info->stream, "%s ",
9611 			       prefix_name (all_prefixes[i], sizeflag));
9612       (*info->fprintf_func) (info->stream, "fwait");
9613       return i + 1;
9614     }
9615 
9616   if (*codep == 0x0f)
9617     {
9618       unsigned char threebyte;
9619 
9620       codep++;
9621       FETCH_DATA (info, codep + 1);
9622       threebyte = *codep;
9623       dp = &dis386_twobyte[threebyte];
9624       need_modrm = twobyte_has_modrm[threebyte];
9625       codep++;
9626     }
9627   else
9628     {
9629       dp = &dis386[*codep];
9630       need_modrm = onebyte_has_modrm[*codep];
9631       codep++;
9632     }
9633 
9634   /* Save sizeflag for printing the extra prefixes later before updating
9635      it for mnemonic and operand processing.  The prefix names depend
9636      only on the address mode.  */
9637   orig_sizeflag = sizeflag;
9638   if (prefixes & PREFIX_ADDR)
9639     sizeflag ^= AFLAG;
9640   if ((prefixes & PREFIX_DATA))
9641     sizeflag ^= DFLAG;
9642 
9643   end_codep = codep;
9644   if (need_modrm)
9645     {
9646       FETCH_DATA (info, codep + 1);
9647       modrm.mod = (*codep >> 6) & 3;
9648       modrm.reg = (*codep >> 3) & 7;
9649       modrm.rm = *codep & 7;
9650     }
9651   else
9652     memset (&modrm, 0, sizeof (modrm));
9653 
9654   need_vex = 0;
9655   memset (&vex, 0, sizeof (vex));
9656 
9657   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9658     {
9659       get_sib (info, sizeflag);
9660       dofloat (sizeflag);
9661     }
9662   else
9663     {
9664       dp = get_valid_dis386 (dp, info);
9665       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9666 	{
9667 	  get_sib (info, sizeflag);
9668 	  for (i = 0; i < MAX_OPERANDS; ++i)
9669 	    {
9670 	      obufp = op_out[i];
9671 	      op_ad = MAX_OPERANDS - 1 - i;
9672 	      if (dp->op[i].rtn)
9673 		(*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9674 	      /* For EVEX instruction after the last operand masking
9675 		 should be printed.  */
9676 	      if (i == 0 && vex.evex)
9677 		{
9678 		  /* Don't print {%k0}.  */
9679 		  if (vex.mask_register_specifier)
9680 		    {
9681 		      oappend ("{");
9682 		      oappend (names_mask[vex.mask_register_specifier]);
9683 		      oappend ("}");
9684 		    }
9685 		  if (vex.zeroing)
9686 		    oappend ("{z}");
9687 
9688 		  /* S/G insns require a mask and don't allow
9689 		     zeroing-masking.  */
9690 		  if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9691 		       || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9692 		      && (vex.mask_register_specifier == 0 || vex.zeroing))
9693 		    oappend ("/(bad)");
9694 		}
9695 	    }
9696 	}
9697     }
9698 
9699   /* Clear instruction information.  */
9700   if (the_info)
9701     {
9702       the_info->insn_info_valid = 0;
9703       the_info->branch_delay_insns = 0;
9704       the_info->data_size = 0;
9705       the_info->insn_type = dis_noninsn;
9706       the_info->target = 0;
9707       the_info->target2 = 0;
9708     }
9709 
9710   /* Reset jump operation indicator.  */
9711   op_is_jump = false;
9712 
9713   {
9714     int jump_detection = 0;
9715 
9716     /* Extract flags.  */
9717     for (i = 0; i < MAX_OPERANDS; ++i)
9718       {
9719 	if ((dp->op[i].rtn == OP_J)
9720 	    || (dp->op[i].rtn == OP_indirE))
9721 	  jump_detection |= 1;
9722 	else if ((dp->op[i].rtn == BND_Fixup)
9723 		 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9724 	  jump_detection |= 2;
9725 	else if ((dp->op[i].bytemode == cond_jump_mode)
9726 		 || (dp->op[i].bytemode == loop_jcxz_mode))
9727 	  jump_detection |= 4;
9728       }
9729 
9730     /* Determine if this is a jump or branch.  */
9731     if ((jump_detection & 0x3) == 0x3)
9732       {
9733 	op_is_jump = true;
9734 	if (jump_detection & 0x4)
9735 	  the_info->insn_type = dis_condbranch;
9736 	else
9737 	  the_info->insn_type =
9738 	    (dp->name && !strncmp(dp->name, "call", 4))
9739 	    ? dis_jsr : dis_branch;
9740       }
9741   }
9742 
9743   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9744      are all 0s in inverted form.  */
9745   if (need_vex && vex.register_specifier != 0)
9746     {
9747       (*info->fprintf_func) (info->stream, "(bad)");
9748       return end_codep - priv.the_buffer;
9749     }
9750 
9751   /* If EVEX.z is set, there must be an actual mask register in use.  */
9752   if (vex.zeroing && vex.mask_register_specifier == 0)
9753     {
9754       (*info->fprintf_func) (info->stream, "(bad)");
9755       return end_codep - priv.the_buffer;
9756     }
9757 
9758   switch (dp->prefix_requirement)
9759     {
9760     case PREFIX_DATA:
9761       /* If only the data prefix is marked as mandatory, its absence renders
9762 	 the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9763       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9764 	{
9765 	  (*info->fprintf_func) (info->stream, "(bad)");
9766 	  return end_codep - priv.the_buffer;
9767 	}
9768       used_prefixes |= PREFIX_DATA;
9769       /* Fall through.  */
9770     case PREFIX_OPCODE:
9771       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9772 	 unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9773 	 used by putop and MMX/SSE operand and may be overridden by the
9774 	 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9775 	 separately.  */
9776       if (((need_vex
9777 	    ? vex.prefix == REPE_PREFIX_OPCODE
9778 	      || vex.prefix == REPNE_PREFIX_OPCODE
9779 	    : (prefixes
9780 	       & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9781 	   && (used_prefixes
9782 	       & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9783 	  || (((need_vex
9784 		? vex.prefix == DATA_PREFIX_OPCODE
9785 		: ((prefixes
9786 		    & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9787 		   == PREFIX_DATA))
9788 	       && (used_prefixes & PREFIX_DATA) == 0))
9789 	  || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9790 	      && !vex.w != !(used_prefixes & PREFIX_DATA)))
9791 	{
9792 	  (*info->fprintf_func) (info->stream, "(bad)");
9793 	  return end_codep - priv.the_buffer;
9794 	}
9795       break;
9796 
9797     case PREFIX_IGNORED:
9798       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9799 	 origins in all_prefixes.  */
9800       used_prefixes &= ~PREFIX_OPCODE;
9801       if (last_data_prefix >= 0)
9802 	all_prefixes[last_data_prefix] = 0x66;
9803       if (last_repz_prefix >= 0)
9804 	all_prefixes[last_repz_prefix] = 0xf3;
9805       if (last_repnz_prefix >= 0)
9806 	all_prefixes[last_repnz_prefix] = 0xf2;
9807       break;
9808     }
9809 
9810   /* Check if the REX prefix is used.  */
9811   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9812     all_prefixes[last_rex_prefix] = 0;
9813 
9814   /* Check if the SEG prefix is used.  */
9815   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9816 		   | PREFIX_FS | PREFIX_GS)) != 0
9817       && (used_prefixes & active_seg_prefix) != 0)
9818     all_prefixes[last_seg_prefix] = 0;
9819 
9820   /* Check if the ADDR prefix is used.  */
9821   if ((prefixes & PREFIX_ADDR) != 0
9822       && (used_prefixes & PREFIX_ADDR) != 0)
9823     all_prefixes[last_addr_prefix] = 0;
9824 
9825   /* Check if the DATA prefix is used.  */
9826   if ((prefixes & PREFIX_DATA) != 0
9827       && (used_prefixes & PREFIX_DATA) != 0
9828       && !need_vex)
9829     all_prefixes[last_data_prefix] = 0;
9830 
9831   /* Print the extra prefixes.  */
9832   prefix_length = 0;
9833   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9834     if (all_prefixes[i])
9835       {
9836 	const char *name;
9837 	name = prefix_name (all_prefixes[i], orig_sizeflag);
9838 	if (name == NULL)
9839 	  abort ();
9840 	prefix_length += strlen (name) + 1;
9841 	(*info->fprintf_func) (info->stream, "%s ", name);
9842       }
9843 
9844   /* Check maximum code length.  */
9845   if ((codep - start_codep) > MAX_CODE_LENGTH)
9846     {
9847       (*info->fprintf_func) (info->stream, "(bad)");
9848       return MAX_CODE_LENGTH;
9849     }
9850 
9851   obufp = mnemonicendp;
9852   for (i = strlen (obuf) + prefix_length; i < 6; i++)
9853     oappend (" ");
9854   oappend (" ");
9855   (*info->fprintf_func) (info->stream, "%s", obuf);
9856 
9857   /* The enter and bound instructions are printed with operands in the same
9858      order as the intel book; everything else is printed in reverse order.  */
9859   if (intel_syntax || two_source_ops)
9860     {
9861       bfd_vma riprel;
9862 
9863       for (i = 0; i < MAX_OPERANDS; ++i)
9864 	op_txt[i] = op_out[i];
9865 
9866       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9867           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9868 	{
9869 	  op_txt[2] = op_out[3];
9870 	  op_txt[3] = op_out[2];
9871 	}
9872 
9873       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9874 	{
9875 	  op_ad = op_index[i];
9876 	  op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9877 	  op_index[MAX_OPERANDS - 1 - i] = op_ad;
9878 	  riprel = op_riprel[i];
9879 	  op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9880 	  op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9881 	}
9882     }
9883   else
9884     {
9885       for (i = 0; i < MAX_OPERANDS; ++i)
9886 	op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9887     }
9888 
9889   needcomma = 0;
9890   for (i = 0; i < MAX_OPERANDS; ++i)
9891     if (*op_txt[i])
9892       {
9893 	if (needcomma)
9894 	  (*info->fprintf_func) (info->stream, ",");
9895 	if (op_index[i] != -1 && !op_riprel[i])
9896 	  {
9897 	    bfd_vma target = (bfd_vma) op_address[op_index[i]];
9898 
9899 	    if (the_info && op_is_jump)
9900 	      {
9901 		the_info->insn_info_valid = 1;
9902 		the_info->branch_delay_insns = 0;
9903 		the_info->data_size = 0;
9904 		the_info->target = target;
9905 		the_info->target2 = 0;
9906 	      }
9907 	    (*info->print_address_func) (target, info);
9908 	  }
9909 	else
9910 	  (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9911 	needcomma = 1;
9912       }
9913 
9914   for (i = 0; i < MAX_OPERANDS; i++)
9915     if (op_index[i] != -1 && op_riprel[i])
9916       {
9917 	(*info->fprintf_func) (info->stream, "        # ");
9918 	(*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
9919 						+ op_address[op_index[i]]), info);
9920 	break;
9921       }
9922   return codep - priv.the_buffer;
9923 }
9924 
9925 static const char *float_mem[] = {
9926   /* d8 */
9927   "fadd{s|}",
9928   "fmul{s|}",
9929   "fcom{s|}",
9930   "fcomp{s|}",
9931   "fsub{s|}",
9932   "fsubr{s|}",
9933   "fdiv{s|}",
9934   "fdivr{s|}",
9935   /* d9 */
9936   "fld{s|}",
9937   "(bad)",
9938   "fst{s|}",
9939   "fstp{s|}",
9940   "fldenv{C|C}",
9941   "fldcw",
9942   "fNstenv{C|C}",
9943   "fNstcw",
9944   /* da */
9945   "fiadd{l|}",
9946   "fimul{l|}",
9947   "ficom{l|}",
9948   "ficomp{l|}",
9949   "fisub{l|}",
9950   "fisubr{l|}",
9951   "fidiv{l|}",
9952   "fidivr{l|}",
9953   /* db */
9954   "fild{l|}",
9955   "fisttp{l|}",
9956   "fist{l|}",
9957   "fistp{l|}",
9958   "(bad)",
9959   "fld{t|}",
9960   "(bad)",
9961   "fstp{t|}",
9962   /* dc */
9963   "fadd{l|}",
9964   "fmul{l|}",
9965   "fcom{l|}",
9966   "fcomp{l|}",
9967   "fsub{l|}",
9968   "fsubr{l|}",
9969   "fdiv{l|}",
9970   "fdivr{l|}",
9971   /* dd */
9972   "fld{l|}",
9973   "fisttp{ll|}",
9974   "fst{l||}",
9975   "fstp{l|}",
9976   "frstor{C|C}",
9977   "(bad)",
9978   "fNsave{C|C}",
9979   "fNstsw",
9980   /* de */
9981   "fiadd{s|}",
9982   "fimul{s|}",
9983   "ficom{s|}",
9984   "ficomp{s|}",
9985   "fisub{s|}",
9986   "fisubr{s|}",
9987   "fidiv{s|}",
9988   "fidivr{s|}",
9989   /* df */
9990   "fild{s|}",
9991   "fisttp{s|}",
9992   "fist{s|}",
9993   "fistp{s|}",
9994   "fbld",
9995   "fild{ll|}",
9996   "fbstp",
9997   "fistp{ll|}",
9998 };
9999 
10000 static const unsigned char float_mem_mode[] = {
10001   /* d8 */
10002   d_mode,
10003   d_mode,
10004   d_mode,
10005   d_mode,
10006   d_mode,
10007   d_mode,
10008   d_mode,
10009   d_mode,
10010   /* d9 */
10011   d_mode,
10012   0,
10013   d_mode,
10014   d_mode,
10015   0,
10016   w_mode,
10017   0,
10018   w_mode,
10019   /* da */
10020   d_mode,
10021   d_mode,
10022   d_mode,
10023   d_mode,
10024   d_mode,
10025   d_mode,
10026   d_mode,
10027   d_mode,
10028   /* db */
10029   d_mode,
10030   d_mode,
10031   d_mode,
10032   d_mode,
10033   0,
10034   t_mode,
10035   0,
10036   t_mode,
10037   /* dc */
10038   q_mode,
10039   q_mode,
10040   q_mode,
10041   q_mode,
10042   q_mode,
10043   q_mode,
10044   q_mode,
10045   q_mode,
10046   /* dd */
10047   q_mode,
10048   q_mode,
10049   q_mode,
10050   q_mode,
10051   0,
10052   0,
10053   0,
10054   w_mode,
10055   /* de */
10056   w_mode,
10057   w_mode,
10058   w_mode,
10059   w_mode,
10060   w_mode,
10061   w_mode,
10062   w_mode,
10063   w_mode,
10064   /* df */
10065   w_mode,
10066   w_mode,
10067   w_mode,
10068   w_mode,
10069   t_mode,
10070   q_mode,
10071   t_mode,
10072   q_mode
10073 };
10074 
10075 #define ST { OP_ST, 0 }
10076 #define STi { OP_STi, 0 }
10077 
10078 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10079 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10080 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10081 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10082 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10083 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10084 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10085 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10086 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10087 
10088 static const struct dis386 float_reg[][8] = {
10089   /* d8 */
10090   {
10091     { "fadd",	{ ST, STi }, 0 },
10092     { "fmul",	{ ST, STi }, 0 },
10093     { "fcom",	{ STi }, 0 },
10094     { "fcomp",	{ STi }, 0 },
10095     { "fsub",	{ ST, STi }, 0 },
10096     { "fsubr",	{ ST, STi }, 0 },
10097     { "fdiv",	{ ST, STi }, 0 },
10098     { "fdivr",	{ ST, STi }, 0 },
10099   },
10100   /* d9 */
10101   {
10102     { "fld",	{ STi }, 0 },
10103     { "fxch",	{ STi }, 0 },
10104     { FGRPd9_2 },
10105     { Bad_Opcode },
10106     { FGRPd9_4 },
10107     { FGRPd9_5 },
10108     { FGRPd9_6 },
10109     { FGRPd9_7 },
10110   },
10111   /* da */
10112   {
10113     { "fcmovb",	{ ST, STi }, 0 },
10114     { "fcmove",	{ ST, STi }, 0 },
10115     { "fcmovbe",{ ST, STi }, 0 },
10116     { "fcmovu",	{ ST, STi }, 0 },
10117     { Bad_Opcode },
10118     { FGRPda_5 },
10119     { Bad_Opcode },
10120     { Bad_Opcode },
10121   },
10122   /* db */
10123   {
10124     { "fcmovnb",{ ST, STi }, 0 },
10125     { "fcmovne",{ ST, STi }, 0 },
10126     { "fcmovnbe",{ ST, STi }, 0 },
10127     { "fcmovnu",{ ST, STi }, 0 },
10128     { FGRPdb_4 },
10129     { "fucomi",	{ ST, STi }, 0 },
10130     { "fcomi",	{ ST, STi }, 0 },
10131     { Bad_Opcode },
10132   },
10133   /* dc */
10134   {
10135     { "fadd",	{ STi, ST }, 0 },
10136     { "fmul",	{ STi, ST }, 0 },
10137     { Bad_Opcode },
10138     { Bad_Opcode },
10139     { "fsub{!M|r}",	{ STi, ST }, 0 },
10140     { "fsub{M|}",	{ STi, ST }, 0 },
10141     { "fdiv{!M|r}",	{ STi, ST }, 0 },
10142     { "fdiv{M|}",	{ STi, ST }, 0 },
10143   },
10144   /* dd */
10145   {
10146     { "ffree",	{ STi }, 0 },
10147     { Bad_Opcode },
10148     { "fst",	{ STi }, 0 },
10149     { "fstp",	{ STi }, 0 },
10150     { "fucom",	{ STi }, 0 },
10151     { "fucomp",	{ STi }, 0 },
10152     { Bad_Opcode },
10153     { Bad_Opcode },
10154   },
10155   /* de */
10156   {
10157     { "faddp",	{ STi, ST }, 0 },
10158     { "fmulp",	{ STi, ST }, 0 },
10159     { Bad_Opcode },
10160     { FGRPde_3 },
10161     { "fsub{!M|r}p",	{ STi, ST }, 0 },
10162     { "fsub{M|}p",	{ STi, ST }, 0 },
10163     { "fdiv{!M|r}p",	{ STi, ST }, 0 },
10164     { "fdiv{M|}p",	{ STi, ST }, 0 },
10165   },
10166   /* df */
10167   {
10168     { "ffreep",	{ STi }, 0 },
10169     { Bad_Opcode },
10170     { Bad_Opcode },
10171     { Bad_Opcode },
10172     { FGRPdf_4 },
10173     { "fucomip", { ST, STi }, 0 },
10174     { "fcomip", { ST, STi }, 0 },
10175     { Bad_Opcode },
10176   },
10177 };
10178 
10179 static char *fgrps[][8] = {
10180   /* Bad opcode 0 */
10181   {
10182     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10183   },
10184 
10185   /* d9_2  1 */
10186   {
10187     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10188   },
10189 
10190   /* d9_4  2 */
10191   {
10192     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10193   },
10194 
10195   /* d9_5  3 */
10196   {
10197     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10198   },
10199 
10200   /* d9_6  4 */
10201   {
10202     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10203   },
10204 
10205   /* d9_7  5 */
10206   {
10207     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10208   },
10209 
10210   /* da_5  6 */
10211   {
10212     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10213   },
10214 
10215   /* db_4  7 */
10216   {
10217     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10218     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10219   },
10220 
10221   /* de_3  8 */
10222   {
10223     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10224   },
10225 
10226   /* df_4  9 */
10227   {
10228     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10229   },
10230 };
10231 
10232 static void
swap_operand(void)10233 swap_operand (void)
10234 {
10235   mnemonicendp[0] = '.';
10236   mnemonicendp[1] = 's';
10237   mnemonicendp += 2;
10238 }
10239 
10240 static void
OP_Skip_MODRM(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10241 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10242 	       int sizeflag ATTRIBUTE_UNUSED)
10243 {
10244   /* Skip mod/rm byte.  */
10245   MODRM_CHECK;
10246   codep++;
10247 }
10248 
10249 static void
dofloat(int sizeflag)10250 dofloat (int sizeflag)
10251 {
10252   const struct dis386 *dp;
10253   unsigned char floatop;
10254 
10255   floatop = codep[-1];
10256 
10257   if (modrm.mod != 3)
10258     {
10259       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10260 
10261       putop (float_mem[fp_indx], sizeflag);
10262       obufp = op_out[0];
10263       op_ad = 2;
10264       OP_E (float_mem_mode[fp_indx], sizeflag);
10265       return;
10266     }
10267   /* Skip mod/rm byte.  */
10268   MODRM_CHECK;
10269   codep++;
10270 
10271   dp = &float_reg[floatop - 0xd8][modrm.reg];
10272   if (dp->name == NULL)
10273     {
10274       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10275 
10276       /* Instruction fnstsw is only one with strange arg.  */
10277       if (floatop == 0xdf && codep[-1] == 0xe0)
10278 	strcpy (op_out[0], names16[0]);
10279     }
10280   else
10281     {
10282       putop (dp->name, sizeflag);
10283 
10284       obufp = op_out[0];
10285       op_ad = 2;
10286       if (dp->op[0].rtn)
10287 	(*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10288 
10289       obufp = op_out[1];
10290       op_ad = 1;
10291       if (dp->op[1].rtn)
10292 	(*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10293     }
10294 }
10295 
10296 /* Like oappend (below), but S is a string starting with '%'.
10297    In Intel syntax, the '%' is elided.  */
10298 static void
oappend_maybe_intel(const char * s)10299 oappend_maybe_intel (const char *s)
10300 {
10301   oappend (s + intel_syntax);
10302 }
10303 
10304 static void
OP_ST(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10305 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10306 {
10307   oappend_maybe_intel ("%st");
10308 }
10309 
10310 static void
OP_STi(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10311 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10312 {
10313   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10314   oappend_maybe_intel (scratchbuf);
10315 }
10316 
10317 /* Capital letters in template are macros.  */
10318 static int
putop(const char * in_template,int sizeflag)10319 putop (const char *in_template, int sizeflag)
10320 {
10321   const char *p;
10322   int alt = 0;
10323   int cond = 1;
10324   unsigned int l = 0, len = 0;
10325   char last[4];
10326 
10327   for (p = in_template; *p; p++)
10328     {
10329       if (len > l)
10330 	{
10331 	  if (l >= sizeof (last) || !ISUPPER (*p))
10332 	    abort ();
10333 	  last[l++] = *p;
10334 	  continue;
10335 	}
10336       switch (*p)
10337 	{
10338 	default:
10339 	  *obufp++ = *p;
10340 	  break;
10341 	case '%':
10342 	  len++;
10343 	  break;
10344 	case '!':
10345 	  cond = 0;
10346 	  break;
10347 	case '{':
10348 	  if (intel_syntax)
10349 	    {
10350 	      while (*++p != '|')
10351 		if (*p == '}' || *p == '\0')
10352 		  abort ();
10353 	      alt = 1;
10354 	    }
10355 	  break;
10356 	case '|':
10357 	  while (*++p != '}')
10358 	    {
10359 	      if (*p == '\0')
10360 		abort ();
10361 	    }
10362 	  break;
10363 	case '}':
10364 	  alt = 0;
10365 	  break;
10366 	case 'A':
10367 	  if (intel_syntax)
10368 	    break;
10369 	  if ((need_modrm && modrm.mod != 3)
10370 	      || (sizeflag & SUFFIX_ALWAYS))
10371 	    *obufp++ = 'b';
10372 	  break;
10373 	case 'B':
10374 	  if (l == 0)
10375 	    {
10376 	    case_B:
10377 	      if (intel_syntax)
10378 		break;
10379 	      if (sizeflag & SUFFIX_ALWAYS)
10380 		*obufp++ = 'b';
10381 	    }
10382 	  else if (l == 1 && last[0] == 'L')
10383 	    {
10384 	      if (address_mode == mode_64bit
10385 		  && !(prefixes & PREFIX_ADDR))
10386 		{
10387 		  *obufp++ = 'a';
10388 		  *obufp++ = 'b';
10389 		  *obufp++ = 's';
10390 		}
10391 
10392 	      goto case_B;
10393 	    }
10394 	  else
10395 	    abort ();
10396 	  break;
10397 	case 'C':
10398 	  if (intel_syntax && !alt)
10399 	    break;
10400 	  if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10401 	    {
10402 	      if (sizeflag & DFLAG)
10403 		*obufp++ = intel_syntax ? 'd' : 'l';
10404 	      else
10405 		*obufp++ = intel_syntax ? 'w' : 's';
10406 	      used_prefixes |= (prefixes & PREFIX_DATA);
10407 	    }
10408 	  break;
10409 	case 'D':
10410 	  if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10411 	    break;
10412 	  USED_REX (REX_W);
10413 	  if (modrm.mod == 3)
10414 	    {
10415 	      if (rex & REX_W)
10416 		*obufp++ = 'q';
10417 	      else
10418 		{
10419 		  if (sizeflag & DFLAG)
10420 		    *obufp++ = intel_syntax ? 'd' : 'l';
10421 		  else
10422 		    *obufp++ = 'w';
10423 		  used_prefixes |= (prefixes & PREFIX_DATA);
10424 		}
10425 	    }
10426 	  else
10427 	    *obufp++ = 'w';
10428 	  break;
10429 	case 'E':		/* For jcxz/jecxz */
10430 	  if (address_mode == mode_64bit)
10431 	    {
10432 	      if (sizeflag & AFLAG)
10433 		*obufp++ = 'r';
10434 	      else
10435 		*obufp++ = 'e';
10436 	    }
10437 	  else
10438 	    if (sizeflag & AFLAG)
10439 	      *obufp++ = 'e';
10440 	  used_prefixes |= (prefixes & PREFIX_ADDR);
10441 	  break;
10442 	case 'F':
10443 	  if (intel_syntax)
10444 	    break;
10445 	  if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10446 	    {
10447 	      if (sizeflag & AFLAG)
10448 		*obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10449 	      else
10450 		*obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10451 	      used_prefixes |= (prefixes & PREFIX_ADDR);
10452 	    }
10453 	  break;
10454 	case 'G':
10455 	  if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10456 	    break;
10457 	  if ((rex & REX_W) || (sizeflag & DFLAG))
10458 	    *obufp++ = 'l';
10459 	  else
10460 	    *obufp++ = 'w';
10461 	  if (!(rex & REX_W))
10462 	    used_prefixes |= (prefixes & PREFIX_DATA);
10463 	  break;
10464 	case 'H':
10465 	  if (intel_syntax)
10466 	    break;
10467 	  if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10468 	      || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10469 	    {
10470 	      used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10471 	      *obufp++ = ',';
10472 	      *obufp++ = 'p';
10473 
10474 	      /* Set active_seg_prefix even if not set in 64-bit mode
10475 		 because here it is a valid branch hint. */
10476 	      if (prefixes & PREFIX_DS)
10477 		{
10478 		  active_seg_prefix = PREFIX_DS;
10479 		  *obufp++ = 't';
10480 		}
10481 	      else
10482 		{
10483 		  active_seg_prefix = PREFIX_CS;
10484 		  *obufp++ = 'n';
10485 		}
10486 	    }
10487 	  break;
10488 	case 'K':
10489 	  USED_REX (REX_W);
10490 	  if (rex & REX_W)
10491 	    *obufp++ = 'q';
10492 	  else
10493 	    *obufp++ = 'd';
10494 	  break;
10495 	case 'L':
10496 	  abort ();
10497 	case 'M':
10498 	  if (intel_mnemonic != cond)
10499 	    *obufp++ = 'r';
10500 	  break;
10501 	case 'N':
10502 	  if ((prefixes & PREFIX_FWAIT) == 0)
10503 	    *obufp++ = 'n';
10504 	  else
10505 	    used_prefixes |= PREFIX_FWAIT;
10506 	  break;
10507 	case 'O':
10508 	  USED_REX (REX_W);
10509 	  if (rex & REX_W)
10510 	    *obufp++ = 'o';
10511 	  else if (intel_syntax && (sizeflag & DFLAG))
10512 	    *obufp++ = 'q';
10513 	  else
10514 	    *obufp++ = 'd';
10515 	  if (!(rex & REX_W))
10516 	    used_prefixes |= (prefixes & PREFIX_DATA);
10517 	  break;
10518 	case '@':
10519 	  if (address_mode == mode_64bit
10520 	      && (isa64 == intel64 || (rex & REX_W)
10521 		  || !(prefixes & PREFIX_DATA)))
10522 	    {
10523 	      if (sizeflag & SUFFIX_ALWAYS)
10524 		*obufp++ = 'q';
10525 	      break;
10526 	    }
10527 	  /* Fall through.  */
10528 	case 'P':
10529 	  if (l == 0)
10530 	    {
10531 	      if ((modrm.mod == 3 || !cond)
10532 		  && !(sizeflag & SUFFIX_ALWAYS))
10533 		break;
10534 	  /* Fall through.  */
10535 	case 'T':
10536 	      if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10537 		  || ((sizeflag & SUFFIX_ALWAYS)
10538 		      && address_mode != mode_64bit))
10539 		{
10540 		  *obufp++ = (sizeflag & DFLAG) ?
10541 			     intel_syntax ? 'd' : 'l' : 'w';
10542 		  used_prefixes |= (prefixes & PREFIX_DATA);
10543 		}
10544 	      else if (sizeflag & SUFFIX_ALWAYS)
10545 		*obufp++ = 'q';
10546 	    }
10547 	  else if (l == 1 && last[0] == 'L')
10548 	    {
10549 	      if ((prefixes & PREFIX_DATA)
10550 		  || (rex & REX_W)
10551 		  || (sizeflag & SUFFIX_ALWAYS))
10552 		{
10553 		  USED_REX (REX_W);
10554 		  if (rex & REX_W)
10555 		    *obufp++ = 'q';
10556 		  else
10557 		    {
10558 		      if (sizeflag & DFLAG)
10559 			*obufp++ = intel_syntax ? 'd' : 'l';
10560 		      else
10561 			*obufp++ = 'w';
10562 		      used_prefixes |= (prefixes & PREFIX_DATA);
10563 		    }
10564 		}
10565 	    }
10566 	  else
10567 	    abort ();
10568 	  break;
10569 	case 'Q':
10570 	  if (l == 0)
10571 	    {
10572 	      if (intel_syntax && !alt)
10573 		break;
10574 	      USED_REX (REX_W);
10575 	      if ((need_modrm && modrm.mod != 3)
10576 		  || (sizeflag & SUFFIX_ALWAYS))
10577 		{
10578 		  if (rex & REX_W)
10579 		    *obufp++ = 'q';
10580 		  else
10581 		    {
10582 		      if (sizeflag & DFLAG)
10583 			*obufp++ = intel_syntax ? 'd' : 'l';
10584 		      else
10585 			*obufp++ = 'w';
10586 		      used_prefixes |= (prefixes & PREFIX_DATA);
10587 		    }
10588 		}
10589 	    }
10590 	  else if (l == 1 && last[0] == 'D')
10591 	    *obufp++ = vex.w ? 'q' : 'd';
10592 	  else if (l == 1 && last[0] == 'L')
10593 	    {
10594 	      if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10595 		       : address_mode != mode_64bit)
10596 		break;
10597 	      if ((rex & REX_W))
10598 		{
10599 		  USED_REX (REX_W);
10600 		  *obufp++ = 'q';
10601 		}
10602 	      else if((address_mode == mode_64bit && cond)
10603 		      || (sizeflag & SUFFIX_ALWAYS))
10604 		*obufp++ = intel_syntax? 'd' : 'l';
10605 	    }
10606 	  else
10607 	    abort ();
10608 	  break;
10609 	case 'R':
10610 	  USED_REX (REX_W);
10611 	  if (rex & REX_W)
10612 	    *obufp++ = 'q';
10613 	  else if (sizeflag & DFLAG)
10614 	    {
10615 	      if (intel_syntax)
10616 		  *obufp++ = 'd';
10617 	      else
10618 		  *obufp++ = 'l';
10619 	    }
10620 	  else
10621 	    *obufp++ = 'w';
10622 	  if (intel_syntax && !p[1]
10623 	      && ((rex & REX_W) || (sizeflag & DFLAG)))
10624 	    *obufp++ = 'e';
10625 	  if (!(rex & REX_W))
10626 	    used_prefixes |= (prefixes & PREFIX_DATA);
10627 	  break;
10628 	case 'S':
10629 	  if (l == 0)
10630 	    {
10631 	    case_S:
10632 	      if (intel_syntax)
10633 		break;
10634 	      if (sizeflag & SUFFIX_ALWAYS)
10635 		{
10636 		  if (rex & REX_W)
10637 		    *obufp++ = 'q';
10638 		  else
10639 		    {
10640 		      if (sizeflag & DFLAG)
10641 			*obufp++ = 'l';
10642 		      else
10643 			*obufp++ = 'w';
10644 		      used_prefixes |= (prefixes & PREFIX_DATA);
10645 		    }
10646 		}
10647 	    }
10648 	  else if (l == 1 && last[0] == 'L')
10649 	    {
10650 	      if (address_mode == mode_64bit
10651 		  && !(prefixes & PREFIX_ADDR))
10652 		{
10653 		  *obufp++ = 'a';
10654 		  *obufp++ = 'b';
10655 		  *obufp++ = 's';
10656 		}
10657 
10658 	      goto case_S;
10659 	    }
10660 	  else
10661 	    abort ();
10662 	  break;
10663 	case 'V':
10664 	  if (l == 0)
10665 	    abort ();
10666 	  else if (l == 1
10667 		   && (last[0] == 'L' || last[0] == 'X'))
10668 	    {
10669 	      if (last[0] == 'X')
10670 		{
10671 		  *obufp++ = '{';
10672 		  *obufp++ = 'v';
10673 		  *obufp++ = 'e';
10674 		  *obufp++ = 'x';
10675 		  *obufp++ = '}';
10676 		}
10677 	      else if (rex & REX_W)
10678 		{
10679 		  *obufp++ = 'a';
10680 		  *obufp++ = 'b';
10681 		  *obufp++ = 's';
10682 		}
10683 	    }
10684 	  else
10685 	    abort ();
10686 	  goto case_S;
10687 	case 'W':
10688 	  if (l == 0)
10689 	    {
10690 	      /* operand size flag for cwtl, cbtw */
10691 	      USED_REX (REX_W);
10692 	      if (rex & REX_W)
10693 		{
10694 		  if (intel_syntax)
10695 		    *obufp++ = 'd';
10696 		  else
10697 		    *obufp++ = 'l';
10698 		}
10699 	      else if (sizeflag & DFLAG)
10700 		*obufp++ = 'w';
10701 	      else
10702 		*obufp++ = 'b';
10703 	      if (!(rex & REX_W))
10704 		used_prefixes |= (prefixes & PREFIX_DATA);
10705 	    }
10706 	  else if (l == 1)
10707 	    {
10708 	      if (!need_vex)
10709 		abort ();
10710 	      if (last[0] == 'X')
10711 		*obufp++ = vex.w ? 'd': 's';
10712 	      else if (last[0] == 'B')
10713 		*obufp++ = vex.w ? 'w': 'b';
10714 	      else
10715 		abort ();
10716 	    }
10717 	  else
10718 	    abort ();
10719 	  break;
10720 	case 'X':
10721 	  if (l != 0)
10722 	    abort ();
10723 	  if (need_vex
10724 	      ? vex.prefix == DATA_PREFIX_OPCODE
10725 	      : prefixes & PREFIX_DATA)
10726 	    {
10727 	      *obufp++ = 'd';
10728 	      used_prefixes |= PREFIX_DATA;
10729 	    }
10730 	  else
10731 	    *obufp++ = 's';
10732 	  break;
10733 	case 'Y':
10734 	  if (l == 1 && last[0] == 'X')
10735 	    {
10736 	      if (!need_vex)
10737 		abort ();
10738 	      if (intel_syntax
10739 		  || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10740 		break;
10741 	      switch (vex.length)
10742 		{
10743 		case 128:
10744 		  *obufp++ = 'x';
10745 		  break;
10746 		case 256:
10747 		  *obufp++ = 'y';
10748 		  break;
10749 		case 512:
10750 		  if (!vex.evex)
10751 		default:
10752 		    abort ();
10753 		}
10754 	    }
10755 	  else
10756 	    abort ();
10757 	  break;
10758 	case 'Z':
10759 	  if (l == 0)
10760 	    {
10761 	      /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10762 	      modrm.mod = 3;
10763 	      if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10764 		*obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10765 	    }
10766 	  else if (l == 1 && last[0] == 'X')
10767 	    {
10768 	      if (!vex.evex)
10769 		abort ();
10770 	      if (intel_syntax
10771 		  || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10772 		break;
10773 	      switch (vex.length)
10774 		{
10775 		case 128:
10776 		  *obufp++ = 'x';
10777 		  break;
10778 		case 256:
10779 		  *obufp++ = 'y';
10780 		  break;
10781 		case 512:
10782 		  *obufp++ = 'z';
10783 		  break;
10784 		default:
10785 		  abort ();
10786 		}
10787 	    }
10788 	  else
10789 	    abort ();
10790 	  break;
10791 	case '^':
10792 	  if (intel_syntax)
10793 	    break;
10794 	  if (isa64 == intel64 && (rex & REX_W))
10795 	    {
10796 	      USED_REX (REX_W);
10797 	      *obufp++ = 'q';
10798 	      break;
10799 	    }
10800 	  if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10801 	    {
10802 	      if (sizeflag & DFLAG)
10803 		*obufp++ = 'l';
10804 	      else
10805 		*obufp++ = 'w';
10806 	      used_prefixes |= (prefixes & PREFIX_DATA);
10807 	    }
10808 	  break;
10809 	}
10810 
10811       if (len == l)
10812 	len = l = 0;
10813     }
10814   *obufp = 0;
10815   mnemonicendp = obufp;
10816   return 0;
10817 }
10818 
10819 static void
oappend(const char * s)10820 oappend (const char *s)
10821 {
10822   obufp = stpcpy (obufp, s);
10823 }
10824 
10825 static void
append_seg(void)10826 append_seg (void)
10827 {
10828   /* Only print the active segment register.  */
10829   if (!active_seg_prefix)
10830     return;
10831 
10832   used_prefixes |= active_seg_prefix;
10833   switch (active_seg_prefix)
10834     {
10835     case PREFIX_CS:
10836       oappend_maybe_intel ("%cs:");
10837       break;
10838     case PREFIX_DS:
10839       oappend_maybe_intel ("%ds:");
10840       break;
10841     case PREFIX_SS:
10842       oappend_maybe_intel ("%ss:");
10843       break;
10844     case PREFIX_ES:
10845       oappend_maybe_intel ("%es:");
10846       break;
10847     case PREFIX_FS:
10848       oappend_maybe_intel ("%fs:");
10849       break;
10850     case PREFIX_GS:
10851       oappend_maybe_intel ("%gs:");
10852       break;
10853     default:
10854       break;
10855     }
10856 }
10857 
10858 static void
OP_indirE(int bytemode,int sizeflag)10859 OP_indirE (int bytemode, int sizeflag)
10860 {
10861   if (!intel_syntax)
10862     oappend ("*");
10863   OP_E (bytemode, sizeflag);
10864 }
10865 
10866 static void
print_operand_value(char * buf,int hex,bfd_vma disp)10867 print_operand_value (char *buf, int hex, bfd_vma disp)
10868 {
10869   if (address_mode == mode_64bit)
10870     {
10871       if (hex)
10872 	{
10873 	  char tmp[30];
10874 	  int i;
10875 	  buf[0] = '0';
10876 	  buf[1] = 'x';
10877 	  sprintf_vma (tmp, disp);
10878 	  for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10879 	  strcpy (buf + 2, tmp + i);
10880 	}
10881       else
10882 	{
10883 	  bfd_signed_vma v = disp;
10884 	  char tmp[30];
10885 	  int i;
10886 	  if (v < 0)
10887 	    {
10888 	      *(buf++) = '-';
10889 	      v = -disp;
10890 	      /* Check for possible overflow on 0x8000000000000000.  */
10891 	      if (v < 0)
10892 		{
10893 		  strcpy (buf, "9223372036854775808");
10894 		  return;
10895 		}
10896 	    }
10897 	  if (!v)
10898 	    {
10899 	      strcpy (buf, "0");
10900 	      return;
10901 	    }
10902 
10903 	  i = 0;
10904 	  tmp[29] = 0;
10905 	  while (v)
10906 	    {
10907 	      tmp[28 - i] = (v % 10) + '0';
10908 	      v /= 10;
10909 	      i++;
10910 	    }
10911 	  strcpy (buf, tmp + 29 - i);
10912 	}
10913     }
10914   else
10915     {
10916       if (hex)
10917 	sprintf (buf, "0x%x", (unsigned int) disp);
10918       else
10919 	sprintf (buf, "%d", (int) disp);
10920     }
10921 }
10922 
10923 /* Put DISP in BUF as signed hex number.  */
10924 
10925 static void
print_displacement(char * buf,bfd_vma disp)10926 print_displacement (char *buf, bfd_vma disp)
10927 {
10928   bfd_signed_vma val = disp;
10929   char tmp[30];
10930   int i, j = 0;
10931 
10932   if (val < 0)
10933     {
10934       buf[j++] = '-';
10935       val = -disp;
10936 
10937       /* Check for possible overflow.  */
10938       if (val < 0)
10939 	{
10940 	  switch (address_mode)
10941 	    {
10942 	    case mode_64bit:
10943 	      strcpy (buf + j, "0x8000000000000000");
10944 	      break;
10945 	    case mode_32bit:
10946 	      strcpy (buf + j, "0x80000000");
10947 	      break;
10948 	    case mode_16bit:
10949 	      strcpy (buf + j, "0x8000");
10950 	      break;
10951 	    }
10952 	  return;
10953 	}
10954     }
10955 
10956   buf[j++] = '0';
10957   buf[j++] = 'x';
10958 
10959   sprintf_vma (tmp, (bfd_vma) val);
10960   for (i = 0; tmp[i] == '0'; i++)
10961     continue;
10962   if (tmp[i] == '\0')
10963     i--;
10964   strcpy (buf + j, tmp + i);
10965 }
10966 
10967 static void
intel_operand_size(int bytemode,int sizeflag)10968 intel_operand_size (int bytemode, int sizeflag)
10969 {
10970   if (vex.b
10971       && (bytemode == x_mode
10972 	  || bytemode == evex_half_bcst_xmmq_mode))
10973     {
10974       if (vex.w)
10975 	oappend ("QWORD PTR ");
10976       else
10977 	oappend ("DWORD PTR ");
10978       return;
10979     }
10980   switch (bytemode)
10981     {
10982     case b_mode:
10983     case b_swap_mode:
10984     case dqb_mode:
10985     case db_mode:
10986       oappend ("BYTE PTR ");
10987       break;
10988     case w_mode:
10989     case dw_mode:
10990     case dqw_mode:
10991       oappend ("WORD PTR ");
10992       break;
10993     case indir_v_mode:
10994       if (address_mode == mode_64bit && isa64 == intel64)
10995 	{
10996 	  oappend ("QWORD PTR ");
10997 	  break;
10998 	}
10999       /* Fall through.  */
11000     case stack_v_mode:
11001       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11002 	{
11003 	  oappend ("QWORD PTR ");
11004 	  break;
11005 	}
11006       /* Fall through.  */
11007     case v_mode:
11008     case v_swap_mode:
11009     case dq_mode:
11010       USED_REX (REX_W);
11011       if (rex & REX_W)
11012 	oappend ("QWORD PTR ");
11013       else if (bytemode == dq_mode)
11014 	oappend ("DWORD PTR ");
11015       else
11016 	{
11017 	  if (sizeflag & DFLAG)
11018 	    oappend ("DWORD PTR ");
11019 	  else
11020 	    oappend ("WORD PTR ");
11021 	  used_prefixes |= (prefixes & PREFIX_DATA);
11022 	}
11023       break;
11024     case z_mode:
11025       if ((rex & REX_W) || (sizeflag & DFLAG))
11026 	*obufp++ = 'D';
11027       oappend ("WORD PTR ");
11028       if (!(rex & REX_W))
11029 	used_prefixes |= (prefixes & PREFIX_DATA);
11030       break;
11031     case a_mode:
11032       if (sizeflag & DFLAG)
11033 	oappend ("QWORD PTR ");
11034       else
11035 	oappend ("DWORD PTR ");
11036       used_prefixes |= (prefixes & PREFIX_DATA);
11037       break;
11038     case movsxd_mode:
11039       if (!(sizeflag & DFLAG) && isa64 == intel64)
11040 	oappend ("WORD PTR ");
11041       else
11042 	oappend ("DWORD PTR ");
11043       used_prefixes |= (prefixes & PREFIX_DATA);
11044       break;
11045     case d_mode:
11046     case d_swap_mode:
11047     case dqd_mode:
11048       oappend ("DWORD PTR ");
11049       break;
11050     case q_mode:
11051     case q_swap_mode:
11052       oappend ("QWORD PTR ");
11053       break;
11054     case m_mode:
11055       if (address_mode == mode_64bit)
11056 	oappend ("QWORD PTR ");
11057       else
11058 	oappend ("DWORD PTR ");
11059       break;
11060     case f_mode:
11061       if (sizeflag & DFLAG)
11062 	oappend ("FWORD PTR ");
11063       else
11064 	oappend ("DWORD PTR ");
11065       used_prefixes |= (prefixes & PREFIX_DATA);
11066       break;
11067     case t_mode:
11068       oappend ("TBYTE PTR ");
11069       break;
11070     case x_mode:
11071     case x_swap_mode:
11072     case evex_x_gscat_mode:
11073     case evex_x_nobcst_mode:
11074     case bw_unit_mode:
11075       if (need_vex)
11076 	{
11077 	  switch (vex.length)
11078 	    {
11079 	    case 128:
11080 	      oappend ("XMMWORD PTR ");
11081 	      break;
11082 	    case 256:
11083 	      oappend ("YMMWORD PTR ");
11084 	      break;
11085 	    case 512:
11086 	      oappend ("ZMMWORD PTR ");
11087 	      break;
11088 	    default:
11089 	      abort ();
11090 	    }
11091 	}
11092       else
11093 	oappend ("XMMWORD PTR ");
11094       break;
11095     case xmm_mode:
11096       oappend ("XMMWORD PTR ");
11097       break;
11098     case ymm_mode:
11099       oappend ("YMMWORD PTR ");
11100       break;
11101     case xmmq_mode:
11102     case evex_half_bcst_xmmq_mode:
11103       if (!need_vex)
11104 	abort ();
11105 
11106       switch (vex.length)
11107 	{
11108 	case 128:
11109 	  oappend ("QWORD PTR ");
11110 	  break;
11111 	case 256:
11112 	  oappend ("XMMWORD PTR ");
11113 	  break;
11114 	case 512:
11115 	  oappend ("YMMWORD PTR ");
11116 	  break;
11117 	default:
11118 	  abort ();
11119 	}
11120       break;
11121     case xmm_mb_mode:
11122       if (!need_vex)
11123 	abort ();
11124 
11125       switch (vex.length)
11126 	{
11127 	case 128:
11128 	case 256:
11129 	case 512:
11130 	  oappend ("BYTE PTR ");
11131 	  break;
11132 	default:
11133 	  abort ();
11134 	}
11135       break;
11136     case xmm_mw_mode:
11137       if (!need_vex)
11138 	abort ();
11139 
11140       switch (vex.length)
11141 	{
11142 	case 128:
11143 	case 256:
11144 	case 512:
11145 	  oappend ("WORD PTR ");
11146 	  break;
11147 	default:
11148 	  abort ();
11149 	}
11150       break;
11151     case xmm_md_mode:
11152       if (!need_vex)
11153 	abort ();
11154 
11155       switch (vex.length)
11156 	{
11157 	case 128:
11158 	case 256:
11159 	case 512:
11160 	  oappend ("DWORD PTR ");
11161 	  break;
11162 	default:
11163 	  abort ();
11164 	}
11165       break;
11166     case xmm_mq_mode:
11167       if (!need_vex)
11168 	abort ();
11169 
11170       switch (vex.length)
11171 	{
11172 	case 128:
11173 	case 256:
11174 	case 512:
11175 	  oappend ("QWORD PTR ");
11176 	  break;
11177 	default:
11178 	  abort ();
11179 	}
11180       break;
11181     case xmmdw_mode:
11182       if (!need_vex)
11183 	abort ();
11184 
11185       switch (vex.length)
11186 	{
11187 	case 128:
11188 	  oappend ("WORD PTR ");
11189 	  break;
11190 	case 256:
11191 	  oappend ("DWORD PTR ");
11192 	  break;
11193 	case 512:
11194 	  oappend ("QWORD PTR ");
11195 	  break;
11196 	default:
11197 	  abort ();
11198 	}
11199       break;
11200     case xmmqd_mode:
11201       if (!need_vex)
11202 	abort ();
11203 
11204       switch (vex.length)
11205 	{
11206 	case 128:
11207 	  oappend ("DWORD PTR ");
11208 	  break;
11209 	case 256:
11210 	  oappend ("QWORD PTR ");
11211 	  break;
11212 	case 512:
11213 	  oappend ("XMMWORD PTR ");
11214 	  break;
11215 	default:
11216 	  abort ();
11217 	}
11218       break;
11219     case ymmq_mode:
11220       if (!need_vex)
11221 	abort ();
11222 
11223       switch (vex.length)
11224 	{
11225 	case 128:
11226 	  oappend ("QWORD PTR ");
11227 	  break;
11228 	case 256:
11229 	  oappend ("YMMWORD PTR ");
11230 	  break;
11231 	case 512:
11232 	  oappend ("ZMMWORD PTR ");
11233 	  break;
11234 	default:
11235 	  abort ();
11236 	}
11237       break;
11238     case ymmxmm_mode:
11239       if (!need_vex)
11240 	abort ();
11241 
11242       switch (vex.length)
11243 	{
11244 	case 128:
11245 	case 256:
11246 	  oappend ("XMMWORD PTR ");
11247 	  break;
11248 	default:
11249 	  abort ();
11250 	}
11251       break;
11252     case o_mode:
11253       oappend ("OWORD PTR ");
11254       break;
11255     case vex_scalar_w_dq_mode:
11256       if (!need_vex)
11257 	abort ();
11258 
11259       if (vex.w)
11260 	oappend ("QWORD PTR ");
11261       else
11262 	oappend ("DWORD PTR ");
11263       break;
11264     case vex_vsib_d_w_dq_mode:
11265     case vex_vsib_q_w_dq_mode:
11266       if (!need_vex)
11267 	abort ();
11268 
11269       if (vex.w)
11270 	oappend ("QWORD PTR ");
11271       else
11272 	oappend ("DWORD PTR ");
11273       break;
11274     case mask_bd_mode:
11275       if (!need_vex || vex.length != 128)
11276 	abort ();
11277       if (vex.w)
11278 	oappend ("DWORD PTR ");
11279       else
11280 	oappend ("BYTE PTR ");
11281       break;
11282     case mask_mode:
11283       if (!need_vex)
11284 	abort ();
11285       if (vex.w)
11286 	oappend ("QWORD PTR ");
11287       else
11288 	oappend ("WORD PTR ");
11289       break;
11290     case v_bnd_mode:
11291     case v_bndmk_mode:
11292     default:
11293       break;
11294     }
11295 }
11296 
11297 static void
OP_E_register(int bytemode,int sizeflag)11298 OP_E_register (int bytemode, int sizeflag)
11299 {
11300   int reg = modrm.rm;
11301   const char **names;
11302 
11303   USED_REX (REX_B);
11304   if ((rex & REX_B))
11305     reg += 8;
11306 
11307   if ((sizeflag & SUFFIX_ALWAYS)
11308       && (bytemode == b_swap_mode
11309 	  || bytemode == bnd_swap_mode
11310 	  || bytemode == v_swap_mode))
11311     swap_operand ();
11312 
11313   switch (bytemode)
11314     {
11315     case b_mode:
11316     case b_swap_mode:
11317       if (reg & 4)
11318 	USED_REX (0);
11319       if (rex)
11320 	names = names8rex;
11321       else
11322 	names = names8;
11323       break;
11324     case w_mode:
11325       names = names16;
11326       break;
11327     case d_mode:
11328     case dw_mode:
11329     case db_mode:
11330       names = names32;
11331       break;
11332     case q_mode:
11333       names = names64;
11334       break;
11335     case m_mode:
11336     case v_bnd_mode:
11337       names = address_mode == mode_64bit ? names64 : names32;
11338       break;
11339     case bnd_mode:
11340     case bnd_swap_mode:
11341       if (reg > 0x3)
11342 	{
11343 	  oappend ("(bad)");
11344 	  return;
11345 	}
11346       names = names_bnd;
11347       break;
11348     case indir_v_mode:
11349       if (address_mode == mode_64bit && isa64 == intel64)
11350 	{
11351 	  names = names64;
11352 	  break;
11353 	}
11354       /* Fall through.  */
11355     case stack_v_mode:
11356       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11357 	{
11358 	  names = names64;
11359 	  break;
11360 	}
11361       bytemode = v_mode;
11362       /* Fall through.  */
11363     case v_mode:
11364     case v_swap_mode:
11365     case dq_mode:
11366     case dqb_mode:
11367     case dqd_mode:
11368     case dqw_mode:
11369       USED_REX (REX_W);
11370       if (rex & REX_W)
11371 	names = names64;
11372       else if (bytemode != v_mode && bytemode != v_swap_mode)
11373 	names = names32;
11374       else
11375 	{
11376 	  if (sizeflag & DFLAG)
11377 	    names = names32;
11378 	  else
11379 	    names = names16;
11380 	  used_prefixes |= (prefixes & PREFIX_DATA);
11381 	}
11382       break;
11383     case movsxd_mode:
11384       if (!(sizeflag & DFLAG) && isa64 == intel64)
11385 	names = names16;
11386       else
11387 	names = names32;
11388       used_prefixes |= (prefixes & PREFIX_DATA);
11389       break;
11390     case va_mode:
11391       names = (address_mode == mode_64bit
11392 	       ? names64 : names32);
11393       if (!(prefixes & PREFIX_ADDR))
11394 	names = (address_mode == mode_16bit
11395 		     ? names16 : names);
11396       else
11397 	{
11398 	  /* Remove "addr16/addr32".  */
11399 	  all_prefixes[last_addr_prefix] = 0;
11400 	  names = (address_mode != mode_32bit
11401 		       ? names32 : names16);
11402 	  used_prefixes |= PREFIX_ADDR;
11403 	}
11404       break;
11405     case mask_bd_mode:
11406     case mask_mode:
11407       if (reg > 0x7)
11408 	{
11409 	  oappend ("(bad)");
11410 	  return;
11411 	}
11412       names = names_mask;
11413       break;
11414     case 0:
11415       return;
11416     default:
11417       oappend (INTERNAL_DISASSEMBLER_ERROR);
11418       return;
11419     }
11420   oappend (names[reg]);
11421 }
11422 
11423 static void
OP_E_memory(int bytemode,int sizeflag)11424 OP_E_memory (int bytemode, int sizeflag)
11425 {
11426   bfd_vma disp = 0;
11427   int add = (rex & REX_B) ? 8 : 0;
11428   int riprel = 0;
11429   int shift;
11430 
11431   if (vex.evex)
11432     {
11433       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
11434       if (vex.b
11435 	  && bytemode != x_mode
11436 	  && bytemode != evex_half_bcst_xmmq_mode)
11437 	{
11438 	  BadOp ();
11439 	  return;
11440 	}
11441       switch (bytemode)
11442 	{
11443 	case dqw_mode:
11444 	case dw_mode:
11445 	case xmm_mw_mode:
11446 	  shift = 1;
11447 	  break;
11448 	case dqb_mode:
11449 	case db_mode:
11450 	case xmm_mb_mode:
11451 	  shift = 0;
11452 	  break;
11453 	case dq_mode:
11454 	  if (address_mode != mode_64bit)
11455 	    {
11456 	case dqd_mode:
11457 	case xmm_md_mode:
11458 	case d_mode:
11459 	case d_swap_mode:
11460 	      shift = 2;
11461 	      break;
11462 	    }
11463 	    /* fall through */
11464 	case vex_scalar_w_dq_mode:
11465 	case vex_vsib_d_w_dq_mode:
11466 	case vex_vsib_q_w_dq_mode:
11467 	case evex_x_gscat_mode:
11468 	  shift = vex.w ? 3 : 2;
11469 	  break;
11470 	case x_mode:
11471 	case evex_half_bcst_xmmq_mode:
11472 	  if (vex.b)
11473 	    {
11474 	      shift = vex.w ? 3 : 2;
11475 	      break;
11476 	    }
11477 	  /* Fall through.  */
11478 	case xmmqd_mode:
11479 	case xmmdw_mode:
11480 	case xmmq_mode:
11481 	case ymmq_mode:
11482 	case evex_x_nobcst_mode:
11483 	case x_swap_mode:
11484 	  switch (vex.length)
11485 	    {
11486 	    case 128:
11487 	      shift = 4;
11488 	      break;
11489 	    case 256:
11490 	      shift = 5;
11491 	      break;
11492 	    case 512:
11493 	      shift = 6;
11494 	      break;
11495 	    default:
11496 	      abort ();
11497 	    }
11498 	  /* Make necessary corrections to shift for modes that need it.  */
11499 	  if (bytemode == xmmq_mode
11500 	      || bytemode == evex_half_bcst_xmmq_mode
11501 	      || (bytemode == ymmq_mode && vex.length == 128))
11502 	    shift -= 1;
11503 	  else if (bytemode == xmmqd_mode)
11504 	    shift -= 2;
11505 	  else if (bytemode == xmmdw_mode)
11506 	    shift -= 3;
11507 	  break;
11508 	case ymm_mode:
11509 	  shift = 5;
11510 	  break;
11511 	case xmm_mode:
11512 	  shift = 4;
11513 	  break;
11514 	case xmm_mq_mode:
11515 	case q_mode:
11516 	case q_swap_mode:
11517 	  shift = 3;
11518 	  break;
11519 	case bw_unit_mode:
11520 	  shift = vex.w ? 1 : 0;
11521 	  break;
11522 	default:
11523 	  abort ();
11524 	}
11525     }
11526   else
11527     shift = 0;
11528 
11529   USED_REX (REX_B);
11530   if (intel_syntax)
11531     intel_operand_size (bytemode, sizeflag);
11532   append_seg ();
11533 
11534   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11535     {
11536       /* 32/64 bit address mode */
11537       int havedisp;
11538       int havesib;
11539       int havebase;
11540       int haveindex;
11541       int needindex;
11542       int needaddr32;
11543       int base, rbase;
11544       int vindex = 0;
11545       int scale = 0;
11546       int addr32flag = !((sizeflag & AFLAG)
11547 			 || bytemode == v_bnd_mode
11548 			 || bytemode == v_bndmk_mode
11549 			 || bytemode == bnd_mode
11550 			 || bytemode == bnd_swap_mode);
11551       bool check_gather = false;
11552       const char **indexes64 = names64;
11553       const char **indexes32 = names32;
11554 
11555       havesib = 0;
11556       havebase = 1;
11557       haveindex = 0;
11558       base = modrm.rm;
11559 
11560       if (base == 4)
11561 	{
11562 	  havesib = 1;
11563 	  vindex = sib.index;
11564 	  USED_REX (REX_X);
11565 	  if (rex & REX_X)
11566 	    vindex += 8;
11567 	  switch (bytemode)
11568 	    {
11569 	    case vex_vsib_d_w_dq_mode:
11570 	    case vex_vsib_q_w_dq_mode:
11571 	      if (!need_vex)
11572 		abort ();
11573 	      if (vex.evex)
11574 		{
11575 		  if (!vex.v)
11576 		    vindex += 16;
11577 		  check_gather = obufp == op_out[1];
11578 		}
11579 
11580 	      haveindex = 1;
11581 	      switch (vex.length)
11582 		{
11583 		case 128:
11584 		  indexes64 = indexes32 = names_xmm;
11585 		  break;
11586 		case 256:
11587 		  if (!vex.w
11588 		      || bytemode == vex_vsib_q_w_dq_mode)
11589 		    indexes64 = indexes32 = names_ymm;
11590 		  else
11591 		    indexes64 = indexes32 = names_xmm;
11592 		  break;
11593 		case 512:
11594 		  if (!vex.w
11595 		      || bytemode == vex_vsib_q_w_dq_mode)
11596 		    indexes64 = indexes32 = names_zmm;
11597 		  else
11598 		    indexes64 = indexes32 = names_ymm;
11599 		  break;
11600 		default:
11601 		  abort ();
11602 		}
11603 	      break;
11604 	    default:
11605 	      haveindex = vindex != 4;
11606 	      break;
11607 	    }
11608 	  scale = sib.scale;
11609 	  base = sib.base;
11610 	  codep++;
11611 	}
11612       else
11613 	{
11614 	  /* Check for mandatory SIB.  */
11615 	  if (bytemode == vex_vsib_d_w_dq_mode
11616 	      || bytemode == vex_vsib_q_w_dq_mode
11617 	      || bytemode == vex_sibmem_mode)
11618 	    {
11619 	      oappend ("(bad)");
11620 	      return;
11621 	    }
11622 	}
11623       rbase = base + add;
11624 
11625       switch (modrm.mod)
11626 	{
11627 	case 0:
11628 	  if (base == 5)
11629 	    {
11630 	      havebase = 0;
11631 	      if (address_mode == mode_64bit && !havesib)
11632 		riprel = 1;
11633 	      disp = get32s ();
11634 	      if (riprel && bytemode == v_bndmk_mode)
11635 		{
11636 		  oappend ("(bad)");
11637 		  return;
11638 		}
11639 	    }
11640 	  break;
11641 	case 1:
11642 	  FETCH_DATA (the_info, codep + 1);
11643 	  disp = *codep++;
11644 	  if ((disp & 0x80) != 0)
11645 	    disp -= 0x100;
11646 	  if (vex.evex && shift > 0)
11647 	    disp <<= shift;
11648 	  break;
11649 	case 2:
11650 	  disp = get32s ();
11651 	  break;
11652 	}
11653 
11654       needindex = 0;
11655       needaddr32 = 0;
11656       if (havesib
11657 	  && !havebase
11658 	  && !haveindex
11659 	  && address_mode != mode_16bit)
11660 	{
11661 	  if (address_mode == mode_64bit)
11662 	    {
11663 	      if (addr32flag)
11664 		{
11665 		  /* Without base nor index registers, zero-extend the
11666 		     lower 32-bit displacement to 64 bits.  */
11667 		  disp = (unsigned int) disp;
11668 		  needindex = 1;
11669 		}
11670 	      needaddr32 = 1;
11671 	    }
11672 	  else
11673 	    {
11674 	      /* In 32-bit mode, we need index register to tell [offset]
11675 		 from [eiz*1 + offset].  */
11676 	      needindex = 1;
11677 	    }
11678 	}
11679 
11680       havedisp = (havebase
11681 		  || needindex
11682 		  || (havesib && (haveindex || scale != 0)));
11683 
11684       if (!intel_syntax)
11685 	if (modrm.mod != 0 || base == 5)
11686 	  {
11687 	    if (havedisp || riprel)
11688 	      print_displacement (scratchbuf, disp);
11689 	    else
11690 	      print_operand_value (scratchbuf, 1, disp);
11691 	    oappend (scratchbuf);
11692 	    if (riprel)
11693 	      {
11694 		set_op (disp, 1);
11695 		oappend (!addr32flag ? "(%rip)" : "(%eip)");
11696 	      }
11697 	  }
11698 
11699       if ((havebase || haveindex || needindex || needaddr32 || riprel)
11700 	  && (address_mode != mode_64bit
11701 	      || ((bytemode != v_bnd_mode)
11702 		  && (bytemode != v_bndmk_mode)
11703 		  && (bytemode != bnd_mode)
11704 		  && (bytemode != bnd_swap_mode))))
11705 	used_prefixes |= PREFIX_ADDR;
11706 
11707       if (havedisp || (intel_syntax && riprel))
11708 	{
11709 	  *obufp++ = open_char;
11710 	  if (intel_syntax && riprel)
11711 	    {
11712 	      set_op (disp, 1);
11713 	      oappend (!addr32flag ? "rip" : "eip");
11714 	    }
11715 	  *obufp = '\0';
11716 	  if (havebase)
11717 	    oappend (address_mode == mode_64bit && !addr32flag
11718 		     ? names64[rbase] : names32[rbase]);
11719 	  if (havesib)
11720 	    {
11721 	      /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11722 		 print index to tell base + index from base.  */
11723 	      if (scale != 0
11724 		  || needindex
11725 		  || haveindex
11726 		  || (havebase && base != ESP_REG_NUM))
11727 		{
11728 		  if (!intel_syntax || havebase)
11729 		    {
11730 		      *obufp++ = separator_char;
11731 		      *obufp = '\0';
11732 		    }
11733 		  if (haveindex)
11734 		    oappend (address_mode == mode_64bit && !addr32flag
11735 			     ? indexes64[vindex] : indexes32[vindex]);
11736 		  else
11737 		    oappend (address_mode == mode_64bit && !addr32flag
11738 			     ? index64 : index32);
11739 
11740 		  *obufp++ = scale_char;
11741 		  *obufp = '\0';
11742 		  sprintf (scratchbuf, "%d", 1 << scale);
11743 		  oappend (scratchbuf);
11744 		}
11745 	    }
11746 	  if (intel_syntax
11747 	      && (disp || modrm.mod != 0 || base == 5))
11748 	    {
11749 	      if (!havedisp || (bfd_signed_vma) disp >= 0)
11750 		{
11751 		  *obufp++ = '+';
11752 		  *obufp = '\0';
11753 		}
11754 	      else if (modrm.mod != 1 && disp != -disp)
11755 		{
11756 		  *obufp++ = '-';
11757 		  *obufp = '\0';
11758 		  disp = -disp;
11759 		}
11760 
11761 	      if (havedisp)
11762 		print_displacement (scratchbuf, disp);
11763 	      else
11764 		print_operand_value (scratchbuf, 1, disp);
11765 	      oappend (scratchbuf);
11766 	    }
11767 
11768 	  *obufp++ = close_char;
11769 	  *obufp = '\0';
11770 
11771 	  if (check_gather)
11772 	    {
11773 	      /* Both XMM/YMM/ZMM registers must be distinct.  */
11774 	      int modrm_reg = modrm.reg;
11775 
11776 	      if (rex & REX_R)
11777 	        modrm_reg += 8;
11778 	      if (!vex.r)
11779 	        modrm_reg += 16;
11780 	      if (vindex == modrm_reg)
11781 		oappend ("/(bad)");
11782 	    }
11783 	}
11784       else if (intel_syntax)
11785 	{
11786 	  if (modrm.mod != 0 || base == 5)
11787 	    {
11788 	      if (!active_seg_prefix)
11789 		{
11790 		  oappend (names_seg[ds_reg - es_reg]);
11791 		  oappend (":");
11792 		}
11793 	      print_operand_value (scratchbuf, 1, disp);
11794 	      oappend (scratchbuf);
11795 	    }
11796 	}
11797     }
11798   else if (bytemode == v_bnd_mode
11799 	   || bytemode == v_bndmk_mode
11800 	   || bytemode == bnd_mode
11801 	   || bytemode == bnd_swap_mode
11802 	   || bytemode == vex_vsib_d_w_dq_mode
11803 	   || bytemode == vex_vsib_q_w_dq_mode)
11804     {
11805       oappend ("(bad)");
11806       return;
11807     }
11808   else
11809     {
11810       /* 16 bit address mode */
11811       used_prefixes |= prefixes & PREFIX_ADDR;
11812       switch (modrm.mod)
11813 	{
11814 	case 0:
11815 	  if (modrm.rm == 6)
11816 	    {
11817 	      disp = get16 ();
11818 	      if ((disp & 0x8000) != 0)
11819 		disp -= 0x10000;
11820 	    }
11821 	  break;
11822 	case 1:
11823 	  FETCH_DATA (the_info, codep + 1);
11824 	  disp = *codep++;
11825 	  if ((disp & 0x80) != 0)
11826 	    disp -= 0x100;
11827 	  if (vex.evex && shift > 0)
11828 	    disp <<= shift;
11829 	  break;
11830 	case 2:
11831 	  disp = get16 ();
11832 	  if ((disp & 0x8000) != 0)
11833 	    disp -= 0x10000;
11834 	  break;
11835 	}
11836 
11837       if (!intel_syntax)
11838 	if (modrm.mod != 0 || modrm.rm == 6)
11839 	  {
11840 	    print_displacement (scratchbuf, disp);
11841 	    oappend (scratchbuf);
11842 	  }
11843 
11844       if (modrm.mod != 0 || modrm.rm != 6)
11845 	{
11846 	  *obufp++ = open_char;
11847 	  *obufp = '\0';
11848 	  oappend (index16[modrm.rm]);
11849 	  if (intel_syntax
11850 	      && (disp || modrm.mod != 0 || modrm.rm == 6))
11851 	    {
11852 	      if ((bfd_signed_vma) disp >= 0)
11853 		{
11854 		  *obufp++ = '+';
11855 		  *obufp = '\0';
11856 		}
11857 	      else if (modrm.mod != 1)
11858 		{
11859 		  *obufp++ = '-';
11860 		  *obufp = '\0';
11861 		  disp = -disp;
11862 		}
11863 
11864 	      print_displacement (scratchbuf, disp);
11865 	      oappend (scratchbuf);
11866 	    }
11867 
11868 	  *obufp++ = close_char;
11869 	  *obufp = '\0';
11870 	}
11871       else if (intel_syntax)
11872 	{
11873 	  if (!active_seg_prefix)
11874 	    {
11875 	      oappend (names_seg[ds_reg - es_reg]);
11876 	      oappend (":");
11877 	    }
11878 	  print_operand_value (scratchbuf, 1, disp & 0xffff);
11879 	  oappend (scratchbuf);
11880 	}
11881     }
11882   if (vex.b
11883       && (bytemode == x_mode
11884 	  || bytemode == evex_half_bcst_xmmq_mode))
11885     {
11886       if (vex.w
11887 	  || bytemode == evex_half_bcst_xmmq_mode)
11888 	{
11889 	  switch (vex.length)
11890 	    {
11891 	    case 128:
11892 	      oappend ("{1to2}");
11893 	      break;
11894 	    case 256:
11895 	      oappend ("{1to4}");
11896 	      break;
11897 	    case 512:
11898 	      oappend ("{1to8}");
11899 	      break;
11900 	    default:
11901 	      abort ();
11902 	    }
11903 	}
11904       else
11905 	{
11906 	  switch (vex.length)
11907 	    {
11908 	    case 128:
11909 	      oappend ("{1to4}");
11910 	      break;
11911 	    case 256:
11912 	      oappend ("{1to8}");
11913 	      break;
11914 	    case 512:
11915 	      oappend ("{1to16}");
11916 	      break;
11917 	    default:
11918 	      abort ();
11919 	    }
11920 	}
11921     }
11922 }
11923 
11924 static void
OP_E(int bytemode,int sizeflag)11925 OP_E (int bytemode, int sizeflag)
11926 {
11927   /* Skip mod/rm byte.  */
11928   MODRM_CHECK;
11929   codep++;
11930 
11931   if (modrm.mod == 3)
11932     OP_E_register (bytemode, sizeflag);
11933   else
11934     OP_E_memory (bytemode, sizeflag);
11935 }
11936 
11937 static void
OP_G(int bytemode,int sizeflag)11938 OP_G (int bytemode, int sizeflag)
11939 {
11940   int add = 0;
11941   const char **names;
11942   USED_REX (REX_R);
11943   if (rex & REX_R)
11944     add += 8;
11945   switch (bytemode)
11946     {
11947     case b_mode:
11948       if (modrm.reg & 4)
11949 	USED_REX (0);
11950       if (rex)
11951 	oappend (names8rex[modrm.reg + add]);
11952       else
11953 	oappend (names8[modrm.reg + add]);
11954       break;
11955     case w_mode:
11956       oappend (names16[modrm.reg + add]);
11957       break;
11958     case d_mode:
11959     case db_mode:
11960     case dw_mode:
11961       oappend (names32[modrm.reg + add]);
11962       break;
11963     case q_mode:
11964       oappend (names64[modrm.reg + add]);
11965       break;
11966     case bnd_mode:
11967       if (modrm.reg > 0x3)
11968 	{
11969 	  oappend ("(bad)");
11970 	  return;
11971 	}
11972       oappend (names_bnd[modrm.reg]);
11973       break;
11974     case v_mode:
11975     case dq_mode:
11976     case dqb_mode:
11977     case dqd_mode:
11978     case dqw_mode:
11979     case movsxd_mode:
11980       USED_REX (REX_W);
11981       if (rex & REX_W)
11982 	oappend (names64[modrm.reg + add]);
11983       else if (bytemode != v_mode && bytemode != movsxd_mode)
11984 	oappend (names32[modrm.reg + add]);
11985       else
11986 	{
11987 	  if (sizeflag & DFLAG)
11988 	    oappend (names32[modrm.reg + add]);
11989 	  else
11990 	    oappend (names16[modrm.reg + add]);
11991 	  used_prefixes |= (prefixes & PREFIX_DATA);
11992 	}
11993       break;
11994     case va_mode:
11995       names = (address_mode == mode_64bit
11996 	       ? names64 : names32);
11997       if (!(prefixes & PREFIX_ADDR))
11998 	{
11999 	  if (address_mode == mode_16bit)
12000 	    names = names16;
12001 	}
12002       else
12003 	{
12004 	  /* Remove "addr16/addr32".  */
12005 	  all_prefixes[last_addr_prefix] = 0;
12006 	  names = (address_mode != mode_32bit
12007 		       ? names32 : names16);
12008 	  used_prefixes |= PREFIX_ADDR;
12009 	}
12010       oappend (names[modrm.reg + add]);
12011       break;
12012     case m_mode:
12013       if (address_mode == mode_64bit)
12014 	oappend (names64[modrm.reg + add]);
12015       else
12016 	oappend (names32[modrm.reg + add]);
12017       break;
12018     case mask_bd_mode:
12019     case mask_mode:
12020       if ((modrm.reg + add) > 0x7)
12021 	{
12022 	  oappend ("(bad)");
12023 	  return;
12024 	}
12025       oappend (names_mask[modrm.reg + add]);
12026       break;
12027     default:
12028       oappend (INTERNAL_DISASSEMBLER_ERROR);
12029       break;
12030     }
12031 }
12032 
12033 static bfd_vma
get64(void)12034 get64 (void)
12035 {
12036   bfd_vma x;
12037 #ifdef BFD64
12038   unsigned int a;
12039   unsigned int b;
12040 
12041   FETCH_DATA (the_info, codep + 8);
12042   a = *codep++ & 0xff;
12043   a |= (*codep++ & 0xff) << 8;
12044   a |= (*codep++ & 0xff) << 16;
12045   a |= (*codep++ & 0xffu) << 24;
12046   b = *codep++ & 0xff;
12047   b |= (*codep++ & 0xff) << 8;
12048   b |= (*codep++ & 0xff) << 16;
12049   b |= (*codep++ & 0xffu) << 24;
12050   x = a + ((bfd_vma) b << 32);
12051 #else
12052   abort ();
12053   x = 0;
12054 #endif
12055   return x;
12056 }
12057 
12058 static bfd_signed_vma
get32(void)12059 get32 (void)
12060 {
12061   bfd_vma x = 0;
12062 
12063   FETCH_DATA (the_info, codep + 4);
12064   x = *codep++ & (bfd_vma) 0xff;
12065   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12066   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12067   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12068   return x;
12069 }
12070 
12071 static bfd_signed_vma
get32s(void)12072 get32s (void)
12073 {
12074   bfd_vma x = 0;
12075 
12076   FETCH_DATA (the_info, codep + 4);
12077   x = *codep++ & (bfd_vma) 0xff;
12078   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12079   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12080   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12081 
12082   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12083 
12084   return x;
12085 }
12086 
12087 static int
get16(void)12088 get16 (void)
12089 {
12090   int x = 0;
12091 
12092   FETCH_DATA (the_info, codep + 2);
12093   x = *codep++ & 0xff;
12094   x |= (*codep++ & 0xff) << 8;
12095   return x;
12096 }
12097 
12098 static void
set_op(bfd_vma op,int riprel)12099 set_op (bfd_vma op, int riprel)
12100 {
12101   op_index[op_ad] = op_ad;
12102   if (address_mode == mode_64bit)
12103     {
12104       op_address[op_ad] = op;
12105       op_riprel[op_ad] = riprel;
12106     }
12107   else
12108     {
12109       /* Mask to get a 32-bit address.  */
12110       op_address[op_ad] = op & 0xffffffff;
12111       op_riprel[op_ad] = riprel & 0xffffffff;
12112     }
12113 }
12114 
12115 static void
OP_REG(int code,int sizeflag)12116 OP_REG (int code, int sizeflag)
12117 {
12118   const char *s;
12119   int add;
12120 
12121   switch (code)
12122     {
12123     case es_reg: case ss_reg: case cs_reg:
12124     case ds_reg: case fs_reg: case gs_reg:
12125       oappend (names_seg[code - es_reg]);
12126       return;
12127     }
12128 
12129   USED_REX (REX_B);
12130   if (rex & REX_B)
12131     add = 8;
12132   else
12133     add = 0;
12134 
12135   switch (code)
12136     {
12137     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12138     case sp_reg: case bp_reg: case si_reg: case di_reg:
12139       s = names16[code - ax_reg + add];
12140       break;
12141     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12142       USED_REX (0);
12143       /* Fall through.  */
12144     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12145       if (rex)
12146 	s = names8rex[code - al_reg + add];
12147       else
12148 	s = names8[code - al_reg];
12149       break;
12150     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12151     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12152       if (address_mode == mode_64bit
12153 	  && ((sizeflag & DFLAG) || (rex & REX_W)))
12154 	{
12155 	  s = names64[code - rAX_reg + add];
12156 	  break;
12157 	}
12158       code += eAX_reg - rAX_reg;
12159       /* Fall through.  */
12160     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12161     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12162       USED_REX (REX_W);
12163       if (rex & REX_W)
12164 	s = names64[code - eAX_reg + add];
12165       else
12166 	{
12167 	  if (sizeflag & DFLAG)
12168 	    s = names32[code - eAX_reg + add];
12169 	  else
12170 	    s = names16[code - eAX_reg + add];
12171 	  used_prefixes |= (prefixes & PREFIX_DATA);
12172 	}
12173       break;
12174     default:
12175       s = INTERNAL_DISASSEMBLER_ERROR;
12176       break;
12177     }
12178   oappend (s);
12179 }
12180 
12181 static void
OP_IMREG(int code,int sizeflag)12182 OP_IMREG (int code, int sizeflag)
12183 {
12184   const char *s;
12185 
12186   switch (code)
12187     {
12188     case indir_dx_reg:
12189       if (intel_syntax)
12190 	s = "dx";
12191       else
12192 	s = "(%dx)";
12193       break;
12194     case al_reg: case cl_reg:
12195       s = names8[code - al_reg];
12196       break;
12197     case eAX_reg:
12198       USED_REX (REX_W);
12199       if (rex & REX_W)
12200 	{
12201 	  s = *names64;
12202 	  break;
12203 	}
12204       /* Fall through.  */
12205     case z_mode_ax_reg:
12206       if ((rex & REX_W) || (sizeflag & DFLAG))
12207 	s = *names32;
12208       else
12209 	s = *names16;
12210       if (!(rex & REX_W))
12211 	used_prefixes |= (prefixes & PREFIX_DATA);
12212       break;
12213     default:
12214       s = INTERNAL_DISASSEMBLER_ERROR;
12215       break;
12216     }
12217   oappend (s);
12218 }
12219 
12220 static void
OP_I(int bytemode,int sizeflag)12221 OP_I (int bytemode, int sizeflag)
12222 {
12223   bfd_signed_vma op;
12224   bfd_signed_vma mask = -1;
12225 
12226   switch (bytemode)
12227     {
12228     case b_mode:
12229       FETCH_DATA (the_info, codep + 1);
12230       op = *codep++;
12231       mask = 0xff;
12232       break;
12233     case v_mode:
12234       USED_REX (REX_W);
12235       if (rex & REX_W)
12236 	op = get32s ();
12237       else
12238 	{
12239 	  if (sizeflag & DFLAG)
12240 	    {
12241 	      op = get32 ();
12242 	      mask = 0xffffffff;
12243 	    }
12244 	  else
12245 	    {
12246 	      op = get16 ();
12247 	      mask = 0xfffff;
12248 	    }
12249 	  used_prefixes |= (prefixes & PREFIX_DATA);
12250 	}
12251       break;
12252     case d_mode:
12253       mask = 0xffffffff;
12254       op = get32 ();
12255       break;
12256     case w_mode:
12257       mask = 0xfffff;
12258       op = get16 ();
12259       break;
12260     case const_1_mode:
12261       if (intel_syntax)
12262 	oappend ("1");
12263       return;
12264     default:
12265       oappend (INTERNAL_DISASSEMBLER_ERROR);
12266       return;
12267     }
12268 
12269   op &= mask;
12270   scratchbuf[0] = '$';
12271   print_operand_value (scratchbuf + 1, 1, op);
12272   oappend_maybe_intel (scratchbuf);
12273   scratchbuf[0] = '\0';
12274 }
12275 
12276 static void
OP_I64(int bytemode,int sizeflag)12277 OP_I64 (int bytemode, int sizeflag)
12278 {
12279   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12280     {
12281       OP_I (bytemode, sizeflag);
12282       return;
12283     }
12284 
12285   USED_REX (REX_W);
12286 
12287   scratchbuf[0] = '$';
12288   print_operand_value (scratchbuf + 1, 1, get64 ());
12289   oappend_maybe_intel (scratchbuf);
12290   scratchbuf[0] = '\0';
12291 }
12292 
12293 static void
OP_sI(int bytemode,int sizeflag)12294 OP_sI (int bytemode, int sizeflag)
12295 {
12296   bfd_signed_vma op;
12297 
12298   switch (bytemode)
12299     {
12300     case b_mode:
12301     case b_T_mode:
12302       FETCH_DATA (the_info, codep + 1);
12303       op = *codep++;
12304       if ((op & 0x80) != 0)
12305 	op -= 0x100;
12306       if (bytemode == b_T_mode)
12307 	{
12308 	  if (address_mode != mode_64bit
12309 	      || !((sizeflag & DFLAG) || (rex & REX_W)))
12310 	    {
12311 	      /* The operand-size prefix is overridden by a REX prefix.  */
12312 	      if ((sizeflag & DFLAG) || (rex & REX_W))
12313 		op &= 0xffffffff;
12314 	      else
12315 		op &= 0xffff;
12316 	  }
12317 	}
12318       else
12319 	{
12320 	  if (!(rex & REX_W))
12321 	    {
12322 	      if (sizeflag & DFLAG)
12323 		op &= 0xffffffff;
12324 	      else
12325 		op &= 0xffff;
12326 	    }
12327 	}
12328       break;
12329     case v_mode:
12330       /* The operand-size prefix is overridden by a REX prefix.  */
12331       if ((sizeflag & DFLAG) || (rex & REX_W))
12332 	op = get32s ();
12333       else
12334 	op = get16 ();
12335       break;
12336     default:
12337       oappend (INTERNAL_DISASSEMBLER_ERROR);
12338       return;
12339     }
12340 
12341   scratchbuf[0] = '$';
12342   print_operand_value (scratchbuf + 1, 1, op);
12343   oappend_maybe_intel (scratchbuf);
12344 }
12345 
12346 static void
OP_J(int bytemode,int sizeflag)12347 OP_J (int bytemode, int sizeflag)
12348 {
12349   bfd_vma disp;
12350   bfd_vma mask = -1;
12351   bfd_vma segment = 0;
12352 
12353   switch (bytemode)
12354     {
12355     case b_mode:
12356       FETCH_DATA (the_info, codep + 1);
12357       disp = *codep++;
12358       if ((disp & 0x80) != 0)
12359 	disp -= 0x100;
12360       break;
12361     case v_mode:
12362     case dqw_mode:
12363       if ((sizeflag & DFLAG)
12364 	  || (address_mode == mode_64bit
12365 	      && ((isa64 == intel64 && bytemode != dqw_mode)
12366 		  || (rex & REX_W))))
12367 	disp = get32s ();
12368       else
12369 	{
12370 	  disp = get16 ();
12371 	  if ((disp & 0x8000) != 0)
12372 	    disp -= 0x10000;
12373 	  /* In 16bit mode, address is wrapped around at 64k within
12374 	     the same segment.  Otherwise, a data16 prefix on a jump
12375 	     instruction means that the pc is masked to 16 bits after
12376 	     the displacement is added!  */
12377 	  mask = 0xffff;
12378 	  if ((prefixes & PREFIX_DATA) == 0)
12379 	    segment = ((start_pc + (codep - start_codep))
12380 		       & ~((bfd_vma) 0xffff));
12381 	}
12382       if (address_mode != mode_64bit
12383 	  || (isa64 != intel64 && !(rex & REX_W)))
12384 	used_prefixes |= (prefixes & PREFIX_DATA);
12385       break;
12386     default:
12387       oappend (INTERNAL_DISASSEMBLER_ERROR);
12388       return;
12389     }
12390   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12391   set_op (disp, 0);
12392   print_operand_value (scratchbuf, 1, disp);
12393   oappend (scratchbuf);
12394 }
12395 
12396 static void
OP_SEG(int bytemode,int sizeflag)12397 OP_SEG (int bytemode, int sizeflag)
12398 {
12399   if (bytemode == w_mode)
12400     oappend (names_seg[modrm.reg]);
12401   else
12402     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12403 }
12404 
12405 static void
OP_DIR(int dummy ATTRIBUTE_UNUSED,int sizeflag)12406 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12407 {
12408   int seg, offset;
12409 
12410   if (sizeflag & DFLAG)
12411     {
12412       offset = get32 ();
12413       seg = get16 ();
12414     }
12415   else
12416     {
12417       offset = get16 ();
12418       seg = get16 ();
12419     }
12420   used_prefixes |= (prefixes & PREFIX_DATA);
12421   if (intel_syntax)
12422     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12423   else
12424     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12425   oappend (scratchbuf);
12426 }
12427 
12428 static void
OP_OFF(int bytemode,int sizeflag)12429 OP_OFF (int bytemode, int sizeflag)
12430 {
12431   bfd_vma off;
12432 
12433   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12434     intel_operand_size (bytemode, sizeflag);
12435   append_seg ();
12436 
12437   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12438     off = get32 ();
12439   else
12440     off = get16 ();
12441 
12442   if (intel_syntax)
12443     {
12444       if (!active_seg_prefix)
12445 	{
12446 	  oappend (names_seg[ds_reg - es_reg]);
12447 	  oappend (":");
12448 	}
12449     }
12450   print_operand_value (scratchbuf, 1, off);
12451   oappend (scratchbuf);
12452 }
12453 
12454 static void
OP_OFF64(int bytemode,int sizeflag)12455 OP_OFF64 (int bytemode, int sizeflag)
12456 {
12457   bfd_vma off;
12458 
12459   if (address_mode != mode_64bit
12460       || (prefixes & PREFIX_ADDR))
12461     {
12462       OP_OFF (bytemode, sizeflag);
12463       return;
12464     }
12465 
12466   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12467     intel_operand_size (bytemode, sizeflag);
12468   append_seg ();
12469 
12470   off = get64 ();
12471 
12472   if (intel_syntax)
12473     {
12474       if (!active_seg_prefix)
12475 	{
12476 	  oappend (names_seg[ds_reg - es_reg]);
12477 	  oappend (":");
12478 	}
12479     }
12480   print_operand_value (scratchbuf, 1, off);
12481   oappend (scratchbuf);
12482 }
12483 
12484 static void
ptr_reg(int code,int sizeflag)12485 ptr_reg (int code, int sizeflag)
12486 {
12487   const char *s;
12488 
12489   *obufp++ = open_char;
12490   used_prefixes |= (prefixes & PREFIX_ADDR);
12491   if (address_mode == mode_64bit)
12492     {
12493       if (!(sizeflag & AFLAG))
12494 	s = names32[code - eAX_reg];
12495       else
12496 	s = names64[code - eAX_reg];
12497     }
12498   else if (sizeflag & AFLAG)
12499     s = names32[code - eAX_reg];
12500   else
12501     s = names16[code - eAX_reg];
12502   oappend (s);
12503   *obufp++ = close_char;
12504   *obufp = 0;
12505 }
12506 
12507 static void
OP_ESreg(int code,int sizeflag)12508 OP_ESreg (int code, int sizeflag)
12509 {
12510   if (intel_syntax)
12511     {
12512       switch (codep[-1])
12513 	{
12514 	case 0x6d:	/* insw/insl */
12515 	  intel_operand_size (z_mode, sizeflag);
12516 	  break;
12517 	case 0xa5:	/* movsw/movsl/movsq */
12518 	case 0xa7:	/* cmpsw/cmpsl/cmpsq */
12519 	case 0xab:	/* stosw/stosl */
12520 	case 0xaf:	/* scasw/scasl */
12521 	  intel_operand_size (v_mode, sizeflag);
12522 	  break;
12523 	default:
12524 	  intel_operand_size (b_mode, sizeflag);
12525 	}
12526     }
12527   oappend_maybe_intel ("%es:");
12528   ptr_reg (code, sizeflag);
12529 }
12530 
12531 static void
OP_DSreg(int code,int sizeflag)12532 OP_DSreg (int code, int sizeflag)
12533 {
12534   if (intel_syntax)
12535     {
12536       switch (codep[-1])
12537 	{
12538 	case 0x6f:	/* outsw/outsl */
12539 	  intel_operand_size (z_mode, sizeflag);
12540 	  break;
12541 	case 0xa5:	/* movsw/movsl/movsq */
12542 	case 0xa7:	/* cmpsw/cmpsl/cmpsq */
12543 	case 0xad:	/* lodsw/lodsl/lodsq */
12544 	  intel_operand_size (v_mode, sizeflag);
12545 	  break;
12546 	default:
12547 	  intel_operand_size (b_mode, sizeflag);
12548 	}
12549     }
12550   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12551      default segment register DS is printed.  */
12552   if (!active_seg_prefix)
12553     active_seg_prefix = PREFIX_DS;
12554   append_seg ();
12555   ptr_reg (code, sizeflag);
12556 }
12557 
12558 static void
OP_C(int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12559 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12560 {
12561   int add;
12562   if (rex & REX_R)
12563     {
12564       USED_REX (REX_R);
12565       add = 8;
12566     }
12567   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12568     {
12569       all_prefixes[last_lock_prefix] = 0;
12570       used_prefixes |= PREFIX_LOCK;
12571       add = 8;
12572     }
12573   else
12574     add = 0;
12575   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12576   oappend_maybe_intel (scratchbuf);
12577 }
12578 
12579 static void
OP_D(int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12580 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12581 {
12582   int add;
12583   USED_REX (REX_R);
12584   if (rex & REX_R)
12585     add = 8;
12586   else
12587     add = 0;
12588   if (intel_syntax)
12589     sprintf (scratchbuf, "dr%d", modrm.reg + add);
12590   else
12591     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12592   oappend (scratchbuf);
12593 }
12594 
12595 static void
OP_T(int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12596 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12597 {
12598   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12599   oappend_maybe_intel (scratchbuf);
12600 }
12601 
12602 static void
OP_MMX(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12603 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12604 {
12605   int reg = modrm.reg;
12606   const char **names;
12607 
12608   used_prefixes |= (prefixes & PREFIX_DATA);
12609   if (prefixes & PREFIX_DATA)
12610     {
12611       names = names_xmm;
12612       USED_REX (REX_R);
12613       if (rex & REX_R)
12614 	reg += 8;
12615     }
12616   else
12617     names = names_mm;
12618   oappend (names[reg]);
12619 }
12620 
12621 static void
OP_XMM(int bytemode,int sizeflag ATTRIBUTE_UNUSED)12622 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12623 {
12624   int reg = modrm.reg;
12625   const char **names;
12626 
12627   USED_REX (REX_R);
12628   if (rex & REX_R)
12629     reg += 8;
12630   if (vex.evex)
12631     {
12632       if (!vex.r)
12633 	reg += 16;
12634     }
12635 
12636   if (bytemode == xmmq_mode
12637       || bytemode == evex_half_bcst_xmmq_mode)
12638     {
12639       switch (vex.length)
12640 	{
12641 	case 128:
12642 	case 256:
12643 	  names = names_xmm;
12644 	  break;
12645 	case 512:
12646 	  names = names_ymm;
12647 	  break;
12648 	default:
12649 	  abort ();
12650 	}
12651     }
12652   else if (bytemode == ymm_mode)
12653     names = names_ymm;
12654   else if (bytemode == tmm_mode)
12655     {
12656       modrm.reg = reg;
12657       if (reg >= 8)
12658 	{
12659 	  oappend ("(bad)");
12660 	  return;
12661 	}
12662       names = names_tmm;
12663     }
12664   else if (need_vex
12665 	   && bytemode != xmm_mode
12666 	   && bytemode != scalar_mode)
12667     {
12668       switch (vex.length)
12669 	{
12670 	case 128:
12671 	  names = names_xmm;
12672 	  break;
12673 	case 256:
12674 	  if (vex.w
12675 	      || bytemode != vex_vsib_q_w_dq_mode)
12676 	    names = names_ymm;
12677 	  else
12678 	    names = names_xmm;
12679 	  break;
12680 	case 512:
12681 	  if (vex.w
12682 	      || bytemode != vex_vsib_q_w_dq_mode)
12683 	    names = names_zmm;
12684 	  else
12685 	    names = names_ymm;
12686 	  break;
12687 	default:
12688 	  abort ();
12689 	}
12690     }
12691   else
12692     names = names_xmm;
12693   oappend (names[reg]);
12694 }
12695 
12696 static void
OP_EM(int bytemode,int sizeflag)12697 OP_EM (int bytemode, int sizeflag)
12698 {
12699   int reg;
12700   const char **names;
12701 
12702   if (modrm.mod != 3)
12703     {
12704       if (intel_syntax
12705 	  && (bytemode == v_mode || bytemode == v_swap_mode))
12706 	{
12707 	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12708 	  used_prefixes |= (prefixes & PREFIX_DATA);
12709 	}
12710       OP_E (bytemode, sizeflag);
12711       return;
12712     }
12713 
12714   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12715     swap_operand ();
12716 
12717   /* Skip mod/rm byte.  */
12718   MODRM_CHECK;
12719   codep++;
12720   used_prefixes |= (prefixes & PREFIX_DATA);
12721   reg = modrm.rm;
12722   if (prefixes & PREFIX_DATA)
12723     {
12724       names = names_xmm;
12725       USED_REX (REX_B);
12726       if (rex & REX_B)
12727 	reg += 8;
12728     }
12729   else
12730     names = names_mm;
12731   oappend (names[reg]);
12732 }
12733 
12734 /* cvt* are the only instructions in sse2 which have
12735    both SSE and MMX operands and also have 0x66 prefix
12736    in their opcode. 0x66 was originally used to differentiate
12737    between SSE and MMX instruction(operands). So we have to handle the
12738    cvt* separately using OP_EMC and OP_MXC */
12739 static void
OP_EMC(int bytemode,int sizeflag)12740 OP_EMC (int bytemode, int sizeflag)
12741 {
12742   if (modrm.mod != 3)
12743     {
12744       if (intel_syntax && bytemode == v_mode)
12745 	{
12746 	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12747 	  used_prefixes |= (prefixes & PREFIX_DATA);
12748 	}
12749       OP_E (bytemode, sizeflag);
12750       return;
12751     }
12752 
12753   /* Skip mod/rm byte.  */
12754   MODRM_CHECK;
12755   codep++;
12756   used_prefixes |= (prefixes & PREFIX_DATA);
12757   oappend (names_mm[modrm.rm]);
12758 }
12759 
12760 static void
OP_MXC(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12761 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12762 {
12763   used_prefixes |= (prefixes & PREFIX_DATA);
12764   oappend (names_mm[modrm.reg]);
12765 }
12766 
12767 static void
OP_EX(int bytemode,int sizeflag)12768 OP_EX (int bytemode, int sizeflag)
12769 {
12770   int reg;
12771   const char **names;
12772 
12773   /* Skip mod/rm byte.  */
12774   MODRM_CHECK;
12775   codep++;
12776 
12777   if (modrm.mod != 3)
12778     {
12779       OP_E_memory (bytemode, sizeflag);
12780       return;
12781     }
12782 
12783   reg = modrm.rm;
12784   USED_REX (REX_B);
12785   if (rex & REX_B)
12786     reg += 8;
12787   if (vex.evex)
12788     {
12789       USED_REX (REX_X);
12790       if ((rex & REX_X))
12791 	reg += 16;
12792     }
12793 
12794   if ((sizeflag & SUFFIX_ALWAYS)
12795       && (bytemode == x_swap_mode
12796 	  || bytemode == d_swap_mode
12797 	  || bytemode == q_swap_mode))
12798     swap_operand ();
12799 
12800   if (need_vex
12801       && bytemode != xmm_mode
12802       && bytemode != xmmdw_mode
12803       && bytemode != xmmqd_mode
12804       && bytemode != xmm_mb_mode
12805       && bytemode != xmm_mw_mode
12806       && bytemode != xmm_md_mode
12807       && bytemode != xmm_mq_mode
12808       && bytemode != xmmq_mode
12809       && bytemode != evex_half_bcst_xmmq_mode
12810       && bytemode != ymm_mode
12811       && bytemode != tmm_mode
12812       && bytemode != vex_scalar_w_dq_mode)
12813     {
12814       switch (vex.length)
12815 	{
12816 	case 128:
12817 	  names = names_xmm;
12818 	  break;
12819 	case 256:
12820 	  names = names_ymm;
12821 	  break;
12822 	case 512:
12823 	  names = names_zmm;
12824 	  break;
12825 	default:
12826 	  abort ();
12827 	}
12828     }
12829   else if (bytemode == xmmq_mode
12830 	   || bytemode == evex_half_bcst_xmmq_mode)
12831     {
12832       switch (vex.length)
12833 	{
12834 	case 128:
12835 	case 256:
12836 	  names = names_xmm;
12837 	  break;
12838 	case 512:
12839 	  names = names_ymm;
12840 	  break;
12841 	default:
12842 	  abort ();
12843 	}
12844     }
12845   else if (bytemode == tmm_mode)
12846     {
12847       modrm.rm = reg;
12848       if (reg >= 8)
12849 	{
12850 	  oappend ("(bad)");
12851 	  return;
12852 	}
12853       names = names_tmm;
12854     }
12855   else if (bytemode == ymm_mode)
12856     names = names_ymm;
12857   else
12858     names = names_xmm;
12859   oappend (names[reg]);
12860 }
12861 
12862 static void
OP_MS(int bytemode,int sizeflag)12863 OP_MS (int bytemode, int sizeflag)
12864 {
12865   if (modrm.mod == 3)
12866     OP_EM (bytemode, sizeflag);
12867   else
12868     BadOp ();
12869 }
12870 
12871 static void
OP_XS(int bytemode,int sizeflag)12872 OP_XS (int bytemode, int sizeflag)
12873 {
12874   if (modrm.mod == 3)
12875     OP_EX (bytemode, sizeflag);
12876   else
12877     BadOp ();
12878 }
12879 
12880 static void
OP_M(int bytemode,int sizeflag)12881 OP_M (int bytemode, int sizeflag)
12882 {
12883   if (modrm.mod == 3)
12884     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12885     BadOp ();
12886   else
12887     OP_E (bytemode, sizeflag);
12888 }
12889 
12890 static void
OP_0f07(int bytemode,int sizeflag)12891 OP_0f07 (int bytemode, int sizeflag)
12892 {
12893   if (modrm.mod != 3 || modrm.rm != 0)
12894     BadOp ();
12895   else
12896     OP_E (bytemode, sizeflag);
12897 }
12898 
12899 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12900    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12901 
12902 static void
NOP_Fixup1(int bytemode,int sizeflag)12903 NOP_Fixup1 (int bytemode, int sizeflag)
12904 {
12905   if ((prefixes & PREFIX_DATA) != 0
12906       || (rex != 0
12907 	  && rex != 0x48
12908 	  && address_mode == mode_64bit))
12909     OP_REG (bytemode, sizeflag);
12910   else
12911     strcpy (obuf, "nop");
12912 }
12913 
12914 static void
NOP_Fixup2(int bytemode,int sizeflag)12915 NOP_Fixup2 (int bytemode, int sizeflag)
12916 {
12917   if ((prefixes & PREFIX_DATA) != 0
12918       || (rex != 0
12919 	  && rex != 0x48
12920 	  && address_mode == mode_64bit))
12921     OP_IMREG (bytemode, sizeflag);
12922 }
12923 
12924 static const char *const Suffix3DNow[] = {
12925 /* 00 */	NULL,		NULL,		NULL,		NULL,
12926 /* 04 */	NULL,		NULL,		NULL,		NULL,
12927 /* 08 */	NULL,		NULL,		NULL,		NULL,
12928 /* 0C */	"pi2fw",	"pi2fd",	NULL,		NULL,
12929 /* 10 */	NULL,		NULL,		NULL,		NULL,
12930 /* 14 */	NULL,		NULL,		NULL,		NULL,
12931 /* 18 */	NULL,		NULL,		NULL,		NULL,
12932 /* 1C */	"pf2iw",	"pf2id",	NULL,		NULL,
12933 /* 20 */	NULL,		NULL,		NULL,		NULL,
12934 /* 24 */	NULL,		NULL,		NULL,		NULL,
12935 /* 28 */	NULL,		NULL,		NULL,		NULL,
12936 /* 2C */	NULL,		NULL,		NULL,		NULL,
12937 /* 30 */	NULL,		NULL,		NULL,		NULL,
12938 /* 34 */	NULL,		NULL,		NULL,		NULL,
12939 /* 38 */	NULL,		NULL,		NULL,		NULL,
12940 /* 3C */	NULL,		NULL,		NULL,		NULL,
12941 /* 40 */	NULL,		NULL,		NULL,		NULL,
12942 /* 44 */	NULL,		NULL,		NULL,		NULL,
12943 /* 48 */	NULL,		NULL,		NULL,		NULL,
12944 /* 4C */	NULL,		NULL,		NULL,		NULL,
12945 /* 50 */	NULL,		NULL,		NULL,		NULL,
12946 /* 54 */	NULL,		NULL,		NULL,		NULL,
12947 /* 58 */	NULL,		NULL,		NULL,		NULL,
12948 /* 5C */	NULL,		NULL,		NULL,		NULL,
12949 /* 60 */	NULL,		NULL,		NULL,		NULL,
12950 /* 64 */	NULL,		NULL,		NULL,		NULL,
12951 /* 68 */	NULL,		NULL,		NULL,		NULL,
12952 /* 6C */	NULL,		NULL,		NULL,		NULL,
12953 /* 70 */	NULL,		NULL,		NULL,		NULL,
12954 /* 74 */	NULL,		NULL,		NULL,		NULL,
12955 /* 78 */	NULL,		NULL,		NULL,		NULL,
12956 /* 7C */	NULL,		NULL,		NULL,		NULL,
12957 /* 80 */	NULL,		NULL,		NULL,		NULL,
12958 /* 84 */	NULL,		NULL,		NULL,		NULL,
12959 /* 88 */	NULL,		NULL,		"pfnacc",	NULL,
12960 /* 8C */	NULL,		NULL,		"pfpnacc",	NULL,
12961 /* 90 */	"pfcmpge",	NULL,		NULL,		NULL,
12962 /* 94 */	"pfmin",	NULL,		"pfrcp",	"pfrsqrt",
12963 /* 98 */	NULL,		NULL,		"pfsub",	NULL,
12964 /* 9C */	NULL,		NULL,		"pfadd",	NULL,
12965 /* A0 */	"pfcmpgt",	NULL,		NULL,		NULL,
12966 /* A4 */	"pfmax",	NULL,		"pfrcpit1",	"pfrsqit1",
12967 /* A8 */	NULL,		NULL,		"pfsubr",	NULL,
12968 /* AC */	NULL,		NULL,		"pfacc",	NULL,
12969 /* B0 */	"pfcmpeq",	NULL,		NULL,		NULL,
12970 /* B4 */	"pfmul",	NULL,		"pfrcpit2",	"pmulhrw",
12971 /* B8 */	NULL,		NULL,		NULL,		"pswapd",
12972 /* BC */	NULL,		NULL,		NULL,		"pavgusb",
12973 /* C0 */	NULL,		NULL,		NULL,		NULL,
12974 /* C4 */	NULL,		NULL,		NULL,		NULL,
12975 /* C8 */	NULL,		NULL,		NULL,		NULL,
12976 /* CC */	NULL,		NULL,		NULL,		NULL,
12977 /* D0 */	NULL,		NULL,		NULL,		NULL,
12978 /* D4 */	NULL,		NULL,		NULL,		NULL,
12979 /* D8 */	NULL,		NULL,		NULL,		NULL,
12980 /* DC */	NULL,		NULL,		NULL,		NULL,
12981 /* E0 */	NULL,		NULL,		NULL,		NULL,
12982 /* E4 */	NULL,		NULL,		NULL,		NULL,
12983 /* E8 */	NULL,		NULL,		NULL,		NULL,
12984 /* EC */	NULL,		NULL,		NULL,		NULL,
12985 /* F0 */	NULL,		NULL,		NULL,		NULL,
12986 /* F4 */	NULL,		NULL,		NULL,		NULL,
12987 /* F8 */	NULL,		NULL,		NULL,		NULL,
12988 /* FC */	NULL,		NULL,		NULL,		NULL,
12989 };
12990 
12991 static void
OP_3DNowSuffix(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12992 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12993 {
12994   const char *mnemonic;
12995 
12996   FETCH_DATA (the_info, codep + 1);
12997   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12998      place where an 8-bit immediate would normally go.  ie. the last
12999      byte of the instruction.  */
13000   obufp = mnemonicendp;
13001   mnemonic = Suffix3DNow[*codep++ & 0xff];
13002   if (mnemonic)
13003     oappend (mnemonic);
13004   else
13005     {
13006       /* Since a variable sized modrm/sib chunk is between the start
13007 	 of the opcode (0x0f0f) and the opcode suffix, we need to do
13008 	 all the modrm processing first, and don't know until now that
13009 	 we have a bad opcode.  This necessitates some cleaning up.  */
13010       op_out[0][0] = '\0';
13011       op_out[1][0] = '\0';
13012       BadOp ();
13013     }
13014   mnemonicendp = obufp;
13015 }
13016 
13017 static const struct op simd_cmp_op[] =
13018 {
13019   { STRING_COMMA_LEN ("eq") },
13020   { STRING_COMMA_LEN ("lt") },
13021   { STRING_COMMA_LEN ("le") },
13022   { STRING_COMMA_LEN ("unord") },
13023   { STRING_COMMA_LEN ("neq") },
13024   { STRING_COMMA_LEN ("nlt") },
13025   { STRING_COMMA_LEN ("nle") },
13026   { STRING_COMMA_LEN ("ord") }
13027 };
13028 
13029 static const struct op vex_cmp_op[] =
13030 {
13031   { STRING_COMMA_LEN ("eq_uq") },
13032   { STRING_COMMA_LEN ("nge") },
13033   { STRING_COMMA_LEN ("ngt") },
13034   { STRING_COMMA_LEN ("false") },
13035   { STRING_COMMA_LEN ("neq_oq") },
13036   { STRING_COMMA_LEN ("ge") },
13037   { STRING_COMMA_LEN ("gt") },
13038   { STRING_COMMA_LEN ("true") },
13039   { STRING_COMMA_LEN ("eq_os") },
13040   { STRING_COMMA_LEN ("lt_oq") },
13041   { STRING_COMMA_LEN ("le_oq") },
13042   { STRING_COMMA_LEN ("unord_s") },
13043   { STRING_COMMA_LEN ("neq_us") },
13044   { STRING_COMMA_LEN ("nlt_uq") },
13045   { STRING_COMMA_LEN ("nle_uq") },
13046   { STRING_COMMA_LEN ("ord_s") },
13047   { STRING_COMMA_LEN ("eq_us") },
13048   { STRING_COMMA_LEN ("nge_uq") },
13049   { STRING_COMMA_LEN ("ngt_uq") },
13050   { STRING_COMMA_LEN ("false_os") },
13051   { STRING_COMMA_LEN ("neq_os") },
13052   { STRING_COMMA_LEN ("ge_oq") },
13053   { STRING_COMMA_LEN ("gt_oq") },
13054   { STRING_COMMA_LEN ("true_us") },
13055 };
13056 
13057 static void
CMP_Fixup(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13058 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13059 {
13060   unsigned int cmp_type;
13061 
13062   FETCH_DATA (the_info, codep + 1);
13063   cmp_type = *codep++ & 0xff;
13064   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13065     {
13066       char suffix [3];
13067       char *p = mnemonicendp - 2;
13068       suffix[0] = p[0];
13069       suffix[1] = p[1];
13070       suffix[2] = '\0';
13071       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13072       mnemonicendp += simd_cmp_op[cmp_type].len;
13073     }
13074   else if (need_vex
13075 	   && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13076     {
13077       char suffix [3];
13078       char *p = mnemonicendp - 2;
13079       suffix[0] = p[0];
13080       suffix[1] = p[1];
13081       suffix[2] = '\0';
13082       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13083       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13084       mnemonicendp += vex_cmp_op[cmp_type].len;
13085     }
13086   else
13087     {
13088       /* We have a reserved extension byte.  Output it directly.  */
13089       scratchbuf[0] = '$';
13090       print_operand_value (scratchbuf + 1, 1, cmp_type);
13091       oappend_maybe_intel (scratchbuf);
13092       scratchbuf[0] = '\0';
13093     }
13094 }
13095 
13096 static void
OP_Mwait(int bytemode,int sizeflag ATTRIBUTE_UNUSED)13097 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13098 {
13099   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13100   if (!intel_syntax)
13101     {
13102       strcpy (op_out[0], names32[0]);
13103       strcpy (op_out[1], names32[1]);
13104       if (bytemode == eBX_reg)
13105 	strcpy (op_out[2], names32[3]);
13106       two_source_ops = 1;
13107     }
13108   /* Skip mod/rm byte.  */
13109   MODRM_CHECK;
13110   codep++;
13111 }
13112 
13113 static void
OP_Monitor(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13114 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13115 	    int sizeflag ATTRIBUTE_UNUSED)
13116 {
13117   /* monitor %{e,r,}ax,%ecx,%edx"  */
13118   if (!intel_syntax)
13119     {
13120       const char **names = (address_mode == mode_64bit
13121 			    ? names64 : names32);
13122 
13123       if (prefixes & PREFIX_ADDR)
13124 	{
13125 	  /* Remove "addr16/addr32".  */
13126 	  all_prefixes[last_addr_prefix] = 0;
13127 	  names = (address_mode != mode_32bit
13128 		   ? names32 : names16);
13129 	  used_prefixes |= PREFIX_ADDR;
13130 	}
13131       else if (address_mode == mode_16bit)
13132 	names = names16;
13133       strcpy (op_out[0], names[0]);
13134       strcpy (op_out[1], names32[1]);
13135       strcpy (op_out[2], names32[2]);
13136       two_source_ops = 1;
13137     }
13138   /* Skip mod/rm byte.  */
13139   MODRM_CHECK;
13140   codep++;
13141 }
13142 
13143 static void
BadOp(void)13144 BadOp (void)
13145 {
13146   /* Throw away prefixes and 1st. opcode byte.  */
13147   codep = insn_codep + 1;
13148   oappend ("(bad)");
13149 }
13150 
13151 static void
REP_Fixup(int bytemode,int sizeflag)13152 REP_Fixup (int bytemode, int sizeflag)
13153 {
13154   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13155      lods and stos.  */
13156   if (prefixes & PREFIX_REPZ)
13157     all_prefixes[last_repz_prefix] = REP_PREFIX;
13158 
13159   switch (bytemode)
13160     {
13161     case al_reg:
13162     case eAX_reg:
13163     case indir_dx_reg:
13164       OP_IMREG (bytemode, sizeflag);
13165       break;
13166     case eDI_reg:
13167       OP_ESreg (bytemode, sizeflag);
13168       break;
13169     case eSI_reg:
13170       OP_DSreg (bytemode, sizeflag);
13171       break;
13172     default:
13173       abort ();
13174       break;
13175     }
13176 }
13177 
13178 static void
SEP_Fixup(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13179 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13180 {
13181   if ( isa64 != amd64 )
13182     return;
13183 
13184   obufp = obuf;
13185   BadOp ();
13186   mnemonicendp = obufp;
13187   ++codep;
13188 }
13189 
13190 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13191    "bnd".  */
13192 
13193 static void
BND_Fixup(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13194 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13195 {
13196   if (prefixes & PREFIX_REPNZ)
13197     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13198 }
13199 
13200 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13201    "notrack".  */
13202 
13203 static void
NOTRACK_Fixup(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13204 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13205 	       int sizeflag ATTRIBUTE_UNUSED)
13206 {
13207 
13208   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13209      we've seen a PREFIX_DS.  */
13210   if ((prefixes & PREFIX_DS) != 0
13211       && (address_mode != mode_64bit || last_data_prefix < 0))
13212     {
13213       /* NOTRACK prefix is only valid on indirect branch instructions.
13214 	 NB: DATA prefix is unsupported for Intel64.  */
13215       active_seg_prefix = 0;
13216       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13217     }
13218 }
13219 
13220 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13221    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13222  */
13223 
13224 static void
HLE_Fixup1(int bytemode,int sizeflag)13225 HLE_Fixup1 (int bytemode, int sizeflag)
13226 {
13227   if (modrm.mod != 3
13228       && (prefixes & PREFIX_LOCK) != 0)
13229     {
13230       if (prefixes & PREFIX_REPZ)
13231 	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13232       if (prefixes & PREFIX_REPNZ)
13233 	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13234     }
13235 
13236   OP_E (bytemode, sizeflag);
13237 }
13238 
13239 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13240    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13241  */
13242 
13243 static void
HLE_Fixup2(int bytemode,int sizeflag)13244 HLE_Fixup2 (int bytemode, int sizeflag)
13245 {
13246   if (modrm.mod != 3)
13247     {
13248       if (prefixes & PREFIX_REPZ)
13249 	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13250       if (prefixes & PREFIX_REPNZ)
13251 	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13252     }
13253 
13254   OP_E (bytemode, sizeflag);
13255 }
13256 
13257 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13258    "xrelease" for memory operand.  No check for LOCK prefix.   */
13259 
13260 static void
HLE_Fixup3(int bytemode,int sizeflag)13261 HLE_Fixup3 (int bytemode, int sizeflag)
13262 {
13263   if (modrm.mod != 3
13264       && last_repz_prefix > last_repnz_prefix
13265       && (prefixes & PREFIX_REPZ) != 0)
13266     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13267 
13268   OP_E (bytemode, sizeflag);
13269 }
13270 
13271 static void
CMPXCHG8B_Fixup(int bytemode,int sizeflag)13272 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13273 {
13274   USED_REX (REX_W);
13275   if (rex & REX_W)
13276     {
13277       /* Change cmpxchg8b to cmpxchg16b.  */
13278       char *p = mnemonicendp - 2;
13279       mnemonicendp = stpcpy (p, "16b");
13280       bytemode = o_mode;
13281     }
13282   else if ((prefixes & PREFIX_LOCK) != 0)
13283     {
13284       if (prefixes & PREFIX_REPZ)
13285 	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13286       if (prefixes & PREFIX_REPNZ)
13287 	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13288     }
13289 
13290   OP_M (bytemode, sizeflag);
13291 }
13292 
13293 static void
XMM_Fixup(int reg,int sizeflag ATTRIBUTE_UNUSED)13294 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13295 {
13296   const char **names;
13297 
13298   if (need_vex)
13299     {
13300       switch (vex.length)
13301 	{
13302 	case 128:
13303 	  names = names_xmm;
13304 	  break;
13305 	case 256:
13306 	  names = names_ymm;
13307 	  break;
13308 	default:
13309 	  abort ();
13310 	}
13311     }
13312   else
13313     names = names_xmm;
13314   oappend (names[reg]);
13315 }
13316 
13317 static void
FXSAVE_Fixup(int bytemode,int sizeflag)13318 FXSAVE_Fixup (int bytemode, int sizeflag)
13319 {
13320   /* Add proper suffix to "fxsave" and "fxrstor".  */
13321   USED_REX (REX_W);
13322   if (rex & REX_W)
13323     {
13324       char *p = mnemonicendp;
13325       *p++ = '6';
13326       *p++ = '4';
13327       *p = '\0';
13328       mnemonicendp = p;
13329     }
13330   OP_M (bytemode, sizeflag);
13331 }
13332 
13333 /* Display the destination register operand for instructions with
13334    VEX. */
13335 
13336 static void
OP_VEX(int bytemode,int sizeflag ATTRIBUTE_UNUSED)13337 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13338 {
13339   int reg, modrm_reg, sib_index = -1;
13340   const char **names;
13341 
13342   if (!need_vex)
13343     abort ();
13344 
13345   reg = vex.register_specifier;
13346   vex.register_specifier = 0;
13347   if (address_mode != mode_64bit)
13348     reg &= 7;
13349   else if (vex.evex && !vex.v)
13350     reg += 16;
13351 
13352   switch (bytemode)
13353     {
13354     case vex_scalar_mode:
13355       oappend (names_xmm[reg]);
13356       return;
13357 
13358     case vex_vsib_d_w_dq_mode:
13359     case vex_vsib_q_w_dq_mode:
13360       /* This must be the 3rd operand.  */
13361       if (obufp != op_out[2])
13362 	abort ();
13363       if (vex.length == 128
13364 	  || (bytemode != vex_vsib_d_w_dq_mode
13365 	      && !vex.w))
13366 	oappend (names_xmm[reg]);
13367       else
13368 	oappend (names_ymm[reg]);
13369 
13370       /* All 3 XMM/YMM registers must be distinct.  */
13371       modrm_reg = modrm.reg;
13372       if (rex & REX_R)
13373 	modrm_reg += 8;
13374 
13375       if (modrm.rm == 4)
13376 	{
13377 	  sib_index = sib.index;
13378 	  if (rex & REX_X)
13379 	    sib_index += 8;
13380 	}
13381 
13382       if (reg == modrm_reg || reg == sib_index)
13383 	strcpy (obufp, "/(bad)");
13384       if (modrm_reg == sib_index || modrm_reg == reg)
13385 	strcat (op_out[0], "/(bad)");
13386       if (sib_index == modrm_reg || sib_index == reg)
13387 	strcat (op_out[1], "/(bad)");
13388 
13389       return;
13390 
13391     case tmm_mode:
13392       /* All 3 TMM registers must be distinct.  */
13393       if (reg >= 8)
13394 	oappend ("(bad)");
13395       else
13396 	{
13397 	  /* This must be the 3rd operand.  */
13398 	  if (obufp != op_out[2])
13399 	    abort ();
13400 	  oappend (names_tmm[reg]);
13401 	  if (reg == modrm.reg || reg == modrm.rm)
13402 	    strcpy (obufp, "/(bad)");
13403 	}
13404 
13405       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13406 	{
13407 	  if (modrm.reg <= 8
13408 	      && (modrm.reg == modrm.rm || modrm.reg == reg))
13409 	    strcat (op_out[0], "/(bad)");
13410 	  if (modrm.rm <= 8
13411 	      && (modrm.rm == modrm.reg || modrm.rm == reg))
13412 	    strcat (op_out[1], "/(bad)");
13413 	}
13414 
13415       return;
13416     }
13417 
13418   switch (vex.length)
13419     {
13420     case 128:
13421       switch (bytemode)
13422 	{
13423 	case vex_mode:
13424 	  names = names_xmm;
13425 	  break;
13426 	case dq_mode:
13427 	  if (rex & REX_W)
13428 	    names = names64;
13429 	  else
13430 	    names = names32;
13431 	  break;
13432 	case mask_bd_mode:
13433 	case mask_mode:
13434 	  if (reg > 0x7)
13435 	    {
13436 	      oappend ("(bad)");
13437 	      return;
13438 	    }
13439 	  names = names_mask;
13440 	  break;
13441 	default:
13442 	  abort ();
13443 	  return;
13444 	}
13445       break;
13446     case 256:
13447       switch (bytemode)
13448 	{
13449 	case vex_mode:
13450 	  names = names_ymm;
13451 	  break;
13452 	case mask_bd_mode:
13453 	case mask_mode:
13454 	  if (reg > 0x7)
13455 	    {
13456 	      oappend ("(bad)");
13457 	      return;
13458 	    }
13459 	  names = names_mask;
13460 	  break;
13461 	default:
13462 	  /* See PR binutils/20893 for a reproducer.  */
13463 	  oappend ("(bad)");
13464 	  return;
13465 	}
13466       break;
13467     case 512:
13468       names = names_zmm;
13469       break;
13470     default:
13471       abort ();
13472       break;
13473     }
13474   oappend (names[reg]);
13475 }
13476 
13477 static void
OP_VexR(int bytemode,int sizeflag)13478 OP_VexR (int bytemode, int sizeflag)
13479 {
13480   if (modrm.mod == 3)
13481     OP_VEX (bytemode, sizeflag);
13482 }
13483 
13484 static void
OP_VexW(int bytemode,int sizeflag)13485 OP_VexW (int bytemode, int sizeflag)
13486 {
13487   OP_VEX (bytemode, sizeflag);
13488 
13489   if (vex.w)
13490     {
13491       /* Swap 2nd and 3rd operands.  */
13492       strcpy (scratchbuf, op_out[2]);
13493       strcpy (op_out[2], op_out[1]);
13494       strcpy (op_out[1], scratchbuf);
13495     }
13496 }
13497 
13498 static void
OP_REG_VexI4(int bytemode,int sizeflag ATTRIBUTE_UNUSED)13499 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13500 {
13501   int reg;
13502   const char **names = names_xmm;
13503 
13504   FETCH_DATA (the_info, codep + 1);
13505   reg = *codep++;
13506 
13507   if (bytemode != x_mode && bytemode != scalar_mode)
13508     abort ();
13509 
13510   reg >>= 4;
13511   if (address_mode != mode_64bit)
13512     reg &= 7;
13513 
13514   if (bytemode == x_mode && vex.length == 256)
13515     names = names_ymm;
13516 
13517   oappend (names[reg]);
13518 
13519   if (vex.w)
13520     {
13521       /* Swap 3rd and 4th operands.  */
13522       strcpy (scratchbuf, op_out[3]);
13523       strcpy (op_out[3], op_out[2]);
13524       strcpy (op_out[2], scratchbuf);
13525     }
13526 }
13527 
13528 static void
OP_VexI4(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13529 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13530 	  int sizeflag ATTRIBUTE_UNUSED)
13531 {
13532   scratchbuf[0] = '$';
13533   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13534   oappend_maybe_intel (scratchbuf);
13535 }
13536 
13537 static void
VPCMP_Fixup(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13538 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13539 	     int sizeflag ATTRIBUTE_UNUSED)
13540 {
13541   unsigned int cmp_type;
13542 
13543   if (!vex.evex)
13544     abort ();
13545 
13546   FETCH_DATA (the_info, codep + 1);
13547   cmp_type = *codep++ & 0xff;
13548   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13549      If it's the case, print suffix, otherwise - print the immediate.  */
13550   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13551       && cmp_type != 3
13552       && cmp_type != 7)
13553     {
13554       char suffix [3];
13555       char *p = mnemonicendp - 2;
13556 
13557       /* vpcmp* can have both one- and two-lettered suffix.  */
13558       if (p[0] == 'p')
13559 	{
13560 	  p++;
13561 	  suffix[0] = p[0];
13562 	  suffix[1] = '\0';
13563 	}
13564       else
13565 	{
13566 	  suffix[0] = p[0];
13567 	  suffix[1] = p[1];
13568 	  suffix[2] = '\0';
13569 	}
13570 
13571       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13572       mnemonicendp += simd_cmp_op[cmp_type].len;
13573     }
13574   else
13575     {
13576       /* We have a reserved extension byte.  Output it directly.  */
13577       scratchbuf[0] = '$';
13578       print_operand_value (scratchbuf + 1, 1, cmp_type);
13579       oappend_maybe_intel (scratchbuf);
13580       scratchbuf[0] = '\0';
13581     }
13582 }
13583 
13584 static const struct op xop_cmp_op[] =
13585 {
13586   { STRING_COMMA_LEN ("lt") },
13587   { STRING_COMMA_LEN ("le") },
13588   { STRING_COMMA_LEN ("gt") },
13589   { STRING_COMMA_LEN ("ge") },
13590   { STRING_COMMA_LEN ("eq") },
13591   { STRING_COMMA_LEN ("neq") },
13592   { STRING_COMMA_LEN ("false") },
13593   { STRING_COMMA_LEN ("true") }
13594 };
13595 
13596 static void
VPCOM_Fixup(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13597 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13598 	     int sizeflag ATTRIBUTE_UNUSED)
13599 {
13600   unsigned int cmp_type;
13601 
13602   FETCH_DATA (the_info, codep + 1);
13603   cmp_type = *codep++ & 0xff;
13604   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13605     {
13606       char suffix[3];
13607       char *p = mnemonicendp - 2;
13608 
13609       /* vpcom* can have both one- and two-lettered suffix.  */
13610       if (p[0] == 'm')
13611 	{
13612 	  p++;
13613 	  suffix[0] = p[0];
13614 	  suffix[1] = '\0';
13615 	}
13616       else
13617 	{
13618 	  suffix[0] = p[0];
13619 	  suffix[1] = p[1];
13620 	  suffix[2] = '\0';
13621 	}
13622 
13623       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13624       mnemonicendp += xop_cmp_op[cmp_type].len;
13625     }
13626   else
13627     {
13628       /* We have a reserved extension byte.  Output it directly.  */
13629       scratchbuf[0] = '$';
13630       print_operand_value (scratchbuf + 1, 1, cmp_type);
13631       oappend_maybe_intel (scratchbuf);
13632       scratchbuf[0] = '\0';
13633     }
13634 }
13635 
13636 static const struct op pclmul_op[] =
13637 {
13638   { STRING_COMMA_LEN ("lql") },
13639   { STRING_COMMA_LEN ("hql") },
13640   { STRING_COMMA_LEN ("lqh") },
13641   { STRING_COMMA_LEN ("hqh") }
13642 };
13643 
13644 static void
PCLMUL_Fixup(int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13645 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13646 	      int sizeflag ATTRIBUTE_UNUSED)
13647 {
13648   unsigned int pclmul_type;
13649 
13650   FETCH_DATA (the_info, codep + 1);
13651   pclmul_type = *codep++ & 0xff;
13652   switch (pclmul_type)
13653     {
13654     case 0x10:
13655       pclmul_type = 2;
13656       break;
13657     case 0x11:
13658       pclmul_type = 3;
13659       break;
13660     default:
13661       break;
13662     }
13663   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13664     {
13665       char suffix [4];
13666       char *p = mnemonicendp - 3;
13667       suffix[0] = p[0];
13668       suffix[1] = p[1];
13669       suffix[2] = p[2];
13670       suffix[3] = '\0';
13671       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13672       mnemonicendp += pclmul_op[pclmul_type].len;
13673     }
13674   else
13675     {
13676       /* We have a reserved extension byte.  Output it directly.  */
13677       scratchbuf[0] = '$';
13678       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13679       oappend_maybe_intel (scratchbuf);
13680       scratchbuf[0] = '\0';
13681     }
13682 }
13683 
13684 static void
MOVSXD_Fixup(int bytemode,int sizeflag)13685 MOVSXD_Fixup (int bytemode, int sizeflag)
13686 {
13687   /* Add proper suffix to "movsxd".  */
13688   char *p = mnemonicendp;
13689 
13690   switch (bytemode)
13691     {
13692     case movsxd_mode:
13693       if (intel_syntax)
13694 	{
13695 	  *p++ = 'x';
13696 	  *p++ = 'd';
13697 	  goto skip;
13698 	}
13699 
13700       USED_REX (REX_W);
13701       if (rex & REX_W)
13702 	{
13703 	  *p++ = 'l';
13704 	  *p++ = 'q';
13705 	}
13706       else
13707 	{
13708 	  *p++ = 'x';
13709 	  *p++ = 'd';
13710 	}
13711       break;
13712     default:
13713       oappend (INTERNAL_DISASSEMBLER_ERROR);
13714       break;
13715     }
13716 
13717  skip:
13718   mnemonicendp = p;
13719   *p = '\0';
13720   OP_E (bytemode, sizeflag);
13721 }
13722 
13723 static void
OP_Mask(int bytemode,int sizeflag ATTRIBUTE_UNUSED)13724 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13725 {
13726   if (!vex.evex
13727       || (bytemode != mask_mode && bytemode != mask_bd_mode))
13728     abort ();
13729 
13730   USED_REX (REX_R);
13731   if ((rex & REX_R) != 0 || !vex.r)
13732     {
13733       BadOp ();
13734       return;
13735     }
13736 
13737   oappend (names_mask [modrm.reg]);
13738 }
13739 
13740 static void
OP_Rounding(int bytemode,int sizeflag ATTRIBUTE_UNUSED)13741 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13742 {
13743   if (modrm.mod == 3 && vex.b)
13744     switch (bytemode)
13745       {
13746       case evex_rounding_64_mode:
13747 	if (address_mode != mode_64bit)
13748 	  {
13749 	    oappend ("(bad)");
13750 	    break;
13751 	  }
13752 	/* Fall through.  */
13753       case evex_rounding_mode:
13754 	oappend (names_rounding[vex.ll]);
13755 	break;
13756       case evex_sae_mode:
13757 	oappend ("{sae}");
13758 	break;
13759       default:
13760 	abort ();
13761 	break;
13762       }
13763 }
13764