1 /* Opcode table for TI TMS320C80 (MVP).
2 Copyright 1996, 1997, 2000, 2005, 2007, 2012
3 Free Software Foundation, Inc.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "opcode/tic80.h"
25
26 /* This file holds various tables for the TMS320C80 (MVP).
27
28 The opcode table is strictly constant data, so the compiler should
29 be able to put it in the .text section.
30
31 This file also holds the operand table. All knowledge about
32 inserting operands into instructions and vice-versa is kept in this
33 file.
34
35 The predefined register table maps from register names to register
36 values. */
37
38
39 /* Table of predefined symbol names, such as general purpose registers,
40 floating point registers, condition codes, control registers, and bit
41 numbers.
42
43 The table is sorted case independently by name so that it is suitable for
44 searching via a binary search using a case independent comparison
45 function.
46
47 Note that the type of the symbol is stored in the upper bits of the value
48 field, which allows the value and type to be passed around as a unit in a
49 single int. The types have to be masked off before using the numeric
50 value as a number.
51 */
52
53 const struct predefined_symbol tic80_predefined_symbols[] =
54 {
55 { "a0", TIC80_OPERAND_FPA | 0 },
56 { "a1", TIC80_OPERAND_FPA | 1 },
57 { "alw.b", TIC80_OPERAND_CC | 7 },
58 { "alw.h", TIC80_OPERAND_CC | 15 },
59 { "alw.w", TIC80_OPERAND_CC | 23 },
60 { "ANASTAT", TIC80_OPERAND_CR | 0x34 },
61 { "BRK1", TIC80_OPERAND_CR | 0x39 },
62 { "BRK2", TIC80_OPERAND_CR | 0x3A },
63 { "CONFIG", TIC80_OPERAND_CR | 2 },
64 { "DLRU", TIC80_OPERAND_CR | 0x500 },
65 { "DTAG0", TIC80_OPERAND_CR | 0x400 },
66 { "DTAG1", TIC80_OPERAND_CR | 0x401 },
67 { "DTAG10", TIC80_OPERAND_CR | 0x40A },
68 { "DTAG11", TIC80_OPERAND_CR | 0x40B },
69 { "DTAG12", TIC80_OPERAND_CR | 0x40C },
70 { "DTAG13", TIC80_OPERAND_CR | 0x40D },
71 { "DTAG14", TIC80_OPERAND_CR | 0x40E },
72 { "DTAG15", TIC80_OPERAND_CR | 0x40F },
73 { "DTAG2", TIC80_OPERAND_CR | 0x402 },
74 { "DTAG3", TIC80_OPERAND_CR | 0x403 },
75 { "DTAG4", TIC80_OPERAND_CR | 0x404 },
76 { "DTAG5", TIC80_OPERAND_CR | 0x405 },
77 { "DTAG6", TIC80_OPERAND_CR | 0x406 },
78 { "DTAG7", TIC80_OPERAND_CR | 0x407 },
79 { "DTAG8", TIC80_OPERAND_CR | 0x408 },
80 { "DTAG9", TIC80_OPERAND_CR | 0x409 },
81 { "ECOMCNTL", TIC80_OPERAND_CR | 0x33 },
82 { "EIP", TIC80_OPERAND_CR | 1 },
83 { "EPC", TIC80_OPERAND_CR | 0 },
84 { "eq.b", TIC80_OPERAND_BITNUM | 0 },
85 { "eq.f", TIC80_OPERAND_BITNUM | 20 },
86 { "eq.h", TIC80_OPERAND_BITNUM | 10 },
87 { "eq.w", TIC80_OPERAND_BITNUM | 20 },
88 { "eq0.b", TIC80_OPERAND_CC | 2 },
89 { "eq0.h", TIC80_OPERAND_CC | 10 },
90 { "eq0.w", TIC80_OPERAND_CC | 18 },
91 { "FLTADR", TIC80_OPERAND_CR | 0x11 },
92 { "FLTDTH", TIC80_OPERAND_CR | 0x14 },
93 { "FLTDTL", TIC80_OPERAND_CR | 0x13 },
94 { "FLTOP", TIC80_OPERAND_CR | 0x10 },
95 { "FLTTAG", TIC80_OPERAND_CR | 0x12 },
96 { "FPST", TIC80_OPERAND_CR | 8 },
97 { "ge.b", TIC80_OPERAND_BITNUM | 5 },
98 { "ge.f", TIC80_OPERAND_BITNUM | 25 },
99 { "ge.h", TIC80_OPERAND_BITNUM | 15 },
100 { "ge.w", TIC80_OPERAND_BITNUM | 25 },
101 { "ge0.b", TIC80_OPERAND_CC | 3 },
102 { "ge0.h", TIC80_OPERAND_CC | 11 },
103 { "ge0.w", TIC80_OPERAND_CC | 19 },
104 { "gt.b", TIC80_OPERAND_BITNUM | 2 },
105 { "gt.f", TIC80_OPERAND_BITNUM | 22 },
106 { "gt.h", TIC80_OPERAND_BITNUM | 12 },
107 { "gt.w", TIC80_OPERAND_BITNUM | 22 },
108 { "gt0.b", TIC80_OPERAND_CC | 1 },
109 { "gt0.h", TIC80_OPERAND_CC | 9 },
110 { "gt0.w", TIC80_OPERAND_CC | 17 },
111 { "hi.b", TIC80_OPERAND_BITNUM | 6 },
112 { "hi.h", TIC80_OPERAND_BITNUM | 16 },
113 { "hi.w", TIC80_OPERAND_BITNUM | 26 },
114 { "hs.b", TIC80_OPERAND_BITNUM | 9 },
115 { "hs.h", TIC80_OPERAND_BITNUM | 19 },
116 { "hs.w", TIC80_OPERAND_BITNUM | 29 },
117 { "ib.f", TIC80_OPERAND_BITNUM | 28 },
118 { "IE", TIC80_OPERAND_CR | 6 },
119 { "ILRU", TIC80_OPERAND_CR | 0x300 },
120 { "in.f", TIC80_OPERAND_BITNUM | 27 },
121 { "IN0P", TIC80_OPERAND_CR | 0x4000 },
122 { "IN1P", TIC80_OPERAND_CR | 0x4001 },
123 { "INTPEN", TIC80_OPERAND_CR | 4 },
124 { "ITAG0", TIC80_OPERAND_CR | 0x200 },
125 { "ITAG1", TIC80_OPERAND_CR | 0x201 },
126 { "ITAG10", TIC80_OPERAND_CR | 0x20A },
127 { "ITAG11", TIC80_OPERAND_CR | 0x20B },
128 { "ITAG12", TIC80_OPERAND_CR | 0x20C },
129 { "ITAG13", TIC80_OPERAND_CR | 0x20D },
130 { "ITAG14", TIC80_OPERAND_CR | 0x20E },
131 { "ITAG15", TIC80_OPERAND_CR | 0x20F },
132 { "ITAG2", TIC80_OPERAND_CR | 0x202 },
133 { "ITAG3", TIC80_OPERAND_CR | 0x203 },
134 { "ITAG4", TIC80_OPERAND_CR | 0x204 },
135 { "ITAG5", TIC80_OPERAND_CR | 0x205 },
136 { "ITAG6", TIC80_OPERAND_CR | 0x206 },
137 { "ITAG7", TIC80_OPERAND_CR | 0x207 },
138 { "ITAG8", TIC80_OPERAND_CR | 0x208 },
139 { "ITAG9", TIC80_OPERAND_CR | 0x209 },
140 { "le.b", TIC80_OPERAND_BITNUM | 3 },
141 { "le.f", TIC80_OPERAND_BITNUM | 23 },
142 { "le.h", TIC80_OPERAND_BITNUM | 13 },
143 { "le.w", TIC80_OPERAND_BITNUM | 23 },
144 { "le0.b", TIC80_OPERAND_CC | 6 },
145 { "le0.h", TIC80_OPERAND_CC | 14 },
146 { "le0.w", TIC80_OPERAND_CC | 22 },
147 { "lo.b", TIC80_OPERAND_BITNUM | 8 },
148 { "lo.h", TIC80_OPERAND_BITNUM | 18 },
149 { "lo.w", TIC80_OPERAND_BITNUM | 28 },
150 { "ls.b", TIC80_OPERAND_BITNUM | 7 },
151 { "ls.h", TIC80_OPERAND_BITNUM | 17 },
152 { "ls.w", TIC80_OPERAND_BITNUM | 27 },
153 { "lt.b", TIC80_OPERAND_BITNUM | 4 },
154 { "lt.f", TIC80_OPERAND_BITNUM | 24 },
155 { "lt.h", TIC80_OPERAND_BITNUM | 14 },
156 { "lt.w", TIC80_OPERAND_BITNUM | 24 },
157 { "lt0.b", TIC80_OPERAND_CC | 4 },
158 { "lt0.h", TIC80_OPERAND_CC | 12 },
159 { "lt0.w", TIC80_OPERAND_CC | 20 },
160 { "MIP", TIC80_OPERAND_CR | 0x31 },
161 { "MPC", TIC80_OPERAND_CR | 0x30 },
162 { "ne.b", TIC80_OPERAND_BITNUM | 1 },
163 { "ne.f", TIC80_OPERAND_BITNUM | 21 },
164 { "ne.h", TIC80_OPERAND_BITNUM | 11 },
165 { "ne.w", TIC80_OPERAND_BITNUM | 21 },
166 { "ne0.b", TIC80_OPERAND_CC | 5 },
167 { "ne0.h", TIC80_OPERAND_CC | 13 },
168 { "ne0.w", TIC80_OPERAND_CC | 21 },
169 { "nev.b", TIC80_OPERAND_CC | 0 },
170 { "nev.h", TIC80_OPERAND_CC | 8 },
171 { "nev.w", TIC80_OPERAND_CC | 16 },
172 { "ob.f", TIC80_OPERAND_BITNUM | 29 },
173 { "or.f", TIC80_OPERAND_BITNUM | 31 },
174 { "ou.f", TIC80_OPERAND_BITNUM | 26 },
175 { "OUTP", TIC80_OPERAND_CR | 0x4002 },
176 { "PKTREQ", TIC80_OPERAND_CR | 0xD },
177 { "PPERROR", TIC80_OPERAND_CR | 0xA },
178 { "r0", TIC80_OPERAND_GPR | 0 },
179 { "r1", TIC80_OPERAND_GPR | 1 },
180 { "r10", TIC80_OPERAND_GPR | 10 },
181 { "r11", TIC80_OPERAND_GPR | 11 },
182 { "r12", TIC80_OPERAND_GPR | 12 },
183 { "r13", TIC80_OPERAND_GPR | 13 },
184 { "r14", TIC80_OPERAND_GPR | 14 },
185 { "r15", TIC80_OPERAND_GPR | 15 },
186 { "r16", TIC80_OPERAND_GPR | 16 },
187 { "r17", TIC80_OPERAND_GPR | 17 },
188 { "r18", TIC80_OPERAND_GPR | 18 },
189 { "r19", TIC80_OPERAND_GPR | 19 },
190 { "r2", TIC80_OPERAND_GPR | 2 },
191 { "r20", TIC80_OPERAND_GPR | 20 },
192 { "r21", TIC80_OPERAND_GPR | 21 },
193 { "r22", TIC80_OPERAND_GPR | 22 },
194 { "r23", TIC80_OPERAND_GPR | 23 },
195 { "r24", TIC80_OPERAND_GPR | 24 },
196 { "r25", TIC80_OPERAND_GPR | 25 },
197 { "r26", TIC80_OPERAND_GPR | 26 },
198 { "r27", TIC80_OPERAND_GPR | 27 },
199 { "r28", TIC80_OPERAND_GPR | 28 },
200 { "r29", TIC80_OPERAND_GPR | 29 },
201 { "r3", TIC80_OPERAND_GPR | 3 },
202 { "r30", TIC80_OPERAND_GPR | 30 },
203 { "r31", TIC80_OPERAND_GPR | 31 },
204 { "r4", TIC80_OPERAND_GPR | 4 },
205 { "r5", TIC80_OPERAND_GPR | 5 },
206 { "r6", TIC80_OPERAND_GPR | 6 },
207 { "r7", TIC80_OPERAND_GPR | 7 },
208 { "r8", TIC80_OPERAND_GPR | 8 },
209 { "r9", TIC80_OPERAND_GPR | 9 },
210 { "SYSSTK", TIC80_OPERAND_CR | 0x20 },
211 { "SYSTMP", TIC80_OPERAND_CR | 0x21 },
212 { "TCOUNT", TIC80_OPERAND_CR | 0xE },
213 { "TSCALE", TIC80_OPERAND_CR | 0xF },
214 { "uo.f", TIC80_OPERAND_BITNUM | 30 },
215 };
216
217 const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol);
218
219 /* This function takes a predefined symbol name in NAME, symbol class
220 in CLASS, and translates it to a numeric value, which it returns.
221
222 If CLASS is zero, any symbol that matches NAME is translated. If
223 CLASS is non-zero, then only a symbol that has symbol_class CLASS is
224 matched.
225
226 If no translation is possible, it returns -1, a value not used by
227 any predefined symbol. Note that the predefined symbol array is
228 presorted case independently by name.
229
230 This function is implemented with the assumption that there are no
231 duplicate names in the predefined symbol array, which happens to be
232 true at the moment.
233
234 */
235
236 int
tic80_symbol_to_value(name,symbol_class)237 tic80_symbol_to_value (name, symbol_class)
238 char *name;
239 int symbol_class;
240 {
241 const struct predefined_symbol *pdsp;
242 int low = 0;
243 int middle;
244 int high = tic80_num_predefined_symbols - 1;
245 int cmp;
246 int rtnval = -1;
247
248 while (low <= high)
249 {
250 middle = (low + high) / 2;
251 cmp = strcasecmp (name, tic80_predefined_symbols[middle].name);
252 if (cmp < 0)
253 {
254 high = middle - 1;
255 }
256 else if (cmp > 0)
257 {
258 low = middle + 1;
259 }
260 else
261 {
262 pdsp = &tic80_predefined_symbols[middle];
263 if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp)))
264 {
265 rtnval = PDS_VALUE (pdsp);
266 }
267 /* For now we assume that there are no duplicate names */
268 break;
269 }
270 }
271 return (rtnval);
272 }
273
274 /* This function takes a value VAL and finds a matching predefined
275 symbol that is in the operand symbol_class specified by CLASS. If CLASS
276 is zero, the first matching symbol is returned. */
277
278 const char *
tic80_value_to_symbol(val,symbol_class)279 tic80_value_to_symbol (val, symbol_class)
280 int val;
281 int symbol_class;
282 {
283 const struct predefined_symbol *pdsp;
284 int ival;
285 char *name;
286
287 name = NULL;
288 for (pdsp = tic80_predefined_symbols;
289 pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols;
290 pdsp++)
291 {
292 ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK;
293 if (ival == val)
294 {
295 if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp)))
296 {
297 /* Found the desired match */
298 name = PDS_NAME (pdsp);
299 break;
300 }
301 }
302 }
303 return (name);
304 }
305
306 /* This function returns a pointer to the next symbol in the predefined
307 symbol table after PDSP, or NULL if PDSP points to the last symbol. If
308 PDSP is NULL, it returns the first symbol in the table. Thus it can be
309 used to walk through the table by first calling it with NULL and then
310 calling it with each value it returned on the previous call, until it
311 returns NULL. */
312
313 const struct predefined_symbol *
tic80_next_predefined_symbol(pdsp)314 tic80_next_predefined_symbol (pdsp)
315 const struct predefined_symbol *pdsp;
316 {
317 if (pdsp == NULL)
318 {
319 pdsp = tic80_predefined_symbols;
320 }
321 else if (pdsp >= tic80_predefined_symbols &&
322 pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1)
323 {
324 pdsp++;
325 }
326 else
327 {
328 pdsp = NULL;
329 }
330 return (pdsp);
331 }
332
333
334
335 /* The operands table. The fields are:
336
337 bits, shift, insertion function, extraction function, flags
338 */
339
340 const struct tic80_operand tic80_operands[] =
341 {
342
343 /* The zero index is used to indicate the end of the list of operands. */
344
345 #define UNUSED (0)
346 { 0, 0, 0, 0, 0 },
347
348 /* Short signed immediate value in bits 14-0. */
349
350 #define SSI (UNUSED + 1)
351 { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
352
353 /* Short unsigned immediate value in bits 14-0 */
354
355 #define SUI (SSI + 1)
356 { 15, 0, NULL, NULL, 0 },
357
358 /* Short unsigned bitfield in bits 14-0. We distinguish this
359 from a regular unsigned immediate value only for the convenience
360 of the disassembler and the user. */
361
362 #define SUBF (SUI + 1)
363 { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
364
365 /* Long signed immediate in following 32 bit word */
366
367 #define LSI (SUBF + 1)
368 { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
369
370 /* Long unsigned immediate in following 32 bit word */
371
372 #define LUI (LSI + 1)
373 { 32, 0, NULL, NULL, 0 },
374
375 /* Long unsigned bitfield in following 32 bit word. We distinguish
376 this from a regular unsigned immediate value only for the
377 convenience of the disassembler and the user. */
378
379 #define LUBF (LUI + 1)
380 { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
381
382 /* Single precision floating point immediate in following 32 bit
383 word. */
384
385 #define SPFI (LUBF + 1)
386 { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
387
388 /* Register in bits 4-0 */
389
390 #define REG_0 (SPFI + 1)
391 { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
392
393 /* Even register in bits 4-0 */
394
395 #define REG_0_E (REG_0 + 1)
396 { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
397
398 /* Register in bits 26-22 */
399
400 #define REG_22 (REG_0_E + 1)
401 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
402
403 /* Even register in bits 26-22 */
404
405 #define REG_22_E (REG_22 + 1)
406 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
407
408 /* Register in bits 31-27 */
409
410 #define REG_DEST (REG_22_E + 1)
411 { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
412
413 /* Even register in bits 31-27 */
414
415 #define REG_DEST_E (REG_DEST + 1)
416 { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
417
418 /* Floating point accumulator register (a0-a3) specified by bit 16 (MSB)
419 and bit 11 (LSB) */
420 /* FIXME! Needs to use functions to insert and extract the register
421 number in bits 16 and 11. */
422
423 #define REG_FPA (REG_DEST_E + 1)
424 { 0, 0, NULL, NULL, TIC80_OPERAND_FPA },
425
426 /* Short signed PC word offset in bits 14-0 */
427
428 #define OFF_SS_PC (REG_FPA + 1)
429 { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
430
431 /* Long signed PC word offset in following 32 bit word */
432
433 #define OFF_SL_PC (OFF_SS_PC + 1)
434 { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
435
436 /* Short signed base relative byte offset in bits 14-0 */
437
438 #define OFF_SS_BR (OFF_SL_PC + 1)
439 { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
440
441 /* Long signed base relative byte offset in following 32 bit word */
442
443 #define OFF_SL_BR (OFF_SS_BR + 1)
444 { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
445
446 /* Long signed base relative byte offset in following 32 bit word
447 with optional ":s" modifier flag in bit 11 */
448
449 #define OFF_SL_BR_SCALED (OFF_SL_BR + 1)
450 { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
451
452 /* BITNUM in bits 31-27 */
453
454 #define BITNUM (OFF_SL_BR_SCALED + 1)
455 { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
456
457 /* Condition code in bits 31-27 */
458
459 #define CC (BITNUM + 1)
460 { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
461
462 /* Control register number in bits 14-0 */
463
464 #define CR_SI (CC + 1)
465 { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
466
467 /* Control register number in next 32 bit word */
468
469 #define CR_LI (CR_SI + 1)
470 { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
471
472 /* A base register in bits 26-22, enclosed in parens */
473
474 #define REG_BASE (CR_LI + 1)
475 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
476
477 /* A base register in bits 26-22, enclosed in parens, with optional ":m"
478 flag in bit 17 (short immediate instructions only) */
479
480 #define REG_BASE_M_SI (REG_BASE + 1)
481 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
482
483 /* A base register in bits 26-22, enclosed in parens, with optional ":m"
484 flag in bit 15 (long immediate and register instructions only) */
485
486 #define REG_BASE_M_LI (REG_BASE_M_SI + 1)
487 { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
488
489 /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
490
491 #define REG_SCALED (REG_BASE_M_LI + 1)
492 { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
493
494 /* Unsigned immediate in bits 4-0, used only for shift instructions */
495
496 #define ROTATE (REG_SCALED + 1)
497 { 5, 0, NULL, NULL, 0 },
498
499 /* Unsigned immediate in bits 9-5, used only for shift instructions */
500 #define ENDMASK (ROTATE + 1)
501 { 5, 5, NULL, NULL, TIC80_OPERAND_ENDMASK },
502
503 };
504
505 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
506
507
508 /* Macros used to generate entries for the opcodes table. */
509
510 #define FIXME 0
511
512 /* Short-Immediate Format Instructions - basic opcode */
513 #define OP_SI(x) (((x) & 0x7F) << 15)
514 #define MASK_SI OP_SI(0x7F)
515
516 /* Long-Immediate Format Instructions - basic opcode */
517 #define OP_LI(x) (((x) & 0x3FF) << 12)
518 #define MASK_LI OP_LI(0x3FF)
519
520 /* Register Format Instructions - basic opcode */
521 #define OP_REG(x) OP_LI(x) /* For readability */
522 #define MASK_REG MASK_LI /* For readability */
523
524 /* The 'n' bit at bit 10 */
525 #define n(x) ((x) << 10)
526
527 /* The 'i' bit at bit 11 */
528 #define i(x) ((x) << 11)
529
530 /* The 'F' bit at bit 27 */
531 #define F(x) ((x) << 27)
532
533 /* The 'E' bit at bit 27 */
534 #define E(x) ((x) << 27)
535
536 /* The 'M' bit at bit 15 in register and long immediate opcodes */
537 #define M_REG(x) ((x) << 15)
538 #define M_LI(x) ((x) << 15)
539
540 /* The 'M' bit at bit 17 in short immediate opcodes */
541 #define M_SI(x) ((x) << 17)
542
543 /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
544 #define SZ_REG(x) ((x) << 13)
545 #define SZ_LI(x) ((x) << 13)
546
547 /* The 'SZ' field at bits 16-15 in short immediate opcodes */
548 #define SZ_SI(x) ((x) << 15)
549
550 /* The 'D' (direct external memory access) bit at bit 10 in long immediate
551 and register opcodes. */
552 #define D(x) ((x) << 10)
553
554 /* The 'S' (scale offset by data size) bit at bit 11 in long immediate
555 and register opcodes. */
556 #define S(x) ((x) << 11)
557
558 /* The 'PD' field at bits 10-9 in floating point instructions */
559 #define PD(x) ((x) << 9)
560
561 /* The 'P2' field at bits 8-7 in floating point instructions */
562 #define P2(x) ((x) << 7)
563
564 /* The 'P1' field at bits 6-5 in floating point instructions */
565 #define P1(x) ((x) << 5)
566
567 /* The 'a' field at bit 16 in vector instructions */
568 #define V_a1(x) ((x) << 16)
569
570 /* The 'a' field at bit 11 in vector instructions */
571 #define V_a0(x) ((x) << 11)
572
573 /* The 'm' field at bit 10 in vector instructions */
574 #define V_m(x) ((x) << 10)
575
576 /* The 'S' field at bit 9 in vector instructions */
577 #define V_S(x) ((x) << 9)
578
579 /* The 'Z' field at bit 8 in vector instructions */
580 #define V_Z(x) ((x) << 8)
581
582 /* The 'p' field at bit 6 in vector instructions */
583 #define V_p(x) ((x) << 6)
584
585 /* The opcode field at bits 21-17 for vector instructions */
586 #define OP_V(x) ((x) << 17)
587 #define MASK_V OP_V(0x1F)
588
589
590 /* The opcode table. Formatted for better readability on a wide screen. Also, all
591 entries with the same mnemonic are sorted so that they are adjacent in the table,
592 allowing the use of a hash table to locate the first of a sequence of opcodes that have
593 a particular name. The short immediate forms also come before the long immediate forms
594 so that the assembler will pick the "best fit" for the size of the operand, except for
595 the case of the PC relative forms, where the long forms come first and are the default
596 forms. */
597
598 const struct tic80_opcode tic80_opcodes[] = {
599
600 /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this
601 specific bit pattern will get disassembled as a nop rather than an rdcr. The
602 mask of all ones ensures that this will happen. */
603
604 {"nop", OP_SI(0x4), ~0, 0, {0} },
605
606 /* The "br" instruction is really "bbz target,r0,31". We put it first so that
607 this specific bit pattern will get disassembled as a br rather than bbz. */
608
609 {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} },
610 {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} },
611 {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} },
612 {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} },
613 {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} },
614 {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} },
615
616 /* Signed integer ADD */
617
618 {"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
619 {"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
620 {"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
621
622 /* Unsigned integer ADD */
623
624 {"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
625 {"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
626 {"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
627
628 /* Bitwise AND */
629
630 {"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
631 {"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
632 {"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
633 {"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
634 {"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
635 {"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
636
637 /* Bitwise AND with ones complement of both sources */
638
639 {"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
640 {"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
641 {"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
642
643 /* Bitwise AND with ones complement of source 1 */
644
645 {"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
646 {"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
647 {"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
648
649 /* Bitwise AND with ones complement of source 2 */
650
651 {"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
652 {"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
653 {"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
654
655 /* Branch Bit One - nonannulled */
656
657 {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
658 {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
659 {"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
660
661 /* Branch Bit One - annulled */
662
663 {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
664 {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
665 {"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
666
667 /* Branch Bit Zero - nonannulled */
668
669 {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
670 {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
671 {"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
672
673 /* Branch Bit Zero - annulled */
674
675 {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} },
676 {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} },
677 {"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} },
678
679 /* Branch Conditional - nonannulled */
680
681 {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
682 {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} },
683 {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} },
684
685 /* Branch Conditional - annulled */
686
687 {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} },
688 {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} },
689 {"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} },
690
691 /* Branch Control Register */
692
693 {"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} },
694 {"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} },
695 {"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} },
696
697 /* Branch and save return - nonannulled */
698
699 {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} },
700 {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} },
701 {"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} },
702
703 /* Branch and save return - annulled */
704
705 {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} },
706 {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} },
707 {"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} },
708
709 /* Send command */
710
711 {"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} },
712 {"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} },
713 {"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} },
714
715 /* Integer compare */
716
717 {"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
718 {"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
719 {"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
720
721 /* Flush data cache subblock - don't clear subblock preset flag */
722
723 {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} },
724 {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} },
725 {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} },
726
727 /* Flush data cache subblock - clear subblock preset flag */
728
729 {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} },
730 {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} },
731 {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} },
732
733 /* Direct load signed data into register */
734
735 {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
736 {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
737 {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
738 {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
739 {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
740 {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
741 {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
742 {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
743
744 /* Direct load unsigned data into register */
745
746 {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
747 {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
748 {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
749 {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
750
751 /* Direct store data into memory */
752
753 {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
754 {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
755 {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
756 {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
757 {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
758 {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
759 {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
760 {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
761
762 /* Emulation stop */
763
764 {"estop", OP_LI(0x3FC), MASK_LI, 0, {0} },
765
766 /* Emulation trap */
767
768 {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} },
769 {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} },
770 {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} },
771
772 /* Floating-point addition */
773
774 {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
775 {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
776 {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
777 {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
778 {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
779 {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
780 {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
781 {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
782
783 /* Floating point compare */
784
785 {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST} },
786 {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST} },
787 {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST} },
788 {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST} },
789 {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
790 {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
791
792 /* Floating point divide */
793
794 {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
795 {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
796 {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
797 {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
798 {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
799 {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
800 {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
801 {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
802
803 /* Floating point multiply */
804
805 {"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
806 {"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
807 {"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_22, REG_DEST} },
808 {"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
809 {"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
810 {"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
811 {"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
812 {"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
813 {"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
814 {"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
815 {"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LUI, REG_22, REG_DEST} },
816 {"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
817
818 /* Convert/Round to Minus Infinity */
819
820 {"frndm.dd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
821 {"frndm.di", OP_REG(0x3E8) | PD(2) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
822 {"frndm.ds", OP_REG(0x3E8) | PD(0) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
823 {"frndm.du", OP_REG(0x3E8) | PD(3) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
824 {"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
825 {"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
826 {"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
827 {"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
828 {"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
829 {"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
830 {"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
831 {"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
832 {"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
833 {"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
834 {"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
835 {"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
836 {"frndm.ud", OP_LI(0x3E9) | PD(1) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
837 {"frndm.ud", OP_REG(0x3E8) | PD(1) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
838 {"frndm.us", OP_LI(0x3E9) | PD(0) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
839 {"frndm.us", OP_REG(0x3E8) | PD(0) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
840
841 /* Convert/Round to Nearest */
842
843 {"frndn.dd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
844 {"frndn.di", OP_REG(0x3E8) | PD(2) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
845 {"frndn.ds", OP_REG(0x3E8) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
846 {"frndn.du", OP_REG(0x3E8) | PD(3) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
847 {"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
848 {"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
849 {"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
850 {"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
851 {"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
852 {"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
853 {"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
854 {"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
855 {"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
856 {"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
857 {"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
858 {"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
859 {"frndn.ud", OP_LI(0x3E9) | PD(1) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
860 {"frndn.ud", OP_REG(0x3E8) | PD(1) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
861 {"frndn.us", OP_LI(0x3E9) | PD(0) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
862 {"frndn.us", OP_REG(0x3E8) | PD(0) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
863
864 /* Convert/Round to Positive Infinity */
865
866 {"frndp.dd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
867 {"frndp.di", OP_REG(0x3E8) | PD(2) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
868 {"frndp.ds", OP_REG(0x3E8) | PD(0) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
869 {"frndp.du", OP_REG(0x3E8) | PD(3) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
870 {"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
871 {"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
872 {"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
873 {"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
874 {"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
875 {"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
876 {"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
877 {"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
878 {"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
879 {"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
880 {"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
881 {"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
882 {"frndp.ud", OP_LI(0x3E9) | PD(1) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
883 {"frndp.ud", OP_REG(0x3E8) | PD(1) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
884 {"frndp.us", OP_LI(0x3E9) | PD(0) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
885 {"frndp.us", OP_REG(0x3E8) | PD(0) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
886
887 /* Convert/Round to Zero */
888
889 {"frndz.dd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
890 {"frndz.di", OP_REG(0x3E8) | PD(2) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
891 {"frndz.ds", OP_REG(0x3E8) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
892 {"frndz.du", OP_REG(0x3E8) | PD(3) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST} },
893 {"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
894 {"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
895 {"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
896 {"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
897 {"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
898 {"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
899 {"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
900 {"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
901 {"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
902 {"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
903 {"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
904 {"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
905 {"frndz.ud", OP_LI(0x3E9) | PD(1) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST_E} },
906 {"frndz.ud", OP_REG(0x3E8) | PD(1) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
907 {"frndz.us", OP_LI(0x3E9) | PD(0) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} },
908 {"frndz.us", OP_REG(0x3E8) | PD(0) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
909
910 /* Floating point square root */
911
912 {"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_DEST_E} },
913 {"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST_E} },
914 {"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST_E} },
915 {"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} },
916 {"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} },
917
918 /* Floating point subtraction */
919
920 { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22_E, REG_DEST_E} },
921 { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0_E, REG_22, REG_DEST_E} },
922 { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22_E, REG_DEST_E} },
923 { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22_E, REG_DEST_E} },
924 { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST_E} },
925 { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST_E} },
926 { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} },
927 { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} },
928
929 /* Illegal instructions */
930
931 {"illop0", OP_SI(0x0), MASK_SI, 0, {0} },
932 {"illopF", 0x1FF << 13, 0x1FF << 13, 0, {0} },
933
934 /* Jump and save return */
935
936 {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} },
937 {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} },
938 {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} },
939 {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} },
940 {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} },
941 {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} },
942
943 /* Load Signed Data Into Register */
944
945 {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
946 {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
947 {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
948 {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
949 {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
950 {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
951 {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} },
952 {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
953 {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
954 {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
955 {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
956 {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
957
958 /* Load Unsigned Data Into Register */
959
960 {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
961 {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
962 {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
963 {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
964 {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
965 {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
966
967 /* Leftmost one */
968
969 {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} },
970
971 /* Bitwise logical OR. Note that "or.tt" and "or" are the same instructions. */
972
973 {"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
974 {"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
975 {"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
976 {"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
977 {"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
978 {"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
979 {"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
980 {"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
981 {"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
982 {"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
983 {"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
984 {"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
985 {"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} },
986 {"or", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} },
987 {"or", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
988
989 /* Read Control Register */
990
991 {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} },
992 {"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} },
993 {"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} },
994
995 /* Rightmost one */
996
997 {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} },
998
999 /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions.
1000 They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */
1001
1002
1003 {"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1004 {"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1005 {"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1006 {"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1007 {"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1008 {"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1009 {"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1010 {"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1011 {"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1012 {"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1013 {"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1014 {"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1015 {"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1016 {"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1017 {"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1018 {"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1019 {"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1020 {"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1021 {"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1022 {"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1023 {"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1024 {"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1025
1026 /* Shift Register Left With Inverted Endmask */
1027
1028 {"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1029 {"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1030 {"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1031 {"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1032 {"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1033 {"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1034 {"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1035 {"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1036 {"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1037 {"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1038 {"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1039 {"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1040 {"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1041 {"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1042 {"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1043 {"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1044
1045 /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions.
1046 They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */
1047
1048 {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1049 {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1050 {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1051 {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1052 {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1053 {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1054 {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1055 {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1056 {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1057 {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1058 {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1059 {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1060 {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1061 {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1062 {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1063 {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1064 {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1065 {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1066 {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1067 {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1068 {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1069 {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1070 {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1071 {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1072 {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1073 {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1074
1075 /* Shift Register Right With Inverted Endmask */
1076
1077 {"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1078 {"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1079 {"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1080 {"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1081 {"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1082 {"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1083 {"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1084 {"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1085 {"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1086 {"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1087 {"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1088 {"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1089 {"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1090 {"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1091 {"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
1092 {"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
1093
1094 /* Store Data into Memory */
1095
1096 {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
1097 {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
1098 {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
1099 {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
1100 {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
1101 {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
1102 {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} },
1103 {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} },
1104 {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
1105 {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} },
1106 {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} },
1107 {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} },
1108
1109 /* Signed Integer Subtract */
1110
1111 {"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
1112 {"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
1113 {"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
1114
1115 /* Unsigned Integer Subtract */
1116
1117 {"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} },
1118 {"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
1119 {"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
1120
1121 /* Write Control Register
1122 Is a special form of the "swcr" instruction so comes before it in the table. */
1123
1124 {"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} },
1125 {"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} },
1126 {"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} },
1127
1128 /* Swap Control Register */
1129
1130 {"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} },
1131 {"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} },
1132 {"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
1133
1134 /* Trap */
1135
1136 {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} },
1137 {"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} },
1138 {"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} },
1139
1140 /* Vector Floating-Point Add */
1141
1142 {"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} },
1143 {"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} },
1144 {"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} },
1145 {"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
1146 {"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
1147
1148 /* Vector Floating-Point Multiply and Add to Accumulator FIXME! This is not yet fully implemented.
1149 From the documentation there appears to be no way to tell the difference between the opcodes for
1150 instructions that have register destinations and instructions that have accumulator destinations.
1151 Further investigation is necessary. Since this isn't critical to getting a TIC80 toolchain up
1152 and running, it is defered until later. */
1153
1154 /* Vector Floating-Point Multiply
1155 Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */
1156
1157 {"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0_E, REG_22_E, REG_22_E} },
1158 {"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22_E, REG_22_E} },
1159 {"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22_E, REG_22_E} },
1160 {"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
1161 {"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
1162
1163 /* Vector Floating-Point Multiply and Subtract from Accumulator
1164 FIXME: See note above for vmac instruction */
1165
1166 /* Vector Floating-Point Subtract Accumulator From Source
1167 FIXME: See note above for vmac instruction */
1168
1169 /* Vector Round With Floating-Point Input
1170 FIXME: See note above for vmac instruction */
1171
1172 /* Vector Round with Integer Input */
1173
1174 {"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22_E}},
1175 {"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}},
1176 {"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}},
1177 {"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
1178 {"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22_E}},
1179 {"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E}},
1180 {"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}},
1181 {"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
1182
1183 /* Vector Floating-Point Subtract */
1184
1185 {"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E} },
1186 {"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E} },
1187 {"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} },
1188 {"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
1189 {"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
1190
1191 /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other
1192 vector instructions so that the disassembler will always print the load/store instruction second for
1193 vector instructions that have two instructions in the same opcode. */
1194
1195 {"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
1196 {"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
1197 {"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
1198 {"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
1199
1200 /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other
1201 vector instructions so that the disassembler will always print the load/store instruction second for
1202 vector instructions that have two instructions in the same opcode. */
1203
1204 {"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
1205 {"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
1206
1207 {"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
1208 {"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
1209 {"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
1210
1211 {"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
1212 {"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
1213 {"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
1214
1215 };
1216
1217 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);
1218