1 /* CPU support. 2 Copyright (C) 1998-2013 Free Software Foundation, Inc. 3 Contributed by Cygnus Solutions. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 /* This file is intended to be included by sim-base.h. 21 22 This file provides an interface between the simulator framework and 23 the selected cpu. */ 24 25 #ifndef SIM_CPU_H 26 #define SIM_CPU_H 27 28 /* Type of function to return an insn name. */ 29 typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int); 30 31 /* Types for register access functions. 32 These routines implement the sim_{fetch,store}_register interface. */ 33 typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int); 34 typedef int (CPUREG_STORE_FN) (sim_cpu *, int, unsigned char *, int); 35 36 /* Types for PC access functions. 37 Some simulators require a functional interface to access the program 38 counter [a macro is insufficient as the PC is kept in a cpu-specific part 39 of the sim_cpu struct]. */ 40 typedef sim_cia (PC_FETCH_FN) (sim_cpu *); 41 typedef void (PC_STORE_FN) (sim_cpu *, sim_cia); 42 43 /* Pseudo baseclass for each cpu. */ 44 45 typedef struct { 46 47 /* Backlink to main state struct. */ 48 SIM_DESC state; 49 #define CPU_STATE(cpu) ((cpu)->base.state) 50 51 /* Processor index within the SD_DESC */ 52 int index; 53 #define CPU_INDEX(cpu) ((cpu)->base.index) 54 55 /* The name of the cpu. */ 56 const char *name; 57 #define CPU_NAME(cpu) ((cpu)->base.name) 58 59 /* Options specific to this cpu. */ 60 struct option_list *options; 61 #define CPU_OPTIONS(cpu) ((cpu)->base.options) 62 63 /* Processor specific core data */ 64 sim_cpu_core core; 65 #define CPU_CORE(cpu) (& (cpu)->base.core) 66 67 /* Number of instructions (used to iterate over CPU_INSN_NAME). */ 68 unsigned int max_insns; 69 #define CPU_MAX_INSNS(cpu) ((cpu)->base.max_insns) 70 71 /* Function to return the name of an insn. */ 72 CPU_INSN_NAME_FN *insn_name; 73 #define CPU_INSN_NAME(cpu) ((cpu)->base.insn_name) 74 75 /* Trace data. See sim-trace.h. */ 76 TRACE_DATA trace_data; 77 #define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data) 78 79 /* Maximum number of debuggable entities. 80 This debugging is not intended for normal use. 81 It is only enabled when the simulator is configured with --with-debug 82 which shouldn't normally be specified. */ 83 #ifndef MAX_DEBUG_VALUES 84 #define MAX_DEBUG_VALUES 4 85 #endif 86 87 /* Boolean array of specified debugging flags. */ 88 char debug_flags[MAX_DEBUG_VALUES]; 89 #define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags) 90 /* Standard values. */ 91 #define DEBUG_INSN_IDX 0 92 #define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */ 93 94 /* Debugging output goes to this or stderr if NULL. 95 We can't store `stderr' here as stderr goes through a callback. */ 96 FILE *debug_file; 97 #define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file) 98 99 /* Profile data. See sim-profile.h. */ 100 PROFILE_DATA profile_data; 101 #define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data) 102 103 #ifdef SIM_HAVE_MODEL 104 /* Machine tables for this cpu. See sim-model.h. */ 105 const MACH *mach; 106 #define CPU_MACH(cpu) ((cpu)->base.mach) 107 /* The selected model. */ 108 const MODEL *model; 109 #define CPU_MODEL(cpu) ((cpu)->base.model) 110 /* Model data (profiling state, etc.). */ 111 void *model_data; 112 #define CPU_MODEL_DATA(cpu) ((cpu)->base.model_data) 113 #endif 114 115 /* Routines to fetch/store registers. */ 116 CPUREG_FETCH_FN *reg_fetch; 117 #define CPU_REG_FETCH(c) ((c)->base.reg_fetch) 118 CPUREG_STORE_FN *reg_store; 119 #define CPU_REG_STORE(c) ((c)->base.reg_store) 120 PC_FETCH_FN *pc_fetch; 121 #define CPU_PC_FETCH(c) ((c)->base.pc_fetch) 122 PC_STORE_FN *pc_store; 123 #define CPU_PC_STORE(c) ((c)->base.pc_store) 124 125 } sim_cpu_base; 126 127 /* Create all cpus. */ 128 extern SIM_RC sim_cpu_alloc_all (SIM_DESC, int, int); 129 /* Create a cpu. */ 130 extern sim_cpu *sim_cpu_alloc (SIM_DESC, int); 131 /* Release resources held by all cpus. */ 132 extern void sim_cpu_free_all (SIM_DESC); 133 /* Release resources held by a cpu. */ 134 extern void sim_cpu_free (sim_cpu *); 135 136 /* Return a pointer to the cpu data for CPU_NAME, or NULL if not found. */ 137 extern sim_cpu *sim_cpu_lookup (SIM_DESC, const char *); 138 139 /* Return prefix to use in cpu specific messages. */ 140 extern const char *sim_cpu_msg_prefix (sim_cpu *); 141 /* Cover fn to sim_io_eprintf. */ 142 extern void sim_io_eprintf_cpu (sim_cpu *, const char *, ...); 143 144 /* Get/set a pc value. */ 145 #define CPU_PC_GET(cpu) ((* CPU_PC_FETCH (cpu)) (cpu)) 146 #define CPU_PC_SET(cpu,newval) ((* CPU_PC_STORE (cpu)) ((cpu), (newval))) 147 /* External interface to accessing the pc. */ 148 sim_cia sim_pc_get (sim_cpu *); 149 void sim_pc_set (sim_cpu *, sim_cia); 150 151 #endif /* SIM_CPU_H */ 152