1package body badger is 2end package body; 3 4package body badger2 is 5end package body badger2; 6 7-- Incorporates Errata 5.4 8 9library ieee; 10use ieee.std_logic_1164.all; 11use ieee.numeric_std.all; 12 13entity accumulator is port ( 14 a: in std_logic_vector(3 downto 0); 15 clk, reset: in std_logic; 16 accum: out std_logic_vector(3 downto 0) 17 ); 18end accumulator; 19 20architecture simple of accumulator is 21 22signal accumL: unsigned(3 downto 0); 23 24begin 25 26 accumulate: process (clk, reset) begin 27 if (reset = '1') then 28 accumL <= "0000"; 29 elsif (clk'event and clk= '1') then 30 accumL <= accumL + to_unsigned(a); 31 end if; 32 end process; 33 34 accum <= std_logic_vector(accumL); 35 36end simple; 37library IEEE; 38use IEEE.std_logic_1164.all; 39use IEEE.std_logic_unsigned.all; 40 41entity adder is port ( 42 a,b : in std_logic_vector (15 downto 0); 43 sum: out std_logic_vector (15 downto 0) 44 ); 45end adder; 46 47architecture dataflow of adder is 48 49begin 50 51 sum <= a + b; 52 53end dataflow; 54library IEEE; 55use IEEE.std_logic_1164.all; 56 57entity pAdderAttr is 58 generic(n : integer := 8); 59 port (a : in std_logic_vector(n - 1 downto 0); 60 b : in std_logic_vector(n - 1 downto 0); 61 cin : in std_logic; 62 sum : out std_logic_vector(n - 1 downto 0); 63 cout : out std_logic); 64end pAdderAttr; 65 66 67architecture loopDemo of pAdderAttr is 68 69begin 70 71 process(a, b, cin) 72 variable carry: std_logic_vector(sum'length downto 0); 73 variable localSum: std_logic_vector(sum'high downto 0); 74 75 begin 76 77 carry(0) := cin; 78 79 for i in sum'reverse_range loop 80 localSum(i) := (a(i) xor b(i)) xor carry(i); 81 carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i))); 82 end loop; 83 84 sum <= localSum; 85 cout <= carry(carry'high - 1); 86 87 end process; 88 89end loopDemo; 90library ieee; 91use ieee.std_logic_1164.all; 92use ieee.numeric_std.all; 93 94entity adder is port ( 95 a,b: in unsigned(3 downto 0); 96 sum: out unsigned(3 downto 0) 97 ); 98end adder; 99 100architecture simple of adder is 101 102begin 103 104 sum <= a + b; 105 106end simple; 107library IEEE; 108use IEEE.std_logic_1164.all; 109 110 111library IEEE; 112use IEEE.std_logic_1164.all; 113 114entity AND2 is port ( 115 i1: in std_logic; 116 i2: in std_logic; 117 y: out std_logic 118 ); 119end AND2; 120 121architecture rtl of AND2 is 122 123begin 124 125 y <= '1' when i1 = '1' and i2 = '1' else '0'; 126 127end rtl; 128library IEEE; 129use IEEE.std_logic_1164.all; 130 131entity asyncLoad is port ( 132 loadVal, d: in std_logic_vector(3 downto 0); 133 clk, load: in std_logic; 134 q: out std_logic_vector(3 downto 0) 135 ); 136end asyncLoad; 137 138architecture rtl of asyncLoad is 139 140begin 141 142 process (clk, load, loadVal) begin 143 if (load = '1') then 144 q <= loadVal; 145 elsif (clk'event and clk = '1' ) then 146 q <= d; 147 end if; 148 end process; 149 150end rtl; 151library IEEE; 152use IEEE.std_logic_1164.all; 153use IEEE.std_logic_unsigned.all; 154 155entity BidirBuf is port ( 156 OE: in std_logic; 157 input: in std_logic_vector; 158 output: out std_logic_vector 159 ); 160end BidirBuf; 161 162architecture behavioral of BidirBuf is 163 164begin 165 166 bidirBuf: process (OE, input) begin 167 if (OE = '1') then 168 output <= input; 169 else 170 output <= (others => 'Z'); 171 end if; 172 end process; 173 174end behavioral; 175library IEEE; 176use IEEE.std_logic_1164.all; 177 178entity BidirCnt is port ( 179 OE: in std_logic; 180 CntEnable: in std_logic; 181 LdCnt: in std_logic; 182 Clk: in std_logic; 183 Rst: in std_logic; 184 Cnt: inout std_logic_vector(3 downto 0) 185 ); 186end BidirCnt; 187 188architecture behavioral of BidirCnt is 189 190 component LoadCnt port ( 191 CntEn: in std_logic; 192 LdCnt: in std_logic; 193 LdData: in std_logic_vector(3 downto 0); 194 Clk: in std_logic; 195 Rst: in std_logic; 196 CntVal: out std_logic_vector(3 downto 0) 197 ); 198 end component; 199 200 component BidirBuf port ( 201 OE: in std_logic; 202 input: in std_logic_vector; 203 output: inout std_logic_vector 204 ); 205 end component; 206 207signal CntVal: std_logic_vector(3 downto 0); 208signal LoadVal: std_logic_vector(3 downto 0); 209 210begin 211 212 u1: loadcnt port map (CntEn => CntEnable, 213 LdCnt => LdCnt, 214 LdData => LoadVal, 215 Clk => Clk, 216 Rst => Rst, 217 CntVal => CntVal 218 ); 219 220 u2: bidirbuf port map (OE => oe, 221 input => CntVal, 222 output => Cnt 223 ); 224 225 LoadVal <= Cnt; 226 227end behavioral; 228library IEEE; 229use IEEE.std_logic_1164.all; 230 231entity BIDIR is port ( 232 ip: in std_logic; 233 oe: in std_logic; 234 op_fb: out std_logic; 235 op: inout std_logic 236 ); 237end BIDIR; 238 239architecture rtl of BIDIR is 240 241begin 242 243 op <= ip when oe = '1' else 'Z'; 244 op_fb <= op; 245 246end rtl; 247 248library IEEE; 249use IEEE.std_logic_1164.all; 250 251use work.primitive.all; 252 253entity bidirbuffer is port ( 254 input: in std_logic; 255 enable: in std_logic; 256 feedback: out std_logic; 257 output: inout std_logic 258 ); 259end bidirbuffer; 260 261architecture structural of bidirbuffer is 262 263begin 264 265 u1: bidir port map (ip => input, 266 oe => enable, 267 op_fb => feedback, 268 op => output 269 ); 270 271end structural; 272library IEEE; 273use IEEE.std_logic_1164.all; 274 275entity clkGen is port ( 276 clk: in std_logic; 277 reset: in std_logic; 278 ClkDiv2, ClkDiv4, 279 ClkDiv6,ClkDiv8: out std_logic 280 ); 281end clkGen; 282 283architecture behav of clkGen is 284 285subtype numClks is std_logic_vector(1 to 4); 286subtype numPatterns is integer range 0 to 11; 287 288type clkTableType is array (numpatterns'low to numPatterns'high) of numClks; 289 290constant clkTable: clkTableType := clkTableType'( 291-- ClkDiv8______ 292-- ClkDiv6_____ | 293-- ClkDiv4____ || 294-- ClkDiv2 __ ||| 295-- |||| 296 "1111", 297 "0111", 298 "1011", 299 "0001", 300 "1100", 301 "0100", 302 "1010", 303 "0010", 304 "1111", 305 "0001", 306 "1001", 307 "0101"); 308 309signal index: numPatterns; 310 311begin 312 313 lookupTable: process (clk, reset) begin 314 if reset = '1' then 315 index <= 0; 316 elsif (clk'event and clk = '1') then 317 if index = numPatterns'high then 318 index <= numPatterns'low; 319 else 320 index <= index + 1; 321 end if; 322 end if; 323 end process; 324 325 (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index); 326 327end behav; 328library ieee; 329use ieee.std_logic_1164.all; 330use ieee.numeric_std.all; 331 332entity counter is port ( 333 clk: in std_logic; 334 enable: in std_logic; 335 reset: in std_logic; 336 count: buffer unsigned(3 downto 0) 337 ); 338end counter; 339 340architecture simple of counter is 341 342begin 343 344 increment: process (clk, reset) begin 345 if reset = '1' then 346 count <= "0000"; 347 elsif(clk'event and clk = '1') then 348 if enable = '1' then 349 count <= count + 1; 350 else 351 count <= count; 352 end if; 353 end if; 354 end process; 355 356end simple; 357library IEEE; 358use IEEE.std_logic_1164.all; 359 360use work.scaleable.all; 361 362entity count8 is port ( 363 clk: in std_logic; 364 rst: in std_logic; 365 count: out std_logic_vector(7 downto 0) 366 ); 367end count8; 368 369architecture structural of count8 is 370 371begin 372 373 u1: scaleUpCnt port map (clk => clk, 374 reset => rst, 375 cnt => count 376 ); 377 378end structural; 379-- Incorporates Errata 5.4 380 381library ieee; 382use ieee.std_logic_1164.all; 383use ieee.numeric_std.all; 384 385entity counter is port ( 386 clk: in std_logic; 387 reset: in std_logic; 388 count: out std_logic_vector(0 to 9) 389 ); 390end counter; 391 392architecture simple of counter is 393 394signal countL: unsigned(0 to 9); 395 396begin 397 398 increment: process (clk, reset) begin 399 if reset = '1' then 400 countL <= to_unsigned(3,10); 401 elsif(clk'event and clk = '1') then 402 countL <= countL + 1; 403 end if; 404 end process; 405 406 count <= std_logic_vector(countL); 407 408end simple; 409-- Incorporates Errata 5.4 410 411library ieee; 412use ieee.std_logic_1164.all; 413use ieee.numeric_std.all; 414 415entity counter is port ( 416 clk: in std_logic; 417 reset: in std_logic; 418 count: out std_logic_vector(9 downto 0) 419 ); 420end counter; 421 422architecture simple of counter is 423 424signal countL: unsigned(9 downto 0); 425 426begin 427 428 increment: process (clk, reset) begin 429 if reset = '1' then 430 countL <= to_unsigned(0,10); 431 elsif(clk'event and clk = '1') then 432 countL <= countL + 1; 433 end if; 434 end process; 435 436 count <= std_logic_vector(countL); 437 438end simple; 439-- Incorporates Errata 5.4 440 441library ieee; 442use ieee.std_logic_1164.all; 443use ieee.numeric_std.all; 444 445entity counter is port ( 446 clk: in std_logic; 447 reset: in std_logic; 448 load: in std_logic; 449 enable: in std_logic; 450 data: in std_logic_vector(3 downto 0); 451 count: out std_logic_vector(3 downto 0) 452 ); 453end counter; 454 455architecture simple of counter is 456 457signal countL: unsigned(3 downto 0); 458 459begin 460 461 increment: process (clk, reset) begin 462 if (reset = '1') then 463 countL <= "0000"; 464 elsif(clk'event and clk = '1') then 465 if (load = '1') then 466 countL <= to_unsigned(data); 467 elsif (enable = '1') then 468 countL <= countL + 1; 469 end if; 470 end if; 471 end process; 472 473 count <= std_logic_vector(countL); 474 475end simple; 476-- Incorporates Errata 5.4 477 478library ieee; 479use ieee.std_logic_1164.all; 480use ieee.numeric_std.all; 481 482entity counter is port ( 483 clk: in std_logic; 484 reset: in std_logic; 485 load: in std_logic; 486 data: in std_logic_vector(3 downto 0); 487 count: out std_logic_vector(3 downto 0) 488 ); 489end counter; 490 491architecture simple of counter is 492 493signal countL: unsigned(3 downto 0); 494 495begin 496 497 increment: process (clk, reset) begin 498 if (reset = '1') then 499 countL <= "0000"; 500 elsif(clk'event and clk = '1') then 501 if (load = '1') then 502 countL <= to_unsigned(data); 503 else 504 countL <= countL + 1; 505 end if; 506 end if; 507 end process; 508 509 count <= std_logic_vector(countL); 510 511end simple; 512library IEEE; 513use IEEE.std_logic_1164.all; 514use IEEE.numeric_std.all; 515 516entity Cnt4Term is port ( 517 clk: in std_logic; 518 Cnt: out std_logic_vector(3 downto 0); 519 TermCnt: out std_logic 520 ); 521end Cnt4Term; 522 523architecture behavioral of Cnt4Term is 524 525signal CntL: unsigned(3 downto 0); 526 527begin 528 529 increment: process begin 530 wait until clk = '1'; 531 CntL <= CntL + 1; 532 end process; 533 534 Cnt <= to_stdlogicvector(CntL); 535 536 TermCnt <= '1' when CntL = "1111" else '0'; 537 538end behavioral; 539 540library IEEE; 541use IEEE.std_logic_1164.all; 542 543entity Counter is port ( 544 clock: in std_logic; 545 Count: out std_logic_vector(3 downto 0) 546 ); 547end Counter; 548 549architecture structural of Counter is 550 551 component Cnt4Term port ( 552 clk: in std_logic; 553 Cnt: out std_logic_vector(3 downto 0); 554 TermCnt: out std_logic); 555 end component; 556 557begin 558 559 u1: Cnt4Term port map (clk => clock, 560 Cnt => Count, 561 TermCnt => open 562 ); 563 564end structural; 565-- Incorporates Errata 5.4 566 567library ieee; 568use ieee.std_logic_1164.all; 569use ieee.numeric_std.all; 570 571entity counter is port ( 572 clk: in std_logic; 573 reset: in std_logic; 574 count: out std_logic_vector(3 downto 0) 575 ); 576end counter; 577 578architecture simple of counter is 579 580signal countL: unsigned(3 downto 0); 581 582begin 583 584 increment: process (clk) begin 585 if(clk'event and clk = '1') then 586 if (reset = '1') then 587 countL <= "0000"; 588 else 589 countL <= countL + 1; 590 end if; 591 end if; 592 end process; 593 594 count <= std_logic_vector(countL); 595 596end simple; 597library IEEE; 598use IEEE.std_logic_1164.all; 599use IEEE.numeric_std.all; 600 601entity convertArith is port ( 602 truncate: out unsigned(3 downto 0); 603 extend: out unsigned(15 downto 0); 604 direction: out unsigned(0 to 7) 605 ); 606end convertArith; 607 608architecture simple of convertArith is 609 610constant Const: unsigned(7 downto 0) := "00111010"; 611 612begin 613 614 truncate <= resize(Const, truncate'length); 615 extend <= resize(Const, extend'length); 616 direction <= resize(Const, direction'length); 617 618end simple; 619library IEEE; 620use IEEE.std_logic_1164.all; 621use IEEE.numeric_std.all; 622 623entity FEWGATES is port ( 624 a,b,c,d: in std_logic; 625 y: out std_logic 626 ); 627end FEWGATES; 628 629architecture concurrent of FEWGATES is 630 631constant THREE: std_logic_vector(1 downto 0) := "11"; 632 633begin 634 635 y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0'; 636 637end concurrent; 638-- incorporates Errata 12.1 639 640library IEEE; 641use IEEE.std_logic_1164.all; 642use IEEE.numeric_std.all; 643 644entity typeConvert is port ( 645 a: out unsigned(7 downto 0) 646 ); 647end typeConvert; 648 649architecture simple of typeConvert is 650 651constant Const: natural := 43; 652 653begin 654 655 a <= To_unsigned(Const,8); 656 657end simple; 658-- Incorporates Errata 5.4 659 660library ieee; 661use ieee.std_logic_1164.all; 662use ieee.numeric_std.all; 663 664entity counter is port ( 665 clk: in std_logic; 666 count: out std_logic_vector(3 downto 0) 667 ); 668end counter; 669 670architecture simple of counter is 671 672signal countL: unsigned(3 downto 0); 673 674begin 675 676 increment: process (clk) begin 677 if (clk'event and clk = '1') then 678 countL <= countL + 1; 679 end if; 680 end process; 681 682 count <= std_logic_vector(countL); 683 684end simple; 685-- Incorporates Errata 5.4 686 687library ieee; 688use ieee.std_logic_1164.all; 689use ieee.numeric_std.all; 690 691entity counter is port ( 692 clk: in std_logic; 693 reset: in std_logic; 694 count: out std_logic_vector(0 to 3) 695 ); 696end counter; 697 698architecture simple of counter is 699 700signal countL: unsigned(0 to 3); 701 702begin 703 704 increment: process (clk, reset) begin 705 if reset = '1' then 706 countL <= "1001"; 707 elsif(clk'event and clk = '1') then 708 countL <= countL + 1; 709 end if; 710 end process; 711 712 count <= std_logic_vector(countL); 713 714end simple; 715library ieee; 716use ieee.std_logic_1164.all; 717use ieee.numeric_std.all; 718 719entity counter is port ( 720 clk: in std_logic; 721 reset: in std_logic; 722 count: out std_logic_vector(3 downto 0) 723 ); 724end counter; 725 726architecture simple of counter is 727 728signal countL: unsigned(3 downto 0); 729 730begin 731 732 increment: process (clk, reset) begin 733 if (reset = '1') then 734 countL <= "0000"; 735 elsif(clk'event and clk = '1') then 736 countL <= countL + "001"; 737 end if; 738 end process; 739 740 count <= std_logic_vector(countL); 741 742end simple; 743-- Incorporates Errata 5.4 744 745library ieee; 746use ieee.std_logic_1164.all; 747use ieee.numeric_std.all; 748 749entity counter is port ( 750 clk: in std_logic; 751 reset: in std_logic; 752 count: out std_logic_vector(3 downto 0) 753 ); 754end counter; 755 756architecture simple of counter is 757 758signal countL: unsigned(3 downto 0); 759 760begin 761 762 increment: process (clk, reset) begin 763 if reset = '1' then 764 countL <= "1001"; 765 elsif(clk'event and clk = '1') then 766 countL <= countL + 1; 767 end if; 768 end process; 769 770 count <= std_logic_vector(countL); 771 772end simple; 773-- Incorporates Errata 5.4 774 775library ieee; 776use ieee.std_logic_1164.all; 777use ieee.numeric_std.all; 778 779entity counter is port ( 780 clk: in std_logic; 781 reset: in std_logic; 782 count: out std_logic_vector(3 downto 0) 783 ); 784end counter; 785 786architecture simple of counter is 787 788signal countL: unsigned(3 downto 0); 789 790begin 791 792 increment: process (clk, reset) begin 793 if (reset = '1') then 794 countL <= "1001"; 795 elsif(clk'event and clk = '1') then 796 countL <= countL + "0001"; 797 end if; 798 end process; 799 800 count <= std_logic_vector(countL); 801 802end simple; 803library IEEE; 804use IEEE.std_logic_1164.all; 805 806use work.decProcs.all; 807 808entity decoder is port ( 809 decIn: in std_logic_vector(1 downto 0); 810 decOut: out std_logic_vector(3 downto 0) 811 ); 812end decoder; 813 814architecture simple of decoder is 815 816begin 817 818 DEC2x4(decIn,decOut); 819 820end simple; 821 822library ieee; 823use ieee.std_logic_1164.all; 824 825entity isa_dec is port 826( 827 dev_adr: in std_logic_vector(19 downto 0); 828 829 decOut_n: out std_logic_vector(5 downto 0) 830 831); 832end isa_dec; 833 834 835architecture synthesis of isa_dec is 836 837 constant CtrlRegRange: std_logic_vector(2 downto 0) := "100"; 838 constant SuperIoRange: std_logic_vector(2 downto 0) := "010"; 839 840 constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000"; 841 constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001"; 842 constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010"; 843 constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011"; 844 constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100"; 845 846 alias sio_dec_n: std_logic is decOut_n(5); 847 alias rst_ctrl_rd_n: std_logic is decOut_n(4); 848 alias atc_stat_rd_n: std_logic is decOut_n(3); 849 alias mgmt_stat_rd_n: std_logic is decOut_n(2); 850 alias io_int_stat_rd_n: std_logic is decOut_n(1); 851 alias int_ctrl_rd_n: std_logic is decOut_n(0); 852 853 alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17); 854 alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0); 855 856begin 857 858 decoder: process (upper, CtrlBits) 859 begin 860 -- Set defaults for outputs - for synthesis reasons. 861 862 sio_dec_n <= '1'; 863 int_ctrl_rd_n <= '1'; 864 io_int_stat_rd_n <= '1'; 865 rst_ctrl_rd_n <= '1'; 866 atc_stat_rd_n <= '1'; 867 mgmt_stat_rd_n <= '1'; 868 869 case upper is 870 871 when SuperIoRange => 872 sio_dec_n <= '0'; 873 874 when CtrlRegRange => 875 876 case CtrlBits is 877 878 when IntCtrlReg => 879 int_ctrl_rd_n <= '0'; 880 881 when IoIntStatReg => 882 io_int_stat_rd_n <= '0'; 883 884 when RstCtrlReg => 885 rst_ctrl_rd_n <= '0'; 886 887 when AtcStatusReg => 888 atc_stat_rd_n <= '0'; 889 890 when MgmtStatusReg => 891 mgmt_stat_rd_n <= '0'; 892 893 when others => 894 null; 895 896 end case; 897 898 when others => 899 null; 900 901 end case; 902 903 end process decoder; 904 905end synthesis; 906library ieee; 907use ieee.std_logic_1164.all; 908 909entity isa_dec is port 910( 911 dev_adr: in std_logic_vector(19 downto 0); 912 913 sio_dec_n: out std_logic; 914 rst_ctrl_rd_n: out std_logic; 915 atc_stat_rd_n: out std_logic; 916 mgmt_stat_rd_n: out std_logic; 917 io_int_stat_rd_n: out std_logic; 918 int_ctrl_rd_n: out std_logic 919); 920end isa_dec; 921 922 923architecture synthesis of isa_dec is 924 925 constant CtrlRegRange: std_logic_vector(2 downto 0) := "100"; 926 constant SuperIoRange: std_logic_vector(2 downto 0) := "010"; 927 928 constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000"; 929 constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001"; 930 constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010"; 931 constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011"; 932 constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100"; 933 934begin 935 936 decoder: process (dev_adr) 937 begin 938 -- Set defaults for outputs 939 940 sio_dec_n <= '1'; 941 int_ctrl_rd_n <= '1'; 942 io_int_stat_rd_n <= '1'; 943 rst_ctrl_rd_n <= '1'; 944 atc_stat_rd_n <= '1'; 945 mgmt_stat_rd_n <= '1'; 946 947 case dev_adr(19 downto 17) is 948 949 when SuperIoRange => 950 sio_dec_n <= '0'; 951 952 when CtrlRegRange => 953 954 case dev_adr(16 downto 0) is 955 956 when IntCtrlReg => 957 int_ctrl_rd_n <= '0'; 958 959 when IoIntStatReg => 960 io_int_stat_rd_n <= '0'; 961 962 when RstCtrlReg => 963 rst_ctrl_rd_n <= '0'; 964 965 when AtcStatusReg => 966 atc_stat_rd_n <= '0'; 967 968 when MgmtStatusReg => 969 mgmt_stat_rd_n <= '0'; 970 971 when others => 972 null; 973 974 end case; 975 976 when others => 977 null; 978 979 end case; 980 981 end process decoder; 982 983end synthesis; 984library ieee; 985use ieee.std_logic_1164.all; 986 987entity isa_dec is port 988( 989 dev_adr: in std_logic_vector(19 downto 0); 990 991 sio_dec_n: out std_logic; 992 rst_ctrl_rd_n: out std_logic; 993 atc_stat_rd_n: out std_logic; 994 mgmt_stat_rd_n: out std_logic; 995 io_int_stat_rd_n:out std_logic; 996 int_ctrl_rd_n: out std_logic 997 ); 998end isa_dec; 999 1000 1001architecture synthesis of isa_dec is 1002 1003 constant CtrlRegRange: std_logic_vector(2 downto 0) := "100"; 1004 constant SuperIoRange: std_logic_vector(2 downto 0) := "010"; 1005 1006 constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000"; 1007 constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001"; 1008 constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010"; 1009 constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011"; 1010 constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100"; 1011 1012begin 1013 sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1'; 1014 1015 int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange) 1016 and (dev_adr(16 downto 0) = IntCtrlReg) else '1'; 1017 1018 io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange) 1019 and (dev_adr(16 downto 0) = IoIntStatReg) else '1'; 1020 1021 rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange) 1022 and (dev_adr(16 downto 0) = RstCtrlReg) else '1'; 1023 1024 atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange) 1025 and (dev_adr(16 downto 0) = AtcStatusReg) else '1'; 1026 1027 mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange) 1028 and (dev_adr(16 downto 0) = MgmtStatusReg) else '1'; 1029 1030 1031end synthesis; 1032library ieee; 1033use ieee.std_logic_1164.all; 1034 1035entity isa_dec is port 1036( 1037 dev_adr: in std_logic_vector(19 downto 0); 1038 cs0_n: in std_logic; 1039 1040 sio_dec_n: out std_logic; 1041 rst_ctrl_rd_n: out std_logic; 1042 atc_stat_rd_n: out std_logic; 1043 mgmt_stat_rd_n: out std_logic; 1044 io_int_stat_rd_n: out std_logic; 1045 int_ctrl_rd_n: out std_logic 1046); 1047end isa_dec; 1048 1049 1050architecture synthesis of isa_dec is 1051 1052 constant CtrlRegRange: std_logic_vector(2 downto 0) := "100"; 1053 constant SuperIoRange: std_logic_vector(2 downto 0) := "010"; 1054 1055 constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000"; 1056 constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001"; 1057 constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010"; 1058 constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011"; 1059 constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100"; 1060 1061begin 1062 1063 decoder: process (dev_adr, cs0_n) 1064 begin 1065 -- Set defaults for outputs - for synthesis reasons. 1066 1067 sio_dec_n <= '1'; 1068 int_ctrl_rd_n <= '1'; 1069 io_int_stat_rd_n <= '1'; 1070 rst_ctrl_rd_n <= '1'; 1071 atc_stat_rd_n <= '1'; 1072 mgmt_stat_rd_n <= '1'; 1073 1074 if (cs0_n = '0') then 1075 case dev_adr(19 downto 17) is 1076 1077 when SuperIoRange => 1078 sio_dec_n <= '0'; 1079 1080 when CtrlRegRange => 1081 1082 case dev_adr(16 downto 0) is 1083 1084 when IntCtrlReg => 1085 int_ctrl_rd_n <= '0'; 1086 1087 when IoIntStatReg => 1088 io_int_stat_rd_n <= '0'; 1089 1090 when RstCtrlReg => 1091 rst_ctrl_rd_n <= '0'; 1092 1093 when AtcStatusReg => 1094 atc_stat_rd_n <= '0'; 1095 1096 when MgmtStatusReg => 1097 mgmt_stat_rd_n <= '0'; 1098 1099 when others => 1100 null; 1101 1102 end case; 1103 1104 when others => 1105 null; 1106 1107 end case; 1108 else 1109 null; 1110 end if; 1111 1112 end process decoder; 1113 1114end synthesis; 1115library ieee; 1116use ieee.std_logic_1164.all; 1117 1118entity isa_dec is port 1119( 1120 dev_adr: in std_logic_vector(19 downto 0); 1121 cs0_n: in std_logic; 1122 1123 sio_dec_n: out std_logic; 1124 rst_ctrl_rd_n: out std_logic; 1125 atc_stat_rd_n: out std_logic; 1126 mgmt_stat_rd_n: out std_logic; 1127 io_int_stat_rd_n: out std_logic; 1128 int_ctrl_rd_n: out std_logic 1129); 1130end isa_dec; 1131 1132 1133architecture synthesis of isa_dec is 1134 1135 constant CtrlRegRange: std_logic_vector(2 downto 0) := "100"; 1136 constant SuperIoRange: std_logic_vector(2 downto 0) := "010"; 1137 1138 constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000"; 1139 constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001"; 1140 constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010"; 1141 constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011"; 1142 constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100"; 1143 1144 signal Lsio_dec_n: std_logic; 1145 signal Lrst_ctrl_rd_n: std_logic; 1146 signal Latc_stat_rd_n: std_logic; 1147 signal Lmgmt_stat_rd_n: std_logic; 1148 signal Lio_int_stat_rd_n: std_logic; 1149 signal Lint_ctrl_rd_n: std_logic; 1150 1151begin 1152 1153 decoder: process (dev_adr) 1154 begin 1155 -- Set defaults for outputs - for synthesis reasons. 1156 1157 Lsio_dec_n <= '1'; 1158 Lint_ctrl_rd_n <= '1'; 1159 Lio_int_stat_rd_n <= '1'; 1160 Lrst_ctrl_rd_n <= '1'; 1161 Latc_stat_rd_n <= '1'; 1162 Lmgmt_stat_rd_n <= '1'; 1163 1164 case dev_adr(19 downto 17) is 1165 1166 when SuperIoRange => 1167 Lsio_dec_n <= '0'; 1168 1169 when CtrlRegRange => 1170 1171 case dev_adr(16 downto 0) is 1172 1173 when IntCtrlReg => 1174 Lint_ctrl_rd_n <= '0'; 1175 1176 when IoIntStatReg => 1177 Lio_int_stat_rd_n <= '0'; 1178 1179 when RstCtrlReg => 1180 Lrst_ctrl_rd_n <= '0'; 1181 1182 when AtcStatusReg => 1183 Latc_stat_rd_n <= '0'; 1184 1185 when MgmtStatusReg => 1186 Lmgmt_stat_rd_n <= '0'; 1187 1188 when others => 1189 null; 1190 1191 end case; 1192 1193 when others => 1194 null; 1195 1196 end case; 1197 1198 end process decoder; 1199 1200 qualify: process (cs0_n) begin 1201 1202 sio_dec_n <= '1'; 1203 int_ctrl_rd_n <= '1'; 1204 io_int_stat_rd_n <= '1'; 1205 rst_ctrl_rd_n <= '1'; 1206 atc_stat_rd_n <= '1'; 1207 mgmt_stat_rd_n <= '1'; 1208 1209 if (cs0_n = '0') then 1210 sio_dec_n <= Lsio_dec_n; 1211 int_ctrl_rd_n <= Lint_ctrl_rd_n; 1212 io_int_stat_rd_n <= Lio_int_stat_rd_n; 1213 rst_ctrl_rd_n <= Lrst_ctrl_rd_n; 1214 atc_stat_rd_n <= Latc_stat_rd_n; 1215 mgmt_stat_rd_n <= Lmgmt_stat_rd_n; 1216 else 1217 null; 1218 end if; 1219 end process qualify; 1220 1221end synthesis; 1222library ieee; 1223use ieee.std_logic_1164.all; 1224 1225entity isa_dec is port 1226( 1227 dev_adr: in std_logic_vector(19 downto 0); 1228 1229 sio_dec_n: out std_logic; 1230 rst_ctrl_rd_n: out std_logic; 1231 atc_stat_rd_n: out std_logic; 1232 mgmt_stat_rd_n: out std_logic; 1233 io_int_stat_rd_n: out std_logic; 1234 int_ctrl_rd_n: out std_logic 1235); 1236end isa_dec; 1237 1238 1239architecture synthesis of isa_dec is 1240 1241 constant CtrlRegRange: std_logic_vector(2 downto 0) := "100"; 1242 constant SuperIoRange: std_logic_vector(2 downto 0) := "010"; 1243 1244 constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000"; 1245 constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001"; 1246 constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010"; 1247 constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011"; 1248 constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100"; 1249 1250begin 1251 1252 decoder: process ( dev_adr) 1253 begin 1254 -- Set defaults for outputs - for synthesis reasons. 1255 1256 sio_dec_n <= '1'; 1257 int_ctrl_rd_n <= '1'; 1258 io_int_stat_rd_n <= '1'; 1259 rst_ctrl_rd_n <= '1'; 1260 atc_stat_rd_n <= '1'; 1261 mgmt_stat_rd_n <= '1'; 1262 1263 if dev_adr(19 downto 17) = SuperIOrange then 1264 1265 sio_dec_n <= '0'; 1266 1267 elsif dev_adr(19 downto 17) = CtrlRegrange then 1268 1269 if dev_adr(16 downto 0) = IntCtrlReg then 1270 1271 int_ctrl_rd_n <= '0'; 1272 1273 elsif dev_adr(16 downto 0)= IoIntStatReg then 1274 1275 io_int_stat_rd_n <= '0'; 1276 1277 elsif dev_adr(16 downto 0) = RstCtrlReg then 1278 1279 rst_ctrl_rd_n <= '0'; 1280 1281 elsif dev_adr(16 downto 0) = AtcStatusReg then 1282 1283 atc_stat_rd_n <= '0'; 1284 1285 elsif dev_adr(16 downto 0) = MgmtStatusReg then 1286 1287 mgmt_stat_rd_n <= '0'; 1288 1289 else 1290 1291 null; 1292 1293 end if; 1294 1295 else 1296 1297 null; 1298 1299 end if; 1300 1301 end process decoder; 1302 1303end synthesis; 1304library IEEE; 1305use IEEE.std_logic_1164.all; 1306 1307package decProcs is 1308 1309 procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0); 1310 decode: out std_logic_vector(3 downto 0) 1311 ); 1312end decProcs; 1313 1314package body decProcs is 1315 1316 procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0); 1317 decode: out std_logic_vector(3 downto 0) 1318 ) is 1319 begin 1320 case inputs is 1321 when "11" => 1322 decode := "1000"; 1323 when "10" => 1324 decode := "0100"; 1325 when "01" => 1326 decode := "0010"; 1327 when "00" => 1328 decode := "0001"; 1329 when others => 1330 decode := "0001"; 1331 end case; 1332 end DEC2x4; 1333 1334end decProcs; 1335library ieee; 1336use ieee.std_logic_1164.all; 1337 1338entity isa_dec is port 1339( 1340 dev_adr: in std_logic_vector(19 downto 0); 1341 1342 sio_dec_n: out std_logic; 1343 rst_ctrl_rd_n: out std_logic; 1344 atc_stat_rd_n: out std_logic; 1345 mgmt_stat_rd_n: out std_logic; 1346 io_int_stat_rd_n:out std_logic; 1347 int_ctrl_rd_n: out std_logic 1348 ); 1349end isa_dec; 1350 1351 1352architecture synthesis of isa_dec is 1353 1354 constant CtrlRegRange: std_logic_vector(2 downto 0) := "100"; 1355 constant SuperIoRange: std_logic_vector(2 downto 0) := "010"; 1356 1357 constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000"; 1358 constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001"; 1359 constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010"; 1360 constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011"; 1361 constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100"; 1362 1363begin 1364 with dev_adr(19 downto 17) select 1365 sio_dec_n <= '0' when SuperIORange, 1366 '1' when others; 1367 1368 with dev_adr(19 downto 0) select 1369 int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg, 1370 '1' when others; 1371 1372 with dev_adr(19 downto 0) select 1373 io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg, 1374 '1' when others; 1375 1376 with dev_adr(19 downto 0) select 1377 rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg, 1378 '1' when others; 1379 1380 with dev_adr(19 downto 0) select 1381 atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg, 1382 '1' when others; 1383 1384 with dev_adr(19 downto 0) select 1385 mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg, 1386 '1' when others; 1387 1388 1389end synthesis; 1390-- Incorporates Errata 5.1 and 5.4 1391 1392library ieee; 1393use ieee.std_logic_1164.all; 1394use ieee.numeric_std.all; 1395 1396entity progPulse is port ( 1397 clk, reset: in std_logic; 1398 loadLength,loadDelay: in std_logic; 1399 data: in std_logic_vector(7 downto 0); 1400 pulse: out std_logic 1401 ); 1402end progPulse; 1403 1404architecture rtl of progPulse is 1405 1406signal delayCnt, pulseCnt: unsigned(7 downto 0); 1407signal delayCntVal, pulseCntVal: unsigned(7 downto 0); 1408signal startPulse, endPulse: std_logic; 1409 1410begin 1411 1412 delayReg: process (clk, reset) begin 1413 if reset = '1' then 1414 delayCntVal <= "11111111"; 1415 elsif clk'event and clk = '1' then 1416 if loadDelay = '1' then 1417 delayCntVal <= unsigned(data); 1418 end if; 1419 end if; 1420 end process; 1421 1422 lengthReg: process (clk, reset) begin 1423 if reset = '1' then 1424 pulseCntVal <= "11111111"; 1425 elsif clk'event and clk = '1' then 1426 if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1) 1427 pulseCntVal <= unsigned(data); 1428 end if; 1429 end if; 1430 end process; 1431 1432 pulseDelay: process (clk, reset) begin 1433 if (reset = '1') then 1434 delayCnt <= "11111111"; 1435 elsif(clk'event and clk = '1') then 1436 if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1) 1437 delayCnt <= delayCntVal; 1438 elsif endPulse = '1' then 1439 delayCnt <= delayCnt - 1; 1440 end if; 1441 end if; 1442 end process; 1443 1444 startPulse <= '1' when delayCnt = "00000000" else '0'; 1445 1446 pulseLength: process (clk, reset) begin 1447 if (reset = '1') then 1448 pulseCnt <= "11111111"; 1449 elsif (clk'event and clk = '1') then 1450 if (loadLength = '1') then 1451 pulseCnt <= pulseCntVal; 1452 elsif (startPulse = '1' and endPulse = '1') then 1453 pulseCnt <= pulseCntVal; 1454 elsif (endPulse = '1') then 1455 pulseCnt <= pulseCnt; 1456 else 1457 pulseCnt <= pulseCnt - 1; 1458 end if; 1459 end if; 1460 end process; 1461 1462 endPulse <= '1' when pulseCnt = "00000000" else '0'; 1463 1464 pulseOutput: process (clk, reset) begin 1465 if (reset = '1') then 1466 pulse <= '0'; 1467 elsif (clk'event and clk = '1') then 1468 if (startPulse = '1') then 1469 pulse <= '1'; 1470 elsif (endPulse = '1') then 1471 pulse <= '0'; 1472 end if; 1473 end if; 1474 end process; 1475 1476 1477end rtl; 1478library IEEE; 1479use IEEE.std_logic_1164.all; 1480 1481entity DFF is port ( 1482 d: in std_logic; 1483 clk: in std_logic; 1484 arst : in std_logic; 1485 q: out std_logic; 1486 ); 1487end DFF; 1488 1489architecture rtl of DFF is 1490 1491begin 1492 1493 process (clk) begin 1494 if arst = '1' then 1495 q <= '0'; 1496 elsif clk'event and clk = '1' then 1497 q <= d; 1498 end if; 1499 end process; 1500 1501end rtl; 1502library IEEE; 1503use IEEE.std_logic_1164.all; 1504 1505entity DFF is port ( 1506 d: in std_logic; 1507 clk: in std_logic; 1508 a,b,c : in std_logic; 1509 q: out std_logic 1510 ); 1511end DFF; 1512 1513architecture rtl of DFF is 1514 1515begin 1516 1517 process (clk, a,b,c) begin 1518 if ((a = '1' and b = '1') or c = '1') then 1519 q <= '0'; 1520 elsif clk'event and clk = '1' then 1521 q <= d; 1522 end if; 1523 end process; 1524 1525end rtl; 1526library IEEE; 1527use IEEE.std_logic_1164.all; 1528 1529entity DFF is port ( 1530 d: in std_logic; 1531 clk: in std_logic; 1532 a,b,c : in std_logic; 1533 q: out std_logic 1534 ); 1535end DFF; 1536 1537architecture rtl of DFF is 1538 1539signal localRst: std_logic; 1540 1541begin 1542 1543 localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0'; 1544 1545 process (clk, localRst) begin 1546 if localRst = '1' then 1547 q <= '0'; 1548 elsif clk'event and clk = '1' then 1549 q <= d; 1550 end if; 1551 end process; 1552 1553end rtl; 1554library IEEE; 1555use IEEE.std_logic_1164.all; 1556 1557entity DFF is port ( 1558 d: in std_logic; 1559 clk: in std_logic; 1560 arst: in std_logic; 1561 q: out std_logic 1562 ); 1563end DFF; 1564 1565architecture rtl of DFF is 1566 1567begin 1568 1569 process (clk, arst) begin 1570 if arst = '1' then 1571 q <= '0'; 1572 elsif clk'event and clk = '1' then 1573 q <= d; 1574 end if; 1575 end process; 1576 1577end rtl; 1578library IEEE; 1579use IEEE.std_logic_1164.all; 1580 1581entity DFF is port ( 1582 d: in std_logic; 1583 clk: in std_logic; 1584 aset : in std_logic; 1585 q: out std_logic 1586 ); 1587end DFF; 1588 1589architecture rtl of DFF is 1590 1591begin 1592 1593 process (clk, aset) begin 1594 if aset = '1' then 1595 q <= '1'; 1596 elsif clk'event and clk = '1' then 1597 q <= d; 1598 end if; 1599 end process; 1600 1601end rtl; 1602library IEEE; 1603use IEEE.std_logic_1164.all; 1604 1605entity DFF is port ( 1606 d1, d2: in std_logic; 1607 clk: in std_logic; 1608 arst : in std_logic; 1609 q1, q2: out std_logic 1610 ); 1611end DFF; 1612 1613architecture rtl of DFF is 1614 1615begin 1616 1617 process (clk, arst) begin 1618 if arst = '1' then 1619 q1 <= '0'; 1620 q2 <= '1'; 1621 elsif clk'event and clk = '1' then 1622 q1 <= d1; 1623 q2 <= d2; 1624 end if; 1625 end process; 1626 1627end rtl; 1628library IEEE; 1629use IEEE.std_logic_1164.all; 1630 1631entity DFF is port ( 1632 d: in std_logic; 1633 clk: in std_logic; 1634 en: in std_logic; 1635 q: out std_logic 1636 ); 1637end DFF; 1638 1639architecture rtl of DFF is 1640 1641begin 1642 1643 process begin 1644 if clk'event and clk = '1' then 1645 if en = '1' then 1646 q <= d; 1647 end if; 1648 end if; 1649 wait on clk; 1650 end process; 1651 1652end rtl; 1653library IEEE; 1654use IEEE.std_logic_1164.all; 1655 1656entity DFFE is port ( 1657 d: in std_logic; 1658 en: in std_logic; 1659 clk: in std_logic; 1660 q: out std_logic 1661 ); 1662end DFFE; 1663 1664architecture rtl of DFFE is 1665 1666begin 1667 1668 process begin 1669 wait until clk = '1'; 1670 if en = '1' then 1671 q <= d; 1672 end if; 1673 end process; 1674 1675end rtl; 1676library IEEE; 1677use IEEE.std_logic_1164.all; 1678 1679entity DFF is port ( 1680 d: in std_logic; 1681 clk: in std_logic; 1682 envector: in std_logic_vector(7 downto 0); 1683 q: out std_logic 1684 ); 1685end DFF; 1686 1687architecture rtl of DFF is 1688 1689begin 1690 1691 process (clk) begin 1692 if clk'event and clk = '1' then 1693 if envector = "10010111" then 1694 q <= d; 1695 end if; 1696 end if; 1697 end process; 1698 1699end rtl; 1700library IEEE; 1701use IEEE.std_logic_1164.all; 1702 1703entity DFF is port ( 1704 d: in std_logic; 1705 clk: in std_logic; 1706 en: in std_logic; 1707 q: out std_logic 1708 ); 1709end DFF; 1710 1711architecture rtl of DFF is 1712 1713begin 1714 1715 process (clk) begin 1716 if clk'event and clk = '1' then 1717 if en = '1' then 1718 q <= d; 1719 end if; 1720 end if; 1721 end process; 1722 1723end rtl; 1724 1725library IEEE; 1726use IEEE.std_logic_1164.all; 1727 1728entity DFFE_SR is port ( 1729 d: in std_logic; 1730 en: in std_logic; 1731 clk: in std_logic; 1732 rst: in std_logic; 1733 prst: in std_logic; 1734 q: out std_logic 1735 ); 1736end DFFE_SR; 1737 1738architecture rtl of DFFE_SR is 1739 1740begin 1741 1742 process (clk, rst, prst) begin 1743 if (prst = '1') then 1744 q <= '1'; 1745 elsif (rst = '1') then 1746 q <= '0'; 1747 elsif (clk'event and clk = '1') then 1748 if (en = '1') then 1749 q <= d; 1750 end if; 1751 end if; 1752 end process; 1753 1754end rtl; 1755 1756 1757library IEEE; 1758use IEEE.std_logic_1164.all; 1759 1760entity flipFlop is port ( 1761 clock, input: in std_logic; 1762 ffOut: out std_logic 1763 ); 1764end flipFlop; 1765 1766architecture simple of flipFlop is 1767 1768 procedure dff (signal clk: in std_logic; 1769 signal d: in std_logic; 1770 signal q: out std_logic 1771 ) is 1772 begin 1773 if clk'event and clk = '1' then 1774 q <= d; 1775 end if; 1776 end procedure dff; 1777 1778begin 1779 1780 dff(clock, input, ffOut); 1781 1782end simple; 1783 1784library IEEE; 1785use IEEE.std_logic_1164.all; 1786 1787entity DFF is port ( 1788 d: in std_logic; 1789 clk: in std_logic; 1790 end: in std_logic; 1791 q: out std_logic 1792 ); 1793end DFF; 1794 1795architecture rtl of DFF is 1796 1797begin 1798 1799 process begin 1800 wait until rising_edge(clk); 1801 if en = '1' then 1802 q <= d; 1803 end if; 1804 end process; 1805 1806end rtl; 1807library IEEE; 1808use IEEE.std_logic_1164.all; 1809 1810entity DFF is port ( 1811 d1, d2: in std_logic; 1812 clk: in std_logic; 1813 srst : in std_logic; 1814 q1, q2: out std_logic 1815 ); 1816end DFF; 1817 1818architecture rtl of DFF is 1819 1820begin 1821 1822 process (clk) begin 1823 if clk'event and clk = '1' then 1824 if srst = '1' then 1825 q1 <= '0'; 1826 q2 <= '1'; 1827 else 1828 q1 <= d1; 1829 q2 <= d2; 1830 end if; 1831 end if; 1832 end process; 1833 1834end rtl; 1835 1836library IEEE; 1837use IEEE.std_logic_1164.all; 1838 1839entity DFFE_SR is port ( 1840 d: in std_logic; 1841 en: in std_logic; 1842 clk: in std_logic; 1843 rst: in std_logic; 1844 prst: in std_logic; 1845 q: out std_logic 1846 ); 1847end DFFE_SR; 1848 1849architecture rtl of DFFE_SR is 1850 1851begin 1852 1853 process (clk, rst, prst) begin 1854 if (rst = '1') then 1855 q <= '0'; 1856 elsif (prst = '1') then 1857 q <= '1'; 1858 elsif (clk'event and clk = '1') then 1859 if (en = '1') then 1860 q <= d; 1861 end if; 1862 end if; 1863 end process; 1864 1865end rtl; 1866 1867 1868library IEEE; 1869use IEEE.std_logic_1164.all; 1870 1871entity DFF is port ( 1872 d: in std_logic; 1873 clk: in std_logic; 1874 srst : in std_logic; 1875 q: out std_logic 1876 ); 1877end DFF; 1878 1879architecture rtl of DFF is 1880 1881begin 1882 1883 process begin 1884 wait until clk = '1'; 1885 if srst = '1' then 1886 q <= '0'; 1887 else 1888 q <= d; 1889 end if; 1890 end process; 1891 1892end rtl; 1893library IEEE; 1894use IEEE.std_logic_1164.all; 1895 1896entity struct_dffe_sr is port ( 1897 d: in std_logic; 1898 clk: in std_logic; 1899 en: in std_logic; 1900 rst,prst: in std_logic; 1901 q: out std_logic 1902 ); 1903end struct_dffe_sr; 1904 1905use work.primitive.all; 1906 1907architecture instance of struct_dffe_sr is 1908 1909begin 1910 1911 ff: dffe_sr port map ( 1912 d => d, 1913 clk => clk, 1914 en => en, 1915 rst => rst, 1916 prst => prst, 1917 q => q 1918 ); 1919 1920end instance; 1921library IEEE; 1922use IEEE.std_logic_1164.all; 1923 1924entity DFF is port ( 1925 d: in std_logic; 1926 clk: in std_logic; 1927 srst : in std_logic; 1928 q: out std_logic 1929 ); 1930end DFF; 1931 1932architecture rtl of DFF is 1933 1934begin 1935 1936 process (clk) begin 1937 if clk'event and clk = '1' then 1938 if srst = '1' then 1939 q <= '0'; 1940 else 1941 q <= d; 1942 end if; 1943 end if; 1944 end process; 1945 1946end rtl; 1947library IEEE; 1948use IEEE.std_logic_1164.all; 1949 1950entity struct_dffe is port ( 1951 d: in std_logic; 1952 clk: in std_logic; 1953 en: in std_logic; 1954 q: out std_logic 1955 ); 1956end struct_dffe; 1957 1958use work.primitive.all; 1959 1960architecture instance of struct_dffe is 1961 1962begin 1963 1964 ff: dffe port map ( 1965 d => d, 1966 clk => clk, 1967 en => en, 1968 q => q 1969 ); 1970 1971end instance; 1972library IEEE; 1973use IEEE.std_logic_1164.all; 1974 1975use work.primitive.all; 1976 1977entity dffTri is 1978 generic (size: integer := 8); 1979 port ( 1980 data: in std_logic_vector(size - 1 downto 0); 1981 clock: in std_logic; 1982 ff_enable: in std_logic; 1983 op_enable: in std_logic; 1984 qout: out std_logic_vector(size - 1 downto 0) 1985 ); 1986end dffTri; 1987 1988architecture parameterize of dffTri is 1989 1990type tribufType is record 1991 ip: std_logic; 1992 oe: std_logic; 1993 op: std_logic; 1994end record; 1995 1996type tribufArrayType is array (integer range <>) of tribufType; 1997 1998signal tri: tribufArrayType(size - 1 downto 0); 1999 2000begin 2001 2002 g0: for i in 0 to size - 1 generate 2003 u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock); 2004 end generate; 2005 2006 g1: for i in 0 to size - 1 generate 2007 u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op); 2008 tri(i).oe <= op_enable; 2009 qout(i) <= tri(i).op; 2010 end generate; 2011 2012end parameterize; 2013library IEEE; 2014use IEEE.std_logic_1164.all; 2015 2016entity DFF is port ( 2017 d: in std_logic; 2018 clk: in std_logic; 2019 en: in std_logic; 2020 q: out std_logic 2021 ); 2022end DFF; 2023 2024architecture rtl of DFF is 2025 2026begin 2027 2028 process begin 2029 wait until clk = '1'; 2030 if en = '1' then 2031 q <= d; 2032 end if; 2033 end process; 2034 2035end rtl; 2036library IEEE; 2037use IEEE.std_logic_1164.all; 2038 2039entity TRIBUF is port ( 2040 ip: in std_logic; 2041 oe: in std_logic; 2042 op: out std_logic bus 2043 ); 2044end TRIBUF; 2045 2046architecture sequential of TRIBUF is 2047 2048begin 2049 2050 enable: process (ip,oe) begin 2051 if (oe = '1') then 2052 op <= ip; 2053 else 2054 op <= null; 2055 end if; 2056 end process; 2057 2058end sequential; 2059library IEEE; 2060use IEEE.std_logic_1164.all; 2061 2062entity DLATCHH is port ( 2063 d: in std_logic; 2064 en: in std_logic; 2065 q: out std_logic 2066 ); 2067end DLATCHH; 2068 2069architecture rtl of DLATCHH is 2070 2071signal qLocal: std_logic; 2072 2073begin 2074 2075 qLocal <= d when en = '1' else qLocal; 2076 2077 q <= qLocal; 2078 2079end rtl; 2080library IEEE; 2081use IEEE.std_logic_1164.all; 2082 2083entity DLATCHH is port ( 2084 d: in std_logic; 2085 en: in std_logic; 2086 q: out std_logic 2087 ); 2088end DLATCHH; 2089 2090architecture rtl of DLATCHH is 2091 2092begin 2093 2094 process (en, d) begin 2095 if en = '1' then 2096 q <= d; 2097 end if; 2098 end process; 2099 2100end rtl; 2101library IEEE; 2102use IEEE.std_logic_1164.all; 2103 2104entity struct_dlatch is port ( 2105 d: in std_logic; 2106 en: in std_logic; 2107 q: out std_logic 2108 ); 2109end struct_dlatch; 2110 2111use work.primitive.all; 2112 2113architecture instance of struct_dlatch is 2114 2115begin 2116 2117 latch: dlatchh port map ( 2118 d => d, 2119 en => en, 2120 q => q 2121 ); 2122 2123end instance; 2124-- Incorporates Errata 5.4 2125 2126library ieee; 2127use ieee.std_logic_1164.all; 2128use ieee.numeric_std.all; 2129 2130entity downCounter is port ( 2131 clk: in std_logic; 2132 reset: in std_logic; 2133 count: out std_logic_vector(3 downto 0) 2134 ); 2135end downCounter; 2136 2137architecture simple of downCounter is 2138 2139signal countL: unsigned(3 downto 0); 2140signal termCnt: std_logic; 2141 2142begin 2143 2144 decrement: process (clk, reset) begin 2145 if (reset = '1') then 2146 countL <= "1011"; -- Reset to 11 2147 termCnt <= '1'; 2148 elsif(clk'event and clk = '1') then 2149 if (termCnt = '1') then 2150 countL <= "1011"; -- Count rolls over to 11 2151 else 2152 countL <= countL - 1; 2153 end if; 2154 2155 if (countL = "0001") then -- Terminal count decoded 1 cycle earlier 2156 termCnt <= '1'; 2157 else 2158 termCnt <= '0'; 2159 end if; 2160 end if; 2161 end process; 2162 2163 count <= std_logic_vector(countL); 2164 2165end simple; 2166library ieee; 2167use ieee.std_logic_1164.all; 2168use ieee.std_logic_unsigned.all; 2169 2170entity compareDC is port ( 2171 addressBus: in std_logic_vector(31 downto 0); 2172 addressHit: out std_logic 2173 ); 2174end compareDC; 2175 2176architecture wontWork of compareDC is 2177 2178begin 2179 2180 compare: process(addressBus) begin 2181 if (addressBus = "011110101011--------------------") then 2182 addressHit <= '1'; 2183 else 2184 addressHit <= '0'; 2185 end if; 2186 end process compare; 2187 2188end wontWork; 2189library ieee; 2190use ieee.std_logic_1164.all; 2191entity encoder is 2192 port (invec: in std_logic_vector(7 downto 0); 2193 enc_out: out std_logic_vector(2 downto 0) 2194 ); 2195end encoder; 2196 2197architecture rtl of encoder is 2198 2199begin 2200 2201 encode: process (invec) begin 2202 case invec is 2203 when "00000001" => 2204 enc_out <= "000"; 2205 2206 when "00000010" => 2207 enc_out <= "001"; 2208 2209 when "00000100" => 2210 enc_out <= "010"; 2211 2212 when "00001000" => 2213 enc_out <= "011"; 2214 2215 when "00010000" => 2216 enc_out <= "100"; 2217 2218 when "00100000" => 2219 enc_out <= "101"; 2220 2221 when "01000000" => 2222 enc_out <= "110"; 2223 2224 when "10000000" => 2225 enc_out <= "111"; 2226 2227 when others => 2228 enc_out <= "000"; 2229 2230 end case; 2231 end process; 2232 2233end rtl; 2234library ieee; 2235use ieee.std_logic_1164.all; 2236 2237entity encoder is 2238 port (invec:in std_logic_vector(7 downto 0); 2239 enc_out:out std_logic_vector(2 downto 0) 2240 ); 2241end encoder; 2242 2243architecture rtl of encoder is 2244begin 2245 process (invec) 2246 begin 2247 if invec(7) = '1' then 2248 enc_out <= "111"; 2249 2250 elsif invec(6) = '1' then 2251 enc_out <= "110"; 2252 2253 elsif invec(5) = '1' then 2254 enc_out <= "101"; 2255 2256 elsif invec(4) = '1' then 2257 enc_out <= "100"; 2258 2259 elsif invec(3) = '1' then 2260 enc_out <= "011"; 2261 2262 elsif invec(2) = '1' then 2263 enc_out <= "010"; 2264 2265 elsif invec(1) = '1' then 2266 enc_out <= "001"; 2267 2268 elsif invec(0) = '1' then 2269 enc_out <= "000"; 2270 2271 else 2272 enc_out <= "000"; 2273 end if; 2274 end process; 2275end rtl; 2276 2277library ieee; 2278use ieee.std_logic_1164.all; 2279entity encoder is 2280 port (invec: in std_logic_vector(7 downto 0); 2281 enc_out: out std_logic_vector(2 downto 0) 2282 ); 2283end encoder; 2284 2285architecture rtl of encoder is 2286 2287begin 2288 enc_out <= "111" when invec(7) = '1' else 2289 "110" when invec(6) = '1' else 2290 "101" when invec(5) = '1' else 2291 "100" when invec(4) = '1' else 2292 "011" when invec(3) = '1' else 2293 "010" when invec(2) = '1' else 2294 "001" when invec(1) = '1' else 2295 "000" when invec(0) = '1' else 2296 "000"; 2297 2298end rtl; 2299-- includes Errata 5.2 2300library ieee; 2301use ieee.std_logic_1164.all; 2302use ieee.numeric_std.all; -- errata 5.2 2303 2304entity compare is port ( 2305 ina: in std_logic_vector (3 downto 0); 2306 inb: in std_logic_vector (2 downto 0); 2307 equal: out std_logic 2308 ); 2309end compare; 2310 2311architecture simple of compare is 2312 2313begin 2314 2315 equalProc: process (ina, inb) begin 2316 if (ina = inb ) then 2317 equal <= '1'; 2318 else 2319 equal <= '0'; 2320 end if; 2321 end process; 2322 2323end simple; 2324library IEEE; 2325use IEEE.std_logic_1164.all; 2326 2327entity LogicFcn is port ( 2328 A: in std_logic; 2329 B: in std_logic; 2330 C: in std_logic; 2331 Y: out std_logic 2332 ); 2333end LogicFcn; 2334 2335architecture behavioral of LogicFcn is 2336 2337begin 2338 2339 fcn: process (A,B,C) begin 2340 2341 if (A = '0' and B = '0') then 2342 Y <= '1'; 2343 elsif C = '1' then 2344 Y <= '1'; 2345 else 2346 Y <= '0'; 2347 end if; 2348 2349 end process; 2350 2351end behavioral; 2352library IEEE; 2353use IEEE.std_logic_1164.all; 2354 2355entity LogicFcn is port ( 2356 A: in std_logic; 2357 B: in std_logic; 2358 C: in std_logic; 2359 Y: out std_logic 2360 ); 2361end LogicFcn; 2362 2363architecture dataflow of LogicFcn is 2364 2365begin 2366 2367 Y <= '1' when (A = '0' AND B = '0') OR 2368 (C = '1') 2369 else '0'; 2370 2371end dataflow; 2372library IEEE; 2373use IEEE.std_logic_1164.all; 2374use work.primitive.all; 2375 2376entity LogicFcn is port ( 2377 A: in std_logic; 2378 B: in std_logic; 2379 C: in std_logic; 2380 Y: out std_logic 2381 ); 2382end LogicFcn; 2383 2384architecture structural of LogicFcn is 2385 2386signal notA, notB, andSignal: std_logic; 2387 2388begin 2389 2390 i1: inverter port map (i => A, 2391 o => notA); 2392 2393 i2: inverter port map (i => B, 2394 o => notB); 2395 2396 a1: and2 port map (i1 => notA, 2397 i2 => notB, 2398 y => andSignal); 2399 2400 o1: or2 port map (i1 => andSignal, 2401 i2 => C, 2402 y => Y); 2403 2404end structural; 2405library IEEE; 2406use IEEE.std_logic_1164.all; 2407 2408entity SimDFF is port ( 2409 D, Clk: in std_logic; 2410 Q: out std_logic 2411 ); 2412end SimDff; 2413 2414architecture SimModel of SimDFF is 2415 2416constant tCQ: time := 8 ns; 2417constant tS: time := 4 ns; 2418constant tH: time := 3 ns; 2419 2420begin 2421 2422 reg: process (Clk, D) begin 2423 2424 -- Assign output tCQ after rising clock edge 2425 if (Clk'event and Clk = '1') then 2426 Q <= D after tCQ; 2427 end if; 2428 2429 -- Check setup time 2430 if (Clk'event and Clk = '1') then 2431 assert (D'last_event >= tS) 2432 report "Setup time violation" 2433 severity Warning; 2434 end if; 2435 2436 -- Check hold time 2437 if (D'event and Clk'stable and Clk = '1') then 2438 assert (D'last_event - Clk'last_event > tH) 2439 report "Hold Time Violation" 2440 severity Warning; 2441 end if; 2442 2443 end process; 2444 2445end simModel; 2446library IEEE; 2447use IEEE.std_logic_1164.all; 2448 2449entity DFF is port ( 2450 d: in std_logic; 2451 clk: in std_logic; 2452 q: out std_logic 2453 ); 2454end DFF; 2455 2456architecture rtl of DFF is 2457 2458begin 2459 2460 process (clk) begin 2461 wait until clk = '1'; 2462 q <= d; 2463 end process; 2464 2465end rtl; 2466library IEEE; 2467use IEEE.std_logic_1164.all; 2468 2469entity DFF is port ( 2470 d: in std_logic; 2471 clk: in std_logic; 2472 q: out std_logic 2473 ); 2474end DFF; 2475 2476architecture rtl of DFF is 2477 2478begin 2479 2480 process begin 2481 wait until clk = '1'; 2482 q <= d; 2483 2484 wait on clk; 2485 end process; 2486 2487end rtl; 2488configuration SimpleGatesCfg of FEWGATES is 2489 2490 for structural 2491 2492 for all: AND2 2493 use entity work.and2(rtl); 2494 end for; 2495 2496 for u3: inverter 2497 use entity work.inverter(rtl); 2498 end for; 2499 2500 for u4: or2 2501 use entity work.or2(rtl); 2502 end for; 2503 2504 end for; 2505 2506end SimpleGatesCfg; 2507configuration SimpleGatesCfg of FEWGATES is 2508 2509 for structural 2510 2511 for u1: and2 2512 use entity work.and2(rtl); 2513 end for; 2514 2515 for u2: and2 2516 use entity work.and2(rtl); 2517 end for; 2518 2519 for u3: inverter 2520 use entity work.inverter(rtl); 2521 end for; 2522 2523 for u4: or2 2524 use entity work.or2(rtl); 2525 end for; 2526 2527 end for; 2528 2529end SimpleGatesCfg; 2530library IEEE; 2531use IEEE.std_logic_1164.all; 2532 2533entity FEWGATES is port ( 2534 a,b,c,d: in std_logic; 2535 y: out std_logic 2536 ); 2537end FEWGATES; 2538 2539use work.and2; 2540use work.or2; 2541use work.inverter; 2542 2543architecture structural of FEWGATES is 2544 2545 component AND2 port ( 2546 i1: in std_logic; 2547 i2: in std_logic; 2548 y: out std_logic 2549 ); 2550 end component; 2551 2552 component OR2 port ( 2553 i1: in std_logic; 2554 i2: in std_logic; 2555 y: out std_logic 2556 ); 2557 end component; 2558 2559 component INVERTER port ( 2560 i: in std_logic; 2561 o: out std_logic 2562 ); 2563 end component; 2564 2565signal a_and_b, c_and_d, not_c_and_d: std_logic; 2566 2567begin 2568 2569 u1: and2 port map (i1 => a , 2570 i2 => b, 2571 y => a_and_b 2572 ); 2573 2574 u2: and2 port map (i1 => c, 2575 i2 => d, 2576 y => c_and_d 2577 ); 2578 2579 u3: inverter port map (i => c_and_d, 2580 o => not_c_and_d); 2581 2582 u4: or2 port map (i1 => a_and_b, 2583 i2 => not_c_and_d, 2584 y => y 2585 ); 2586end structural; 2587library IEEE; 2588use IEEE.std_logic_1164.all; 2589 2590entity FEWGATES is port ( 2591 a,b,c,d: in std_logic; 2592 y: out std_logic 2593 ); 2594end FEWGATES; 2595 2596use work.and2; 2597use work.or2; 2598use work.inverter; 2599 2600architecture structural of FEWGATES is 2601 2602 component AND2 port ( 2603 i1: in std_logic; 2604 i2: in std_logic; 2605 y: out std_logic 2606 ); 2607 end component; 2608 2609 component OR2 port ( 2610 i1: in std_logic; 2611 i2: in std_logic; 2612 y: out std_logic 2613 ); 2614 end component; 2615 2616 component INVERTER port ( 2617 i: in std_logic; 2618 o: out std_logic 2619 ); 2620 end component; 2621 2622signal a_and_b, c_and_d, not_c_and_d: std_logic; 2623 2624-- Configution specifications 2625 2626for all: and2 use entity work.and2(rtl); 2627for u3: inverter use entity work.inverter(rtl); 2628for u4: or2 use entity work.or2(rtl); 2629 2630begin 2631 2632 u1: and2 port map (i1 => a, i2 => b, 2633 y => a_and_b 2634 ); 2635 2636 u2: and2 port map (i1 => c, i2 => d, 2637 y => c_and_d 2638 ); 2639 2640 u3: inverter port map (i => c_and_d, 2641 o => not_c_and_d); 2642 2643 u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d, 2644 y => y 2645 ); 2646end structural; 2647library IEEE; 2648use IEEE.std_logic_1164.all; 2649 2650entity FEWGATES is port ( 2651 a,b,c,d: in std_logic; 2652 y: out std_logic 2653 ); 2654end FEWGATES; 2655 2656use work.GatesPkg.all; 2657 2658architecture structural of FEWGATES is 2659 2660signal a_and_b, c_and_d, not_c_and_d: std_logic; 2661 2662begin 2663 2664 u1: and2 port map (i1 => a , 2665 i2 => b, 2666 y => a_and_b 2667 ); 2668 2669 u2: and2 port map (i1 => c, 2670 i2 => d, 2671 y => c_and_d 2672 ); 2673 2674 u3: inverter port map (i => c_and_d, 2675 o => not_c_and_d); 2676 2677 u4: or2 port map (i1 => a_and_b, 2678 i2 => not_c_and_d, 2679 y => y 2680 ); 2681end structural; 2682library IEEE; 2683use IEEE.std_logic_1164.all; 2684 2685 2686entity FEWGATES is port ( 2687 a,b,c,d: in std_logic; 2688 y: out std_logic 2689 ); 2690end FEWGATES; 2691 2692architecture concurrent of FEWGATES is 2693 2694signal a_and_b, c_and_d, not_c_and_d: std_logic; 2695 2696begin 2697 2698 a_and_b <= '1' when a = '1' and b = '1' else '0'; 2699 c_and_d <= '1' when c = '1' and d = '1' else '0'; 2700 2701 not_c_and_d <= not c_and_d; 2702 2703 y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0'; 2704 2705end concurrent; 2706library IEEE; 2707use IEEE.std_logic_1164.all; 2708 2709package GatesPkg is 2710 2711 component AND2 port ( 2712 i1: in std_logic; 2713 i2: in std_logic; 2714 y: out std_logic 2715 ); 2716 end component; 2717 2718 component OR2 port ( 2719 i1: in std_logic; 2720 i2: in std_logic; 2721 y: out std_logic 2722 ); 2723 end component; 2724 2725 component INVERTER port ( 2726 i: in std_logic; 2727 o: out std_logic 2728 ); 2729 end component; 2730 2731end GatesPkg; 2732library IEEE; 2733use IEEE.std_logic_1164.all; 2734 2735use work.primitive.all; 2736 2737entity FEWGATES is port ( 2738 a,b,c,d: in std_logic; 2739 y: out std_logic 2740 ); 2741end FEWGATES; 2742 2743architecture structural of FEWGATES is 2744 2745signal a_and_b, c_and_d, not_c_and_d: std_logic; 2746 2747begin 2748 2749 u1: and2 port map (i1 => a , 2750 i2 => b, 2751 y => a_and_b 2752 ); 2753 2754 u2: and2 port map (i1 =>c, 2755 i2 => d, 2756 y => c_and_d 2757 ); 2758 2759 u3: inverter port map (a => c_and_d, 2760 y => not_c_and_d); 2761 2762 u4: or2 port map (i1 => a_and_b, 2763 i2 => not_c_and_d, 2764 y => y 2765 ); 2766 2767end structural; 2768library IEEE; 2769use IEEE.std_logic_1164.all; 2770 2771entity AND2 is port ( 2772 i1: in std_logic; 2773 i2: in std_logic; 2774 y: out std_logic 2775 ); 2776end AND2; 2777 2778architecture rtl of AND2 is 2779 2780begin 2781 2782 y <= '1' when i1 = '1' and i2 = '1' else '0'; 2783 2784end rtl; 2785 2786library IEEE; 2787use IEEE.std_logic_1164.all; 2788 2789entity OR2 is port ( 2790 i1: in std_logic; 2791 i2: in std_logic; 2792 y: out std_logic 2793 ); 2794end OR2; 2795 2796architecture rtl of OR2 is 2797 2798begin 2799 2800 y <= '1' when i1 = '1' or i2 = '1' else '0'; 2801 2802end rtl; 2803 2804library IEEE; 2805use IEEE.std_logic_1164.all; 2806 2807entity INVERTER is port ( 2808 i: in std_logic; 2809 o: out std_logic 2810 ); 2811end INVERTER; 2812 2813architecture rtl of INVERTER is 2814 2815begin 2816 2817 o <= not i; 2818 2819end rtl; 2820 2821library IEEE; 2822use IEEE.std_logic_1164.all; 2823 2824entity FEWGATES is port ( 2825 a,b,c,d: in std_logic; 2826 y: out std_logic 2827 ); 2828end FEWGATES; 2829 2830architecture structural of FEWGATES is 2831 2832 component AND2 port ( 2833 i1: in std_logic; 2834 i2: in std_logic; 2835 y: out std_logic 2836 ); 2837 end component; 2838 2839 component OR2 port ( 2840 i1: in std_logic; 2841 i2: in std_logic; 2842 y: out std_logic 2843 ); 2844 end component; 2845 2846 component INVERTER port ( 2847 i: in std_logic; 2848 o: out std_logic 2849 ); 2850 end component; 2851 2852signal a_and_b, c_and_d, not_c_and_d: std_logic; 2853 2854begin 2855 2856 u1: and2 port map (i1 => a , 2857 i2 => b, 2858 y => a_and_b 2859 ); 2860 2861 u2: and2 port map (i1 => c, 2862 i2 => d, 2863 y => c_and_d 2864 ); 2865 2866 u3: inverter port map (i => c_and_d, 2867 o => not_c_and_d); 2868 2869 u4: or2 port map (i1 => a_and_b, 2870 i2 => not_c_and_d, 2871 y => y 2872 ); 2873end structural; 2874library IEEE; 2875use IEEE.std_logic_1164.all; 2876 2877use work.simPrimitives.all; 2878 2879entity simHierarchy is port ( 2880 A, B, Clk: in std_logic; 2881 Y: out std_logic 2882 ); 2883end simHierarchy; 2884 2885architecture hierarchical of simHierarchy is 2886 2887signal ADly, BDly, OrGateDly, ClkDly: std_logic; 2888signal OrGate, FlopOut: std_logic; 2889 2890begin 2891 2892 ADly <= transport A after 2 ns; 2893 BDly <= transport B after 2 ns; 2894 OrGateDly <= transport OrGate after 1.5 ns; 2895 ClkDly <= transport Clk after 1 ns; 2896 2897 u1: OR2 generic map (tPD => 10 ns) 2898 port map ( I1 => ADly, 2899 I2 => BDly, 2900 Y => OrGate 2901 ); 2902 2903 u2: simDFF generic map ( tS => 4 ns, 2904 tH => 3 ns, 2905 tCQ => 8 ns 2906 ) 2907 port map ( D => OrGateDly, 2908 Clk => ClkDly, 2909 Q => FlopOut 2910 ); 2911 2912 Y <= transport FlopOut after 2 ns; 2913 2914end hierarchical; 2915library IEEE; 2916use IEEE.std_logic_1164.all; 2917 2918library IEEE; 2919use IEEE.std_logic_1164.all; 2920 2921entity INVERTER is port ( 2922 i: in std_logic; 2923 o: out std_logic 2924 ); 2925end INVERTER; 2926 2927architecture rtl of INVERTER is 2928 2929begin 2930 2931 o <= not i; 2932 2933end rtl; 2934-------------------------------------------------------------------------------- 2935--| File name : $RCSfile: io1164.vhd $ 2936--| Library : SUPPORT 2937--| Revision : $Revision: 1.1 $ 2938--| Author(s) : Vantage Analysis Systems, Inc; Des Young 2939--| Integration : Des Young 2940--| Creation : Nov 1995 2941--| Status : $State: Exp $ 2942--| 2943--| Purpose : IO routines for std_logic_1164. 2944--| Assumptions : Numbers use radixed character set with no prefix. 2945--| Limitations : Does not read VHDL pound-radixed numbers. 2946--| Known Errors: none 2947--| 2948--| Description: 2949--| This is a modified library. The source is basically that donated by 2950--| Vantage to libutil. Des Young removed std_ulogic_vector support (to 2951--| conform to synthesizable libraries), and added read_oct/hex to integer. 2952--| 2953--| ======================================================================= 2954--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights 2955--| reserved. This package is provided by Vantage Analysis Systems. 2956--| The package may not be sold without the express written consent of 2957--| Vantage Analysis Systems, Inc. 2958--| 2959--| The VHDL for this package may be copied and/or distributed as long as 2960--| this copyright notice is retained in the source and any modifications 2961--| are clearly marked in the History: list. 2962--| 2963--| Title : IO1164 package VHDL source 2964--| Package Name: somelib.IO1164 2965--| File Name : io1164.vhdl 2966--| Author(s) : dbb 2967--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types 2968--| in manner consistent with TEXTIO package. 2969--| * Provides procedures to read and write logic values as 2970--| binary, octal, or hexadecimal values ('X' as appropriate). 2971--| These should be particularly useful for models 2972--| to read in stimulus as 0/1/x or octal or hex. 2973--| Subprograms : 2974--| Notes : 2975--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94 2976--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95 2977--| (This is because that type is not supported for synthesis). 2978--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95 2979--| 2980--| ======================================================================= 2981--| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright. 2982--| ======================================================================= 2983--| 2984-------------------------------------------------------------------------------- 2985 2986library ieee; 2987package io1164 is 2988 2989 --$ !VANTAGE_METACOMMENTS_ON 2990 --$ !VANTAGE_DNA_ON 2991 2992 -- import std_logic package 2993 use ieee.std_logic_1164.all; 2994 2995 -- import textio package 2996 use std.textio.all; 2997 2998 -- 2999 -- the READ and WRITE procedures act similarly to the procedures in the 3000 -- STD.TEXTIO package. for each type, there are two read procedures and 3001 -- one write procedure for converting between character and internal 3002 -- representations of values. each value is represented as the string of 3003 -- characters that you would use in VHDL code. (remember that apostrophes 3004 -- and quotation marks are not used.) input is case-insensitive. output 3005 -- is in upper case. see the following LRM sections for more information: 3006 -- 3007 -- 2.3 - Subprogram Overloading 3008 -- 3.3 - Access Types (STD.TEXTIO.LINE is an access type) 3009 -- 7.3.6 - Allocators (allocators create access values) 3010 -- 14.3 - Package TEXTIO 3011 -- 3012 3013 -- Note that the procedures for std_ulogic will match calls with the value 3014 -- parameter of type std_logic. 3015 3016 -- 3017 -- declare READ procedures to overload like in TEXTIO 3018 -- 3019 procedure read(l: inout line; value: out std_ulogic ; good: out boolean); 3020 procedure read(l: inout line; value: out std_ulogic ); 3021 procedure read(l: inout line; value: out std_logic_vector ; good: out boolean); 3022 procedure read(l: inout line; value: out std_logic_vector ); 3023 3024 -- 3025 -- declare WRITE procedures to overload like in TEXTIO 3026 -- 3027 procedure write(l : inout line ; 3028 value : in std_ulogic ; 3029 justified: in side := right; 3030 field : in width := 0 ); 3031 procedure write(l : inout line ; 3032 value : in std_logic_vector ; 3033 justified: in side := right; 3034 field : in width := 0 ); 3035 3036 -- 3037 -- declare procedures to convert between logic values and octal 3038 -- or hexadecimal ('X' where appropriate). 3039 -- 3040 3041 -- octal / std_logic_vector 3042 procedure read_oct (l : inout line ; 3043 value : out std_logic_vector ; 3044 good : out boolean ); 3045 procedure read_oct (l : inout line ; 3046 value : out std_logic_vector ); 3047 procedure write_oct(l : inout line ; 3048 value : in std_logic_vector ; 3049 justified : in side := right; 3050 field : in width := 0 ); 3051 3052 -- hexadecimal / std_logic_vector 3053 procedure read_hex (l : inout line ; 3054 value : out std_logic_vector ; 3055 good : out boolean ); 3056 procedure read_hex (l : inout line ; 3057 value : out std_logic_vector ); 3058 procedure write_hex(l : inout line ; 3059 value : in std_logic_vector ; 3060 justified : in side := right; 3061 field : in width := 0 ); 3062 3063 -- read a number into an integer 3064 procedure read_oct(l : inout line; 3065 value : out integer; 3066 good : out boolean); 3067 procedure read_oct(l : inout line; 3068 value : out integer); 3069 procedure read_hex(l : inout line; 3070 value : out integer; 3071 good : out boolean); 3072 procedure read_hex(l : inout line; 3073 value : out integer); 3074 3075end io1164; 3076 3077-------------------------------------------------------------------------------- 3078--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved 3079--| This package is provided by Vantage Analysis Systems. 3080--| The package may not be sold without the express written consent of 3081--| Vantage Analysis Systems, Inc. 3082--| 3083--| The VHDL for this package may be copied and/or distributed as long as 3084--| this copyright notice is retained in the source and any modifications 3085--| are clearly marked in the History: list. 3086--| 3087--| Title : IO1164 package body VHDL source 3088--| Package Name: VANTAGE_LOGIC.IO1164 3089--| File Name : io1164.vhdl 3090--| Author(s) : dbb 3091--| Purpose : source for IO1164 package body 3092--| Subprograms : 3093--| Notes : see package declaration 3094--| History : see package declaration 3095-------------------------------------------------------------------------------- 3096 3097package body io1164 is 3098 3099 3100 --$ !VANTAGE_METACOMMENTS_ON 3101 --$ !VANTAGE_DNA_ON 3102 3103 -- define lowercase conversion of characters for canonical comparison 3104 type char2char_t is array (character'low to character'high) of character; 3105 constant lowcase: char2char_t := ( 3106 nul, soh, stx, etx, eot, enq, ack, bel, 3107 bs, ht, lf, vt, ff, cr, so, si, 3108 dle, dc1, dc2, dc3, dc4, nak, syn, etb, 3109 can, em, sub, esc, fsp, gsp, rsp, usp, 3110 3111 ' ', '!', '"', '#', '$', '%', '&', ''', 3112 '(', ')', '*', '+', ',', '-', '.', '/', 3113 '0', '1', '2', '3', '4', '5', '6', '7', 3114 '8', '9', ':', ';', '<', '=', '>', '?', 3115 3116 '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 3117 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 3118 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 3119 'x', 'y', 'z', '[', '\', ']', '^', '_', 3120 3121 '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 3122 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 3123 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 3124 'x', 'y', 'z', '{', '|', '}', '~', del); 3125 3126 -- define conversions between various types 3127 3128 -- logic -> character 3129 type f_logic_to_character_t is 3130 array (std_ulogic'low to std_ulogic'high) of character; 3131 constant f_logic_to_character : f_logic_to_character_t := 3132 ( 3133 'U' => 'U', 3134 'X' => 'X', 3135 '0' => '0', 3136 '1' => '1', 3137 'Z' => 'Z', 3138 'W' => 'W', 3139 'L' => 'L', 3140 'H' => 'H', 3141 '-' => '-' 3142 ); 3143 3144 -- character, integer, logic 3145 3146 constant x_charcode : integer := -1; 3147 constant maxoct_charcode: integer := 7; 3148 constant maxhex_charcode: integer := 15; 3149 constant bad_charcode : integer := integer'left; 3150 3151 type digit2int_t is 3152 array ( character'low to character'high ) of integer; 3153 constant octdigit2int: digit2int_t := ( 3154 '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4, 3155 '5' => 5, '6' => 6, '7' => 7, 3156 'X' | 'x' => x_charcode, others => bad_charcode ); 3157 constant hexdigit2int: digit2int_t := ( 3158 '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4, 3159 '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, 3160 'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12, 3161 'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15, 3162 'X' | 'x' => x_charcode, others => bad_charcode ); 3163 3164 constant oct_bits_per_digit: integer := 3; 3165 constant hex_bits_per_digit: integer := 4; 3166 3167 type int2octdigit_t is 3168 array ( 0 to maxoct_charcode ) of character; 3169 constant int2octdigit: int2octdigit_t := 3170 ( 0 => '0', 1 => '1', 2 => '2', 3 => '3', 3171 4 => '4', 5 => '5', 6 => '6', 7 => '7' ); 3172 3173 type int2hexdigit_t is 3174 array ( 0 to maxhex_charcode ) of character; 3175 constant int2hexdigit: int2hexdigit_t := 3176 ( 0 => '0', 1 => '1', 2 => '2', 3 => '3', 3177 4 => '4', 5 => '5', 6 => '6', 7 => '7', 3178 8 => '8', 9 => '9', 10 => 'A', 11 => 'B', 3179 12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' ); 3180 3181 type oct_logic_vector_t is 3182 array(1 to oct_bits_per_digit) of std_ulogic; 3183 type octint2logic_t is 3184 array (x_charcode to maxoct_charcode) of oct_logic_vector_t; 3185 constant octint2logic : octint2logic_t := ( 3186 ( 'X', 'X', 'X' ), 3187 ( '0', '0', '0' ), 3188 ( '0', '0', '1' ), 3189 ( '0', '1', '0' ), 3190 ( '0', '1', '1' ), 3191 ( '1', '0', '0' ), 3192 ( '1', '0', '1' ), 3193 ( '1', '1', '0' ), 3194 ( '1', '1', '1' ) 3195 ); 3196 3197 type hex_logic_vector_t is 3198 array(1 to hex_bits_per_digit) of std_ulogic; 3199 type hexint2logic_t is 3200 array (x_charcode to maxhex_charcode) of hex_logic_vector_t; 3201 constant hexint2logic : hexint2logic_t := ( 3202 ( 'X', 'X', 'X', 'X' ), 3203 ( '0', '0', '0', '0' ), 3204 ( '0', '0', '0', '1' ), 3205 ( '0', '0', '1', '0' ), 3206 ( '0', '0', '1', '1' ), 3207 ( '0', '1', '0', '0' ), 3208 ( '0', '1', '0', '1' ), 3209 ( '0', '1', '1', '0' ), 3210 ( '0', '1', '1', '1' ), 3211 ( '1', '0', '0', '0' ), 3212 ( '1', '0', '0', '1' ), 3213 ( '1', '0', '1', '0' ), 3214 ( '1', '0', '1', '1' ), 3215 ( '1', '1', '0', '0' ), 3216 ( '1', '1', '0', '1' ), 3217 ( '1', '1', '1', '0' ), 3218 ( '1', '1', '1', '1' ) 3219 ); 3220 3221 ---------------------------------------------------------------------------- 3222 -- READ procedure bodies 3223 -- 3224 -- The strategy for duplicating TEXTIO's overloading of procedures 3225 -- with and without GOOD parameters is to put all the logic in the 3226 -- version with the GOOD parameter and to have the version without 3227 -- GOOD approximate a runtime error by use of an assertion. 3228 -- 3229 ---------------------------------------------------------------------------- 3230 3231 -- 3232 -- std_ulogic 3233 -- note: compatible with std_logic 3234 -- 3235 3236 procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is 3237 3238 variable c : character; -- char read while looping 3239 variable m : line; -- safe copy of L 3240 variable success: boolean := false; -- readable version of GOOD 3241 variable done : boolean := false; -- flag to say done reading chars 3242 3243 begin 3244 3245 -- 3246 -- algorithm: 3247 -- 3248 -- if there are characters in the line 3249 -- save a copy of the line 3250 -- get the next character 3251 -- if got one 3252 -- set value 3253 -- if all ok 3254 -- free temp copy 3255 -- else 3256 -- free passed in line 3257 -- assign copy back to line 3258 -- set GOOD 3259 -- 3260 3261 -- only operate on lines that contain characters 3262 if ( ( l /= null ) and ( l.all'length /= 0 ) ) then 3263 3264 -- save a copy of string in case read fails 3265 m := new string'( l.all ); 3266 3267 -- grab the next character 3268 read( l, c, success ); 3269 3270 -- if read ok 3271 if success then 3272 3273-- 3274-- an issue here is whether lower-case values should be accepted or not 3275-- 3276 3277 -- determine the value 3278 case c is 3279 when 'U' | 'u' => value := 'U'; 3280 when 'X' | 'x' => value := 'X'; 3281 when '0' => value := '0'; 3282 when '1' => value := '1'; 3283 when 'Z' | 'z' => value := 'Z'; 3284 when 'W' | 'w' => value := 'W'; 3285 when 'L' | 'l' => value := 'L'; 3286 when 'H' | 'h' => value := 'H'; 3287 when '-' => value := '-'; 3288 when others => success := false; 3289 end case; 3290 3291 end if; 3292 3293 -- free working storage 3294 if success then 3295 deallocate( m ); 3296 else 3297 deallocate( l ); 3298 l := m; 3299 end if; 3300 3301 end if; -- non null access, non empty string 3302 3303 -- set output parameter 3304 good := success; 3305 3306 end read; 3307 3308 procedure read( l: inout line; value: out std_ulogic ) is 3309 variable success: boolean; -- internal good flag 3310 begin 3311 read( l, value, success ); -- use safe version 3312 assert success 3313 report "IO1164.READ: Unable to read STD_ULOGIC value." 3314 severity error; 3315 end read; 3316 3317 -- 3318 -- std_logic_vector 3319 -- note: NOT compatible with std_ulogic_vector 3320 -- 3321 3322 procedure read(l : inout line ; 3323 value: out std_logic_vector; 3324 good : out boolean ) is 3325 3326 variable m : line ; -- saved copy of L 3327 variable success : boolean := true; -- readable GOOD 3328 variable logic_value : std_logic ; -- value for one array element 3329 variable c : character ; -- read a character 3330 3331 begin 3332 3333 -- 3334 -- algorithm: 3335 -- 3336 -- this procedure strips off leading whitespace, and then calls the 3337 -- READ procedure for each single logic value element in the output 3338 -- array. 3339 -- 3340 3341 -- only operate on lines that contain characters 3342 if ( ( l /= null ) and ( l.all'length /= 0 ) ) then 3343 3344 -- save a copy of string in case read fails 3345 m := new string'( l.all ); 3346 3347 -- loop for each element in output array 3348 for i in value'range loop 3349 3350 -- prohibit internal blanks 3351 if i /= value'left then 3352 if l.all'length = 0 then 3353 success := false; 3354 exit; 3355 end if; 3356 c := l.all(l.all'left); 3357 if c = ' ' or c = ht then 3358 success := false; 3359 exit; 3360 end if; 3361 end if; 3362 3363 -- read the next logic value 3364 read( l, logic_value, success ); 3365 3366 -- stuff the value in if ok, else bail out 3367 if success then 3368 value( i ) := logic_value; 3369 else 3370 exit; 3371 end if; 3372 3373 end loop; -- each element in output array 3374 3375 -- free working storage 3376 if success then 3377 deallocate( m ); 3378 else 3379 deallocate( l ); 3380 l := m; 3381 end if; 3382 3383 elsif ( value'length /= 0 ) then 3384 -- string is empty but the return array has 1+ elements 3385 success := false; 3386 end if; 3387 3388 -- set output parameter 3389 good := success; 3390 3391 end read; 3392 3393 procedure read(l: inout line; value: out std_logic_vector ) is 3394 variable success: boolean; 3395 begin 3396 read( l, value, success ); 3397 assert success 3398 report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value." 3399 severity error; 3400 end read; 3401 3402 ---------------------------------------------------------------------------- 3403 -- WRITE procedure bodies 3404 ---------------------------------------------------------------------------- 3405 3406 -- 3407 -- std_ulogic 3408 -- note: compatible with std_logic 3409 -- 3410 3411 procedure write(l : inout line ; 3412 value : in std_ulogic ; 3413 justified: in side := right; 3414 field : in width := 0 ) is 3415 begin 3416 3417 -- 3418 -- algorithm: 3419 -- 3420 -- just write out the string associated with the enumerated 3421 -- value. 3422 -- 3423 3424 case value is 3425 when 'U' => write( l, character'('U'), justified, field ); 3426 when 'X' => write( l, character'('X'), justified, field ); 3427 when '0' => write( l, character'('0'), justified, field ); 3428 when '1' => write( l, character'('1'), justified, field ); 3429 when 'Z' => write( l, character'('Z'), justified, field ); 3430 when 'W' => write( l, character'('W'), justified, field ); 3431 when 'L' => write( l, character'('L'), justified, field ); 3432 when 'H' => write( l, character'('H'), justified, field ); 3433 when '-' => write( l, character'('-'), justified, field ); 3434 end case; 3435 end write; 3436 3437 -- 3438 -- std_logic_vector 3439 -- note: NOT compatible with std_ulogic_vector 3440 -- 3441 3442 procedure write(l : inout line ; 3443 value : in std_logic_vector ; 3444 justified: in side := right; 3445 field : in width := 0 ) is 3446 3447 variable m: line; -- build up intermediate string 3448 3449 begin 3450 3451 -- 3452 -- algorithm: 3453 -- 3454 -- for each value in array 3455 -- add string representing value to intermediate string 3456 -- write intermediate string to line parameter 3457 -- free intermediate string 3458 -- 3459 3460 -- for each value in array 3461 for i in value'range loop 3462 3463 -- add string representing value to intermediate string 3464 write( m, value( i ) ); 3465 3466 end loop; 3467 3468 -- write intermediate string to line parameter 3469 write( l, m.all, justified, field ); 3470 3471 -- free intermediate string 3472 deallocate( m ); 3473 3474 end write; 3475 3476 3477-------------------------------------------------------------------------------- 3478 3479 ---------------------------------------------------------------------------- 3480 -- procedure bodies for octal and hexadecimal read and write 3481 ---------------------------------------------------------------------------- 3482 3483 -- 3484 -- std_logic_vector/octal 3485 -- note: NOT compatible with std_ulogic_vector 3486 -- 3487 3488 procedure read_oct(l : inout line ; 3489 value : out std_logic_vector; 3490 good : out boolean ) is 3491 3492 variable m : line ; -- safe L 3493 variable success : boolean := true; -- readable GOOD 3494 variable logic_value : std_logic ; -- elem value 3495 variable c : character ; -- char read 3496 variable charcode : integer ; -- char->int 3497 variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit 3498 variable bitpos : integer ; -- in state vec. 3499 begin 3500 3501 -- 3502 -- algorithm: 3503 -- 3504 -- skip over leading blanks, then read a digit 3505 -- and do a conversion into a logic value 3506 -- for each element in array 3507 -- 3508 3509 -- make sure logic array is right size to read this base 3510 success := ( ( value'length rem oct_bits_per_digit ) = 0 ); 3511 if success then 3512 3513 -- only operate on non-empty strings 3514 if ( ( l /= null ) and ( l.all'length /= 0 ) ) then 3515 3516 -- save old copy of string in case read fails 3517 m := new string'( l.all ); 3518 3519 -- pick off leading white space and get first significant char 3520 c := ' '; 3521 while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop 3522 read( l, c, success ); 3523 end loop; 3524 3525 -- turn character into integer 3526 charcode := octdigit2int( c ); 3527 3528 -- not doing any bits yet 3529 bitpos := 0; 3530 3531 -- check for bad first character 3532 if charcode = bad_charcode then 3533 success := false; 3534 else 3535 -- loop through each value in array 3536 oct_logic_vector := octint2logic( charcode ); 3537 for i in value'range loop 3538 3539 -- doing the next bit 3540 bitpos := bitpos + 1; 3541 3542 -- stick the value in 3543 value( i ) := oct_logic_vector( bitpos ); 3544 3545 -- read the next character if we're not at array end 3546 if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then 3547 read( l, c, success ); 3548 if not success then 3549 exit; 3550 end if; 3551 -- turn character into integer 3552 charcode := octdigit2int( c ); 3553 -- check for bad char 3554 if charcode = bad_charcode then 3555 success := false; 3556 exit; 3557 end if; 3558 -- reset bit position 3559 bitpos := 0; 3560 -- turn character code into state array 3561 oct_logic_vector := octint2logic( charcode ); 3562 end if; 3563 3564 end loop; -- each index in return array 3565 3566 end if; -- if bad first character 3567 3568 -- clean up working storage 3569 if success then 3570 deallocate( m ); 3571 else 3572 deallocate( l ); 3573 l := m; 3574 end if; 3575 3576 -- no characters to read for return array that isn't null slice 3577 elsif ( value'length /= 0 ) then 3578 success := false; 3579 end if; -- non null access, non empty string 3580 3581 end if; 3582 3583 -- set out parameter of success 3584 good := success; 3585 3586 end read_oct; 3587 3588 3589 procedure read_oct(l : inout line ; 3590 value : out std_logic_vector) is 3591 variable success: boolean; -- internal good flag 3592 begin 3593 read_oct( l, value, success ); -- use safe version 3594 assert success 3595 report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value." 3596 severity error; 3597 end read_oct; 3598 3599 procedure write_oct(l : inout line ; 3600 value : in std_logic_vector ; 3601 justified: in side := right; 3602 field : in width := 0 ) is 3603 3604 variable m : line ; -- safe copy of L 3605 variable goodlength : boolean ; -- array is ok len for this base 3606 variable isx : boolean ; -- an X in this digit 3607 variable integer_value: integer ; -- accumulate integer value 3608 variable c : character; -- character read 3609 variable charpos : integer ; -- index string being contructed 3610 variable bitpos : integer ; -- bit index inside digit 3611 3612 begin 3613 3614 -- 3615 -- algorithm: 3616 -- 3617 -- make sure this array can be written in this base 3618 -- create a string to place intermediate results 3619 -- initialize counters and flags to beginning of string 3620 -- for each item in array 3621 -- note unknown, else accumulate logic into integer 3622 -- if at this digit's last bit 3623 -- stuff digit just computed into intermediate result 3624 -- reset flags and counters except for charpos 3625 -- write intermediate result into line 3626 -- free work storage 3627 -- 3628 3629 -- make sure this array can be written in this base 3630 goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 ); 3631 assert goodlength 3632 report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3." 3633 severity error; 3634 if goodlength then 3635 3636 -- create a string to place intermediate results 3637 m := new string(1 to ( value'length / oct_bits_per_digit ) ); 3638 3639 -- initialize counters and flags to beginning of string 3640 charpos := 0; 3641 bitpos := 0; 3642 isx := false; 3643 integer_value := 0; 3644 3645 -- for each item in array 3646 for i in value'range loop 3647 3648 -- note unknown, else accumulate logic into integer 3649 case value(i) is 3650 when '0' | 'L' => 3651 integer_value := integer_value * 2; 3652 when '1' | 'H' => 3653 integer_value := ( integer_value * 2 ) + 1; 3654 when others => 3655 isx := true; 3656 end case; 3657 3658 -- see if we've done this digit's last bit 3659 bitpos := bitpos + 1; 3660 if bitpos = oct_bits_per_digit then 3661 3662 -- stuff the digit just computed into the intermediate result 3663 charpos := charpos + 1; 3664 if isx then 3665 m.all(charpos) := 'X'; 3666 else 3667 m.all(charpos) := int2octdigit( integer_value ); 3668 end if; 3669 3670 -- reset flags and counters except for location in string being constructed 3671 bitpos := 0; 3672 isx := false; 3673 integer_value := 0; 3674 3675 end if; 3676 3677 end loop; 3678 3679 -- write intermediate result into line 3680 write( l, m.all, justified, field ); 3681 3682 -- free work storage 3683 deallocate( m ); 3684 3685 end if; 3686 3687 end write_oct; 3688 3689 -- 3690 -- std_logic_vector/hexadecimal 3691 -- note: NOT compatible with std_ulogic_vector 3692 -- 3693 3694 procedure read_hex(l : inout line ; 3695 value : out std_logic_vector; 3696 good : out boolean ) is 3697 3698 variable m : line ; -- safe L 3699 variable success : boolean := true; -- readable GOOD 3700 variable logic_value : std_logic ; -- elem value 3701 variable c : character ; -- char read 3702 variable charcode : integer ; -- char->int 3703 variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit 3704 variable bitpos : integer ; -- in state vec. 3705 begin 3706 3707 -- 3708 -- algorithm: 3709 -- 3710 -- skip over leading blanks, then read a digit 3711 -- and do a conversion into a logic value 3712 -- for each element in array 3713 -- 3714 3715 -- make sure logic array is right size to read this base 3716 success := ( ( value'length rem hex_bits_per_digit ) = 0 ); 3717 if success then 3718 3719 -- only operate on non-empty strings 3720 if ( ( l /= null ) and ( l.all'length /= 0 ) ) then 3721 3722 -- save old copy of string in case read fails 3723 m := new string'( l.all ); 3724 3725 -- pick off leading white space and get first significant char 3726 c := ' '; 3727 while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop 3728 read( l, c, success ); 3729 end loop; 3730 3731 -- turn character into integer 3732 charcode := hexdigit2int( c ); 3733 3734 -- not doing any bits yet 3735 bitpos := 0; 3736 3737 -- check for bad first character 3738 if charcode = bad_charcode then 3739 success := false; 3740 else 3741 -- loop through each value in array 3742 hex_logic_vector := hexint2logic( charcode ); 3743 for i in value'range loop 3744 3745 -- doing the next bit 3746 bitpos := bitpos + 1; 3747 3748 -- stick the value in 3749 value( i ) := hex_logic_vector( bitpos ); 3750 3751 -- read the next character if we're not at array end 3752 if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then 3753 read( l, c, success ); 3754 if not success then 3755 exit; 3756 end if; 3757 -- turn character into integer 3758 charcode := hexdigit2int( c ); 3759 -- check for bad char 3760 if charcode = bad_charcode then 3761 success := false; 3762 exit; 3763 end if; 3764 -- reset bit position 3765 bitpos := 0; 3766 -- turn character code into state array 3767 hex_logic_vector := hexint2logic( charcode ); 3768 end if; 3769 3770 end loop; -- each index in return array 3771 3772 end if; -- if bad first character 3773 3774 -- clean up working storage 3775 if success then 3776 deallocate( m ); 3777 else 3778 deallocate( l ); 3779 l := m; 3780 end if; 3781 3782 -- no characters to read for return array that isn't null slice 3783 elsif ( value'length /= 0 ) then 3784 success := false; 3785 end if; -- non null access, non empty string 3786 3787 end if; 3788 3789 -- set out parameter of success 3790 good := success; 3791 3792 end read_hex; 3793 3794 3795 procedure read_hex(l : inout line ; 3796 value : out std_logic_vector) is 3797 variable success: boolean; -- internal good flag 3798 begin 3799 read_hex( l, value, success ); -- use safe version 3800 assert success 3801 report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value." 3802 severity error; 3803 end read_hex; 3804 3805 procedure write_hex(l : inout line ; 3806 value : in std_logic_vector ; 3807 justified: in side := right; 3808 field : in width := 0 ) is 3809 3810 variable m : line ; -- safe copy of L 3811 variable goodlength : boolean ; -- array is ok len for this base 3812 variable isx : boolean ; -- an X in this digit 3813 variable integer_value: integer ; -- accumulate integer value 3814 variable c : character; -- character read 3815 variable charpos : integer ; -- index string being contructed 3816 variable bitpos : integer ; -- bit index inside digit 3817 3818 begin 3819 3820 -- 3821 -- algorithm: 3822 -- 3823 -- make sure this array can be written in this base 3824 -- create a string to place intermediate results 3825 -- initialize counters and flags to beginning of string 3826 -- for each item in array 3827 -- note unknown, else accumulate logic into integer 3828 -- if at this digit's last bit 3829 -- stuff digit just computed into intermediate result 3830 -- reset flags and counters except for charpos 3831 -- write intermediate result into line 3832 -- free work storage 3833 -- 3834 3835 -- make sure this array can be written in this base 3836 goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 ); 3837 assert goodlength 3838 report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4." 3839 severity error; 3840 if goodlength then 3841 3842 -- create a string to place intermediate results 3843 m := new string(1 to ( value'length / hex_bits_per_digit ) ); 3844 3845 -- initialize counters and flags to beginning of string 3846 charpos := 0; 3847 bitpos := 0; 3848 isx := false; 3849 integer_value := 0; 3850 3851 -- for each item in array 3852 for i in value'range loop 3853 3854 -- note unknown, else accumulate logic into integer 3855 case value(i) is 3856 when '0' | 'L' => 3857 integer_value := integer_value * 2; 3858 when '1' | 'H' => 3859 integer_value := ( integer_value * 2 ) + 1; 3860 when others => 3861 isx := true; 3862 end case; 3863 3864 -- see if we've done this digit's last bit 3865 bitpos := bitpos + 1; 3866 if bitpos = hex_bits_per_digit then 3867 3868 -- stuff the digit just computed into the intermediate result 3869 charpos := charpos + 1; 3870 if isx then 3871 m.all(charpos) := 'X'; 3872 else 3873 m.all(charpos) := int2hexdigit( integer_value ); 3874 end if; 3875 3876 -- reset flags and counters except for location in string being constructed 3877 bitpos := 0; 3878 isx := false; 3879 integer_value := 0; 3880 3881 end if; 3882 3883 end loop; 3884 3885 -- write intermediate result into line 3886 write( l, m.all, justified, field ); 3887 3888 -- free work storage 3889 deallocate( m ); 3890 3891 end if; 3892 3893 end write_hex; 3894 3895------------------------------------------------------------------------------ 3896 3897 ------------------------------------ 3898 -- Read octal/hex numbers to integer 3899 ------------------------------------ 3900 3901 -- 3902 -- Read octal to integer 3903 -- 3904 3905 procedure read_oct(l : inout line; 3906 value : out integer; 3907 good : out boolean) is 3908 3909 variable pos : integer; 3910 variable digit : integer; 3911 variable result : integer := 0; 3912 variable success : boolean := true; 3913 variable c : character; 3914 variable old_l : line := l; 3915 3916 begin 3917 -- algorithm: 3918 -- 3919 -- skip leading white space, read digit, convert 3920 -- into integer 3921 -- 3922 if (l /= NULL) then 3923 -- set pos to start of actual number by skipping white space 3924 pos := l'LEFT; 3925 c := l(pos); 3926 while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop 3927 pos := pos + 1; 3928 c := l(pos); 3929 end loop; 3930 3931 -- check for start of valid number 3932 digit := octdigit2int(l(pos)); 3933 3934 if ((digit = bad_charcode) or (digit = x_charcode)) then 3935 good := FALSE; 3936 return; 3937 else 3938 -- calculate integer value 3939 for i in pos to l'RIGHT loop 3940 digit := octdigit2int(l(pos)); 3941 exit when (digit = bad_charcode) or (digit = x_charcode); 3942 result := (result * 8) + digit; 3943 pos := pos + 1; 3944 end loop; 3945 value := result; 3946 -- shrink line 3947 if (pos > 1) then 3948 l := new string'(old_l(pos to old_l'HIGH)); 3949 deallocate(old_l); 3950 end if; 3951 good := TRUE; 3952 return; 3953 end if; 3954 else 3955 good := FALSE; 3956 end if; 3957 3958 end read_oct; 3959 3960 -- simple version 3961 procedure read_oct(l : inout line; 3962 value : out integer) is 3963 3964 variable success: boolean; -- internal good flag 3965 3966 begin 3967 read_oct( l, value, success ); -- use safe version 3968 assert success 3969 report "IO1164.READ_OCT: Unable to read octal integer value." 3970 severity error; 3971 end read_oct; 3972 3973 3974 -- 3975 -- Read hex to integer 3976 -- 3977 3978 procedure read_hex(l : inout line; 3979 value : out integer; 3980 good : out boolean) is 3981 3982 variable pos : integer; 3983 variable digit : integer; 3984 variable result : integer := 0; 3985 variable success : boolean := true; 3986 variable c : character; 3987 variable old_l : line := l; 3988 3989 begin 3990 -- algorithm: 3991 -- 3992 -- skip leading white space, read digit, convert 3993 -- into integer 3994 -- 3995 if (l /= NULL) then 3996 -- set pos to start of actual number by skipping white space 3997 pos := l'LEFT; 3998 c := l(pos); 3999 while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop 4000 pos := pos + 1; 4001 c := l(pos); 4002 end loop; 4003 4004 -- check for start of valid number 4005 digit := hexdigit2int(l(pos)); 4006 4007 if ((digit = bad_charcode) or (digit = x_charcode)) then 4008 good := FALSE; 4009 return; 4010 else 4011 -- calculate integer value 4012 for i in pos to l'RIGHT loop 4013 digit := hexdigit2int(l(pos)); 4014 exit when (digit = bad_charcode) or (digit = x_charcode); 4015 result := (result * 16) + digit; 4016 pos := pos + 1; 4017 end loop; 4018 value := result; 4019 -- shrink line 4020 if (pos > 1) then 4021 l := new string'(old_l(pos to old_l'HIGH)); 4022 deallocate(old_l); 4023 end if; 4024 good := TRUE; 4025 return; 4026 end if; 4027 else 4028 good := FALSE; 4029 end if; 4030 4031 end read_hex; 4032 4033 -- simple version 4034 procedure read_hex(l : inout line; 4035 value : out integer) is 4036 4037 variable success: boolean; -- internal good flag 4038 4039 begin 4040 read_hex( l, value, success ); -- use safe version 4041 assert success 4042 report "IO1164.READ_HEX: Unable to read hex integer value." 4043 severity error; 4044 end read_hex; 4045 4046end io1164; 4047library IEEE; 4048use IEEE.std_logic_1164.all; 4049use IEEE.numeric_std.all; 4050 4051entity asyncLdCnt is port ( 4052 loadVal: in std_logic_vector(3 downto 0); 4053 clk, load: in std_logic; 4054 q: out std_logic_vector(3 downto 0) 4055 ); 4056end asyncLdCnt; 4057 4058architecture rtl of asyncLdCnt is 4059 4060signal qLocal: unsigned(3 downto 0); 4061 4062begin 4063 4064 process (clk, load, loadVal) begin 4065 if (load = '1') then 4066 qLocal <= to_unsigned(loadVal); 4067 elsif (clk'event and clk = '1' ) then 4068 qLocal <= qLocal + 1; 4069 end if; 4070 end process; 4071 4072 q <= to_stdlogicvector(qLocal); 4073 4074end rtl; 4075library IEEE; 4076use IEEE.std_logic_1164.all; 4077use IEEE.std_logic_unsigned.all; 4078 4079entity LoadCnt is port ( 4080 CntEn: in std_logic; 4081 LdCnt: in std_logic; 4082 LdData: in std_logic_vector(3 downto 0); 4083 Clk: in std_logic; 4084 Rst: in std_logic; 4085 CntVal: out std_logic_vector(3 downto 0) 4086 ); 4087end LoadCnt; 4088 4089architecture behavioral of LoadCnt is 4090 4091signal Cnt: std_logic_vector(3 downto 0); 4092 4093begin 4094 4095 counter: process (Clk, Rst) begin 4096 if Rst = '1' then 4097 Cnt <= (others => '0'); 4098 elsif (Clk'event and Clk = '1') then 4099 if (LdCnt = '1') then 4100 Cnt <= LdData; 4101 elsif (CntEn = '1') then 4102 Cnt <= Cnt + 1; 4103 else 4104 Cnt <= Cnt; 4105 end if; 4106 end if; 4107 end process; 4108 4109 CntVal <= Cnt; 4110 4111end behavioral; 4112library IEEE; 4113use IEEE.std_logic_1164.all; 4114library UTILS; 4115use UTILS.io1164.all; 4116use std.textio.all; 4117 4118entity loadCntTB is 4119end loadCntTB; 4120 4121architecture testbench of loadCntTB is 4122 4123 component loadCnt port ( 4124 data: in std_logic_vector (7 downto 0); 4125 load: in std_logic; 4126 clk: in std_logic; 4127 rst: in std_logic; 4128 q: out std_logic_vector (7 downto 0) 4129 ); 4130 end component; 4131 4132file vectorFile: text is in "vectorfile"; 4133type vectorType is record 4134 data: std_logic_vector(7 downto 0); 4135 load: std_logic; 4136 rst: std_logic; 4137 q: std_logic_vector(7 downto 0); 4138end record; 4139 4140signal testVector: vectorType; 4141signal TestClk: std_logic := '0'; 4142signal Qout: std_logic_vector(7 downto 0); 4143 4144constant ClkPeriod: time := 100 ns; 4145 4146for all: loadCnt use entity work.loadcnt(rtl); 4147 4148begin 4149 4150-- File reading and stimulus application 4151 readVec: process 4152 variable VectorLine: line; 4153 variable VectorValid: boolean; 4154 variable vRst: std_logic; 4155 variable vLoad: std_logic; 4156 variable vData: std_logic_vector(7 downto 0); 4157 variable vQ: std_logic_vector(7 downto 0); 4158 4159 begin 4160 while not endfile (vectorFile) loop 4161 readline(vectorFile, VectorLine); 4162 4163 read(VectorLine, vRst, good => VectorValid); 4164 next when not VectorValid; 4165 read(VectorLine, vLoad); 4166 read(VectorLine, vData); 4167 read(VectorLine, vQ); 4168 4169 wait for ClkPeriod/4; 4170 4171 testVector.Rst <= vRst; 4172 testVector.Load <= vLoad; 4173 testVector.Data <= vData; 4174 testVector.Q <= vQ; 4175 4176 wait for (ClkPeriod/4) * 3; 4177 4178 end loop; 4179 4180 assert false 4181 report "Simulation complete" 4182 severity note; 4183 4184 wait; 4185 4186 end process; 4187 4188-- Free running test clock 4189 TestClk <= not TestClk after ClkPeriod/2; 4190 4191-- Instance of design being tested 4192 u1: loadCnt port map (Data => testVector.Data, 4193 load => testVector.Load, 4194 clk => TestClk, 4195 rst => testVector.Rst, 4196 q => Qout 4197 ); 4198 4199-- Process to verify outputs 4200 verify: process (TestClk) 4201 variable ErrorMsg: line; 4202 begin 4203 if (TestClk'event and TestClk = '0') then 4204 if Qout /= testVector.Q then 4205 write(ErrorMsg, string'("Vector failed ")); 4206 write(ErrorMsg, now); 4207 writeline(output, ErrorMsg); 4208 end if; 4209 end if; 4210 end process; 4211 4212 4213end testbench; 4214library IEEE; 4215use IEEE.std_logic_1164.all; 4216use IEEE.std_logic_unsigned.all; 4217 4218entity loadCnt is port ( 4219 data: in std_logic_vector (7 downto 0); 4220 load: in std_logic; 4221 clk: in std_logic; 4222 rst: in std_logic; 4223 q: out std_logic_vector (7 downto 0) 4224 ); 4225end loadCnt; 4226 4227architecture rtl of loadCnt is 4228 4229signal cnt: std_logic_vector (7 downto 0); 4230 4231begin 4232 4233 counter: process (clk, rst) begin 4234 if (rst = '1') then 4235 cnt <= (others => '0'); 4236 elsif (clk'event and clk = '1') then 4237 if (load = '1') then 4238 cnt <= data; 4239 else 4240 cnt <= cnt + 1; 4241 end if; 4242 end if; 4243 end process; 4244 4245 q <= cnt; 4246 4247end rtl; 4248library IEEE; 4249use IEEE.std_logic_1164.all; 4250use IEEE.std_logic_unsigned.all; 4251 4252entity multiplier is port ( 4253 a,b : in std_logic_vector (15 downto 0); 4254 product: out std_logic_vector (31 downto 0) 4255 ); 4256end multiplier; 4257 4258architecture dataflow of multiplier is 4259 4260begin 4261 4262 product <= a * b; 4263 4264end dataflow; 4265library IEEE; 4266use IEEE.std_logic_1164.all; 4267 4268entity mux is port ( 4269 A, B, Sel: in std_logic; 4270 Y: out std_logic 4271 ); 4272end mux; 4273 4274architecture simModel of mux is 4275 4276-- Delay Constants 4277constant tPD_A: time := 10 ns; 4278constant tPD_B: time := 15 ns; 4279constant tPD_Sel: time := 5 ns; 4280 4281begin 4282 4283 DelayMux: process (A, B, Sel) 4284 4285 variable localY: std_logic; -- Zero delay place holder for Y 4286 4287 begin 4288 4289 -- Zero delay model 4290 case Sel is 4291 when '0' => 4292 localY := A; 4293 when others => 4294 localY := B; 4295 end case; 4296 4297 -- Delay calculation 4298 if (B'event) then 4299 Y <= localY after tPD_B; 4300 elsif (A'event) then 4301 Y <= localY after tPD_A; 4302 else 4303 Y <= localY after tPD_Sel; 4304 end if; 4305 4306 end process; 4307 4308 4309end simModel; 4310library IEEE; 4311use IEEE.std_logic_1164.all; 4312use IEEE.std_logic_unsigned.all; 4313 4314entity ForceShare is port ( 4315 a,b,c,d,e,f: in std_logic_vector (7 downto 0); 4316 result: out std_logic_vector(7 downto 0) 4317 ); 4318end ForceShare; 4319 4320architecture behaviour of ForceShare is 4321 4322begin 4323 4324 sum: process (a,c,b,d,e,f) 4325 begin 4326 4327 if (a + b = "10011010") then 4328 result <= c; 4329 elsif (a + b = "01011001") then 4330 result <= d; 4331 elsif (a + b = "10111011") then 4332 result <= e; 4333 else 4334 result <= f; 4335 end if; 4336 end process; 4337 4338end behaviour; 4339library IEEE; 4340use IEEE.std_logic_1164.all; 4341 4342entity TRIBUF8 is port ( 4343 ip: in std_logic_vector(7 downto 0); 4344 oe: in std_logic; 4345 op: out std_logic_vector(7 downto 0) 4346 ); 4347end TRIBUF8; 4348 4349architecture concurrent of TRIBUF8 is 4350 4351begin 4352 4353 op <= ip when oe = '1' else (others => 'Z'); 4354 4355end concurrent; 4356library IEEE; 4357use IEEE.std_logic_1164.all; 4358 4359entity TRIBUF is port ( 4360 ip: in std_logic; 4361 oe: in std_logic; 4362 op: out std_logic 4363 ); 4364end TRIBUF; 4365 4366architecture concurrent of TRIBUF is 4367 4368begin 4369 4370 op <= ip when oe = '1' else 'Z'; 4371 4372end concurrent; 4373library IEEE; 4374use IEEE.std_logic_1164.all; 4375 4376entity TRIBUF8 is port ( 4377 ip: in std_logic_vector(7 downto 0); 4378 oe: in std_logic; 4379 op: out std_logic_vector(7 downto 0) 4380 ); 4381end TRIBUF8; 4382 4383architecture sequential of TRIBUF8 is 4384 4385begin 4386 4387 enable: process (ip,oe) begin 4388 if (oe = '1') then 4389 op <= ip; 4390 else 4391 op <= (others => 'Z'); 4392 end if; 4393 end process; 4394 4395end sequential; 4396library IEEE; 4397use IEEE.std_logic_1164.all; 4398 4399entity TRIBUF is port ( 4400 ip: in bit; 4401 oe: in bit; 4402 op: out bit 4403 ); 4404end TRIBUF; 4405 4406architecture sequential of TRIBUF is 4407 4408begin 4409 4410 enable: process (ip,oe) begin 4411 if (oe = '1') then 4412 op <= ip; 4413 else 4414 op <= null; 4415 end if; 4416 end process; 4417 4418end sequential; 4419library IEEE; 4420use IEEE.std_logic_1164.all; 4421 4422entity TRIBUF is port ( 4423 ip: in std_logic; 4424 oe: in std_logic; 4425 op: out std_logic 4426 ); 4427end TRIBUF; 4428 4429architecture sequential of TRIBUF is 4430 4431begin 4432 4433 enable: process (ip,oe) begin 4434 if (oe = '1') then 4435 op <= ip; 4436 else 4437 op <= 'Z'; 4438 end if; 4439 end process; 4440 4441end sequential; 4442library IEEE; 4443use IEEE.std_logic_1164.all; 4444 4445use work.primitive.all; 4446 4447entity tribuffer is port ( 4448 input: in std_logic; 4449 enable: in std_logic; 4450 output: out std_logic 4451 ); 4452end tribuffer; 4453 4454architecture structural of tribuffer is 4455 4456begin 4457 4458 u1: tribuf port map (ip => input, 4459 oe => enable, 4460 op => output 4461 ); 4462 4463end structural; 4464library ieee; 4465use ieee.std_logic_1164.all; 4466 4467use work.primitive.all; 4468 4469entity oddParityGen is 4470 generic ( width : integer := 8 ); 4471 port (ad: in std_logic_vector (width - 1 downto 0); 4472 oddParity : out std_logic ) ; 4473end oddParityGen; 4474 4475architecture scaleable of oddParityGen is 4476 4477signal genXor: std_logic_vector(ad'range); 4478 4479begin 4480 4481 genXOR(0) <= '0'; 4482 4483 parTree: for i in 1 to ad'high generate 4484 x1: xor2 port map (i1 => genXor(i - 1), 4485 i2 => ad(i - 1), 4486 y => genXor(i) 4487 ); 4488 end generate; 4489 4490 oddParity <= genXor(ad'high) ; 4491 4492end scaleable ; 4493library ieee; 4494use ieee.std_logic_1164.all; 4495 4496entity oddParityLoop is 4497 generic ( width : integer := 8 ); 4498 port (ad: in std_logic_vector (width - 1 downto 0); 4499 oddParity : out std_logic ) ; 4500end oddParityLoop ; 4501 4502architecture scaleable of oddParityLoop is 4503begin 4504 4505 process (ad) 4506 variable loopXor: std_logic; 4507 begin 4508 loopXor := '0'; 4509 4510 for i in 0 to width -1 loop 4511 loopXor := loopXor xor ad( i ) ; 4512 end loop ; 4513 4514 oddParity <= loopXor ; 4515 4516 end process; 4517 4518end scaleable ; 4519library IEEE; 4520use IEEE.std_logic_1164.all; 4521 4522library IEEE; 4523use IEEE.std_logic_1164.all; 4524 4525entity OR2 is port ( 4526 i1: in std_logic; 4527 i2: in std_logic; 4528 y: out std_logic 4529 ); 4530end OR2; 4531 4532architecture rtl of OR2 is 4533 4534begin 4535 4536 y <= '1' when i1 = '1' or i2 = '1' else '0'; 4537 4538end rtl; 4539library IEEE; 4540USE IEEE.std_logic_1164.all; 4541 4542 4543entity OR2 is port ( 4544 I1, I2: in std_logic; 4545 Y: out std_logic 4546 ); 4547end OR2; 4548 4549architecture simple of OR2 is 4550 4551begin 4552 4553 Y <= I1 OR I2 after 10 ns; 4554 4555end simple; 4556library IEEE; 4557USE IEEE.std_logic_1164.all; 4558 4559package simPrimitives is 4560 4561 component OR2 4562 generic (tPD: time := 1 ns); 4563 4564 port (I1, I2: in std_logic; 4565 Y: out std_logic 4566 ); 4567 end component; 4568 4569end simPrimitives; 4570 4571 4572library IEEE; 4573USE IEEE.std_logic_1164.all; 4574 4575entity OR2 is 4576 generic (tPD: time := 1 ns); 4577 4578 port (I1, I2: in std_logic; 4579 Y: out std_logic 4580 ); 4581end OR2; 4582 4583architecture simple of OR2 is 4584 4585begin 4586 4587 Y <= I1 OR I2 after tPD; 4588 4589end simple; 4590library ieee; 4591use ieee.std_logic_1164.all; 4592use ieee.numeric_std.all; 4593 4594entity adder is port ( 4595 a,b: in std_logic_vector(3 downto 0); 4596 sum: out std_logic_vector(3 downto 0); 4597 overflow: out std_logic 4598 ); 4599end adder; 4600 4601architecture concat of adder is 4602 4603signal localSum: std_logic_vector(4 downto 0); 4604 4605begin 4606 4607 localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b)); 4608 4609 sum <= localSum(3 downto 0); 4610 overflow <= localSum(4); 4611 4612end concat; 4613library IEEE; 4614use IEEE.std_logic_1164.all; 4615 4616use work.primitive.all; 4617 4618entity paramDFF is 4619 generic (size: integer := 8); 4620 port ( 4621 data: in std_logic_vector(size - 1 downto 0); 4622 clock: in std_logic; 4623 reset: in std_logic; 4624 ff_enable: in std_logic; 4625 op_enable: in std_logic; 4626 qout: out std_logic_vector(size - 1 downto 0) 4627 ); 4628end paramDFF; 4629 4630architecture parameterize of paramDFF is 4631 4632signal reg: std_logic_vector(size - 1 downto 0); 4633 4634begin 4635 4636 u1: pDFFE generic map (n => size) 4637 port map (d => data, 4638 clk =>clock, 4639 rst => reset, 4640 en => ff_enable, 4641 q => reg 4642 ); 4643 u2: pTRIBUF generic map (n => size) 4644 port map (ip => reg, 4645 oe => op_enable, 4646 op => qout 4647 ); 4648 4649end paramterize; 4650library ieee; 4651use ieee.std_logic_1164.all; 4652 4653use work.primitive.all; 4654 4655entity oddParityGen is 4656 generic ( width : integer := 32 ); 4657 port (ad: in std_logic_vector (width - 1 downto 0); 4658 oddParity : out std_logic ) ; 4659end oddParityGen; 4660 4661architecture scaleable of oddParityGen is 4662 4663signal genXor: std_logic_vector(ad'range); 4664 4665signal one: std_logic := '1'; 4666 4667begin 4668 4669 parTree: for i in ad'range generate 4670 g0: if i = 0 generate 4671 x0: xor2 port map (i1 => one, 4672 i2 => one, 4673 y => genXor(0) 4674 ); 4675 end generate; 4676 4677 g1: if i > 0 and i <= ad'high generate 4678 x1: xor2 port map (i1 => genXor(i - 1), 4679 i2 => ad(i - 1), 4680 y => genXor(i) 4681 ); 4682 end generate; 4683 4684 end generate; 4685 4686 oddParity <= genXor(ad'high) ; 4687 4688end scaleable ; 4689library ieee; 4690use ieee.std_logic_1164.all; 4691 4692use work.primitive.all; 4693 4694entity oddParityGen is 4695 generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2 4696 port (ad: in std_logic_vector (width - 1 downto 0); 4697 oddParity : out std_logic ) ; 4698end oddParityGen; 4699 4700architecture scaleable of oddParityGen is 4701 4702signal stage0: std_logic_vector(31 downto 0); 4703signal stage1: std_logic_vector(15 downto 0); 4704signal stage2: std_logic_vector(7 downto 0); 4705signal stage3: std_logic_vector(3 downto 0); 4706signal stage4: std_logic_vector(1 downto 0); 4707 4708begin 4709 4710 g4: for i in stage4'range generate 4711 g41: if (ad'length > 2) generate 4712 x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i)); 4713 end generate; 4714 end generate; 4715 4716 g3: for i in stage3'range generate 4717 g31: if (ad'length > 4) generate 4718 x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i)); 4719 end generate; 4720 end generate; 4721 4722 g2: for i in stage2'range generate 4723 g21: if (ad'length > 8) generate 4724 x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i)); 4725 end generate; 4726 end generate; 4727 4728 g1: for i in stage1'range generate 4729 g11: if (ad'length > 16) generate 4730 x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i)); 4731 end generate; 4732 end generate; 4733 4734 4735 s1: for i in ad'range generate 4736 s14: if (ad'length = 2) generate 4737 stage4(i) <= ad(i); 4738 end generate; 4739 4740 s13: if (ad'length = 4) generate 4741 stage3(i) <= ad(i); 4742 end generate; 4743 4744 s12: if (ad'length = 8) generate 4745 stage2(i) <= ad(i); 4746 end generate; 4747 4748 s11: if (ad'length = 16) generate 4749 stage1(i) <= ad(i); 4750 end generate; 4751 4752 s10: if (ad'length = 32) generate 4753 stage0(i) <= ad(i); 4754 end generate; 4755 4756 end generate; 4757 4758 4759 genPar: xor2 port map (stage4(0), stage4(1), oddParity); 4760 4761end scaleable ; 4762library IEEE; 4763use IEEE.std_logic_1164.all; 4764use IEEE.numeric_std.all; 4765 4766entity powerOfFour is port( 4767 clk : in std_logic; 4768 inputVal : in unsigned(3 downto 0); 4769 power : out unsigned(15 downto 0) 4770 ); 4771end powerOfFour; 4772 4773architecture behavioral of powerOfFour is 4774 4775 function Pow( N, Exp : integer ) return integer is 4776 Variable Result : integer := 1; 4777 4778 begin 4779 for i in 1 to Exp loop 4780 Result := Result * N; 4781 end loop; 4782 return( Result ); 4783 end Pow; 4784 4785signal inputValInt: integer range 0 to 15; 4786signal powerL: integer range 0 to 65535; 4787 4788begin 4789 4790 inputValInt <= to_integer(inputVal); 4791 power <= to_unsigned(powerL,16); 4792 4793 process begin 4794 wait until Clk = '1'; 4795 4796 powerL <= Pow(inputValInt,4); 4797 4798 end process; 4799 4800end behavioral; 4801package PowerPkg is 4802 component Power port( 4803 Clk : in bit; 4804 inputVal : in bit_vector(0 to 3); 4805 power : out bit_vector(0 to 15) ); 4806 end component; 4807end PowerPkg; 4808 4809use work.bv_math.all; 4810use work.int_math.all; 4811use work.PowerPkg.all; 4812 4813entity Power is port( 4814 Clk : in bit; 4815 inputVal : in bit_vector(0 to 3); 4816 power : out bit_vector(0 to 15) ); 4817end Power; 4818 4819 4820 4821 4822architecture funky of Power is 4823 4824 function Pow( N, Exp : integer ) return integer is 4825 Variable Result : integer := 1; 4826 Variable i : integer := 0; 4827 begin 4828 while( i < Exp ) loop 4829 Result := Result * N; 4830 i := i + 1; 4831 end loop; 4832 return( Result ); 4833 end Pow; 4834 4835 4836 function RollVal( CntlVal : integer ) return integer is 4837 begin 4838 return( Pow( 2, CntlVal ) + 2 ); 4839 end RollVal; 4840 4841 4842begin 4843 process 4844 begin 4845 wait until Clk = '1'; 4846 4847 power <= i2bv(Rollval(bv2I(inputVal)),16); 4848 4849 end process; 4850end funky; 4851library ieee; 4852use ieee.std_logic_1164.all; 4853use ieee.numeric_std.all; 4854 4855entity priority_encoder is port 4856 (interrupts : in std_logic_vector(7 downto 0); 4857 priority : in std_logic_vector(2 downto 0); 4858 result : out std_logic_vector(2 downto 0) 4859 ); 4860end priority_encoder; 4861 4862architecture behave of priority_encoder is 4863begin 4864 4865 process (interrupts) 4866 variable selectIn : integer; 4867 variable LoopCount : integer; 4868 begin 4869 4870 LoopCount := 1; 4871 selectIn := to_integer(to_unsigned(priority)); 4872 4873 while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop 4874 4875 if (selectIn = 0) then 4876 selectIn := 7; 4877 else 4878 selectIn := selectIn - 1; 4879 end if; 4880 4881 LoopCount := LoopCount + 1; 4882 4883 end loop; 4884 4885 result <= std_logic_vector(to_unsigned(selectIn,3)); 4886 4887 end process; 4888 4889end behave; 4890library IEEE; 4891use IEEE.std_logic_1164.all; 4892 4893package primitive is 4894 component DFFE port ( 4895 d: in std_logic; 4896 q: out std_logic; 4897 en: in std_logic; 4898 clk: in std_logic 4899 ); 4900 end component; 4901 4902 component DFFE_SR port ( 4903 d: in std_logic; 4904 en: in std_logic; 4905 clk: in std_logic; 4906 rst: in std_logic; 4907 prst: in std_logic; 4908 q: out std_logic 4909 ); 4910 end component; 4911 4912 component DLATCHH port ( 4913 d: in std_logic; 4914 en: in std_logic; 4915 q: out std_logic 4916 ); 4917 end component; 4918 4919 component AND2 port ( 4920 i1: in std_logic; 4921 i2: in std_logic; 4922 y: out std_logic 4923 ); 4924 end component; 4925 4926 component OR2 port ( 4927 i1: in std_logic; 4928 i2: in std_logic; 4929 y: out std_logic 4930 ); 4931 end component; 4932 4933 component INVERTER port ( 4934 i: in std_logic; 4935 o: out std_logic 4936 ); 4937 end component; 4938 4939 component TRIBUF port ( 4940 ip: in std_logic; 4941 oe: in std_logic; 4942 op: out std_logic 4943 ); 4944 end component; 4945 4946 component BIDIR port ( 4947 ip: in std_logic; 4948 oe: in std_logic; 4949 op_fb: out std_logic; 4950 op: inout std_logic 4951 ); 4952 end component; 4953 4954end package; 4955 4956library IEEE; 4957use IEEE.std_logic_1164.all; 4958 4959entity DFFE is port ( 4960 d: in std_logic; 4961 q: out std_logic; 4962 en: in std_logic; 4963 clk: in std_logic 4964 ); 4965end DFFE; 4966 4967architecture rtl of DFFE is 4968 4969begin 4970 4971 process begin 4972 wait until clk = '1'; 4973 if (en = '1') then 4974 q <= d; 4975 end if; 4976 end process; 4977 4978end rtl; 4979 4980library IEEE; 4981use IEEE.std_logic_1164.all; 4982 4983entity DFFE_SR is port ( 4984 d: in std_logic; 4985 en: in std_logic; 4986 clk: in std_logic; 4987 rst: in std_logic; 4988 prst: in std_logic; 4989 q: out std_logic 4990 ); 4991end DFFE_SR; 4992 4993architecture rtl of DFFE_SR is 4994 4995begin 4996 4997 process (clk, rst, prst) begin 4998 if (rst = '1') then 4999 q <= '0'; 5000 elsif (prst = '1') then 5001 q <= '1'; 5002 elsif (clk'event and clk = '1') then 5003 if (en = '1') then 5004 q <= d; 5005 end if; 5006 end if; 5007 end process; 5008 5009end rtl; 5010 5011library IEEE; 5012use IEEE.std_logic_1164.all; 5013 5014entity DLATCHH is port ( 5015 d: in std_logic; 5016 en: in std_logic; 5017 q: out std_logic 5018 ); 5019end DLATCHH; 5020 5021architecture rtl of DLATCHH is 5022 5023begin 5024 5025 process (en) begin 5026 if (en = '1') then 5027 q <= d; 5028 end if; 5029 end process; 5030 5031end rtl; 5032 5033 5034library IEEE; 5035use IEEE.std_logic_1164.all; 5036 5037entity AND2 is port ( 5038 i1: in std_logic; 5039 i2: in std_logic; 5040 y: out std_logic 5041 ); 5042end AND2; 5043 5044architecture rtl of AND2 is 5045 5046begin 5047 5048 y <= '1' when i1 = '1' and i2 = '1' else '0'; 5049 5050end rtl; 5051 5052 5053library IEEE; 5054use IEEE.std_logic_1164.all; 5055 5056entity OR2 is port ( 5057 i1: in std_logic; 5058 i2: in std_logic; 5059 y: out std_logic 5060 ); 5061end OR2; 5062 5063architecture rtl of OR2 is 5064 5065begin 5066 5067 y <= '1' when i1 = '1' or i2 = '1' else '0'; 5068 5069end rtl; 5070 5071 5072 5073library IEEE; 5074use IEEE.std_logic_1164.all; 5075 5076entity INVERTER is port ( 5077 i: in std_logic; 5078 o: out std_logic 5079 ); 5080end INVERTER; 5081 5082architecture rtl of INVERTER is 5083 5084begin 5085 5086 o <= not i; 5087 5088end rtl; 5089 5090 5091library IEEE; 5092use IEEE.std_logic_1164.all; 5093 5094entity TRIBUF is port ( 5095 ip: in std_logic; 5096 oe: in std_logic; 5097 op: out std_logic 5098 ); 5099end TRIBUF; 5100 5101architecture rtl of TRIBUF is 5102 5103begin 5104 5105 op <= ip when oe = '1' else 'Z'; 5106 5107end rtl; 5108 5109 5110library IEEE; 5111use IEEE.std_logic_1164.all; 5112 5113entity BIDIR is port ( 5114 ip: in std_logic; 5115 oe: in std_logic; 5116 op_fb: out std_logic; 5117 op: inout std_logic 5118 ); 5119end BIDIR; 5120 5121architecture rtl of BIDIR is 5122 5123begin 5124 5125 op <= ip when oe = '1' else 'Z'; 5126 op_fb <= op; 5127 5128end rtl; 5129 5130library ieee; 5131use ieee.std_logic_1164.all; 5132use ieee.numeric_std.all; 5133 5134entity progPulse is port ( 5135 clk, reset: in std_logic; 5136 loadLength,loadDelay: in std_logic; 5137 data: in std_logic_vector(7 downto 0); 5138 pulse: out std_logic 5139 ); 5140end progPulse; 5141 5142architecture rtl of progPulse is 5143 5144signal downCnt, downCntData: unsigned(7 downto 0); 5145signal downCntLd, downCntEn: std_logic; 5146signal delayCntVal, pulseCntVal: unsigned(7 downto 0); 5147signal startPulse, endPulse: std_logic; 5148 5149subtype fsmType is std_logic_vector(1 downto 0); 5150constant loadDelayCnt : fsmType := "00"; 5151constant waitDelayEnd : fsmType := "10"; 5152constant loadLengthCnt : fsmType := "11"; 5153constant waitLengthEnd : fsmType := "01"; 5154 5155signal currState, nextState: fsmType; 5156 5157begin 5158 5159 delayreg: process (clk, reset) begin 5160 if reset = '1' then 5161 delayCntVal <= "11111111"; 5162 elsif clk'event and clk = '1' then 5163 if loadDelay = '1' then 5164 delayCntVal <= to_unsigned(data); 5165 end if; 5166 end if; 5167 end process; 5168 5169 lengthReg: process (clk, reset) begin 5170 if reset = '1' then 5171 pulseCntVal <= "11111111"; 5172 elsif clk'event and clk = '1' then 5173 if loadDelay = '1' then 5174 pulseCntVal <= to_unsigned(data); 5175 end if; 5176 end if; 5177 end process; 5178 5179 nextStProc: process (currState, downCnt, loadDelay, loadLength) begin 5180 case currState is 5181 when loadDelayCnt => 5182 nextState <= waitDelayEnd; 5183 5184 when waitDelayEnd => 5185 if (loadDelay = '1' or loadLength = '1') then 5186 nextState <= loadDelayCnt; 5187 elsif (downCnt = 0) then 5188 nextState <= loadLengthCnt; 5189 else 5190 nextState <= waitDelayEnd; 5191 end if; 5192 5193 when loadLengthCnt => 5194 if (loadDelay = '1' or loadLength = '1') then 5195 nextState <= loadDelayCnt; 5196 else 5197 nextState <= waitLengthEnd; 5198 end if; 5199 5200 when waitLengthEnd => 5201 if (loadDelay = '1' or loadLength = '1') then 5202 nextState <= loadDelayCnt; 5203 elsif (downCnt = 0) then 5204 nextState <= loadDelayCnt; 5205 else 5206 nextState <= waitDelayEnd; 5207 end if; 5208 5209 when others => 5210 null; 5211 5212 end case; 5213 end process nextStProc; 5214 5215 currStProc: process (clk, reset) begin 5216 if (reset = '1') then 5217 currState <= loadDelayCnt; 5218 elsif (clk'event and clk = '1') then 5219 currState <= nextState; 5220 end if; 5221 end process currStProc; 5222 5223 outConProc: process (currState, delayCntVal, pulseCntVal) begin 5224 case currState is 5225 when loadDelayCnt => 5226 downCntEn <= '0'; 5227 downCntLd <= '1'; 5228 downCntData <= delayCntVal; 5229 5230 when waitDelayEnd => 5231 downCntEn <= '1'; 5232 downCntLd <= '0'; 5233 downCntData <= delayCntVal; 5234 5235 when loadLengthCnt => 5236 downCntEn <= '0'; 5237 downCntLd <= '1'; 5238 downCntData <= pulseCntVal; 5239 5240 when waitLengthEnd => 5241 downCntEn <= '1'; 5242 downCntLd <= '0'; 5243 downCntData <= pulseCntVal; 5244 5245 when others => 5246 downCntEn <= '0'; 5247 downCntLd <= '1'; 5248 downCntData <= pulseCntVal; 5249 5250 end case; 5251 end process outConProc; 5252 5253 downCntr: process (clk,reset) begin 5254 if (reset = '1') then 5255 downCnt <= "00000000"; 5256 elsif (clk'event and clk = '1') then 5257 if (downCntLd = '1') then 5258 downCnt <= downCntData; 5259 elsif (downCntEn = '1') then 5260 downCnt <= downCnt - 1; 5261 else 5262 downCnt <= downCnt; 5263 end if; 5264 end if; 5265 end process; 5266 5267 -- Assign pulse output 5268 pulse <= currState(0); 5269 5270 5271end rtl; 5272library ieee; 5273use ieee.std_logic_1164.all; 5274 5275entity pulseErr is port 5276 (a: in std_logic; 5277 b: out std_logic 5278 ); 5279end pulseErr; 5280 5281architecture behavior of pulseErr is 5282 5283signal c: std_logic; 5284 5285begin 5286 5287 pulse: process (a,c) begin 5288 b <= c XOR a; 5289 5290 c <= a; 5291 end process; 5292 5293end behavior; 5294library ieee; 5295use ieee.std_logic_1164.all; 5296use ieee.numeric_std.all; 5297 5298entity progPulse is port ( 5299 clk, reset: in std_logic; 5300 loadLength,loadDelay: in std_logic; 5301 data: in std_logic_vector(7 downto 0); 5302 pulse: out std_logic 5303 ); 5304end progPulse; 5305 5306architecture rtl of progPulse is 5307 5308signal downCnt, downCntData: unsigned(7 downto 0); 5309signal downCntLd, downCntEn: std_logic; 5310signal delayCntVal, pulseCntVal: unsigned(7 downto 0); 5311signal startPulse, endPulse: std_logic; 5312 5313type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd); 5314signal currState, nextState: progPulseFsmType; 5315 5316begin 5317 5318 delayreg: process (clk, reset) begin 5319 if reset = '1' then 5320 delayCntVal <= "11111111"; 5321 elsif clk'event and clk = '1' then 5322 if loadDelay = '1' then 5323 delayCntVal <= to_unsigned(data); 5324 end if; 5325 end if; 5326 end process; 5327 5328 lengthReg: process (clk, reset) begin 5329 if reset = '1' then 5330 pulseCntVal <= "11111111"; 5331 elsif clk'event and clk = '1' then 5332 if loadDelay = '1' then 5333 pulseCntVal <= to_unsigned(data); 5334 end if; 5335 end if; 5336 end process; 5337 5338 nextStProc: process (currState, downCnt, loadDelay, loadLength) begin 5339 case currState is 5340 when loadDelayCnt => 5341 nextState <= waitDelayEnd; 5342 5343 when waitDelayEnd => 5344 if (loadDelay = '1' or loadLength = '1') then 5345 nextState <= loadDelayCnt; 5346 elsif (downCnt = 0) then 5347 nextState <= loadLengthCnt; 5348 else 5349 nextState <= waitDelayEnd; 5350 end if; 5351 5352 when loadLengthCnt => 5353 if (loadDelay = '1' or loadLength = '1') then 5354 nextState <= loadDelayCnt; 5355 else 5356 nextState <= waitLengthEnd; 5357 end if; 5358 5359 when waitLengthEnd => 5360 if (loadDelay = '1' or loadLength = '1') then 5361 nextState <= loadDelayCnt; 5362 elsif (downCnt = 0) then 5363 nextState <= loadDelayCnt; 5364 else 5365 nextState <= waitDelayEnd; 5366 end if; 5367 5368 when others => 5369 null; 5370 5371 end case; 5372 end process nextStProc; 5373 5374 currStProc: process (clk, reset) begin 5375 if (reset = '1') then 5376 currState <= loadDelayCnt; 5377 elsif (clk'event and clk = '1') then 5378 currState <= nextState; 5379 end if; 5380 end process currStProc; 5381 5382 outConProc: process (currState, delayCntVal, pulseCntVal) begin 5383 case currState is 5384 when loadDelayCnt => 5385 downCntEn <= '0'; 5386 downCntLd <= '1'; 5387 downCntData <= delayCntVal; 5388 pulse <= '0'; 5389 5390 when waitDelayEnd => 5391 downCntEn <= '1'; 5392 downCntLd <= '0'; 5393 downCntData <= delayCntVal; 5394 pulse <= '0'; 5395 5396 when loadLengthCnt => 5397 downCntEn <= '0'; 5398 downCntLd <= '1'; 5399 downCntData <= pulseCntVal; 5400 pulse <= '1'; 5401 5402 when waitLengthEnd => 5403 downCntEn <= '1'; 5404 downCntLd <= '0'; 5405 downCntData <= pulseCntVal; 5406 pulse <= '1'; 5407 5408 when others => 5409 downCntEn <= '0'; 5410 downCntLd <= '1'; 5411 downCntData <= pulseCntVal; 5412 pulse <= '0'; 5413 5414 end case; 5415 end process outConProc; 5416 5417 downCntr: process (clk,reset) begin 5418 if (reset = '1') then 5419 downCnt <= "00000000"; 5420 elsif (clk'event and clk = '1') then 5421 if (downCntLd = '1') then 5422 downCnt <= downCntData; 5423 elsif (downCntEn = '1') then 5424 downCnt <= downCnt - 1; 5425 else 5426 downCnt <= downCnt; 5427 end if; 5428 end if; 5429 end process; 5430 5431 5432end rtl; 5433library ieee; 5434use ieee.std_logic_1164.all; 5435use ieee.numeric_std.all; 5436 5437entity progPulseFsm is port ( 5438 downCnt: in std_logic_vector(7 downto 0); 5439 delayCntVal: in std_logic_vector(7 downto 0); 5440 lengthCntVal: in std_logic_vector(7 downto 0); 5441 loadLength: in std_logic; 5442 loadDelay: in std_logic; 5443 clk: in std_logic; 5444 reset: in std_logic; 5445 5446 downCntEn: out std_logic; 5447 downCntLd: out std_logic; 5448 downCntData: out std_logic_vector(7 downto 0); 5449 5450 pulse: out std_logic 5451 ); 5452end progPulseFsm; 5453 5454architecture fsm of progPulseFsm is 5455 5456type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd); 5457type stateVec is array (3 downto 0) of std_logic; 5458type stateBits is array (progPulseFsmType) of stateVec; 5459 5460signal loadVal: std_logic; 5461 5462constant stateTable: stateBits := ( 5463 loadDelayCnt => "0010", 5464 waitDelayEnd => "0100", 5465 loadLengthCnt => "0011", 5466 waitLengthEnd => "1101" ); 5467-- ^^^^ 5468-- ||||__ loadVal 5469-- |||___ downCntLd 5470-- ||____ downCntEn 5471-- |_____ pulse 5472 5473signal currState, nextState: progPulseFsmType; 5474 5475begin 5476 5477 nextStProc: process (currState, downCnt, loadDelay, loadLength) begin 5478 case currState is 5479 when loadDelayCnt => 5480 nextState <= waitDelayEnd; 5481 5482 when waitDelayEnd => 5483 if (loadDelay = '1' or loadLength = '1') then 5484 nextState <= loadDelayCnt; 5485 elsif (to_unsigned(downCnt) = 0) then 5486 nextState <= loadLengthCnt; 5487 else 5488 nextState <= waitDelayEnd; 5489 end if; 5490 5491 when loadLengthCnt => 5492 if (loadDelay = '1' or loadLength = '1') then 5493 nextState <= loadDelayCnt; 5494 else 5495 nextState <= waitLengthEnd; 5496 end if; 5497 5498 when waitLengthEnd => 5499 if (loadDelay = '1' or loadLength = '1') then 5500 nextState <= loadDelayCnt; 5501 elsif (to_unsigned(downCnt) = 0) then 5502 nextState <= loadDelayCnt; 5503 else 5504 nextState <= waitDelayEnd; 5505 end if; 5506 5507 when others => 5508 null; 5509 5510 end case; 5511 5512 end process nextStProc; 5513 5514 currStProc: process (clk, reset) begin 5515 if (reset = '1') then 5516 currState <= loadDelayCnt; 5517 elsif (clk'event and clk = '1') then 5518 currState <= nextState; 5519 end if; 5520 end process currStProc; 5521 5522 pulse <= stateTable(currState)(3); 5523 downCntEn <= stateTable(currState)(2); 5524 downCntLd <= stateTable(currState)(1); 5525 loadVal <= stateTable(currState)(0); 5526 5527 downCntData <= delayCntVal when loadVal = '0' else lengthCntVal; 5528 5529end fsm; 5530-- Incorporates Errata 6.1 5531 5532library ieee; 5533use ieee.std_logic_1164.all; 5534use ieee.numeric_std.all; 5535 5536entity progPulseFsm is port ( 5537 downCnt: in std_logic_vector(7 downto 0); 5538 delayCntVal: in std_logic_vector(7 downto 0); 5539 lengthCntVal: in std_logic_vector(7 downto 0); 5540 loadLength: in std_logic; 5541 loadDelay: in std_logic; 5542 clk: in std_logic; 5543 reset: in std_logic; 5544 5545 downCntEn: out std_logic; 5546 downCntLd: out std_logic; 5547 downtCntData: out std_logic_vector(7 downto 0); 5548 5549 pulse: out std_logic 5550 ); 5551end progPulseFsm; 5552 5553architecture fsm of progPulseFsm is 5554 5555type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd); 5556signal currState, nextState: progPulseFsmType; 5557signal downCntL: unsigned (7 downto 0); 5558 5559begin 5560 5561 downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned 5562 5563 nextStProc: process (currState, downCntL, loadDelay, loadLength) begin 5564 case currState is 5565 when loadDelayCnt => 5566 nextState <= waitDelayEnd; 5567 5568 when waitDelayEnd => 5569 if (loadDelay = '1' or loadLength = '1') then 5570 nextState <= loadDelayCnt; 5571 elsif (downCntL = 0) then 5572 nextState <= loadLengthCnt; 5573 else 5574 nextState <= waitDelayEnd; 5575 end if; 5576 5577 when loadLengthCnt => 5578 if (loadDelay = '1' or loadLength = '1') then 5579 nextState <= loadDelayCnt; 5580 else 5581 nextState <= waitLengthEnd; 5582 end if; 5583 5584 when waitLengthEnd => 5585 if (loadDelay = '1' or loadLength = '1') then 5586 nextState <= loadDelayCnt; 5587 elsif (downCntL = 0) then 5588 nextState <= loadDelayCnt; 5589 else 5590 nextState <= waitDelayEnd; 5591 end if; 5592 5593 when others => 5594 null; 5595 5596 end case; 5597 5598 end process nextStProc; 5599 5600 currStProc: process (clk, reset) begin 5601 if (reset = '1') then 5602 currState <= loadDelayCnt; 5603 elsif (clk'event and clk = '1') then 5604 currState <= nextState; 5605 end if; 5606 end process currStProc; 5607 5608 outConProc: process (currState, delayCntVal, lengthCntVal) begin 5609 case currState is 5610 when loadDelayCnt => 5611 downCntEn <= '0'; 5612 downCntLd <= '1'; 5613 downtCntData <= delayCntVal; 5614 pulse <= '0'; 5615 5616 when waitDelayEnd => 5617 downCntEn <= '1'; 5618 downCntLd <= '0'; 5619 downtCntData <= delayCntVal; 5620 pulse <= '0'; 5621 5622 when loadLengthCnt => 5623 downCntEn <= '0'; 5624 downCntLd <= '1'; 5625 downtCntData <= lengthCntVal; 5626 pulse <= '1'; 5627 5628 when waitLengthEnd => 5629 downCntEn <= '1'; 5630 downCntLd <= '0'; 5631 downtCntData <= lengthCntVal; 5632 pulse <= '1'; 5633 5634 when others => 5635 downCntEn <= '0'; 5636 downCntLd <= '1'; 5637 downtCntData <= delayCntVal; 5638 pulse <= '0'; 5639 5640 end case; 5641 end process outConProc; 5642 5643end fsm; 5644-- Incorporates errata 5.4 5645 5646library IEEE; 5647use IEEE.std_logic_1164.all; 5648use IEEE.numeric_std.all; 5649 5650use work.specialFunctions.all; 5651 5652entity powerOfFour is port( 5653 clk : in std_logic; 5654 inputVal : in std_logic_vector(3 downto 0); 5655 power : out std_logic_vector(15 downto 0) 5656 ); 5657end powerOfFour; 5658 5659architecture behavioral of powerOfFour is 5660 5661begin 5662 5663 process begin 5664 wait until Clk = '1'; 5665 5666 power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16)); 5667 5668 end process; 5669 5670end behavioral; 5671-- Incorporate errata 5.4 5672 5673library IEEE; 5674use IEEE.std_logic_1164.all; 5675use IEEE.numeric_std.all; 5676 5677entity powerOfFour is port( 5678 clk : in std_logic; 5679 inputVal : in std_logic_vector(3 downto 0); 5680 power : out std_logic_vector(15 downto 0) 5681 ); 5682end powerOfFour; 5683 5684architecture behavioral of powerOfFour is 5685 5686 function Pow( N, Exp : integer ) return integer is 5687 Variable Result : integer := 1; 5688 5689 begin 5690 for i in 1 to Exp loop 5691 Result := Result * N; 5692 end loop; 5693 return( Result ); 5694 end Pow; 5695 5696begin 5697 5698 process begin 5699 wait until Clk = '1'; 5700 5701 power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16)); 5702 5703 end process; 5704 5705end behavioral; 5706library IEEE; 5707use IEEE.std_logic_1164.all; 5708use IEEE.std_logic_arith.all; 5709use IEEE.std_logic_unsigned.all; 5710 5711entity powerOfFour is port( 5712 clk : in std_logic; 5713 inputVal : in std_logic_vector(3 downto 0); 5714 power : out std_logic_vector(15 downto 0) 5715 ); 5716end powerOfFour; 5717 5718architecture behavioral of powerOfFour is 5719 5720 function Pow( N, Exp : integer ) return integer is 5721 Variable Result : integer := 1; 5722 5723 begin 5724 for i in 1 to Exp loop 5725 Result := Result * N; 5726 end loop; 5727 return( Result ); 5728 end Pow; 5729 5730begin 5731 5732 process begin 5733 wait until Clk = '1'; 5734 5735 power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16); 5736 5737 end process; 5738 5739end behavioral; 5740library IEEE; 5741use IEEE.std_logic_1164.all; 5742 5743entity regFile is port ( 5744 clk, rst: in std_logic; 5745 data: in std_logic_vector(31 downto 0); 5746 regSel: in std_logic_vector(1 downto 0); 5747 wrEnable: in std_logic; 5748 regOut: out std_logic_vector(31 downto 0) 5749 ); 5750end regFile; 5751 5752architecture behavioral of regFile is 5753 5754subtype reg is std_logic_vector(31 downto 0); 5755type regArray is array (integer range <>) of reg; 5756 5757signal registerFile: regArray(0 to 3); 5758 5759begin 5760 5761 regProc: process (clk, rst) 5762 variable i: integer; 5763 5764 begin 5765 i := 0; 5766 5767 if rst = '1' then 5768 while i <= registerFile'high loop 5769 registerFile(i) <= (others => '0'); 5770 i := i + 1; 5771 end loop; 5772 5773 elsif clk'event and clk = '1' then 5774 if (wrEnable = '1') then 5775 case regSel is 5776 when "00" => 5777 registerFile(0) <= data; 5778 when "01" => 5779 registerFile(1) <= data; 5780 when "10" => 5781 registerFile(2) <= data; 5782 when "11" => 5783 registerFile(3) <= data; 5784 when others => 5785 null; 5786 end case; 5787 end if; 5788 end if; 5789 end process; 5790 5791 outputs: process(regSel, registerFile) begin 5792 case regSel is 5793 when "00" => 5794 regOut <= registerFile(0); 5795 when "01" => 5796 regOut <= registerFile(1); 5797 when "10" => 5798 regOut <= registerFile(2); 5799 when "11" => 5800 regOut <= registerFile(3); 5801 when others => 5802 null; 5803 end case; 5804 end process; 5805 5806end behavioral; 5807library IEEE; 5808use IEEE.std_logic_1164.all; 5809 5810entity DFF is port ( 5811 d1,d2: in std_logic; 5812 q1,q2: out std_logic; 5813 clk: in std_logic; 5814 rst : in std_logic 5815 ); 5816end DFF; 5817 5818architecture rtl of DFF is 5819 5820begin 5821 5822 resetLatch: process (clk, rst) begin 5823 if rst = '1' then 5824 q1 <= '0'; 5825 elsif clk'event and clk = '1' then 5826 q1 <= d1; 5827 q2 <= d2; 5828 end if; 5829 end process; 5830 5831end rtl; 5832library ieee; 5833use ieee.std_logic_1164.all; 5834 5835entity resFcnDemo is port ( 5836 a, b: in std_logic; 5837 oeA,oeB: in std_logic; 5838 result: out std_logic 5839 ); 5840end resFcnDemo; 5841 5842architecture multiDriver of resFcnDemo is 5843 5844begin 5845 5846 result <= a when oeA = '1' else 'Z'; 5847 result <= b when oeB = '1' else 'Z'; 5848 5849end multiDriver; 5850library IEEE; 5851use IEEE.std_logic_1164.all; 5852 5853use work.primitive.all; 5854 5855entity scaleDFF is port ( 5856 data: in std_logic_vector(7 downto 0); 5857 clock: in std_logic; 5858 enable: in std_logic; 5859 qout: out std_logic_vector(7 downto 0) 5860 ); 5861end scaleDFF; 5862 5863architecture scalable of scaleDFF is 5864 5865begin 5866 5867 u1: sDFFE port map (d => data, 5868 clk =>clock, 5869 en => enable, 5870 q => qout 5871 ); 5872 5873end scalable; 5874library ieee; 5875use ieee.std_logic_1164.all; 5876use ieee.std_logic_unsigned.all; 5877 5878entity sevenSegment is port ( 5879 bcdInputs: in std_logic_vector (3 downto 0); 5880 a_n, b_n, c_n, d_n, 5881 e_n, f_n, g_n: out std_logic 5882 ); 5883end sevenSegment; 5884 5885architecture behavioral of sevenSegment is 5886 5887signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic; 5888signal oe: std_logic; 5889 5890begin 5891 5892 bcd2sevSeg: process (bcdInputs) begin 5893 5894 -- Assign default to "off" 5895 la_n <= '1'; lb_n <= '1'; 5896 lc_n <= '1'; ld_n <= '1'; 5897 le_n <= '1'; lf_n <= '1'; 5898 lg_n <= '1'; 5899 5900 case bcdInputs is 5901 when "0000" => la_n <= '0'; lb_n <= '0'; 5902 lc_n <= '0'; ld_n <= '0'; 5903 le_n <= '0'; lf_n <= '0'; 5904 5905 when "0001" => lb_n <= '0'; lc_n <= '0'; 5906 5907 when "0010" => la_n <= '0'; lb_n <= '0'; 5908 ld_n <= '0'; le_n <= '0'; 5909 lg_n <= '0'; 5910 5911 when "0011" => la_n <= '0'; lb_n <= '0'; 5912 lc_n <= '0'; ld_n <= '0'; 5913 lg_n <= '0'; 5914 5915 when "0100" => lb_n <= '0'; lc_n <= '0'; 5916 lf_n <= '0'; lg_n <= '0'; 5917 5918 when "0101" => la_n <= '0'; lc_n <= '0'; 5919 ld_n <= '0'; lf_n <= '0'; 5920 lg_n <= '0'; 5921 5922 when "0110" => la_n <= '0'; lc_n <= '0'; 5923 ld_n <= '0'; le_n <= '0'; 5924 lf_n <= '0'; lg_n <= '0'; 5925 5926 when "0111" => la_n <= '0'; lb_n <= '0'; 5927 lc_n <= '0'; 5928 5929 when "1000" => la_n <= '0'; lb_n <= '0'; 5930 lc_n <= '0'; ld_n <= '0'; 5931 le_n <= '0'; lf_n <= '0'; 5932 lg_n <= '0'; 5933 5934 when "1001" => la_n <= '0'; lb_n <= '0'; 5935 lc_n <= '0'; ld_n <= '0'; 5936 lf_n <= '0'; lg_n <= '0'; 5937 5938-- All other inputs possibilities are "don't care" 5939 5940 when others => la_n <= 'X'; lb_n <= 'X'; 5941 lc_n <= 'X'; ld_n <= 'X'; 5942 le_n <= 'X'; lf_n <= 'X'; 5943 lg_n <= 'X'; 5944 5945 end case; 5946 5947 end process bcd2sevSeg; 5948 5949 -- Disable outputs for all invalid input values 5950 5951 oe <= '1' when (bcdInputs < 10) else '0'; 5952 5953 a_n <= la_n when oe = '1' else 'Z'; 5954 b_n <= lb_n when oe = '1' else 'Z'; 5955 c_n <= lc_n when oe = '1' else 'Z'; 5956 d_n <= ld_n when oe = '1' else 'Z'; 5957 e_n <= le_n when oe = '1' else 'Z'; 5958 f_n <= lf_n when oe = '1' else 'Z'; 5959 g_n <= lg_n when oe = '1' else 'Z'; 5960 5961 5962end behavioral; 5963library ieee; 5964use ieee.std_logic_1164.all; 5965 5966use std.textio.all; 5967 5968entity sevenSegmentTB is 5969end sevenSegmentTB; 5970 5971architecture testbench of sevenSegmentTB is 5972 5973component sevenSegment port ( 5974 bcdInputs: in std_logic_vector (3 downto 0); 5975 a_n, b_n, c_n, d_n, 5976 e_n, f_n, g_n: out std_logic 5977 ); 5978end component; 5979 5980type vector is record 5981 bcdStimulus: std_logic_vector(3 downto 0); 5982 sevSegOut: std_logic_vector(6 downto 0); 5983end record; 5984 5985constant NumVectors: integer:= 17; 5986constant PropDelay: time := 40 ns; 5987constant SimLoopDelay: time := 10 ns; 5988 5989type vectorArray is array (0 to NumVectors - 1) of vector; 5990constant vectorTable: vectorArray := ( 5991 (bcdStimulus => "0000", sevSegOut => "0000001"), 5992 (bcdStimulus => "0001", sevSegOut => "1001111"), 5993 (bcdStimulus => "0010", sevSegOut => "0010010"), 5994 (bcdStimulus => "0011", sevSegOut => "0000110"), 5995 (bcdStimulus => "0100", sevSegOut => "1001100"), 5996 (bcdStimulus => "0101", sevSegOut => "0100100"), 5997 (bcdStimulus => "0110", sevSegOut => "0100000"), 5998 (bcdStimulus => "0111", sevSegOut => "0001111"), 5999 (bcdStimulus => "1000", sevSegOut => "0000000"), 6000 (bcdStimulus => "1001", sevSegOut => "0000100"), 6001 (bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"), 6002 (bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"), 6003 (bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"), 6004 (bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"), 6005 (bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"), 6006 (bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"), 6007 (bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails 6008 ); 6009 6010for all : sevenSegment use entity work.sevenSegment(behavioral); 6011 6012signal StimInputs: std_logic_vector(3 downto 0); 6013signal CaptureOutputs: std_logic_vector(6 downto 0); 6014 6015begin 6016 6017 u1: sevenSegment port map (bcdInputs => StimInputs, 6018 a_n => CaptureOutputs(6), 6019 b_n => CaptureOutputs(5), 6020 c_n => CaptureOutputs(4), 6021 d_n => CaptureOutputs(3), 6022 e_n => CaptureOutputs(2), 6023 f_n => CaptureOutputs(1), 6024 g_n => CaptureOutputs(0)); 6025 6026 LoopStim: process 6027 variable FoundError: boolean := false; 6028 variable TempVector: vector; 6029 variable ErrorMsgLine: line; 6030 begin 6031 6032 for i in vectorTable'range loop 6033 TempVector := vectorTable(i); 6034 6035 StimInputs <= TempVector.bcdStimulus; 6036 6037 wait for PropDelay; 6038 6039 if CaptureOutputs /= TempVector.sevSegOut then 6040 write (ErrorMsgLine, string'("Vector failed at ")); 6041 write (ErrorMsgLine, now); 6042 writeline (output, ErrorMsgLine); 6043 FoundError := true; 6044 end if; 6045 6046 wait for SimLoopDelay; 6047 6048 end loop; 6049 6050 assert FoundError 6051 report "No errors. All vectors passed." 6052 severity note; 6053 6054 wait; 6055 6056 end process; 6057 6058end testbench; 6059library ieee; 6060use ieee.std_logic_1164.all; 6061 6062entity sevenSegment is port ( 6063 bcdInputs: in std_logic_vector (3 downto 0); 6064 a_n, b_n, c_n, d_n, 6065 e_n, f_n, g_n: out std_logic 6066 ); 6067end sevenSegment; 6068 6069architecture behavioral of sevenSegment is 6070 6071begin 6072 6073 bcd2sevSeg: process (bcdInputs) begin 6074 6075 -- Assign default to "off" 6076 a_n <= '1'; b_n <= '1'; 6077 c_n <= '1'; d_n <= '1'; 6078 e_n <= '1'; f_n <= '1'; 6079 g_n <= '1'; 6080 6081 case bcdInputs is 6082 when "0000" => 6083 a_n <= '0'; b_n <= '0'; 6084 c_n <= '0'; d_n <= '0'; 6085 e_n <= '0'; f_n <= '0'; 6086 6087 when "0001" => 6088 b_n <= '0'; c_n <= '0'; 6089 6090 when "0010" => 6091 a_n <= '0'; b_n <= '0'; 6092 d_n <= '0'; e_n <= '0'; 6093 g_n <= '0'; 6094 6095 when "0011" => 6096 a_n <= '0'; b_n <= '0'; 6097 c_n <= '0'; d_n <= '0'; 6098 g_n <= '0'; 6099 6100 when "0100" => 6101 b_n <= '0'; c_n <= '0'; 6102 f_n <= '0'; g_n <= '0'; 6103 6104 when "0101" => 6105 a_n <= '0'; c_n <= '0'; 6106 d_n <= '0'; f_n <= '0'; 6107 g_n <= '0'; 6108 6109 when "0110" => 6110 a_n <= '0'; c_n <= '0'; 6111 d_n <= '0'; e_n <= '0'; 6112 f_n <= '0'; g_n <= '0'; 6113 6114 when "0111" => 6115 a_n <= '0'; b_n <= '0'; 6116 c_n <= '0'; 6117 6118 when "1000" => 6119 a_n <= '0'; b_n <= '0'; 6120 c_n <= '0'; d_n <= '0'; 6121 e_n <= '0'; f_n <= '0'; 6122 g_n <= '0'; 6123 6124 when "1001" => 6125 a_n <= '0'; b_n <= '0'; 6126 c_n <= '0'; d_n <= '0'; 6127 f_n <= '0'; g_n <= '0'; 6128 6129 when others => 6130 null; 6131 6132 end case; 6133 6134 end process bcd2sevSeg; 6135 6136end behavioral; 6137library IEEE; 6138use IEEE.std_logic_1164.all; 6139use IEEE.std_logic_unsigned.all; 6140 6141entity ForceShare is port ( 6142 a,b,c,d,e,f: in std_logic_vector (7 downto 0); 6143 result: out std_logic_vector(7 downto 0) 6144 ); 6145end ForceShare; 6146 6147architecture behaviour of ForceShare is 6148 6149begin 6150 6151 sum: process (a,c,b,d,e,f) 6152 variable tempSum: std_logic_vector(7 downto 0); 6153 begin 6154 6155 tempSum := a + b; -- temporary node for sum 6156 6157 if (tempSum = "10011010") then 6158 result <= c; 6159 elsif (tempSum = "01011001") then 6160 result <= d; 6161 elsif (tempSum = "10111011") then 6162 result <= e; 6163 else 6164 result <= f; 6165 end if; 6166 end process; 6167 6168end behaviour; 6169library IEEE; 6170use IEEE.std_logic_1164.all; 6171 6172entity shifter is port ( 6173 clk, rst: in std_logic; 6174 shiftEn,shiftIn: std_logic; 6175 q: out std_logic_vector (15 downto 0) 6176 ); 6177end shifter; 6178 6179 6180architecture behav of shifter is 6181 6182signal qLocal: std_logic_vector(15 downto 0); 6183 6184begin 6185 6186 shift: process (clk, rst) begin 6187 if (rst = '1') then 6188 qLocal <= (others => '0'); 6189 elsif (clk'event and clk = '1') then 6190 if (shiftEn = '1') then 6191 qLocal <= qLocal(14 downto 0) & shiftIn; 6192 else 6193 qLocal <= qLocal; 6194 end if; 6195 end if; 6196 6197 q <= qLocal; 6198 end process; 6199 6200end behav; 6201library ieee; 6202use ieee.std_logic_1164.all; 6203 6204entity lastAssignment is port 6205 (a, b: in std_logic; 6206 selA, selb: in std_logic; 6207 result: out std_logic 6208 ); 6209end lastAssignment; 6210 6211architecture behavioral of lastAssignment is 6212 6213begin 6214 6215 demo: process (a,b,selA,selB) begin 6216 if (selA = '1') then 6217 result <= a; 6218 else 6219 result <= '0'; 6220 end if; 6221 6222 if (selB = '1') then 6223 result <= b; 6224 else 6225 result <= '0'; 6226 end if; 6227 end process demo; 6228 6229end behavioral; 6230library ieee; 6231use ieee.std_logic_1164.all; 6232 6233entity signalDemo is port ( 6234 a: in std_logic; 6235 b: out std_logic 6236 ); 6237end signalDemo; 6238 6239architecture basic of signalDemo is 6240 6241signal c: std_logic; 6242 6243begin 6244 6245 demo: process (a) begin 6246 6247 c <= a; 6248 6249 if c = '0' then 6250 b <= a; 6251 else 6252 b <= '0'; 6253 end if; 6254 6255 end process; 6256 6257end basic; 6258library ieee; 6259use ieee.std_logic_1164.all; 6260 6261entity signalDemo is port ( 6262 a: in std_logic; 6263 b: out std_logic 6264 ); 6265end signalDemo; 6266 6267architecture basic of signalDemo is 6268 6269signal c: std_logic; 6270 6271begin 6272 6273 demo: process (a) begin 6274 6275 c <= a; 6276 6277 if c = '1' then 6278 b <= a; 6279 else 6280 b <= '0'; 6281 end if; 6282 6283 end process; 6284 6285end basic; 6286library IEEE; 6287USE IEEE.std_logic_1164.all; 6288 6289package simPrimitives is 6290 6291 component OR2 6292 generic (tPD: time := 1 ns); 6293 6294 port (I1, I2: in std_logic; 6295 Y: out std_logic 6296 ); 6297 end component; 6298 6299 component SimDFF 6300 generic(tCQ: time := 1 ns; 6301 tS : time := 1 ns; 6302 tH : time := 1 ns 6303 ); 6304 port (D, Clk: in std_logic; 6305 Q: out std_logic 6306 ); 6307 end component; 6308 6309 6310end simPrimitives; 6311 6312 6313library IEEE; 6314USE IEEE.std_logic_1164.all; 6315 6316entity OR2 is 6317 generic (tPD: time := 1 ns); 6318 6319 port (I1, I2: in std_logic; 6320 Y: out std_logic 6321 ); 6322end OR2; 6323 6324architecture simple of OR2 is 6325 6326begin 6327 6328 Y <= I1 OR I2 after tPD; 6329 6330end simple; 6331 6332 6333 6334library IEEE; 6335use IEEE.std_logic_1164.all; 6336 6337entity SimDFF is 6338 generic(tCQ: time := 1 ns; 6339 tS : time := 1 ns; 6340 tH : time := 1 ns 6341 ); 6342 port (D, Clk: in std_logic; 6343 Q: out std_logic 6344 ); 6345end SimDff; 6346 6347architecture SimModel of SimDFF is 6348 6349begin 6350 6351 reg: process (Clk, D) begin 6352 6353 -- Assign output tCQ after rising clock edge 6354 if (Clk'event and Clk = '1') then 6355 Q <= D after tCQ; 6356 end if; 6357 6358 -- Check setup time 6359 if (Clk'event and Clk = '1') then 6360 assert (D'last_event >= tS) 6361 report "Setup time violation" 6362 severity Warning; 6363 end if; 6364 6365 -- Check hold time 6366 if (D'event and Clk'stable and Clk = '1') then 6367 assert (D'last_event - Clk'last_event > tH) 6368 report "Hold Time Violation" 6369 severity Warning; 6370 end if; 6371 6372 end process; 6373 6374end simModel; 6375 6376library IEEE; 6377use IEEE.std_logic_1164.all; 6378 6379entity SRFF is port ( 6380 s,r: in std_logic; 6381 clk: in std_logic; 6382 q: out std_logic 6383 ); 6384end SRFF; 6385 6386architecture rtl of SRFF is 6387 6388begin 6389 6390 process begin 6391 wait until rising_edge(clk); 6392 if s = '0' and r = '1' then 6393 q <= '0'; 6394 elsif s = '1' and r = '0' then 6395 q <= '1'; 6396 end if; 6397 end process; 6398 6399end rtl; 6400library IEEE; 6401use IEEE.std_logic_1164.all; 6402 6403entity SRFF is port ( 6404 s,r: in std_logic; 6405 clk: in std_logic; 6406 q: out std_logic 6407 ); 6408end SRFF; 6409 6410architecture rtl of SRFF is 6411 6412begin 6413 6414 process begin 6415 wait until clk = '1'; 6416 if s = '0' and r = '1' then 6417 q <= '0'; 6418 elsif s = '1' and r = '0' then 6419 q <= '1'; 6420 end if; 6421 end process; 6422 6423end rtl; 6424library IEEE; 6425use IEEE.std_logic_1164.all; 6426 6427package scaleable is 6428 component scaleUpCnt port ( 6429 clk: in std_logic; 6430 reset: in std_logic; 6431 cnt: in std_logic_vector 6432 ); 6433 end component; 6434end scaleable; 6435 6436library IEEE; 6437use IEEE.std_logic_1164.all; 6438 6439use work.primitive.all; 6440 6441entity scaleUpCnt is port ( 6442 clk: in std_logic; 6443 reset: in std_logic; 6444 cnt: out std_logic_vector 6445 ); 6446end scaleUpCnt; 6447 6448architecture scaleable of scaleUpCnt is 6449 6450signal one: std_logic := '1'; 6451signal cntL: std_logic_vector(cnt'range); 6452signal andTerm: std_logic_vector(cnt'range); 6453 6454begin 6455 6456-- Special case is the least significant bit 6457 6458 lsb: tff port map (t => one, 6459 reset => reset, 6460 clk => clk, 6461 q => cntL(cntL'low) 6462 ); 6463 6464 andTerm(0) <= cntL(cntL'low); 6465 6466 6467-- General case for all other bits 6468 6469 genAnd: for i in 1 to cntL'high generate 6470 andTerm(i) <= andTerm(i - 1) and cntL(i); 6471 end generate; 6472 6473 genTFF: for i in 1 to cntL'high generate 6474 t1: tff port map (t => andTerm(i), 6475 clk => clk, 6476 reset => reset, 6477 q => cntl(i) 6478 ); 6479 end generate; 6480 6481 cnt <= CntL; 6482 6483end scaleable; 6484library IEEE; 6485use IEEE.std_logic_1164.all; 6486 6487entity pci_target is port ( 6488 PCI_Frame_n: in std_logic; -- PCI Frame# 6489 PCI_Irdy_n: in std_logic; -- PCI Irdy# 6490 Hit: in std_logic; -- Hit on address decode 6491 D_Done: in std_logic; -- Device decode complete 6492 Term: in std_logic; -- Terminate transaction 6493 Ready: in std_logic; -- Ready to transfer data 6494 Cmd_Write: in std_logic; -- Command is Write 6495 Cmd_Read: in std_logic; -- Command is Read 6496 T_Abort: in std_logic; -- Target error - abort transaction 6497 PCI_Clk: in std_logic; -- PCI Clock 6498 PCI_Reset_n: in std_logic; -- PCI Reset# 6499 6500 PCI_Devsel_n: out std_logic; -- PCI Devsel# 6501 PCI_Trdy_n: out std_logic; -- PCI Trdy# 6502 PCI_Stop_n: out std_logic; -- PCI Stop# 6503 OE_AD: out std_logic; -- PCI AD bus enable 6504 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 6505 OE_Stop_n: out std_logic; -- PCI Stop# enable 6506 OE_Devsel_n: out std_logic -- PCI Devsel# enable 6507 6508 ); 6509end pci_target; 6510 6511architecture fsm of pci_target is 6512 6513signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 6514 6515subtype targetFsmType is std_logic_vector(2 downto 0); 6516 6517constant Idle: targetFsmType := "000"; 6518constant B_Busy: targetFsmType := "101"; 6519constant Backoff: targetFsmType := "010"; 6520constant S_Data: targetFsmType := "011"; 6521constant Turn_Ar: targetFsmType := "110"; 6522 6523signal currState, nextState: targetFsmType; 6524 6525begin 6526 6527 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 6528 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 6529 case currState is 6530 when IDLE => 6531 if (PCI_Frame_n = '0' and Hit = '0') then 6532 nextState <= B_BUSY; 6533 else 6534 nextState <= IDLE; 6535 end if; 6536 6537 when B_BUSY => 6538 if (PCI_Frame_n ='1' and D_Done = '1') or 6539 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 6540 nextState <= IDLE; 6541 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 6542 (Term = '0' or (Term = '1' and Ready = '1') ) then 6543 nextState <= S_Data; 6544 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 6545 (Term = '1' and Ready = '0') then 6546 nextState <= BACKOFF; 6547 else 6548 nextState <= B_BUSY; 6549 end if; 6550 6551 when S_DATA => 6552 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 6553 nextState <= BACKOFF; 6554 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 6555 nextState <= TURN_AR; 6556 else 6557 nextState <= S_DATA; 6558 end if; 6559 6560 6561 when BACKOFF => 6562 if PCI_Frame_n = '1' then 6563 nextState <= TURN_AR; 6564 else 6565 nextState <= BACKOFF; 6566 end if; 6567 6568 when TURN_AR => 6569 if (PCI_Frame_n = '0' and Hit = '0') then 6570 nextState <= B_BUSY; 6571 else 6572 nextState <= IDLE; 6573 end if; 6574 6575 when others => 6576 null; 6577 end case; 6578 end process nxtStProc; 6579 6580 6581 curStProc: process (PCI_Clk, PCI_Reset_n) begin 6582 if (PCI_Reset_n = '0') then 6583 currState <= Idle; 6584 elsif (PCI_Clk'event and PCI_Clk = '1') then 6585 currState <= nextState; 6586 end if; 6587 end process curStProc; 6588 6589 6590 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 6591 Cmd_Read, T_Abort, Term) begin 6592 case currState is 6593 when S_Data => 6594 if (Cmd_Read = '1') then 6595 OE_AD <= '1'; 6596 else 6597 OE_AD <= '0'; 6598 end if; 6599 6600 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 6601 LPCI_Trdy_n <= '0'; 6602 else 6603 LPCI_Trdy_n <= '1'; 6604 end if; 6605 6606 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 6607 LPCI_Stop_n <= '0'; 6608 else 6609 LPCI_Stop_n <= '1'; 6610 end if; 6611 6612 if (T_Abort = '0') then 6613 LPCI_Devsel_n <= '0'; 6614 else 6615 LPCI_Devsel_n <= '1'; 6616 end if; 6617 6618 OE_Trdy_n <= '1'; 6619 OE_Stop_n <= '1'; 6620 OE_Devsel_n <= '1'; 6621 6622 when Backoff => 6623 if (Cmd_Read = '1') then 6624 OE_AD <= '1'; 6625 else 6626 OE_AD <= '0'; 6627 end if; 6628 6629 LPCI_Stop_n <= '0'; 6630 6631 OE_Trdy_n <= '1'; 6632 OE_Stop_n <= '1'; 6633 OE_Devsel_n <= '1'; 6634 6635 if (T_Abort = '0') then 6636 LPCI_Devsel_n <= '0'; 6637 else 6638 LPCI_Devsel_n <= '1'; 6639 end if; 6640 6641 when Turn_Ar => 6642 6643 OE_Trdy_n <= '1'; 6644 OE_Stop_n <= '1'; 6645 OE_Devsel_n <= '1'; 6646 6647 when others => 6648 6649 OE_Trdy_n <= '0'; 6650 OE_Stop_n <= '0'; 6651 OE_Devsel_n <= '0'; 6652 OE_AD <= '0'; 6653 LPCI_Trdy_n <= '1'; 6654 LPCI_Stop_n <= '1'; 6655 LPCI_Devsel_n <= '1'; 6656 6657 end case; 6658 6659 end process outConProc; 6660 6661 PCI_Devsel_n <= LPCI_Devsel_n; 6662 PCI_Trdy_n <= LPCI_Trdy_n; 6663 PCI_Stop_n <= LPCI_Stop_n; 6664 6665end fsm; 6666library IEEE; 6667use IEEE.std_logic_1164.all; 6668 6669entity pci_target is port ( 6670 PCI_Frame_n: in std_logic; -- PCI Frame# 6671 PCI_Irdy_n: in std_logic; -- PCI Irdy# 6672 Hit: in std_logic; -- Hit on address decode 6673 D_Done: in std_logic; -- Device decode complete 6674 Term: in std_logic; -- Terminate transaction 6675 Ready: in std_logic; -- Ready to transfer data 6676 Cmd_Write: in std_logic; -- Command is Write 6677 Cmd_Read: in std_logic; -- Command is Read 6678 T_Abort: in std_logic; -- Target error - abort transaction 6679 PCI_Clk: in std_logic; -- PCI Clock 6680 PCI_Reset_n: in std_logic; -- PCI Reset# 6681 6682 PCI_Devsel_n: out std_logic; -- PCI Devsel# 6683 PCI_Trdy_n: out std_logic; -- PCI Trdy# 6684 PCI_Stop_n: out std_logic; -- PCI Stop# 6685 OE_AD: out std_logic; -- PCI AD bus enable 6686 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 6687 OE_Stop_n: out std_logic; -- PCI Stop# enable 6688 OE_Devsel_n: out std_logic -- PCI Devsel# enable 6689 6690 ); 6691end pci_target; 6692 6693architecture fsm of pci_target is 6694 6695signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 6696 6697subtype targetFsmType is std_logic_vector(2 downto 0); 6698 6699constant Idle: targetFsmType := "000"; 6700constant B_Busy: targetFsmType := "001"; 6701constant Backoff: targetFsmType := "011"; 6702constant S_Data: targetFsmType := "010"; 6703constant Turn_Ar: targetFsmType := "110"; 6704 6705signal currState, nextState: targetFsmType; 6706 6707begin 6708 6709 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 6710 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 6711 case currState is 6712 when IDLE => 6713 if (PCI_Frame_n = '0' and Hit = '0') then 6714 nextState <= B_BUSY; 6715 else 6716 nextState <= IDLE; 6717 end if; 6718 6719 when B_BUSY => 6720 if (PCI_Frame_n ='1' and D_Done = '1') or 6721 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 6722 nextState <= IDLE; 6723 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 6724 (Term = '0' or (Term = '1' and Ready = '1') ) then 6725 nextState <= S_Data; 6726 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 6727 (Term = '1' and Ready = '0') then 6728 nextState <= BACKOFF; 6729 else 6730 nextState <= B_BUSY; 6731 end if; 6732 6733 when S_DATA => 6734 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 6735 nextState <= BACKOFF; 6736 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 6737 nextState <= TURN_AR; 6738 else 6739 nextState <= S_DATA; 6740 end if; 6741 6742 6743 when BACKOFF => 6744 if PCI_Frame_n = '1' then 6745 nextState <= TURN_AR; 6746 else 6747 nextState <= BACKOFF; 6748 end if; 6749 6750 when TURN_AR => 6751 if (PCI_Frame_n = '0' and Hit = '0') then 6752 nextState <= B_BUSY; 6753 else 6754 nextState <= IDLE; 6755 end if; 6756 6757 when others => 6758 null; 6759 end case; 6760 end process nxtStProc; 6761 6762 6763 curStProc: process (PCI_Clk, PCI_Reset_n) begin 6764 if (PCI_Reset_n = '0') then 6765 currState <= Idle; 6766 elsif (PCI_Clk'event and PCI_Clk = '1') then 6767 currState <= nextState; 6768 end if; 6769 end process curStProc; 6770 6771 6772 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 6773 Cmd_Read, T_Abort, Term) begin 6774 case currState is 6775 when S_Data => 6776 if (Cmd_Read = '1') then 6777 OE_AD <= '1'; 6778 else 6779 OE_AD <= '0'; 6780 end if; 6781 6782 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 6783 LPCI_Trdy_n <= '0'; 6784 else 6785 LPCI_Trdy_n <= '1'; 6786 end if; 6787 6788 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 6789 LPCI_Stop_n <= '0'; 6790 else 6791 LPCI_Stop_n <= '1'; 6792 end if; 6793 6794 if (T_Abort = '0') then 6795 LPCI_Devsel_n <= '0'; 6796 else 6797 LPCI_Devsel_n <= '1'; 6798 end if; 6799 6800 OE_Trdy_n <= '1'; 6801 OE_Stop_n <= '1'; 6802 OE_Devsel_n <= '1'; 6803 6804 when Backoff => 6805 if (Cmd_Read = '1') then 6806 OE_AD <= '1'; 6807 else 6808 OE_AD <= '0'; 6809 end if; 6810 6811 LPCI_Stop_n <= '0'; 6812 6813 OE_Trdy_n <= '1'; 6814 OE_Stop_n <= '1'; 6815 OE_Devsel_n <= '1'; 6816 6817 if (T_Abort = '0') then 6818 LPCI_Devsel_n <= '0'; 6819 else 6820 LPCI_Devsel_n <= '1'; 6821 end if; 6822 6823 when Turn_Ar => 6824 6825 OE_Trdy_n <= '1'; 6826 OE_Stop_n <= '1'; 6827 OE_Devsel_n <= '1'; 6828 6829 when others => 6830 6831 OE_Trdy_n <= '0'; 6832 OE_Stop_n <= '0'; 6833 OE_Devsel_n <= '0'; 6834 OE_AD <= '0'; 6835 LPCI_Trdy_n <= '1'; 6836 LPCI_Stop_n <= '1'; 6837 LPCI_Devsel_n <= '1'; 6838 6839 end case; 6840 6841 end process outConProc; 6842 6843 PCI_Devsel_n <= LPCI_Devsel_n; 6844 PCI_Trdy_n <= LPCI_Trdy_n; 6845 PCI_Stop_n <= LPCI_Stop_n; 6846 6847end fsm; 6848library IEEE; 6849use IEEE.std_logic_1164.all; 6850 6851entity pci_target is port ( 6852 PCI_Frame_n: in std_logic; -- PCI Frame# 6853 PCI_Irdy_n: in std_logic; -- PCI Irdy# 6854 Hit: in std_logic; -- Hit on address decode 6855 D_Done: in std_logic; -- Device decode complete 6856 Term: in std_logic; -- Terminate transaction 6857 Ready: in std_logic; -- Ready to transfer data 6858 Cmd_Write: in std_logic; -- Command is Write 6859 Cmd_Read: in std_logic; -- Command is Read 6860 T_Abort: in std_logic; -- Target error - abort transaction 6861 PCI_Clk: in std_logic; -- PCI Clock 6862 PCI_Reset_n: in std_logic; -- PCI Reset# 6863 6864 PCI_Devsel_n: out std_logic; -- PCI Devsel# 6865 PCI_Trdy_n: out std_logic; -- PCI Trdy# 6866 PCI_Stop_n: out std_logic; -- PCI Stop# 6867 OE_AD: out std_logic; -- PCI AD bus enable 6868 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 6869 OE_Stop_n: out std_logic; -- PCI Stop# enable 6870 OE_Devsel_n: out std_logic -- PCI Devsel# enable 6871 6872 ); 6873end pci_target; 6874 6875architecture fsm of pci_target is 6876 6877signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 6878 6879subtype targetFsmType is std_logic_vector(2 downto 0); 6880 6881constant Idle: targetFsmType := "000"; 6882constant B_Busy: targetFsmType := "001"; 6883constant Backoff: targetFsmType := "010"; 6884constant S_Data: targetFsmType := "011"; 6885constant Turn_Ar: targetFsmType := "100"; 6886 6887signal currState, nextState: targetFsmType; 6888 6889begin 6890 6891 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 6892 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 6893 case currState is 6894 when IDLE => 6895 if (PCI_Frame_n = '0' and Hit = '0') then 6896 nextState <= B_BUSY; 6897 else 6898 nextState <= IDLE; 6899 end if; 6900 6901 when B_BUSY => 6902 if (PCI_Frame_n ='1' and D_Done = '1') or 6903 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 6904 nextState <= IDLE; 6905 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 6906 (Term = '0' or (Term = '1' and Ready = '1') ) then 6907 nextState <= S_Data; 6908 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 6909 (Term = '1' and Ready = '0') then 6910 nextState <= BACKOFF; 6911 else 6912 nextState <= B_BUSY; 6913 end if; 6914 6915 when S_DATA => 6916 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 6917 nextState <= BACKOFF; 6918 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 6919 nextState <= TURN_AR; 6920 else 6921 nextState <= S_DATA; 6922 end if; 6923 6924 6925 when BACKOFF => 6926 if PCI_Frame_n = '1' then 6927 nextState <= TURN_AR; 6928 else 6929 nextState <= BACKOFF; 6930 end if; 6931 6932 when TURN_AR => 6933 if (PCI_Frame_n = '0' and Hit = '0') then 6934 nextState <= B_BUSY; 6935 else 6936 nextState <= IDLE; 6937 end if; 6938 6939 when others => 6940 null; 6941 end case; 6942 end process nxtStProc; 6943 6944 6945 curStProc: process (PCI_Clk, PCI_Reset_n) begin 6946 if (PCI_Reset_n = '0') then 6947 currState <= Idle; 6948 elsif (PCI_Clk'event and PCI_Clk = '1') then 6949 currState <= nextState; 6950 end if; 6951 end process curStProc; 6952 6953 6954 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 6955 Cmd_Read, T_Abort, Term) begin 6956 case currState is 6957 when S_Data => 6958 if (Cmd_Read = '1') then 6959 OE_AD <= '1'; 6960 else 6961 OE_AD <= '0'; 6962 end if; 6963 6964 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 6965 LPCI_Trdy_n <= '0'; 6966 else 6967 LPCI_Trdy_n <= '1'; 6968 end if; 6969 6970 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 6971 LPCI_Stop_n <= '0'; 6972 else 6973 LPCI_Stop_n <= '1'; 6974 end if; 6975 6976 if (T_Abort = '0') then 6977 LPCI_Devsel_n <= '0'; 6978 else 6979 LPCI_Devsel_n <= '1'; 6980 end if; 6981 6982 OE_Trdy_n <= '1'; 6983 OE_Stop_n <= '1'; 6984 OE_Devsel_n <= '1'; 6985 6986 when Backoff => 6987 if (Cmd_Read = '1') then 6988 OE_AD <= '1'; 6989 else 6990 OE_AD <= '0'; 6991 end if; 6992 6993 LPCI_Stop_n <= '0'; 6994 6995 OE_Trdy_n <= '1'; 6996 OE_Stop_n <= '1'; 6997 OE_Devsel_n <= '1'; 6998 6999 if (T_Abort = '0') then 7000 LPCI_Devsel_n <= '0'; 7001 else 7002 LPCI_Devsel_n <= '1'; 7003 end if; 7004 7005 when Turn_Ar => 7006 7007 OE_Trdy_n <= '1'; 7008 OE_Stop_n <= '1'; 7009 OE_Devsel_n <= '1'; 7010 7011 when others => 7012 7013 OE_Trdy_n <= '0'; 7014 OE_Stop_n <= '0'; 7015 OE_Devsel_n <= '0'; 7016 OE_AD <= '0'; 7017 LPCI_Trdy_n <= '1'; 7018 LPCI_Stop_n <= '1'; 7019 LPCI_Devsel_n <= '1'; 7020 7021 end case; 7022 7023 end process outConProc; 7024 7025 PCI_Devsel_n <= LPCI_Devsel_n; 7026 PCI_Trdy_n <= LPCI_Trdy_n; 7027 PCI_Stop_n <= LPCI_Stop_n; 7028 7029end fsm; 7030library IEEE; 7031use IEEE.std_logic_1164.all; 7032 7033entity pci_target is port ( 7034 PCI_Frame_n: in std_logic; -- PCI Frame# 7035 PCI_Irdy_n: in std_logic; -- PCI Irdy# 7036 Hit: in std_logic; -- Hit on address decode 7037 D_Done: in std_logic; -- Device decode complete 7038 Term: in std_logic; -- Terminate transaction 7039 Ready: in std_logic; -- Ready to transfer data 7040 Cmd_Write: in std_logic; -- Command is Write 7041 Cmd_Read: in std_logic; -- Command is Read 7042 T_Abort: in std_logic; -- Target error - abort transaction 7043 PCI_Clk: in std_logic; -- PCI Clock 7044 PCI_Reset_n: in std_logic; -- PCI Reset# 7045 7046 PCI_Devsel_n: out std_logic; -- PCI Devsel# 7047 PCI_Trdy_n: out std_logic; -- PCI Trdy# 7048 PCI_Stop_n: out std_logic; -- PCI Stop# 7049 OE_AD: out std_logic; -- PCI AD bus enable 7050 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 7051 OE_Stop_n: out std_logic; -- PCI Stop# enable 7052 OE_Devsel_n: out std_logic -- PCI Devsel# enable 7053 7054 ); 7055end pci_target; 7056 7057architecture fsm of pci_target is 7058 7059signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 7060 7061subtype targetFsmType is std_logic_vector(3 downto 0); 7062 7063constant Idle: targetFsmType := "0000"; 7064constant B_Busy: targetFsmType := "0001"; 7065constant Backoff: targetFsmType := "0011"; 7066constant S_Data: targetFsmType := "1100"; 7067constant Turn_Ar: targetFsmType := "1101"; 7068 7069signal currState, nextState: targetFsmType; 7070 7071begin 7072 7073 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 7074 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 7075 case currState is 7076 when IDLE => 7077 if (PCI_Frame_n = '0' and Hit = '0') then 7078 nextState <= B_BUSY; 7079 else 7080 nextState <= IDLE; 7081 end if; 7082 7083 when B_BUSY => 7084 if (PCI_Frame_n ='1' and D_Done = '1') or 7085 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 7086 nextState <= IDLE; 7087 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7088 (Term = '0' or (Term = '1' and Ready = '1') ) then 7089 nextState <= S_Data; 7090 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7091 (Term = '1' and Ready = '0') then 7092 nextState <= BACKOFF; 7093 else 7094 nextState <= B_BUSY; 7095 end if; 7096 7097 when S_DATA => 7098 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 7099 nextState <= BACKOFF; 7100 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 7101 nextState <= TURN_AR; 7102 else 7103 nextState <= S_DATA; 7104 end if; 7105 7106 7107 when BACKOFF => 7108 if PCI_Frame_n = '1' then 7109 nextState <= TURN_AR; 7110 else 7111 nextState <= BACKOFF; 7112 end if; 7113 7114 when TURN_AR => 7115 if (PCI_Frame_n = '0' and Hit = '0') then 7116 nextState <= B_BUSY; 7117 else 7118 nextState <= IDLE; 7119 end if; 7120 7121 when others => 7122 null; 7123 end case; 7124 end process nxtStProc; 7125 7126 7127 curStProc: process (PCI_Clk, PCI_Reset_n) begin 7128 if (PCI_Reset_n = '0') then 7129 currState <= Idle; 7130 elsif (PCI_Clk'event and PCI_Clk = '1') then 7131 currState <= nextState; 7132 end if; 7133 end process curStProc; 7134 7135 7136 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 7137 Cmd_Read, T_Abort, Term) begin 7138 case currState is 7139 when S_Data => 7140 if (Cmd_Read = '1') then 7141 OE_AD <= '1'; 7142 else 7143 OE_AD <= '0'; 7144 end if; 7145 7146 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 7147 LPCI_Trdy_n <= '0'; 7148 else 7149 LPCI_Trdy_n <= '1'; 7150 end if; 7151 7152 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 7153 LPCI_Stop_n <= '0'; 7154 else 7155 LPCI_Stop_n <= '1'; 7156 end if; 7157 7158 if (T_Abort = '0') then 7159 LPCI_Devsel_n <= '0'; 7160 else 7161 LPCI_Devsel_n <= '1'; 7162 end if; 7163 7164 OE_Trdy_n <= '1'; 7165 OE_Stop_n <= '1'; 7166 OE_Devsel_n <= '1'; 7167 7168 when Backoff => 7169 if (Cmd_Read = '1') then 7170 OE_AD <= '1'; 7171 else 7172 OE_AD <= '0'; 7173 end if; 7174 7175 LPCI_Stop_n <= '0'; 7176 7177 OE_Trdy_n <= '1'; 7178 OE_Stop_n <= '1'; 7179 OE_Devsel_n <= '1'; 7180 7181 if (T_Abort = '0') then 7182 LPCI_Devsel_n <= '0'; 7183 else 7184 LPCI_Devsel_n <= '1'; 7185 end if; 7186 7187 when Turn_Ar => 7188 7189 OE_Trdy_n <= '1'; 7190 OE_Stop_n <= '1'; 7191 OE_Devsel_n <= '1'; 7192 7193 when others => 7194 7195 OE_Trdy_n <= '0'; 7196 OE_Stop_n <= '0'; 7197 OE_Devsel_n <= '0'; 7198 OE_AD <= '0'; 7199 LPCI_Trdy_n <= '1'; 7200 LPCI_Stop_n <= '1'; 7201 LPCI_Devsel_n <= '1'; 7202 7203 end case; 7204 7205 end process outConProc; 7206 7207 PCI_Devsel_n <= LPCI_Devsel_n; 7208 PCI_Trdy_n <= LPCI_Trdy_n; 7209 PCI_Stop_n <= LPCI_Stop_n; 7210 7211end fsm; 7212library IEEE; 7213use IEEE.std_logic_1164.all; 7214 7215entity pci_target is port ( 7216 PCI_Frame_n: in std_logic; -- PCI Frame# 7217 PCI_Irdy_n: in std_logic; -- PCI Irdy# 7218 Hit: in std_logic; -- Hit on address decode 7219 D_Done: in std_logic; -- Device decode complete 7220 Term: in std_logic; -- Terminate transaction 7221 Ready: in std_logic; -- Ready to transfer data 7222 Cmd_Write: in std_logic; -- Command is Write 7223 Cmd_Read: in std_logic; -- Command is Read 7224 T_Abort: in std_logic; -- Target error - abort transaction 7225 PCI_Clk: in std_logic; -- PCI Clock 7226 PCI_Reset_n: in std_logic; -- PCI Reset# 7227 7228 PCI_Devsel_n: out std_logic; -- PCI Devsel# 7229 PCI_Trdy_n: out std_logic; -- PCI Trdy# 7230 PCI_Stop_n: out std_logic; -- PCI Stop# 7231 OE_AD: out std_logic; -- PCI AD bus enable 7232 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 7233 OE_Stop_n: out std_logic; -- PCI Stop# enable 7234 OE_Devsel_n: out std_logic -- PCI Devsel# enable 7235 7236 ); 7237end pci_target; 7238 7239architecture fsm of pci_target is 7240 7241signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 7242 7243subtype targetFsmType is std_logic_vector(2 downto 0); 7244 7245constant Idle: targetFsmType := "000"; 7246constant B_Busy: targetFsmType := "101"; 7247constant Backoff: targetFsmType := "010"; 7248constant S_Data: targetFsmType := "011"; 7249constant Turn_Ar: targetFsmType := "110"; 7250constant Dont_Care: targetFsmType := "XXX"; 7251 7252signal currState, nextState: targetFsmType; 7253 7254begin 7255 7256 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 7257 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 7258 case currState is 7259 when IDLE => 7260 if (PCI_Frame_n = '0' and Hit = '0') then 7261 nextState <= B_BUSY; 7262 else 7263 nextState <= IDLE; 7264 end if; 7265 7266 when B_BUSY => 7267 if (PCI_Frame_n ='1' and D_Done = '1') or 7268 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 7269 nextState <= IDLE; 7270 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7271 (Term = '0' or (Term = '1' and Ready = '1') ) then 7272 nextState <= S_Data; 7273 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7274 (Term = '1' and Ready = '0') then 7275 nextState <= BACKOFF; 7276 else 7277 nextState <= B_BUSY; 7278 end if; 7279 7280 when S_DATA => 7281 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 7282 nextState <= BACKOFF; 7283 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 7284 nextState <= TURN_AR; 7285 else 7286 nextState <= S_DATA; 7287 end if; 7288 7289 7290 when BACKOFF => 7291 if PCI_Frame_n = '1' then 7292 nextState <= TURN_AR; 7293 else 7294 nextState <= BACKOFF; 7295 end if; 7296 7297 when TURN_AR => 7298 if (PCI_Frame_n = '0' and Hit = '0') then 7299 nextState <= B_BUSY; 7300 else 7301 nextState <= IDLE; 7302 end if; 7303 7304 when others => 7305 nextState <= Dont_Care; 7306 end case; 7307 end process nxtStProc; 7308 7309 7310 curStProc: process (PCI_Clk, PCI_Reset_n) begin 7311 if (PCI_Reset_n = '0') then 7312 currState <= Idle; 7313 elsif (PCI_Clk'event and PCI_Clk = '1') then 7314 currState <= nextState; 7315 end if; 7316 end process curStProc; 7317 7318 7319 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 7320 Cmd_Read, T_Abort, Term) begin 7321 7322 -- Set default output assignments 7323 OE_Trdy_n <= '0'; 7324 OE_Stop_n <= '0'; 7325 OE_Devsel_n <= '0'; 7326 OE_AD <= '0'; 7327 LPCI_Trdy_n <= '1'; 7328 LPCI_Stop_n <= '1'; 7329 LPCI_Devsel_n <= '1'; 7330 7331 case currState is 7332 when S_Data => 7333 if (Cmd_Read = '1') then 7334 OE_AD <= '1'; 7335 else 7336 OE_AD <= '0'; 7337 end if; 7338 7339 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 7340 LPCI_Trdy_n <= '0'; 7341 else 7342 LPCI_Trdy_n <= '1'; 7343 end if; 7344 7345 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 7346 LPCI_Stop_n <= '0'; 7347 else 7348 LPCI_Stop_n <= '1'; 7349 end if; 7350 7351 if (T_Abort = '0') then 7352 LPCI_Devsel_n <= '0'; 7353 else 7354 LPCI_Devsel_n <= '1'; 7355 end if; 7356 7357 OE_Trdy_n <= '1'; 7358 OE_Stop_n <= '1'; 7359 OE_Devsel_n <= '1'; 7360 7361 when Backoff => 7362 if (Cmd_Read = '1') then 7363 OE_AD <= '1'; 7364 else 7365 OE_AD <= '0'; 7366 end if; 7367 7368 LPCI_Stop_n <= '0'; 7369 7370 OE_Trdy_n <= '1'; 7371 OE_Stop_n <= '1'; 7372 OE_Devsel_n <= '1'; 7373 7374 if (T_Abort = '0') then 7375 LPCI_Devsel_n <= '0'; 7376 else 7377 LPCI_Devsel_n <= '1'; 7378 end if; 7379 7380 when Turn_Ar => 7381 7382 OE_Trdy_n <= '1'; 7383 OE_Stop_n <= '1'; 7384 OE_Devsel_n <= '1'; 7385 7386 when others => 7387 7388 OE_Trdy_n <= '0'; 7389 OE_Stop_n <= '0'; 7390 OE_Devsel_n <= '0'; 7391 OE_AD <= '0'; 7392 LPCI_Trdy_n <= '1'; 7393 LPCI_Stop_n <= '1'; 7394 LPCI_Devsel_n <= '1'; 7395 7396 end case; 7397 7398 end process outConProc; 7399 7400 PCI_Devsel_n <= LPCI_Devsel_n; 7401 PCI_Trdy_n <= LPCI_Trdy_n; 7402 PCI_Stop_n <= LPCI_Stop_n; 7403 7404end fsm; 7405library IEEE; 7406use IEEE.std_logic_1164.all; 7407 7408entity pci_target is port ( 7409 PCI_Frame_n: in std_logic; -- PCI Frame# 7410 PCI_Irdy_n: in std_logic; -- PCI Irdy# 7411 Hit: in std_logic; -- Hit on address decode 7412 D_Done: in std_logic; -- Device decode complete 7413 Term: in std_logic; -- Terminate transaction 7414 Ready: in std_logic; -- Ready to transfer data 7415 Cmd_Write: in std_logic; -- Command is Write 7416 Cmd_Read: in std_logic; -- Command is Read 7417 T_Abort: in std_logic; -- Target error - abort transaction 7418 PCI_Clk: in std_logic; -- PCI Clock 7419 PCI_Reset_n: in std_logic; -- PCI Reset# 7420 7421 PCI_Devsel_n: out std_logic; -- PCI Devsel# 7422 PCI_Stop_n: out std_logic; -- PCI Stop# 7423 PCI_Trdy_n: out std_logic; -- PCI Trdy# 7424 OE_AD: out std_logic; -- PCI AD bus enable 7425 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 7426 OE_Stop_n: out std_logic; -- PCI Stop# enable 7427 OE_Devsel_n: out std_logic -- PCI Devsel# enable 7428 ); 7429end pci_target; 7430 7431architecture fsm of pci_target is 7432 7433signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 7434 7435type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar); 7436 7437signal currState, nextState: targetFsmType; 7438 7439begin 7440 7441-- Process to generate next state logic 7442 7443 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 7444 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 7445 case currState is 7446 when Idle => 7447 if (PCI_Frame_n = '0' and Hit = '0') then 7448 nextState <= B_Busy; 7449 else 7450 nextState <= Idle; 7451 end if; 7452 7453 when B_Busy => 7454 if (PCI_Frame_n ='1' and D_Done = '1') or 7455 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 7456 nextState <= Idle; 7457 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7458 (Term = '0' or (Term = '1' and Ready = '1') ) then 7459 nextState <= S_Data; 7460 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7461 (Term = '1' and Ready = '0') then 7462 nextState <= Backoff; 7463 else 7464 nextState <= B_Busy; 7465 end if; 7466 7467 when S_Data => 7468 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 7469 nextState <= Backoff; 7470 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 7471 nextState <= Turn_Ar; 7472 else 7473 nextState <= S_Data; 7474 end if; 7475 7476 7477 when Backoff => 7478 if PCI_Frame_n = '1' then 7479 nextState <= Turn_Ar; 7480 else 7481 nextState <= Backoff; 7482 end if; 7483 7484 when Turn_Ar => 7485 if (PCI_Frame_n = '0' and Hit = '0') then 7486 nextState <= B_Busy; 7487 else 7488 nextState <= Idle; 7489 end if; 7490 7491 when others => 7492 null; 7493 7494 end case; 7495 7496 end process nxtStProc; 7497 7498 7499-- Process to register the current state 7500 7501 curStProc: process (PCI_Clk, PCI_Reset_n) begin 7502 if (PCI_Reset_n = '0') then 7503 currState <= Idle; 7504 elsif (PCI_Clk'event and PCI_Clk = '1') then 7505 currState <= nextState; 7506 end if; 7507 end process curStProc; 7508 7509 7510-- Process to generate outputs 7511 7512 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 7513 Cmd_Read, T_Abort, Term) begin 7514 case currState is 7515 when S_Data => 7516 if (Cmd_Read = '1') then 7517 OE_AD <= '1'; 7518 else 7519 OE_AD <= '0'; 7520 end if; 7521 7522 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 7523 LPCI_Trdy_n <= '0'; 7524 else 7525 LPCI_Trdy_n <= '1'; 7526 end if; 7527 7528 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 7529 LPCI_Stop_n <= '0'; 7530 else 7531 LPCI_Stop_n <= '1'; 7532 end if; 7533 7534 if (T_Abort = '0') then 7535 LPCI_Devsel_n <= '0'; 7536 else 7537 LPCI_Devsel_n <= '1'; 7538 end if; 7539 7540 OE_Trdy_n <= '1'; 7541 OE_Stop_n <= '1'; 7542 OE_Devsel_n <= '1'; 7543 7544 when Backoff => 7545 if (Cmd_Read = '1') then 7546 OE_AD <= '1'; 7547 else 7548 OE_AD <= '0'; 7549 end if; 7550 7551 LPCI_Stop_n <= '0'; 7552 7553 OE_Trdy_n <= '1'; 7554 OE_Stop_n <= '1'; 7555 OE_Devsel_n <= '1'; 7556 7557 if (T_Abort = '0') then 7558 LPCI_Devsel_n <= '0'; 7559 else 7560 LPCI_Devsel_n <= '1'; 7561 end if; 7562 7563 when Turn_Ar => 7564 7565 OE_Trdy_n <= '1'; 7566 OE_Stop_n <= '1'; 7567 OE_Devsel_n <= '1'; 7568 7569 when others => 7570 7571 OE_Trdy_n <= '0'; 7572 OE_Stop_n <= '0'; 7573 OE_Devsel_n <= '0'; 7574 OE_AD <= '0'; 7575 LPCI_Trdy_n <= '1'; 7576 LPCI_Stop_n <= '1'; 7577 LPCI_Devsel_n <= '1'; 7578 7579 end case; 7580 7581 end process outConProc; 7582 7583-- Assign output ports 7584 7585 PCI_Devsel_n <= LPCI_Devsel_n; 7586 PCI_Trdy_n <= LPCI_Trdy_n; 7587 PCI_Stop_n <= LPCI_Stop_n; 7588 7589end fsm; 7590-- Incorporates Errata 10.1 and 10.2 7591 7592library IEEE; 7593use IEEE.std_logic_1164.all; 7594 7595entity pci_target is port ( 7596 PCI_Frame_n: in std_logic; -- PCI Frame# 7597 PCI_Irdy_n: in std_logic; -- PCI Irdy# 7598 Hit: in std_logic; -- Hit on address decode 7599 D_Done: in std_logic; -- Device decode complete 7600 Term: in std_logic; -- Terminate transaction 7601 Ready: in std_logic; -- Ready to transfer data 7602 Cmd_Write: in std_logic; -- Command is Write 7603 Cmd_Read: in std_logic; -- Command is Read 7604 T_Abort: in std_logic; -- Target error - abort transaction 7605 PCI_Clk: in std_logic; -- PCI Clock 7606 PCI_Reset_n: in std_logic; -- PCI Reset# 7607 7608 PCI_Devsel_n: out std_logic; -- PCI Devsel# 7609 PCI_Trdy_n: out std_logic; -- PCI Trdy# 7610 PCI_Stop_n: out std_logic; -- PCI Stop# 7611 OE_AD: out std_logic; -- PCI AD bus enable 7612 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 7613 OE_Stop_n: out std_logic; -- PCI Stop# enable 7614 OE_Devsel_n: out std_logic -- PCI Devsel# enable 7615 ); 7616end pci_target; 7617 7618architecture fsm of pci_target is 7619 7620signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 7621 7622subtype targetFsmType is std_logic_vector(4 downto 0); 7623 7624constant Idle: integer := 0; 7625constant B_Busy: integer := 1; 7626constant Backoff: integer := 2; 7627constant S_Data: integer := 3; 7628constant Turn_Ar: integer := 4; 7629 7630signal currState, nextState: targetFsmType; 7631 7632begin 7633 7634 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 7635 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 7636 7637 nextState <= (others => '0'); 7638 7639 if currState(Idle) = '1' then 7640 if (PCI_Frame_n = '0' and Hit = '0') then 7641 nextState(B_Busy) <= '1'; 7642 else 7643 nextState(Idle) <= '1'; 7644 end if; 7645 end if; 7646 7647 if currState(B_Busy) = '1' then 7648 if (PCI_Frame_n ='1' and D_Done = '1') or 7649 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 7650 nextState(Idle) <= '1'; 7651 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7652 (Term = '0' or (Term = '1' and Ready = '1') ) then 7653 nextState(S_Data) <= '1'; 7654 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7655 (Term = '1' and Ready = '0') then 7656 nextState(Backoff) <= '1'; 7657 else 7658 nextState(B_Busy) <= '1'; 7659 end if; 7660 end if; 7661 7662 if currState(S_Data) = '1' then 7663 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and 7664 (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 7665 nextState(Backoff) <= '1'; 7666 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 7667 nextState(Turn_Ar) <= '1'; 7668 else 7669 nextState(S_Data) <= '1'; 7670 end if; 7671 end if; 7672 7673 7674 if currState(Backoff) = '1' then 7675 if PCI_Frame_n = '1' then 7676 nextState(Turn_Ar) <= '1'; 7677 else 7678 nextState(Backoff) <= '1'; 7679 end if; 7680 end if; 7681 7682 if currState(Turn_Ar) = '1' then 7683 if (PCI_Frame_n = '0' and Hit = '0') then 7684 nextState(B_Busy) <= '1'; 7685 else 7686 nextState(Idle) <= '1'; 7687 end if; 7688 end if; 7689 7690 end process nxtStProc; 7691 7692 7693 curStProc: process (PCI_Clk, PCI_Reset_n) begin 7694 if (PCI_Reset_n = '0') then 7695 currState <= (others => '0'); -- per Errata 10.2 7696 currState(Idle) <= '1'; 7697 elsif (PCI_Clk'event and PCI_Clk = '1') then 7698 currState <= nextState; 7699 end if; 7700 end process curStProc; 7701 7702 7703 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 7704 Cmd_Read, T_Abort, Term) begin 7705 OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1 7706 OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1'; 7707 LPCI_Devsel_n <= '1'; 7708 7709 if (currState(S_Data) = '1') then 7710 if (Cmd_Read = '1') then 7711 OE_AD <= '1'; 7712 else 7713 OE_AD <= '0'; 7714 end if; 7715 7716 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 7717 LPCI_Trdy_n <= '0'; 7718 else 7719 LPCI_Trdy_n <= '1'; 7720 end if; 7721 7722 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 7723 LPCI_Stop_n <= '0'; 7724 else 7725 LPCI_Stop_n <= '1'; 7726 end if; 7727 7728 if (T_Abort = '0') then 7729 LPCI_Devsel_n <= '0'; 7730 else 7731 LPCI_Devsel_n <= '1'; 7732 end if; 7733 7734 OE_Trdy_n <= '1'; 7735 OE_Stop_n <= '1'; 7736 OE_Devsel_n <= '1'; 7737 end if; 7738 7739 7740 if (currState(Backoff) = '1') then 7741 if (Cmd_Read = '1') then 7742 OE_AD <= '1'; 7743 else 7744 OE_AD <= '0'; 7745 end if; 7746 7747 LPCI_Stop_n <= '0'; 7748 7749 OE_Trdy_n <= '1'; 7750 OE_Stop_n <= '1'; 7751 OE_Devsel_n <= '1'; 7752 7753 if (T_Abort = '0') then 7754 LPCI_Devsel_n <= '0'; 7755 else 7756 LPCI_Devsel_n <= '1'; 7757 end if; 7758 end if; 7759 7760 7761 if (currState(Turn_Ar) = '1') then 7762 OE_Trdy_n <= '1'; 7763 OE_Stop_n <= '1'; 7764 OE_Devsel_n <= '1'; 7765 end if; 7766 7767 if (currState(Idle) = '1' or currState(B_Busy) = '1') then 7768 OE_Trdy_n <= '0'; 7769 OE_Stop_n <= '0'; 7770 OE_Devsel_n <= '0'; 7771 OE_AD <= '0'; 7772 LPCI_Trdy_n <= '1'; 7773 LPCI_Stop_n <= '1'; 7774 LPCI_Devsel_n <= '1'; 7775 end if; 7776 7777 end process outConProc; 7778 7779 PCI_Devsel_n <= LPCI_Devsel_n; 7780 PCI_Trdy_n <= LPCI_Trdy_n; 7781 PCI_Stop_n <= LPCI_Stop_n; 7782 7783end fsm; 7784library IEEE; 7785use IEEE.std_logic_1164.all; 7786 7787entity pci_target is port ( 7788 PCI_Frame_n: in std_logic; -- PCI Frame# 7789 PCI_Irdy_n: in std_logic; -- PCI Irdy# 7790 Hit: in std_logic; -- Hit on address decode 7791 D_Done: in std_logic; -- Device decode complete 7792 Term: in std_logic; -- Terminate transaction 7793 Ready: in std_logic; -- Ready to transfer data 7794 Cmd_Write: in std_logic; -- Command is Write 7795 Cmd_Read: in std_logic; -- Command is Read 7796 T_Abort: in std_logic; -- Target error - abort transaction 7797 PCI_Clk: in std_logic; -- PCI Clock 7798 PCI_Reset_n: in std_logic; -- PCI Reset# 7799 7800 PCI_Devsel_n: out std_logic; -- PCI Devsel# 7801 PCI_Trdy_n: out std_logic; -- PCI Trdy# 7802 PCI_Stop_n: out std_logic; -- PCI Stop# 7803 OE_AD: out std_logic; -- PCI AD bus enable 7804 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 7805 OE_Stop_n: out std_logic; -- PCI Stop# enable 7806 OE_Devsel_n: out std_logic -- PCI Devsel# enable 7807 7808 ); 7809end pci_target; 7810 7811architecture fsm of pci_target is 7812 7813signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 7814 7815subtype targetFsmType is std_logic_vector(2 downto 0); 7816 7817constant Idle: targetFsmType := "000"; 7818constant B_Busy: targetFsmType := "001"; 7819constant Backoff: targetFsmType := "011"; 7820constant S_Data: targetFsmType := "110"; 7821constant Turn_Ar: targetFsmType := "100"; 7822 7823signal currState, nextState: targetFsmType; 7824 7825begin 7826 7827 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 7828 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 7829 case currState is 7830 when IDLE => 7831 if (PCI_Frame_n = '0' and Hit = '0') then 7832 nextState <= B_BUSY; 7833 else 7834 nextState <= IDLE; 7835 end if; 7836 7837 when B_BUSY => 7838 if (PCI_Frame_n ='1' and D_Done = '1') or 7839 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 7840 nextState <= IDLE; 7841 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7842 (Term = '0' or (Term = '1' and Ready = '1') ) then 7843 nextState <= S_Data; 7844 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 7845 (Term = '1' and Ready = '0') then 7846 nextState <= BACKOFF; 7847 else 7848 nextState <= B_BUSY; 7849 end if; 7850 7851 when S_DATA => 7852 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 7853 nextState <= BACKOFF; 7854 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 7855 nextState <= TURN_AR; 7856 else 7857 nextState <= S_DATA; 7858 end if; 7859 7860 7861 when BACKOFF => 7862 if PCI_Frame_n = '1' then 7863 nextState <= TURN_AR; 7864 else 7865 nextState <= BACKOFF; 7866 end if; 7867 7868 when TURN_AR => 7869 if (PCI_Frame_n = '0' and Hit = '0') then 7870 nextState <= B_BUSY; 7871 else 7872 nextState <= IDLE; 7873 end if; 7874 7875 when others => 7876 nextState <= IDLE; 7877 end case; 7878 end process nxtStProc; 7879 7880 7881 curStProc: process (PCI_Clk, PCI_Reset_n) begin 7882 if (PCI_Reset_n = '0') then 7883 currState <= Idle; 7884 elsif (PCI_Clk'event and PCI_Clk = '1') then 7885 currState <= nextState; 7886 end if; 7887 end process curStProc; 7888 7889 7890 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 7891 Cmd_Read, T_Abort, Term) begin 7892 7893 -- Set default output assignments 7894 OE_Trdy_n <= '0'; 7895 OE_Stop_n <= '0'; 7896 OE_Devsel_n <= '0'; 7897 OE_AD <= '0'; 7898 LPCI_Trdy_n <= '1'; 7899 LPCI_Stop_n <= '1'; 7900 LPCI_Devsel_n <= '1'; 7901 7902 case currState is 7903 when S_Data => 7904 if (Cmd_Read = '1') then 7905 OE_AD <= '1'; 7906 else 7907 OE_AD <= '0'; 7908 end if; 7909 7910 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 7911 LPCI_Trdy_n <= '0'; 7912 else 7913 LPCI_Trdy_n <= '1'; 7914 end if; 7915 7916 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 7917 LPCI_Stop_n <= '0'; 7918 else 7919 LPCI_Stop_n <= '1'; 7920 end if; 7921 7922 if (T_Abort = '0') then 7923 LPCI_Devsel_n <= '0'; 7924 else 7925 LPCI_Devsel_n <= '1'; 7926 end if; 7927 7928 OE_Trdy_n <= '1'; 7929 OE_Stop_n <= '1'; 7930 OE_Devsel_n <= '1'; 7931 7932 when Backoff => 7933 if (Cmd_Read = '1') then 7934 OE_AD <= '1'; 7935 else 7936 OE_AD <= '0'; 7937 end if; 7938 7939 LPCI_Stop_n <= '0'; 7940 7941 OE_Trdy_n <= '1'; 7942 OE_Stop_n <= '1'; 7943 OE_Devsel_n <= '1'; 7944 7945 if (T_Abort = '0') then 7946 LPCI_Devsel_n <= '0'; 7947 else 7948 LPCI_Devsel_n <= '1'; 7949 end if; 7950 7951 when Turn_Ar => 7952 7953 OE_Trdy_n <= '1'; 7954 OE_Stop_n <= '1'; 7955 OE_Devsel_n <= '1'; 7956 7957 when others => 7958 7959 OE_Trdy_n <= '0'; 7960 OE_Stop_n <= '0'; 7961 OE_Devsel_n <= '0'; 7962 OE_AD <= '0'; 7963 LPCI_Trdy_n <= '1'; 7964 LPCI_Stop_n <= '1'; 7965 LPCI_Devsel_n <= '1'; 7966 7967 end case; 7968 7969 end process outConProc; 7970 7971 PCI_Devsel_n <= LPCI_Devsel_n; 7972 PCI_Trdy_n <= LPCI_Trdy_n; 7973 PCI_Stop_n <= LPCI_Stop_n; 7974 7975end fsm; 7976library IEEE; 7977use IEEE.std_logic_1164.all; 7978 7979entity pci_target is port ( 7980 PCI_Frame_n: in std_logic; -- PCI Frame# 7981 PCI_Irdy_n: in std_logic; -- PCI Irdy# 7982 Hit: in std_logic; -- Hit on address decode 7983 D_Done: in std_logic; -- Device decode complete 7984 Term: in std_logic; -- Terminate transaction 7985 Ready: in std_logic; -- Ready to transfer data 7986 Cmd_Write: in std_logic; -- Command is Write 7987 Cmd_Read: in std_logic; -- Command is Read 7988 T_Abort: in std_logic; -- Target error - abort transaction 7989 PCI_Clk: in std_logic; -- PCI Clock 7990 PCI_Reset_n: in std_logic; -- PCI Reset# 7991 7992 PCI_Devsel_n: out std_logic; -- PCI Devsel# 7993 PCI_Trdy_n: out std_logic; -- PCI Trdy# 7994 PCI_Stop_n: out std_logic; -- PCI Stop# 7995 OE_AD: out std_logic; -- PCI AD bus enable 7996 OE_Trdy_n: out std_logic; -- PCI Trdy# enable 7997 OE_Stop_n: out std_logic; -- PCI Stop# enable 7998 OE_Devsel_n: out std_logic -- PCI Devsel# enable 7999 ); 8000end pci_target; 8001 8002architecture fsm of pci_target is 8003 8004 signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic; 8005 8006 subtype targetFsmType is std_logic_vector(2 downto 0); 8007 8008 constant Idle: targetFsmType := "000"; 8009 constant B_Busy: targetFsmType := "001"; 8010 constant Backoff: targetFsmType := "011"; 8011 constant S_Data: targetFsmType := "110"; 8012 constant Turn_Ar: targetFsmType := "100"; 8013 8014 signal currState, nextState: targetFsmType; 8015 8016begin 8017 8018 nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n, 8019 LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin 8020 case currState is 8021 when Idle => 8022 if (PCI_Frame_n = '0' and Hit = '0') then 8023 nextState <= B_Busy; 8024 else 8025 nextState <= Idle; 8026 end if; 8027 8028 when B_Busy => 8029 if (PCI_Frame_n ='1' and D_Done = '1') or 8030 (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then 8031 nextState <= Idle; 8032 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 8033 (Term = '0' or (Term = '1' and Ready = '1') ) then 8034 nextState <= S_Data; 8035 elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and 8036 (Term = '1' and Ready = '0') then 8037 nextState <= Backoff; 8038 else 8039 nextState <= B_Busy; 8040 end if; 8041 8042 when S_Data => 8043 if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and 8044 (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then 8045 nextState <= Backoff; 8046 elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then 8047 nextState <= Turn_Ar; 8048 else 8049 nextState <= S_Data; 8050 end if; 8051 8052 8053 when Backoff => 8054 if PCI_Frame_n = '1' then 8055 nextState <= Turn_Ar; 8056 else 8057 nextState <= Backoff; 8058 end if; 8059 8060 when Turn_Ar => 8061 if (PCI_Frame_n = '0' and Hit = '0') then 8062 nextState <= B_Busy; 8063 else 8064 nextState <= Idle; 8065 end if; 8066 8067 when others => 8068 null; 8069 end case; 8070 end process nxtStProc; 8071 8072 8073 curStProc: process (PCI_Clk, PCI_Reset_n) begin 8074 if (PCI_Reset_n = '0') then 8075 currState <= Idle; 8076 elsif (PCI_Clk'event and PCI_Clk = '1') then 8077 currState <= nextState; 8078 end if; 8079 end process curStProc; 8080 8081 8082 outConProc: process (currState, Ready, T_Abort, Cmd_Write, 8083 Cmd_Read, T_Abort, Term) begin 8084 case currState is 8085 when S_Data => 8086 if (Cmd_Read = '1') then 8087 OE_AD <= '1'; 8088 else 8089 OE_AD <= '0'; 8090 end if; 8091 8092 if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then 8093 LPCI_Trdy_n <= '0'; 8094 else 8095 LPCI_Trdy_n <= '1'; 8096 end if; 8097 8098 if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then 8099 LPCI_Stop_n <= '0'; 8100 else 8101 LPCI_Stop_n <= '1'; 8102 end if; 8103 8104 if (T_Abort = '0') then 8105 LPCI_Devsel_n <= '0'; 8106 else 8107 LPCI_Devsel_n <= '1'; 8108 end if; 8109 8110 OE_Trdy_n <= '1'; 8111 OE_Stop_n <= '1'; 8112 OE_Devsel_n <= '1'; 8113 8114 when Backoff => 8115 if (Cmd_Read = '1') then 8116 OE_AD <= '1'; 8117 else 8118 OE_AD <= '0'; 8119 end if; 8120 8121 LPCI_Stop_n <= '0'; 8122 8123 OE_Trdy_n <= '1'; 8124 OE_Stop_n <= '1'; 8125 OE_Devsel_n <= '1'; 8126 8127 if (T_Abort = '0') then 8128 LPCI_Devsel_n <= '0'; 8129 else 8130 LPCI_Devsel_n <= '1'; 8131 end if; 8132 8133 when Turn_Ar => 8134 8135 OE_Trdy_n <= '1'; 8136 OE_Stop_n <= '1'; 8137 OE_Devsel_n <= '1'; 8138 8139 when others => 8140 8141 OE_Trdy_n <= '0'; 8142 OE_Stop_n <= '0'; 8143 OE_Devsel_n <= '0'; 8144 OE_AD <= '0'; 8145 LPCI_Trdy_n <= '1'; 8146 LPCI_Stop_n <= '1'; 8147 LPCI_Devsel_n <= '1'; 8148 8149 end case; 8150 8151 end process outConProc; 8152 8153 PCI_Devsel_n <= LPCI_Devsel_n; 8154 PCI_Trdy_n <= LPCI_Trdy_n; 8155 PCI_Stop_n <= LPCI_Stop_n; 8156 8157end fsm; 8158library ieee; 8159use ieee.std_logic_1164.all; 8160 8161entity test is port ( 8162 a: in std_logic; 8163 z: out std_logic; 8164 en: in std_logic 8165 ); 8166end test; 8167 8168architecture simple of test is 8169 8170begin 8171 8172 z <= a when en = '1' else 'z'; 8173 8174end simple; 8175