1 /*========================== begin_copyright_notice ============================ 2 3 Copyright (C) 2017-2021 Intel Corporation 4 5 SPDX-License-Identifier: MIT 6 7 ============================= end_copyright_notice ===========================*/ 8 9 #ifndef _BINARYENCODING_H_ 10 #define _BINARYENCODING_H_ 11 12 #include <string> 13 #include <fstream> 14 15 #include "FlowGraph.h" 16 #include "Common_BinaryEncoding.h" 17 18 /////////////////////////////////////////////////////////////////////////////// 19 // Constants 20 /////////////////////////////////////////////////////////////////////////////// 21 22 typedef enum _AccessMode_ { 23 ACCESS_MODE_ALIGN1, 24 ACCESS_MODE_ALIGN16 25 } AccessMode; 26 27 typedef enum _predicate_state_ { 28 PREDICATE_STATE_NORMAL, 29 PREDICATE_STATE_INVERT 30 } PredicateState; 31 32 typedef enum _predicate_ 33 { 34 PREDICATE_OFF, 35 PREDICATE_ALIGN16_SEQUENTIAL, 36 PREDICATE_ALIGN16_REP_X, 37 PREDICATE_ALIGN16_REP_Y, 38 PREDICATE_ALIGN16_REP_Z, 39 PREDICATE_ALIGN16_REP_W, 40 PREDICATE_ALIGN16_ANY4H, 41 PREDICATE_ALIGN16_ALL4H, 42 43 PREDICATE_ALIGN1_SEQUENTIAL = 1, 44 PREDICATE_ALIGN1_ANYV, 45 PREDICATE_ALIGN1_ALLV, 46 PREDICATE_ALIGN1_ANY2H, 47 PREDICATE_ALIGN1_ALL2H, 48 PREDICATE_ALIGN1_ANY4H, 49 PREDICATE_ALIGN1_ALL4H, 50 PREDICATE_ALIGN1_ANY8H, 51 PREDICATE_ALIGN1_ALL8H, 52 PREDICATE_ALIGN1_ANY16H, 53 PREDICATE_ALIGN1_ALL16H, 54 // valid for Gen7 only 55 PREDICATE_ALIGN1_ANY32H, 56 PREDICATE_ALIGN1_ALL32H 57 } Predicate; 58 59 typedef enum _ConditionCodes_ 60 { 61 COND_CODE_NONE, 62 COND_CODE_Z, 63 COND_CODE_NZ, 64 COND_CODE_G, 65 COND_CODE_GE, 66 COND_CODE_L, 67 COND_CODE_LE, 68 COND_CODE_C, 69 COND_CODE_O, 70 COND_CODE_ANY, 71 COND_CODE_ALL 72 } ConditionCodes; 73 74 typedef enum _QtrCtrl_ 75 { 76 QTR_CTRL_1Q, 77 QTR_CTRL_2Q, 78 QTR_CTRL_3Q, 79 QTR_CTRL_4Q 80 } QtrCtrl; 81 82 typedef enum _ComprCtrl_ 83 { 84 COMPR_CTRL_NORMAL, 85 COMPR_CTRL_COMPRESSED 86 } ComprCtrl; 87 88 // GT 89 typedef enum _CmptCtrl_ 90 { 91 CMPT_CTRL_NORMAL, 92 CMPT_CTRL_COMPACTED 93 } CmptCtrl; 94 95 96 /////////////////////////////////////////////////////////////////////////////// 97 // Gen7 specific fields 98 /////////////////////////////////////////////////////////////////////////////// 99 typedef enum _ThreeSrcType_ 100 { 101 THREE_SRC_TYPE_F = 0, 102 THREE_SRC_TYPE_D = 1, 103 THREE_SRC_TYPE_UD = 2, 104 THREE_SRC_TYPE_DF = 3, 105 THREE_SRC_TYPE_HF = 4, 106 } ThreeSrcType; 107 108 typedef enum _NibCtrl_ 109 { 110 NIB_FALSE = 0, 111 NIB_TRUE = 1 112 } NibCtrl; 113 114 /////////////////////////////////////////////////////////////////////////////// 115 // End of Gen7 specific fields 116 /////////////////////////////////////////////////////////////////////////////// 117 typedef enum _threadControl_ { 118 THREAD_CTRL_NORMAL, 119 THREAD_CTRL_ATOMIC, 120 THREAD_CTRL_SWITCH 121 } ThreadCtrl; 122 123 typedef enum _CInstModifier_ 124 { 125 INST_MOD_NONE, 126 INST_MOD_SAT 127 } InstModifier; 128 129 typedef enum _DepCtrl_ 130 { 131 DEP_CTRL_NORMAL, 132 DEP_CTRL_DIS_CLEAR, 133 DEP_CTRL_DIS_CHECK, 134 DEP_CTRL_DIS_CHECK_CLEAR_DEST 135 } DepCtrl; 136 137 typedef enum _SrcMod_ 138 { 139 SRC_MOD_NONE, 140 SRC_MOD_ABSOLUTE, 141 SRC_MOD_NEGATE, 142 SRC_MOD_NEGATE_OF_ABSOLUTE 143 } SrcMod; 144 145 typedef enum _SrcType_ 146 { 147 SRC_TYPE_UD, 148 SRC_TYPE_D, 149 SRC_TYPE_UW, 150 SRC_TYPE_W, 151 SRC_TYPE_UB, 152 SRC_TYPE_B, 153 SRC_TYPE_DF, 154 SRC_TYPE_F, 155 SRC_TYPE_UQ = 8, 156 SRC_TYPE_Q = 9, 157 SRC_TYPE_HF = 10, 158 SRC_TYPE_UNDEF = 0xFFFFFFFF 159 } SrcType; 160 161 typedef enum _SrcImmType_ 162 { 163 SRC_IMM_TYPE_UD, 164 SRC_IMM_TYPE_D, 165 SRC_IMM_TYPE_UW, 166 SRC_IMM_TYPE_W, 167 SRC_IMM_TYPE_UV, 168 SRC_IMM_TYPE_VF, 169 SRC_IMM_TYPE_V, 170 SRC_IMM_TYPE_F, 171 SRC_IMM_TYPE_UQ = 8, 172 SRC_IMM_TYPE_Q = 9, 173 SRC_IMM_TYPE_DF = 10, 174 SRC_IMM_TYPE_HF = 11, 175 SRC_IMM_TYPE_UNDEF = 0xFFFFFFFF 176 } SrcImmType; 177 178 const int aSrcImmType[] = 179 { 180 // byte counts 181 4,// UD 182 4,// D 183 2,// UW 184 2,// W 185 4,// UV 186 4,// VF 187 4,// V 188 4 // F 189 }; 190 191 typedef enum _DstType_ 192 { 193 DST_TYPE_UD, 194 DST_TYPE_D, 195 DST_TYPE_UW, 196 DST_TYPE_W, 197 DST_TYPE_UB, 198 DST_TYPE_B, 199 DST_TYPE_DF, 200 DST_TYPE_F = 7, 201 DST_TYPE_UQ = 8, 202 DST_TYPE_Q = 9, 203 DST_TYPE_HF = 10, // for half float 204 DST_TYPE_UNDEF = 0xFFFFFFFF 205 } DstType; 206 207 typedef enum _IdxType_ 208 { 209 IDX_TYPE_D, 210 IDX_TYPE_W 211 } IdxType; 212 213 typedef enum _VertStride_ 214 { 215 VERT_STRIDE_0, 216 VERT_STRIDE_1, 217 VERT_STRIDE_2, 218 VERT_STRIDE_4, 219 VERT_STRIDE_8, 220 VERT_STRIDE_16, 221 VERT_STRIDE_32, 222 VERT_STRIDE_ONE_DIMEN = 15 223 } EncVertStride, *pEncVertStride; 224 225 typedef enum _Width_ 226 { 227 WIDTH_1, 228 WIDTH_2, 229 WIDTH_4, 230 WIDTH_8, 231 WIDTH_16 232 } EncWidth, *pEncWidth; 233 234 typedef enum _HorzStride_ 235 { 236 HORZ_STRIDE_0, 237 HORZ_STRIDE_1, 238 HORZ_STRIDE_2, 239 HORZ_STRIDE_4 240 } EncHorzStride, *pEncHorzStride; 241 242 const uint32_t VERT_STRIDE_VxH = 0xFFFFFFFF; 243 244 /////////////////////////////////////////////////// 245 //// 32 bit message descriptor in send instruction 246 /////////////////////////////////////////////////// 247 //typedef struct _sEncMsgDescriptor_ 248 //{ 249 // unsigned short ResponseLength : 4, 250 // MessageLength : 4, 251 // TargetUnitId : 6, 252 // Reserved : 1, 253 // EndOfThread : 1; 254 //} * psEncMsgDescriptor, sEncMsgDescriptor; 255 256 ///////////////////////////////////////////////// 257 // 6 bit extended message descriptor in send instruction 258 ///////////////////////////////////////////////// 259 typedef struct _sEncExtMsgDescriptor_ 260 { 261 uint32_t TargetUnitId : 4, 262 Reserved : 1, 263 EndOfThread : 1, 264 ExtMessageLength : 4, 265 Reserved2 : 1, 266 CPSLODCompensation : 1, 267 Reserved3 : 4, 268 ExtFunctionControl : 16; 269 } *psEncExtMsgDescriptor, sEncExtMsgDescriptor; 270 // 271 //typedef union _EncMsgDescriptor_ 272 //{ 273 // uint32_t ulData; 274 // sEncMsgDescriptor MsgDescriptor; 275 //} * pEncMsgDescriptor, EncMsgDescriptor; 276 277 typedef union _EncExtMsgDescriptor_ 278 { 279 uint32_t ulData; 280 sEncExtMsgDescriptor ExtMsgDescriptor; 281 } *pEncExtMsgDescriptor, EncExtMsgDescriptor; 282 283 284 285 286 //////////////////////////////////////////////// 287 // 128 bit ISA instruction 288 // Version 0.75 289 //////////////////////////////////////////////// 290 291 #define bitsPredicate_0 20 292 #define bitsPredicate_1 16 293 #define bitsThreadCtrl_0 15 294 #define bitsThreadCtrl_1 14 295 #define bitsQtrCtrl_0 13 296 #define bitsQtrCtrl_1 12 297 #define bitsComprCtrl_0 13 298 #define bitsComprCtrl_1 12 299 300 #define bitsCompactCtrl_0 29 301 #define bitsCompactCtrl_1 29 302 303 #define bitsAccessMode_0 8 304 #define bitsAccessMode_1 8 305 #define bitsOpCode_0 6 306 #define bitsOpCode_1 0 307 #define bitsInstModifier_0 31 308 #define bitsInstModifier_1 31 309 #define bitsExecSize_0 23 310 #define bitsExecSize_1 21 311 312 #define bitsDstAddrMode_0 63 313 #define bitsDstAddrMode_1 63 314 #define bitsDstHorzStride_0 62 315 #define bitsDstHorzStride_1 61 316 #define bitsDstRegNumOWord_0 60 317 #define bitsDstRegNumOWord_1 52 318 #define bitsDstRegNumByte_0 60 319 #define bitsDstRegNumByte_1 48 320 #define bitsDstChanEn_0 51 321 #define bitsDstChanEn_1 48 322 323 #define bitsDstArchRegFile_0 60 324 #define bitsDstArchRegFile_1 57 325 #define bitsDstArchRegNum_0 56 326 #define bitsDstArchRegNum_1 53 327 #define bitsDstArchSubRegNumOWord_0 52 328 #define bitsDstArchSubRegNumOWord_1 52 329 #define bitsDstArchSubRegNumWord_0 52 330 #define bitsDstArchSubRegNumWord_1 49 331 #define bitsDstArchSubRegNumByte_0 52 332 #define bitsDstArchSubRegNumByte_1 48 333 #define bitsDstImm16_0 63 334 #define bitsDstImm16_1 48 335 336 #define bitsSrcAddrMode_0 79 337 #define bitsSrcAddrMode_1 79 338 #define bitsSrcAddrMode_2 111 339 #define bitsSrcAddrMode_3 111 340 #define bitsSrcSrcMod_0 78 341 #define bitsSrcSrcMod_1 77 342 #define bitsSrcSrcMod_2 110 343 #define bitsSrcSrcMod_3 109 344 #define bitsSrcRegNumOWord_0 76 345 #define bitsSrcRegNumOWord_1 68 346 #define bitsSrcRegNumOWord_2 108 347 #define bitsSrcRegNumOWord_3 100 348 #define bitsSrcRegNumByte_0 76 349 #define bitsSrcRegNumByte_1 64 350 #define bitsSrcRegNumByte_2 108 351 #define bitsSrcRegNumByte_3 96 352 #define bitsSrcChanSel_0_0 65 353 #define bitsSrcChanSel_0_1 64 354 #define bitsSrcChanSel_0_2 97 355 #define bitsSrcChanSel_0_3 96 356 #define bitsSrcChanSel_1_0 67 357 #define bitsSrcChanSel_1_1 66 358 #define bitsSrcChanSel_1_2 99 359 #define bitsSrcChanSel_1_3 98 360 #define bitsSrcChanSel_2_0 81 361 #define bitsSrcChanSel_2_1 80 362 #define bitsSrcChanSel_2_2 113 363 #define bitsSrcChanSel_2_3 112 364 #define bitsSrcChanSel_3_0 83 365 #define bitsSrcChanSel_3_1 82 366 #define bitsSrcChanSel_3_2 115 367 #define bitsSrcChanSel_3_3 114 368 #define bitsSrcVertStride_0 88 369 #define bitsSrcVertStride_1 85 370 #define bitsSrcVertStride_2 120 371 #define bitsSrcVertStride_3 117 372 #define bitsSrcWidth_0 84 373 #define bitsSrcWidth_1 82 374 #define bitsSrcWidth_2 116 375 #define bitsSrcWidth_3 114 376 #define bitsSrcHorzStride_0 81 377 #define bitsSrcHorzStride_1 80 378 #define bitsSrcHorzStride_2 113 379 #define bitsSrcHorzStride_3 112 380 381 #define bitsSrcArchRegFile_0 76 382 #define bitsSrcArchRegFile_1 73 383 #define bitsSrcArchRegFile_2 108 384 #define bitsSrcArchRegFile_3 105 385 #define bitsSrcArchRegNum_0 72 386 #define bitsSrcArchRegNum_1 69 387 #define bitsSrcArchRegNum_2 104 388 #define bitsSrcArchRegNum_3 101 389 #define bitsSrcArchSubRegNumOWord_0 68 390 #define bitsSrcArchSubRegNumOWord_1 68 391 #define bitsSrcArchSubRegNumOWord_2 100 392 #define bitsSrcArchSubRegNumOWord_3 100 393 #define bitsSrcArchSubRegNumWord_0 68 394 #define bitsSrcArchSubRegNumWord_1 65 395 #define bitsSrcArchSubRegNumWord_2 100 396 #define bitsSrcArchSubRegNumWord_3 97 397 #define bitsSrcArchSubRegNumByte_0 68 398 #define bitsSrcArchSubRegNumByte_1 64 399 #define bitsSrcArchSubRegNumByte_2 100 400 #define bitsSrcArchSubRegNumByte_3 96 401 402 #define bitsSharedFunctionID_0 27 403 #define bitsSharedFunctionID_1 24 404 405 #define bitsExMsgLength_0 67 406 #define bitsExMsgLength_1 64 407 // CNL uses bit 31 to encode this flag. 408 #define bitsExDescCPSLOD_0 31 409 #define bitsExDescCPSLOD_1 31 410 // SKL+ extended message descriptor 411 #define bitsSendExDesc16 64 412 #define bitsSendExDesc19 67 413 #define bitsSendExDesc20 80 414 #define bitsSendExDesc23 83 415 #define bitsSendExDesc24 85 416 #define bitsSendExDesc27 88 417 #define bitsSendExDesc28 91 418 #define bitsSendExDesc31 94 419 420 #define bitsSendsExDescFuncCtrl_0 95 421 #define bitsSendsExDescFuncCtrl_1 80 422 423 #define bitsMsgDescriptor_0 127 424 #define bitsMsgDescriptor_1 96 425 #define bitsMsgDescriptorImm_0 126 426 #define bitsMsgDescriptorImm_1 96 427 #define bitsMsgDescriptorReg_0 120 428 #define bitsMsgDescriptorReg_1 96 429 #define bitsEndOfThread_0 127 430 #define bitsEndOfThread_1 127 431 #define bitsSendDesc_29 125 432 #define bitsSendDesc_30 126 433 434 #define bitsCpu_0 47 435 #define bitsCpu_1 47 436 #define bitsMathFunction_0 27 437 #define bitsMathFunction_1 24 438 #define bitsMathPartPrec_0 14 439 #define bitsMathPartPrec_1 14 440 441 #define bitsSrcImm64_0 127 442 #define bitsSrcImm64_1 96 443 #define bitsSrcImm64_2 95 444 #define bitsSrcImm64_3 64 445 446 // for SKL+ send instruction 447 #define bitsNoSrcDepSet_0 28 448 #define bitsNoSrcDepSet_1 28 449 450 //////////////////////////////////////////////// 451 // 3 Source ISA instruction 452 // Version 0.0 453 //////////////////////////////////////////////// 454 455 // DW0 [31:0] same as regular ISA 456 #define bits3SrcDstChanEn_0 52 457 #define bits3SrcDstChanEn_1 49 458 #define bits3SrcDstRegNumOWord_0 63 459 #define bits3SrcDstRegNumOWord_1 55 460 #define bits3SrcDstRegNumDWord_0 63 461 #define bits3SrcDstRegNumDWord_1 53 462 463 // src0 src1 src2 464 #define bits3SrcRepCtrl_0 64 465 #define bits3SrcRepCtrl_1 64 466 #define bits3SrcRepCtrl_2 85 467 #define bits3SrcRepCtrl_3 85 468 #define bits3SrcRepCtrl_4 106 469 #define bits3SrcRepCtrl_5 106 470 471 // Swizzle controls 472 #define bits3SrcSwizzle_0 72 473 #define bits3SrcSwizzle_1 65 474 #define bits3SrcSwizzle_2 93 475 #define bits3SrcSwizzle_3 86 476 #define bits3SrcSwizzle_4 114 477 #define bits3SrcSwizzle_5 107 478 479 #define bits3SrcChanSel_0_0 66 480 #define bits3SrcChanSel_0_1 65 481 #define bits3SrcChanSel_0_2 87 482 #define bits3SrcChanSel_0_3 86 483 #define bits3SrcChanSel_0_4 108 484 #define bits3SrcChanSel_0_5 107 485 486 #define bits3SrcChanSel_1_0 68 487 #define bits3SrcChanSel_1_1 67 488 #define bits3SrcChanSel_1_2 89 489 #define bits3SrcChanSel_1_3 88 490 #define bits3SrcChanSel_1_4 110 491 #define bits3SrcChanSel_1_5 109 492 493 #define bits3SrcChanSel_2_0 70 494 #define bits3SrcChanSel_2_1 69 495 #define bits3SrcChanSel_2_2 91 496 #define bits3SrcChanSel_2_3 90 497 #define bits3SrcChanSel_2_4 112 498 #define bits3SrcChanSel_2_5 111 499 500 #define bits3SrcChanSel_3_0 72 501 #define bits3SrcChanSel_3_1 71 502 #define bits3SrcChanSel_3_2 93 503 #define bits3SrcChanSel_3_3 92 504 #define bits3SrcChanSel_3_4 114 505 #define bits3SrcChanSel_3_5 113 506 507 #define bits3SrcSrcRegNumHWord_4 125 508 #define bits3SrcSrcRegNumHWord_5 118 509 510 #define bits3SrcSrcRegNumOWord_0 83 511 #define bits3SrcSrcRegNumOWord_1 75 512 #define bits3SrcSrcRegNumOWord_2 104 513 #define bits3SrcSrcRegNumOWord_3 96 514 #define bits3SrcSrcRegNumOWord_4 125 515 #define bits3SrcSrcRegNumOWord_5 117 516 517 // Get/Setbits cannot cross 32 bit boundary 518 #define bits3SrcSrcRegNumDWord_0 83 519 #define bits3SrcSrcRegNumDWord_1 73 520 #define bits3SrcSrcRegNumDWord_2 104 521 #define bits3SrcSrcRegNumDWord_3 96 522 #define bits3SrcSrcRegNumDWord_4 125 523 #define bits3SrcSrcRegNumDWord_5 115 524 #define bits3SrcSrcRegNumDWord_6 95 525 #define bits3SrcSrcRegNumDWord_7 94 526 527 #define bits3SrcSrc0RegDWord_L 73 528 #define bits3SrcSrc0RegDWord_H 83 529 #define bits3SrcSrc1RegDWord1_L 96 530 #define bits3SrcSrc1RegDWord1_H 104 531 #define bits3SrcSrc1RegDWord2_L 94 532 #define bits3SrcSrc1RegDWord2_H 95 533 #define bits3SrcSrc2RegDWord_L 115 534 #define bits3SrcSrc2RegDWord_H 125 535 536 #define bits3SrcSrc0SubRegNumW_L 84 537 #define bits3SrcSrc0SubRegNumW_H 84 538 #define bits3SrcSrc1SubRegNumW_L 105 539 #define bits3SrcSrc1SubRegNumW_H 105 540 #define bits3SrcSrc2SubRegNumW_L 126 541 #define bits3SrcSrc2SubRegNumW_H 126 542 543 // various bits for split send 544 #define bitsSendsSrc1RegFile_0 36 545 #define bitsSendsSrc1RegFile_1 36 546 #define bitsSendsSrc1AddrImmSign_0 41 547 #define bitsSendsSrc1AddrImmSign_1 41 548 #define bitsSendsSrc1AddrMode_0 42 549 #define bitsSendsSrc1AddrMode_1 42 550 #define bitsSendsSrc1AddrImm8_4_0 47 551 #define bitsSendsSrc1AddrImm8_4_1 43 552 #define bitsSendsSrc1RegNum_0 51 553 #define bitsSendsSrc1RegNum_1 44 554 #define bitsSendsSrc1AddrSubRegNum_0 51 555 #define bitsSendsSrc1AddrSubRegNum_1 48 556 557 #define bitsSendsDstRegFile_0 35 558 #define bitsSendsDstRegFile_1 35 559 #define bitsSendsDstSubRegNum_0 52 560 #define bitsSendsDstSubRegNum_1 52 561 #define bitsSendsDstAddrImm8_4_0 56 562 #define bitsSendsDstAddrImm8_4_1 52 563 #define bitsSendsDstRegNum_0 60 564 #define bitsSendsDstRegNum_1 53 565 #define bitsSendsDstAddrSubRegNum_0 60 566 #define bitsSendsDstAddrSubRegNum_1 57 567 #define bitsSendsDstAddrImmSign_0 62 568 #define bitsSendsDstAddrImmSign_1 62 569 #define bitsSendsDstAddrMode_0 63 570 #define bitsSendsDstAddrMode_1 63 571 572 #define bitsSendsSelReg32Desc_0 77 573 #define bitsSendsSelReg32Desc_1 77 574 575 #define bitsSendsSelReg32ExDesc_0 61 576 #define bitsSendsSelReg32ExDesc_1 61 577 578 #define bitsSendsSrc0AddrImmSign_0 78 579 #define bitsSendsSrc0AddrImmSign_1 78 580 #define bitsSendsSrc0AddrMode_0 79 581 #define bitsSendsSrc0AddrMode_1 79 582 #define bitsSendsSrc0AddrImm8_4_0 72 583 #define bitsSendsSrc0AddrImm8_4_1 68 584 #define bitsSendsSrc0RegNum_0 76 585 #define bitsSendsSrc0RegNum_1 69 586 #define bitsSendsSrc0AddrSubRegNum_0 76 587 #define bitsSendsSrc0AddrSubRegNum_1 73 588 #define bitsSendsSrc0Type_0 43 589 #define bitsSendsSrc0Type_1 43 590 #define bitsSendsSrc0RegFile_0 41 591 #define bitsSendsSrc0RegFile_1 42 592 593 #define bitsSendsExDescRegNum_0 82 594 #define bitsSendsExDescRegNum_1 80 595 596 597 // Reserved [84:84], [105:105] 598 599 //////////////////////////////////////////////// 600 // 64 bit ISA instruction 601 // Version 0.0 602 //////////////////////////////////////////////// 603 604 // Opcode [6:0] same as 128 bit 605 606 607 608 // SKL 3src special bits 609 #define bits3SrcSrc1Type 36 610 #define bits3SrcSrc2Type 35 611 #define bits3SrcSrc0Subregnum 84 612 #define bits3SrcSrc1Subregnum 105 613 #define bits3SrcSrc2Subregnum 126 614 #define bits3SrcDstSubregnum_1 55 615 #define bits3SrcDstSubregnum_0 53 616 617 // platform dependent bit positions for instruction fields 618 // these will be set dynamically once 619 extern unsigned long bitsFlagSubRegNum[2]; 620 extern unsigned long bitsNibCtrl[2]; 621 extern unsigned long bits3SrcFlagSubRegNum[2]; 622 extern unsigned long bits3SrcSrcType[2]; 623 extern unsigned long bits3SrcDstType[2]; 624 extern unsigned long bits3SrcNibCtrl[2]; 625 extern unsigned long bits3SrcDstRegFile[2]; 626 627 extern unsigned long bitsDepCtrl[2]; 628 extern unsigned long bitsWECtrl[2]; 629 extern unsigned long bitsDstRegFile[2]; 630 extern unsigned long bitsDstType[2]; 631 extern unsigned long bitsDstIdxRegNum[2]; 632 extern unsigned long bitsDstIdxImmOWord[2]; 633 extern unsigned long bitsDstIdxImmByte[2]; 634 extern unsigned long bitsDstIdxImmMSB[2]; 635 extern unsigned long bitsSrcRegFile[4]; 636 extern unsigned long bitsSrcType[4]; 637 extern unsigned long bitsSrcIdxRegNum[4]; 638 extern unsigned long bitsSrcIdxImmOWord[4]; 639 extern unsigned long bitsSrcIdxImmByte[4]; 640 extern unsigned long bitsSrcIdxImmMSB[4]; 641 extern unsigned long bitsJIP[2]; 642 extern unsigned long bitsUIP[2]; 643 extern unsigned long bits3SrcSrcMod[6]; 644 645 #define SET_BIT_RANGE(field, high, low) \ 646 (field)[0] = high; \ 647 (field)[1] = low; 648 649 #define SET_BIT_RANGES(field, high1, low1, high2, low2) \ 650 (field)[0] = high1; \ 651 (field)[1] = low1; \ 652 (field)[2] = high2; \ 653 (field)[3] = low2; 654 655 #define SET_BIT_RANGES2(field, high1, low1, high2, low2, high3, low3) \ 656 (field)[0] = high1; \ 657 (field)[1] = low1; \ 658 (field)[2] = high2; \ 659 (field)[3] = low2; \ 660 (field)[4] = high3; \ 661 (field)[5] = low3; 662 663 /////////////////////////////////////////////////////////////////////////////// 664 // Data Structure for Binary Instructions 665 /////////////////////////////////////////////////////////////////////////////// 666 667 /////////////////////////////////////////////////////////////////////////////// 668 // Data Structure for Binary Encoding 669 /////////////////////////////////////////////////////////////////////////////// 670 namespace vISA 671 { 672 class BinaryEncoding : public BinaryEncodingBase 673 { 674 675 public: BinaryEncoding(Mem_Manager & m,G4_Kernel & k,std::string fname)676 BinaryEncoding(Mem_Manager &m, G4_Kernel& k, std::string fname) 677 : 678 BinaryEncodingBase(m, k, fname) {} 679 ~BinaryEncoding()680 virtual ~BinaryEncoding() 681 { 682 683 }; 684 685 private: 686 687 void insertWaitDst(G4_INST*); 688 //void insertInstPointer(G4_INST*); 689 void EncodeOpCode(G4_INST*); 690 void EncodeExecSize(G4_INST*); 691 void EncodeQtrControl(G4_INST*); 692 void EncodeAccessMode(G4_INST*); 693 void EncodeFlagReg(G4_INST*); 694 void EncodeFlagRegPredicate(G4_INST*); 695 void EncodeCondModifier(G4_INST*); 696 void EncodeInstModifier(G4_INST*); 697 void EncodeMathControl(G4_INST*); 698 void EncodeInstOptionsString(G4_INST*); 699 void EncodeSendMsgDesc29_30(G4_INST*); 700 701 void EncodeSrc2RegNum(G4_INST* inst, BinInst *mybin, G4_Operand *src2); 702 void EncodeSrc1RegNum(G4_INST *inst, BinInst *mybin, G4_Operand *src1); 703 void EncodeSrc0RegNum(G4_INST* inst, BinInst *mybin, G4_Operand *src0); 704 void EncodeDstRegNum(G4_INST* inst, BinInst *mybin, G4_DstRegRegion *dst); 705 706 /* 707 * encoding operands 708 */ 709 Status EncodeOperandDst(G4_INST*); 710 Status EncodeOperandSrc0(G4_INST*); 711 Status EncodeOperandSrc1(G4_INST*); 712 Status EncodeOperandSrc2(G4_INST*); 713 Status EncodeExtMsgDescr(G4_INST*); 714 Status EncodeOperands(G4_INST*); 715 Status DoAllEncoding(G4_INST*); 716 Status EncodeSplitSendDst(G4_INST*); 717 Status EncodeSplitSendSrc0(G4_INST*); 718 Status EncodeSplitSendSrc1(G4_INST*); 719 Status EncodeSplitSendSrc2(G4_INST*); 720 721 Status EncodeIndirectCallTarget(G4_INST*); 722 723 void SetCmpSrc1Imm32(BinInst *mybin, uint32_t immediateData, G4_Operand* src); 724 725 virtual void SetCompactCtrl(BinInst *mybin, uint32_t value); 726 virtual uint32_t GetCompactCtrl(BinInst *mybin); 727 728 void SetBranchOffsets(G4_INST* inst, 729 uint32_t JIP, 730 uint32_t UIP = 0); 731 732 // return true for backfard jumps/calls, false for forward ones 733 bool EncodeConditionalBranches(G4_INST *, uint32_t); 734 735 public: 736 737 // all platform specific bit locations are initialized here InitPlatform(TARGET_PLATFORM platform)738 static void InitPlatform(TARGET_PLATFORM platform) 739 { 740 BinaryEncodingBase::InitPlatform(); 741 742 // BDW+ encoding 743 SET_BIT_RANGE(bitsFlagRegNum, 33, 33); 744 SET_BIT_RANGE(bitsFlagSubRegNum, 32, 32); 745 SET_BIT_RANGE(bitsNibCtrl, 11, 11); 746 SET_BIT_RANGE(bits3SrcFlagSubRegNum, 32, 32); 747 SET_BIT_RANGE(bits3SrcFlagRegNum, 33, 33); 748 SET_BIT_RANGE(bits3SrcSrcType, 45, 43); 749 SET_BIT_RANGE(bits3SrcDstType, 48, 46); 750 SET_BIT_RANGE(bits3SrcNibCtrl, 11, 11); 751 752 SET_BIT_RANGE(bitsDepCtrl, 10, 9); 753 SET_BIT_RANGE(bitsWECtrl, 34, 34); 754 SET_BIT_RANGE(bitsDstRegFile, 36, 35); 755 SET_BIT_RANGE(bitsDstType, 40, 37); 756 SET_BIT_RANGE(bitsDstIdxRegNum, 60, 57); 757 SET_BIT_RANGE(bitsDstIdxImmOWord, 56, 52); 758 SET_BIT_RANGE(bitsDstIdxImmByte, 56, 48); 759 SET_BIT_RANGE(bitsDstIdxImmMSB, 47, 47); 760 SET_BIT_RANGES(bitsSrcRegFile, 42, 41, 90, 89); 761 SET_BIT_RANGES(bitsSrcType, 46, 43, 94, 91); 762 SET_BIT_RANGES(bitsSrcIdxRegNum, 76, 73, 108, 105); 763 SET_BIT_RANGES(bitsSrcIdxImmOWord, 72, 68, 104, 100); 764 SET_BIT_RANGES(bitsSrcIdxImmByte, 72, 64, 104, 96); 765 SET_BIT_RANGES(bitsSrcIdxImmMSB, 95, 95, 121, 121); 766 SET_BIT_RANGE(bitsJIP, 127, 96); 767 SET_BIT_RANGE(bitsUIP, 95, 64); 768 SET_BIT_RANGES2(bits3SrcSrcMod, 38, 37, 40, 39, 42, 41); 769 } 770 771 772 Status ProduceBinaryInstructions(); 773 774 //Status commitLabels(); 775 //Status CommitRelativeAddresses(); 776 777 virtual void DoAll(); 778 779 //Status DeleteMemForBins(); 780 781 void CompactInstructions(); 782 void Compact(); 783 784 //char *GetKernelBuffer() { return buffer; }; 785 //void SetKernelBuffer(char *_buffer) { buffer = _buffer; }; 786 alloc(size_t size)787 void *alloc(size_t size) { return mem.alloc(size); }; 788 compactOneInstruction(G4_INST * inst)789 inline bool compactOneInstruction(G4_INST *inst) 790 { 791 G4_opcode op = inst->opcode(); 792 BinInst *mybin = inst->getBinInst(); 793 if (op == G4_if || op == G4_else || op == G4_endif || 794 op == G4_while || op == G4_halt || 795 op == G4_break || op == G4_cont || 796 /* GetComprCtrl(mybin) == COMPR_CTRL_COMPRESSED || */ 797 mybin->GetDontCompactFlag()) 798 { 799 // do not compact conditional branches 800 return false; 801 } 802 803 // ToDo: disable compacting nop/return until it is clear that we can compact them 804 if (op == G4_nop || op == G4_return) 805 { 806 return false; 807 } 808 809 // temporary WA, to be removed later 810 if (op == G4_call) 811 { 812 return false; 813 } 814 815 return BDWcompactOneInstruction(inst); 816 } 817 }; 818 } 819 820 #endif 821