1 /** 2 * @file 3 * @brief Contains additional external requirements defs for external includes. 4 * @note DO NOT EDIT THIS FILE, your changes will be lost. 5 * Edit ir/be/sparc/sparc_spec.pl instead. 6 * created by: ir/be/scripts/generate_regalloc_if.pl ir/be/sparc/sparc_spec.pl ir/be/sparc 7 * @date Mon Nov 19 18:12:23 2012 8 */ 9 #ifndef FIRM_BE_SPARC_GEN_SPARC_REGALLOC_IF_H 10 #define FIRM_BE_SPARC_GEN_SPARC_REGALLOC_IF_H 11 12 #include "bearch.h" 13 #include "sparc_nodes_attr.h" 14 15 /** global register indices for sparc registers */ 16 enum reg_indices { 17 REG_FPFLAGS, 18 REG_L0, 19 REG_L1, 20 REG_L2, 21 REG_L3, 22 REG_L4, 23 REG_L5, 24 REG_L6, 25 REG_L7, 26 REG_G0, 27 REG_G1, 28 REG_G2, 29 REG_G3, 30 REG_G4, 31 REG_G5, 32 REG_G6, 33 REG_G7, 34 REG_O0, 35 REG_O1, 36 REG_O2, 37 REG_O3, 38 REG_O4, 39 REG_O5, 40 REG_SP, 41 REG_O7, 42 REG_I0, 43 REG_I1, 44 REG_I2, 45 REG_I3, 46 REG_I4, 47 REG_I5, 48 REG_FRAME_POINTER, 49 REG_I7, 50 REG_F0, 51 REG_F1, 52 REG_F2, 53 REG_F3, 54 REG_F4, 55 REG_F5, 56 REG_F6, 57 REG_F7, 58 REG_F8, 59 REG_F9, 60 REG_F10, 61 REG_F11, 62 REG_F12, 63 REG_F13, 64 REG_F14, 65 REG_F15, 66 REG_F16, 67 REG_F17, 68 REG_F18, 69 REG_F19, 70 REG_F20, 71 REG_F21, 72 REG_F22, 73 REG_F23, 74 REG_F24, 75 REG_F25, 76 REG_F26, 77 REG_F27, 78 REG_F28, 79 REG_F29, 80 REG_F30, 81 REG_F31, 82 REG_Y, 83 REG_FLAGS, 84 85 N_SPARC_REGISTERS 86 }; 87 /** local register indices for sparc registers */ 88 enum { 89 REG_FPFLAGS_CLASS_FPFLAGS = 0, 90 REG_GP_L0 = 0, 91 REG_GP_L1 = 1, 92 REG_GP_L2 = 2, 93 REG_GP_L3 = 3, 94 REG_GP_L4 = 4, 95 REG_GP_L5 = 5, 96 REG_GP_L6 = 6, 97 REG_GP_L7 = 7, 98 REG_GP_G0 = 8, 99 REG_GP_G1 = 9, 100 REG_GP_G2 = 10, 101 REG_GP_G3 = 11, 102 REG_GP_G4 = 12, 103 REG_GP_G5 = 13, 104 REG_GP_G6 = 14, 105 REG_GP_G7 = 15, 106 REG_GP_O0 = 16, 107 REG_GP_O1 = 17, 108 REG_GP_O2 = 18, 109 REG_GP_O3 = 19, 110 REG_GP_O4 = 20, 111 REG_GP_O5 = 21, 112 REG_GP_SP = 22, 113 REG_GP_O7 = 23, 114 REG_GP_I0 = 24, 115 REG_GP_I1 = 25, 116 REG_GP_I2 = 26, 117 REG_GP_I3 = 27, 118 REG_GP_I4 = 28, 119 REG_GP_I5 = 29, 120 REG_GP_FRAME_POINTER = 30, 121 REG_GP_I7 = 31, 122 REG_FP_F0 = 0, 123 REG_FP_F1 = 1, 124 REG_FP_F2 = 2, 125 REG_FP_F3 = 3, 126 REG_FP_F4 = 4, 127 REG_FP_F5 = 5, 128 REG_FP_F6 = 6, 129 REG_FP_F7 = 7, 130 REG_FP_F8 = 8, 131 REG_FP_F9 = 9, 132 REG_FP_F10 = 10, 133 REG_FP_F11 = 11, 134 REG_FP_F12 = 12, 135 REG_FP_F13 = 13, 136 REG_FP_F14 = 14, 137 REG_FP_F15 = 15, 138 REG_FP_F16 = 16, 139 REG_FP_F17 = 17, 140 REG_FP_F18 = 18, 141 REG_FP_F19 = 19, 142 REG_FP_F20 = 20, 143 REG_FP_F21 = 21, 144 REG_FP_F22 = 22, 145 REG_FP_F23 = 23, 146 REG_FP_F24 = 24, 147 REG_FP_F25 = 25, 148 REG_FP_F26 = 26, 149 REG_FP_F27 = 27, 150 REG_FP_F28 = 28, 151 REG_FP_F29 = 29, 152 REG_FP_F30 = 30, 153 REG_FP_F31 = 31, 154 REG_MUL_DIV_HIGH_RES_Y = 0, 155 REG_FLAGS_CLASS_FLAGS = 0, 156 157 }; 158 159 /** number of registers in sparc register classes. */ 160 enum { 161 N_sparc_fpflags_class_REGS = 1, 162 N_sparc_gp_REGS = 32, 163 N_sparc_fp_REGS = 32, 164 N_sparc_mul_div_high_res_REGS = 1, 165 N_sparc_flags_class_REGS = 1, 166 167 }; 168 enum reg_classes { 169 CLASS_sparc_fpflags_class = 0, 170 CLASS_sparc_gp = 1, 171 CLASS_sparc_fp = 2, 172 CLASS_sparc_mul_div_high_res = 3, 173 CLASS_sparc_flags_class = 4, 174 N_SPARC_CLASSES = 5 175 }; 176 177 178 179 extern const arch_register_t sparc_registers[N_SPARC_REGISTERS]; 180 181 extern arch_register_class_t sparc_reg_classes[N_SPARC_CLASSES]; 182 183 void sparc_register_init(void); 184 185 #endif 186