1 //===---------------------------- Context.h ---------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// 10 /// This file defines a class for holding ownership of various simulated 11 /// hardware units. A Context also provides a utility routine for constructing 12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire 13 /// stages. 14 /// 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_MCA_CONTEXT_H 18 #define LLVM_MCA_CONTEXT_H 19 20 #include "llvm/MC/MCRegisterInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/MCA/HardwareUnits/HardwareUnit.h" 23 #include "llvm/MCA/Pipeline.h" 24 #include "llvm/MCA/SourceMgr.h" 25 #include <memory> 26 27 namespace llvm { 28 namespace mca { 29 30 /// This is a convenience struct to hold the parameters necessary for creating 31 /// the pre-built "default" out-of-order pipeline. 32 struct PipelineOptions { 33 PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS, 34 unsigned LQS, unsigned SQS, bool NoAlias, 35 bool ShouldEnableBottleneckAnalysis = false) MicroOpQueueSizePipelineOptions36 : MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr), 37 DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS), 38 StoreQueueSize(SQS), AssumeNoAlias(NoAlias), 39 EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {} 40 unsigned MicroOpQueueSize; 41 unsigned DecodersThroughput; // Instructions per cycle. 42 unsigned DispatchWidth; 43 unsigned RegisterFileSize; 44 unsigned LoadQueueSize; 45 unsigned StoreQueueSize; 46 bool AssumeNoAlias; 47 bool EnableBottleneckAnalysis; 48 }; 49 50 class Context { 51 SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware; 52 const MCRegisterInfo &MRI; 53 const MCSubtargetInfo &STI; 54 55 public: Context(const MCRegisterInfo & R,const MCSubtargetInfo & S)56 Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {} 57 Context(const Context &C) = delete; 58 Context &operator=(const Context &C) = delete; 59 getMCRegisterInfo()60 const MCRegisterInfo &getMCRegisterInfo() const { return MRI; } getMCSubtargetInfo()61 const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; } 62 addHardwareUnit(std::unique_ptr<HardwareUnit> H)63 void addHardwareUnit(std::unique_ptr<HardwareUnit> H) { 64 Hardware.push_back(std::move(H)); 65 } 66 67 /// Construct a basic pipeline for simulating an out-of-order pipeline. 68 /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages. 69 std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts, 70 SourceMgr &SrcMgr); 71 }; 72 73 } // namespace mca 74 } // namespace llvm 75 #endif // LLVM_MCA_CONTEXT_H 76