1 //===- HexagonFrameLowering.cpp - Define frame lowering -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "HexagonFrameLowering.h"
11 #include "HexagonBlockRanges.h"
12 #include "HexagonInstrInfo.h"
13 #include "HexagonMachineFunctionInfo.h"
14 #include "HexagonRegisterInfo.h"
15 #include "HexagonSubtarget.h"
16 #include "HexagonTargetMachine.h"
17 #include "MCTargetDesc/HexagonBaseInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/ADT/PostOrderIterator.h"
23 #include "llvm/ADT/SetVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/CodeGen/LivePhysRegs.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineMemOperand.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineOperand.h"
37 #include "llvm/CodeGen/MachinePostDominators.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/RegisterScavenging.h"
41 #include "llvm/CodeGen/TargetRegisterInfo.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCDwarf.h"
46 #include "llvm/MC/MCRegisterInfo.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "llvm/Target/TargetOptions.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstdint>
60 #include <iterator>
61 #include <limits>
62 #include <map>
63 #include <utility>
64 #include <vector>
65
66 #define DEBUG_TYPE "hexagon-pei"
67
68 // Hexagon stack frame layout as defined by the ABI:
69 //
70 // Incoming arguments
71 // passed via stack
72 // |
73 // |
74 // SP during function's FP during function's |
75 // +-- runtime (top of stack) runtime (bottom) --+ |
76 // | | |
77 // --++---------------------+------------------+-----------------++-+-------
78 // | parameter area for | variable-size | fixed-size |LR| arg
79 // | called functions | local objects | local objects |FP|
80 // --+----------------------+------------------+-----------------+--+-------
81 // <- size known -> <- size unknown -> <- size known ->
82 //
83 // Low address High address
84 //
85 // <--- stack growth
86 //
87 //
88 // - In any circumstances, the outgoing function arguments are always accessi-
89 // ble using the SP, and the incoming arguments are accessible using the FP.
90 // - If the local objects are not aligned, they can always be accessed using
91 // the FP.
92 // - If there are no variable-sized objects, the local objects can always be
93 // accessed using the SP, regardless whether they are aligned or not. (The
94 // alignment padding will be at the bottom of the stack (highest address),
95 // and so the offset with respect to the SP will be known at the compile-
96 // -time.)
97 //
98 // The only complication occurs if there are both, local aligned objects, and
99 // dynamically allocated (variable-sized) objects. The alignment pad will be
100 // placed between the FP and the local objects, thus preventing the use of the
101 // FP to access the local objects. At the same time, the variable-sized objects
102 // will be between the SP and the local objects, thus introducing an unknown
103 // distance from the SP to the locals.
104 //
105 // To avoid this problem, a new register is created that holds the aligned
106 // address of the bottom of the stack, referred in the sources as AP (aligned
107 // pointer). The AP will be equal to "FP-p", where "p" is the smallest pad
108 // that aligns AP to the required boundary (a maximum of the alignments of
109 // all stack objects, fixed- and variable-sized). All local objects[1] will
110 // then use AP as the base pointer.
111 // [1] The exception is with "fixed" stack objects. "Fixed" stack objects get
112 // their name from being allocated at fixed locations on the stack, relative
113 // to the FP. In the presence of dynamic allocation and local alignment, such
114 // objects can only be accessed through the FP.
115 //
116 // Illustration of the AP:
117 // FP --+
118 // |
119 // ---------------+---------------------+-----+-----------------------++-+--
120 // Rest of the | Local stack objects | Pad | Fixed stack objects |LR|
121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
122 // ---------------+---------------------+-----+-----------------+-----+--+--
123 // |<-- Multiple of the -->|
124 // stack alignment +-- AP
125 //
126 // The AP is set up at the beginning of the function. Since it is not a dedi-
127 // cated (reserved) register, it needs to be kept live throughout the function
128 // to be available as the base register for local object accesses.
129 // Normally, an address of a stack objects is obtained by a pseudo-instruction
130 // PS_fi. To access local objects with the AP register present, a different
131 // pseudo-instruction needs to be used: PS_fia. The PS_fia takes one extra
132 // argument compared to PS_fi: the first input register is the AP register.
133 // This keeps the register live between its definition and its uses.
134
135 // The AP register is originally set up using pseudo-instruction PS_aligna:
136 // AP = PS_aligna A
137 // where
138 // A - required stack alignment
139 // The alignment value must be the maximum of all alignments required by
140 // any stack object.
141
142 // The dynamic allocation uses a pseudo-instruction PS_alloca:
143 // Rd = PS_alloca Rs, A
144 // where
145 // Rd - address of the allocated space
146 // Rs - minimum size (the actual allocated can be larger to accommodate
147 // alignment)
148 // A - required alignment
149
150 using namespace llvm;
151
152 static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
153 cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
154
155 static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots",
156 cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
157 cl::ZeroOrMore);
158
159 static cl::opt<int> SpillFuncThreshold("spill-func-threshold",
160 cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"),
161 cl::init(6), cl::ZeroOrMore);
162
163 static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os",
164 cl::Hidden, cl::desc("Specify Os spill func threshold"),
165 cl::init(1), cl::ZeroOrMore);
166
167 static cl::opt<bool> EnableStackOVFSanitizer("enable-stackovf-sanitizer",
168 cl::Hidden, cl::desc("Enable runtime checks for stack overflow."),
169 cl::init(false), cl::ZeroOrMore);
170
171 static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame",
172 cl::init(true), cl::Hidden, cl::ZeroOrMore,
173 cl::desc("Enable stack frame shrink wrapping"));
174
175 static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit",
176 cl::init(std::numeric_limits<unsigned>::max()), cl::Hidden, cl::ZeroOrMore,
177 cl::desc("Max count of stack frame shrink-wraps"));
178
179 static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long",
180 cl::Hidden, cl::desc("Enable long calls for save-restore stubs."),
181 cl::init(false), cl::ZeroOrMore);
182
183 static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true),
184 cl::Hidden, cl::desc("Refrain from using FP whenever possible"));
185
186 static cl::opt<bool> OptimizeSpillSlots("hexagon-opt-spill", cl::Hidden,
187 cl::init(true), cl::desc("Optimize spill slots"));
188
189 #ifndef NDEBUG
190 static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
191 cl::init(std::numeric_limits<unsigned>::max()));
192 static unsigned SpillOptCount = 0;
193 #endif
194
195 namespace llvm {
196
197 void initializeHexagonCallFrameInformationPass(PassRegistry&);
198 FunctionPass *createHexagonCallFrameInformation();
199
200 } // end namespace llvm
201
202 namespace {
203
204 class HexagonCallFrameInformation : public MachineFunctionPass {
205 public:
206 static char ID;
207
HexagonCallFrameInformation()208 HexagonCallFrameInformation() : MachineFunctionPass(ID) {
209 PassRegistry &PR = *PassRegistry::getPassRegistry();
210 initializeHexagonCallFrameInformationPass(PR);
211 }
212
213 bool runOnMachineFunction(MachineFunction &MF) override;
214
getRequiredProperties() const215 MachineFunctionProperties getRequiredProperties() const override {
216 return MachineFunctionProperties().set(
217 MachineFunctionProperties::Property::NoVRegs);
218 }
219 };
220
221 char HexagonCallFrameInformation::ID = 0;
222
223 } // end anonymous namespace
224
runOnMachineFunction(MachineFunction & MF)225 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
226 auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
227 bool NeedCFI = MF.needsFrameMoves();
228
229 if (!NeedCFI)
230 return false;
231 HFI.insertCFIInstructions(MF);
232 return true;
233 }
234
235 INITIALIZE_PASS(HexagonCallFrameInformation, "hexagon-cfi",
236 "Hexagon call frame information", false, false)
237
createHexagonCallFrameInformation()238 FunctionPass *llvm::createHexagonCallFrameInformation() {
239 return new HexagonCallFrameInformation();
240 }
241
242 /// Map a register pair Reg to the subregister that has the greater "number",
243 /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
getMax32BitSubRegister(unsigned Reg,const TargetRegisterInfo & TRI,bool hireg=true)244 static unsigned getMax32BitSubRegister(unsigned Reg,
245 const TargetRegisterInfo &TRI,
246 bool hireg = true) {
247 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
248 return Reg;
249
250 unsigned RegNo = 0;
251 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
252 if (hireg) {
253 if (*SubRegs > RegNo)
254 RegNo = *SubRegs;
255 } else {
256 if (!RegNo || *SubRegs < RegNo)
257 RegNo = *SubRegs;
258 }
259 }
260 return RegNo;
261 }
262
263 /// Returns the callee saved register with the largest id in the vector.
getMaxCalleeSavedReg(ArrayRef<CalleeSavedInfo> CSI,const TargetRegisterInfo & TRI)264 static unsigned getMaxCalleeSavedReg(ArrayRef<CalleeSavedInfo> CSI,
265 const TargetRegisterInfo &TRI) {
266 static_assert(Hexagon::R1 > 0,
267 "Assume physical registers are encoded as positive integers");
268 if (CSI.empty())
269 return 0;
270
271 unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
272 for (unsigned I = 1, E = CSI.size(); I < E; ++I) {
273 unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
274 if (Reg > Max)
275 Max = Reg;
276 }
277 return Max;
278 }
279
280 /// Checks if the basic block contains any instruction that needs a stack
281 /// frame to be already in place.
needsStackFrame(const MachineBasicBlock & MBB,const BitVector & CSR,const HexagonRegisterInfo & HRI)282 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
283 const HexagonRegisterInfo &HRI) {
284 for (auto &I : MBB) {
285 const MachineInstr *MI = &I;
286 if (MI->isCall())
287 return true;
288 unsigned Opc = MI->getOpcode();
289 switch (Opc) {
290 case Hexagon::PS_alloca:
291 case Hexagon::PS_aligna:
292 return true;
293 default:
294 break;
295 }
296 // Check individual operands.
297 for (const MachineOperand &MO : MI->operands()) {
298 // While the presence of a frame index does not prove that a stack
299 // frame will be required, all frame indexes should be within alloc-
300 // frame/deallocframe. Otherwise, the code that translates a frame
301 // index into an offset would have to be aware of the placement of
302 // the frame creation/destruction instructions.
303 if (MO.isFI())
304 return true;
305 if (MO.isReg()) {
306 Register R = MO.getReg();
307 // Virtual registers will need scavenging, which then may require
308 // a stack slot.
309 if (Register::isVirtualRegister(R))
310 return true;
311 for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
312 if (CSR[*S])
313 return true;
314 continue;
315 }
316 if (MO.isRegMask()) {
317 // A regmask would normally have all callee-saved registers marked
318 // as preserved, so this check would not be needed, but in case of
319 // ever having other regmasks (for other calling conventions),
320 // make sure they would be processed correctly.
321 const uint32_t *BM = MO.getRegMask();
322 for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
323 unsigned R = x;
324 // If this regmask does not preserve a CSR, a frame will be needed.
325 if (!(BM[R/32] & (1u << (R%32))))
326 return true;
327 }
328 }
329 }
330 }
331 return false;
332 }
333
334 /// Returns true if MBB has a machine instructions that indicates a tail call
335 /// in the block.
hasTailCall(const MachineBasicBlock & MBB)336 static bool hasTailCall(const MachineBasicBlock &MBB) {
337 MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
338 if (I == MBB.end())
339 return false;
340 unsigned RetOpc = I->getOpcode();
341 return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
342 }
343
344 /// Returns true if MBB contains an instruction that returns.
hasReturn(const MachineBasicBlock & MBB)345 static bool hasReturn(const MachineBasicBlock &MBB) {
346 for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
347 if (I->isReturn())
348 return true;
349 return false;
350 }
351
352 /// Returns the "return" instruction from this block, or nullptr if there
353 /// isn't any.
getReturn(MachineBasicBlock & MBB)354 static MachineInstr *getReturn(MachineBasicBlock &MBB) {
355 for (auto &I : MBB)
356 if (I.isReturn())
357 return &I;
358 return nullptr;
359 }
360
isRestoreCall(unsigned Opc)361 static bool isRestoreCall(unsigned Opc) {
362 switch (Opc) {
363 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
364 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
365 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
366 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
367 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
368 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
369 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
370 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
371 return true;
372 }
373 return false;
374 }
375
isOptNone(const MachineFunction & MF)376 static inline bool isOptNone(const MachineFunction &MF) {
377 return MF.getFunction().hasOptNone() ||
378 MF.getTarget().getOptLevel() == CodeGenOpt::None;
379 }
380
isOptSize(const MachineFunction & MF)381 static inline bool isOptSize(const MachineFunction &MF) {
382 const Function &F = MF.getFunction();
383 return F.hasOptSize() && !F.hasMinSize();
384 }
385
isMinSize(const MachineFunction & MF)386 static inline bool isMinSize(const MachineFunction &MF) {
387 return MF.getFunction().hasMinSize();
388 }
389
390 /// Implements shrink-wrapping of the stack frame. By default, stack frame
391 /// is created in the function entry block, and is cleaned up in every block
392 /// that returns. This function finds alternate blocks: one for the frame
393 /// setup (prolog) and one for the cleanup (epilog).
findShrunkPrologEpilog(MachineFunction & MF,MachineBasicBlock * & PrologB,MachineBasicBlock * & EpilogB) const394 void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
395 MachineBasicBlock *&PrologB, MachineBasicBlock *&EpilogB) const {
396 static unsigned ShrinkCounter = 0;
397
398 if (MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl() &&
399 MF.getFunction().isVarArg())
400 return;
401 if (ShrinkLimit.getPosition()) {
402 if (ShrinkCounter >= ShrinkLimit)
403 return;
404 ShrinkCounter++;
405 }
406
407 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
408
409 MachineDominatorTree MDT;
410 MDT.runOnMachineFunction(MF);
411 MachinePostDominatorTree MPT;
412 MPT.runOnMachineFunction(MF);
413
414 using UnsignedMap = DenseMap<unsigned, unsigned>;
415 using RPOTType = ReversePostOrderTraversal<const MachineFunction *>;
416
417 UnsignedMap RPO;
418 RPOTType RPOT(&MF);
419 unsigned RPON = 0;
420 for (RPOTType::rpo_iterator I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
421 RPO[(*I)->getNumber()] = RPON++;
422
423 // Don't process functions that have loops, at least for now. Placement
424 // of prolog and epilog must take loop structure into account. For simpli-
425 // city don't do it right now.
426 for (auto &I : MF) {
427 unsigned BN = RPO[I.getNumber()];
428 for (auto SI = I.succ_begin(), SE = I.succ_end(); SI != SE; ++SI) {
429 // If found a back-edge, return.
430 if (RPO[(*SI)->getNumber()] <= BN)
431 return;
432 }
433 }
434
435 // Collect the set of blocks that need a stack frame to execute. Scan
436 // each block for uses/defs of callee-saved registers, calls, etc.
437 SmallVector<MachineBasicBlock*,16> SFBlocks;
438 BitVector CSR(Hexagon::NUM_TARGET_REGS);
439 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
440 for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
441 CSR[*S] = true;
442
443 for (auto &I : MF)
444 if (needsStackFrame(I, CSR, HRI))
445 SFBlocks.push_back(&I);
446
447 LLVM_DEBUG({
448 dbgs() << "Blocks needing SF: {";
449 for (auto &B : SFBlocks)
450 dbgs() << " " << printMBBReference(*B);
451 dbgs() << " }\n";
452 });
453 // No frame needed?
454 if (SFBlocks.empty())
455 return;
456
457 // Pick a common dominator and a common post-dominator.
458 MachineBasicBlock *DomB = SFBlocks[0];
459 for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
460 DomB = MDT.findNearestCommonDominator(DomB, SFBlocks[i]);
461 if (!DomB)
462 break;
463 }
464 MachineBasicBlock *PDomB = SFBlocks[0];
465 for (unsigned i = 1, n = SFBlocks.size(); i < n; ++i) {
466 PDomB = MPT.findNearestCommonDominator(PDomB, SFBlocks[i]);
467 if (!PDomB)
468 break;
469 }
470 LLVM_DEBUG({
471 dbgs() << "Computed dom block: ";
472 if (DomB)
473 dbgs() << printMBBReference(*DomB);
474 else
475 dbgs() << "<null>";
476 dbgs() << ", computed pdom block: ";
477 if (PDomB)
478 dbgs() << printMBBReference(*PDomB);
479 else
480 dbgs() << "<null>";
481 dbgs() << "\n";
482 });
483 if (!DomB || !PDomB)
484 return;
485
486 // Make sure that DomB dominates PDomB and PDomB post-dominates DomB.
487 if (!MDT.dominates(DomB, PDomB)) {
488 LLVM_DEBUG(dbgs() << "Dom block does not dominate pdom block\n");
489 return;
490 }
491 if (!MPT.dominates(PDomB, DomB)) {
492 LLVM_DEBUG(dbgs() << "PDom block does not post-dominate dom block\n");
493 return;
494 }
495
496 // Finally, everything seems right.
497 PrologB = DomB;
498 EpilogB = PDomB;
499 }
500
501 /// Perform most of the PEI work here:
502 /// - saving/restoring of the callee-saved registers,
503 /// - stack frame creation and destruction.
504 /// Normally, this work is distributed among various functions, but doing it
505 /// in one place allows shrink-wrapping of the stack frame.
emitPrologue(MachineFunction & MF,MachineBasicBlock & MBB) const506 void HexagonFrameLowering::emitPrologue(MachineFunction &MF,
507 MachineBasicBlock &MBB) const {
508 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
509
510 MachineFrameInfo &MFI = MF.getFrameInfo();
511 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
512
513 MachineBasicBlock *PrologB = &MF.front(), *EpilogB = nullptr;
514 if (EnableShrinkWrapping)
515 findShrunkPrologEpilog(MF, PrologB, EpilogB);
516
517 bool PrologueStubs = false;
518 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
519 insertPrologueInBlock(*PrologB, PrologueStubs);
520 updateEntryPaths(MF, *PrologB);
521
522 if (EpilogB) {
523 insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
524 insertEpilogueInBlock(*EpilogB);
525 } else {
526 for (auto &B : MF)
527 if (B.isReturnBlock())
528 insertCSRRestoresInBlock(B, CSI, HRI);
529
530 for (auto &B : MF)
531 if (B.isReturnBlock())
532 insertEpilogueInBlock(B);
533
534 for (auto &B : MF) {
535 if (B.empty())
536 continue;
537 MachineInstr *RetI = getReturn(B);
538 if (!RetI || isRestoreCall(RetI->getOpcode()))
539 continue;
540 for (auto &R : CSI)
541 RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
542 }
543 }
544
545 if (EpilogB) {
546 // If there is an epilog block, it may not have a return instruction.
547 // In such case, we need to add the callee-saved registers as live-ins
548 // in all blocks on all paths from the epilog to any return block.
549 unsigned MaxBN = MF.getNumBlockIDs();
550 BitVector DoneT(MaxBN+1), DoneF(MaxBN+1), Path(MaxBN+1);
551 updateExitPaths(*EpilogB, *EpilogB, DoneT, DoneF, Path);
552 }
553 }
554
555 /// Returns true if the target can safely skip saving callee-saved registers
556 /// for noreturn nounwind functions.
enableCalleeSaveSkip(const MachineFunction & MF) const557 bool HexagonFrameLowering::enableCalleeSaveSkip(
558 const MachineFunction &MF) const {
559 const auto &F = MF.getFunction();
560 assert(F.hasFnAttribute(Attribute::NoReturn) &&
561 F.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
562 !F.getFunction().hasFnAttribute(Attribute::UWTable));
563 (void)F;
564
565 // No need to save callee saved registers if the function does not return.
566 return MF.getSubtarget<HexagonSubtarget>().noreturnStackElim();
567 }
568
569 // Helper function used to determine when to eliminate the stack frame for
570 // functions marked as noreturn and when the noreturn-stack-elim options are
571 // specified. When both these conditions are true, then a FP may not be needed
572 // if the function makes a call. It is very similar to enableCalleeSaveSkip,
573 // but it used to check if the allocframe can be eliminated as well.
enableAllocFrameElim(const MachineFunction & MF)574 static bool enableAllocFrameElim(const MachineFunction &MF) {
575 const auto &F = MF.getFunction();
576 const auto &MFI = MF.getFrameInfo();
577 const auto &HST = MF.getSubtarget<HexagonSubtarget>();
578 assert(!MFI.hasVarSizedObjects() &&
579 !HST.getRegisterInfo()->needsStackRealignment(MF));
580 return F.hasFnAttribute(Attribute::NoReturn) &&
581 F.hasFnAttribute(Attribute::NoUnwind) &&
582 !F.hasFnAttribute(Attribute::UWTable) && HST.noreturnStackElim() &&
583 MFI.getStackSize() == 0;
584 }
585
insertPrologueInBlock(MachineBasicBlock & MBB,bool PrologueStubs) const586 void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
587 bool PrologueStubs) const {
588 MachineFunction &MF = *MBB.getParent();
589 MachineFrameInfo &MFI = MF.getFrameInfo();
590 auto &HST = MF.getSubtarget<HexagonSubtarget>();
591 auto &HII = *HST.getInstrInfo();
592 auto &HRI = *HST.getRegisterInfo();
593
594 Align MaxAlign = std::max(MFI.getMaxAlign(), getStackAlign());
595
596 // Calculate the total stack frame size.
597 // Get the number of bytes to allocate from the FrameInfo.
598 unsigned FrameSize = MFI.getStackSize();
599 // Round up the max call frame size to the max alignment on the stack.
600 unsigned MaxCFA = alignTo(MFI.getMaxCallFrameSize(), MaxAlign);
601 MFI.setMaxCallFrameSize(MaxCFA);
602
603 FrameSize = MaxCFA + alignTo(FrameSize, MaxAlign);
604 MFI.setStackSize(FrameSize);
605
606 bool AlignStack = (MaxAlign > getStackAlign());
607
608 // Get the number of bytes to allocate from the FrameInfo.
609 unsigned NumBytes = MFI.getStackSize();
610 unsigned SP = HRI.getStackRegister();
611 unsigned MaxCF = MFI.getMaxCallFrameSize();
612 MachineBasicBlock::iterator InsertPt = MBB.begin();
613
614 SmallVector<MachineInstr *, 4> AdjustRegs;
615 for (auto &MBB : MF)
616 for (auto &MI : MBB)
617 if (MI.getOpcode() == Hexagon::PS_alloca)
618 AdjustRegs.push_back(&MI);
619
620 for (auto MI : AdjustRegs) {
621 assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
622 expandAlloca(MI, HII, SP, MaxCF);
623 MI->eraseFromParent();
624 }
625
626 DebugLoc dl = MBB.findDebugLoc(InsertPt);
627
628 if (MF.getFunction().isVarArg() &&
629 MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
630 // Calculate the size of register saved area.
631 int NumVarArgRegs = 6 - FirstVarArgSavedReg;
632 int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0)
633 ? NumVarArgRegs * 4
634 : NumVarArgRegs * 4 + 4;
635 if (RegisterSavedAreaSizePlusPadding > 0) {
636 // Decrement the stack pointer by size of register saved area plus
637 // padding if any.
638 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
639 .addReg(SP)
640 .addImm(-RegisterSavedAreaSizePlusPadding)
641 .setMIFlag(MachineInstr::FrameSetup);
642
643 int NumBytes = 0;
644 // Copy all the named arguments below register saved area.
645 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
646 for (int i = HMFI.getFirstNamedArgFrameIndex(),
647 e = HMFI.getLastNamedArgFrameIndex(); i >= e; --i) {
648 uint64_t ObjSize = MFI.getObjectSize(i);
649 Align ObjAlign = MFI.getObjectAlign(i);
650
651 // Determine the kind of load/store that should be used.
652 unsigned LDOpc, STOpc;
653 uint64_t OpcodeChecker = ObjAlign.value();
654
655 // Handle cases where alignment of an object is > its size.
656 if (ObjAlign > ObjSize) {
657 if (ObjSize <= 1)
658 OpcodeChecker = 1;
659 else if (ObjSize <= 2)
660 OpcodeChecker = 2;
661 else if (ObjSize <= 4)
662 OpcodeChecker = 4;
663 else if (ObjSize > 4)
664 OpcodeChecker = 8;
665 }
666
667 switch (OpcodeChecker) {
668 case 1:
669 LDOpc = Hexagon::L2_loadrb_io;
670 STOpc = Hexagon::S2_storerb_io;
671 break;
672 case 2:
673 LDOpc = Hexagon::L2_loadrh_io;
674 STOpc = Hexagon::S2_storerh_io;
675 break;
676 case 4:
677 LDOpc = Hexagon::L2_loadri_io;
678 STOpc = Hexagon::S2_storeri_io;
679 break;
680 case 8:
681 default:
682 LDOpc = Hexagon::L2_loadrd_io;
683 STOpc = Hexagon::S2_storerd_io;
684 break;
685 }
686
687 unsigned RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3
688 : Hexagon::R6;
689 int LoadStoreCount = ObjSize / OpcodeChecker;
690
691 if (ObjSize % OpcodeChecker)
692 ++LoadStoreCount;
693
694 // Get the start location of the load. NumBytes is basically the
695 // offset from the stack pointer of previous function, which would be
696 // the caller in this case, as this function has variable argument
697 // list.
698 if (NumBytes != 0)
699 NumBytes = alignTo(NumBytes, ObjAlign);
700
701 int Count = 0;
702 while (Count < LoadStoreCount) {
703 // Load the value of the named argument on stack.
704 BuildMI(MBB, InsertPt, dl, HII.get(LDOpc), RegUsed)
705 .addReg(SP)
706 .addImm(RegisterSavedAreaSizePlusPadding +
707 ObjAlign.value() * Count + NumBytes)
708 .setMIFlag(MachineInstr::FrameSetup);
709
710 // Store it below the register saved area plus padding.
711 BuildMI(MBB, InsertPt, dl, HII.get(STOpc))
712 .addReg(SP)
713 .addImm(ObjAlign.value() * Count + NumBytes)
714 .addReg(RegUsed)
715 .setMIFlag(MachineInstr::FrameSetup);
716
717 Count++;
718 }
719 NumBytes += MFI.getObjectSize(i);
720 }
721
722 // Make NumBytes 8 byte aligned
723 NumBytes = alignTo(NumBytes, 8);
724
725 // If the number of registers having variable arguments is odd,
726 // leave 4 bytes of padding to get to the location where first
727 // variable argument which was passed through register was copied.
728 NumBytes = (NumVarArgRegs % 2 == 0) ? NumBytes : NumBytes + 4;
729
730 for (int j = FirstVarArgSavedReg, i = 0; j < 6; ++j, ++i) {
731 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io))
732 .addReg(SP)
733 .addImm(NumBytes + 4 * i)
734 .addReg(Hexagon::R0 + j)
735 .setMIFlag(MachineInstr::FrameSetup);
736 }
737 }
738 }
739
740 if (hasFP(MF)) {
741 insertAllocframe(MBB, InsertPt, NumBytes);
742 if (AlignStack) {
743 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
744 .addReg(SP)
745 .addImm(-int64_t(MaxAlign.value()));
746 }
747 // If the stack-checking is enabled, and we spilled the callee-saved
748 // registers inline (i.e. did not use a spill function), then call
749 // the stack checker directly.
750 if (EnableStackOVFSanitizer && !PrologueStubs)
751 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
752 .addExternalSymbol("__runtime_stack_check");
753 } else if (NumBytes > 0) {
754 assert(alignTo(NumBytes, 8) == NumBytes);
755 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
756 .addReg(SP)
757 .addImm(-int(NumBytes));
758 }
759 }
760
insertEpilogueInBlock(MachineBasicBlock & MBB) const761 void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const {
762 MachineFunction &MF = *MBB.getParent();
763 auto &HST = MF.getSubtarget<HexagonSubtarget>();
764 auto &HII = *HST.getInstrInfo();
765 auto &HRI = *HST.getRegisterInfo();
766 unsigned SP = HRI.getStackRegister();
767
768 MachineBasicBlock::iterator InsertPt = MBB.getFirstTerminator();
769 DebugLoc dl = MBB.findDebugLoc(InsertPt);
770
771 if (!hasFP(MF)) {
772 MachineFrameInfo &MFI = MF.getFrameInfo();
773 unsigned NumBytes = MFI.getStackSize();
774 if (MF.getFunction().isVarArg() &&
775 MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl()) {
776 // On Hexagon Linux, deallocate the stack for the register saved area.
777 int NumVarArgRegs = 6 - FirstVarArgSavedReg;
778 int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
779 (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
780 NumBytes += RegisterSavedAreaSizePlusPadding;
781 }
782 if (NumBytes) {
783 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
784 .addReg(SP)
785 .addImm(NumBytes);
786 }
787 return;
788 }
789
790 MachineInstr *RetI = getReturn(MBB);
791 unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
792
793 // Handle EH_RETURN.
794 if (RetOpc == Hexagon::EH_RETURN_JMPR) {
795 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
796 .addDef(Hexagon::D15)
797 .addReg(Hexagon::R30);
798 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
799 .addReg(SP)
800 .addReg(Hexagon::R28);
801 return;
802 }
803
804 // Check for RESTORE_DEALLOC_RET* tail call. Don't emit an extra dealloc-
805 // frame instruction if we encounter it.
806 if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
807 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
808 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
809 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
810 MachineBasicBlock::iterator It = RetI;
811 ++It;
812 // Delete all instructions after the RESTORE (except labels).
813 while (It != MBB.end()) {
814 if (!It->isLabel())
815 It = MBB.erase(It);
816 else
817 ++It;
818 }
819 return;
820 }
821
822 // It is possible that the restoring code is a call to a library function.
823 // All of the restore* functions include "deallocframe", so we need to make
824 // sure that we don't add an extra one.
825 bool NeedsDeallocframe = true;
826 if (!MBB.empty() && InsertPt != MBB.begin()) {
827 MachineBasicBlock::iterator PrevIt = std::prev(InsertPt);
828 unsigned COpc = PrevIt->getOpcode();
829 if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
830 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
831 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
832 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
833 COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
834 NeedsDeallocframe = false;
835 }
836
837 if (!MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl() ||
838 !MF.getFunction().isVarArg()) {
839 if (!NeedsDeallocframe)
840 return;
841 // If the returning instruction is PS_jmpret, replace it with
842 // dealloc_return, otherwise just add deallocframe. The function
843 // could be returning via a tail call.
844 if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
845 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
846 .addDef(Hexagon::D15)
847 .addReg(Hexagon::R30);
848 return;
849 }
850 unsigned NewOpc = Hexagon::L4_return;
851 MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
852 .addDef(Hexagon::D15)
853 .addReg(Hexagon::R30);
854 // Transfer the function live-out registers.
855 NewI->copyImplicitOps(MF, *RetI);
856 MBB.erase(RetI);
857 } else {
858 // L2_deallocframe instruction after it.
859 // Calculate the size of register saved area.
860 int NumVarArgRegs = 6 - FirstVarArgSavedReg;
861 int RegisterSavedAreaSizePlusPadding = (NumVarArgRegs % 2 == 0) ?
862 (NumVarArgRegs * 4) : (NumVarArgRegs * 4 + 4);
863
864 MachineBasicBlock::iterator Term = MBB.getFirstTerminator();
865 MachineBasicBlock::iterator I = (Term == MBB.begin()) ? MBB.end()
866 : std::prev(Term);
867 if (I == MBB.end() ||
868 (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT &&
869 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC &&
870 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 &&
871 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC))
872 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
873 .addDef(Hexagon::D15)
874 .addReg(Hexagon::R30);
875 if (RegisterSavedAreaSizePlusPadding != 0)
876 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
877 .addReg(SP)
878 .addImm(RegisterSavedAreaSizePlusPadding);
879 }
880 }
881
insertAllocframe(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertPt,unsigned NumBytes) const882 void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB,
883 MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const {
884 MachineFunction &MF = *MBB.getParent();
885 auto &HST = MF.getSubtarget<HexagonSubtarget>();
886 auto &HII = *HST.getInstrInfo();
887 auto &HRI = *HST.getRegisterInfo();
888
889 // Check for overflow.
890 // Hexagon_TODO: Ugh! hardcoding. Is there an API that can be used?
891 const unsigned int ALLOCFRAME_MAX = 16384;
892
893 // Create a dummy memory operand to avoid allocframe from being treated as
894 // a volatile memory reference.
895 auto *MMO = MF.getMachineMemOperand(MachinePointerInfo::getStack(MF, 0),
896 MachineMemOperand::MOStore, 4, Align(4));
897
898 DebugLoc dl = MBB.findDebugLoc(InsertPt);
899 unsigned SP = HRI.getStackRegister();
900
901 if (NumBytes >= ALLOCFRAME_MAX) {
902 // Emit allocframe(#0).
903 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
904 .addDef(SP)
905 .addReg(SP)
906 .addImm(0)
907 .addMemOperand(MMO);
908
909 // Subtract the size from the stack pointer.
910 unsigned SP = HRI.getStackRegister();
911 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
912 .addReg(SP)
913 .addImm(-int(NumBytes));
914 } else {
915 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
916 .addDef(SP)
917 .addReg(SP)
918 .addImm(NumBytes)
919 .addMemOperand(MMO);
920 }
921 }
922
updateEntryPaths(MachineFunction & MF,MachineBasicBlock & SaveB) const923 void HexagonFrameLowering::updateEntryPaths(MachineFunction &MF,
924 MachineBasicBlock &SaveB) const {
925 SetVector<unsigned> Worklist;
926
927 MachineBasicBlock &EntryB = MF.front();
928 Worklist.insert(EntryB.getNumber());
929
930 unsigned SaveN = SaveB.getNumber();
931 auto &CSI = MF.getFrameInfo().getCalleeSavedInfo();
932
933 for (unsigned i = 0; i < Worklist.size(); ++i) {
934 unsigned BN = Worklist[i];
935 MachineBasicBlock &MBB = *MF.getBlockNumbered(BN);
936 for (auto &R : CSI)
937 if (!MBB.isLiveIn(R.getReg()))
938 MBB.addLiveIn(R.getReg());
939 if (BN != SaveN)
940 for (auto &SB : MBB.successors())
941 Worklist.insert(SB->getNumber());
942 }
943 }
944
updateExitPaths(MachineBasicBlock & MBB,MachineBasicBlock & RestoreB,BitVector & DoneT,BitVector & DoneF,BitVector & Path) const945 bool HexagonFrameLowering::updateExitPaths(MachineBasicBlock &MBB,
946 MachineBasicBlock &RestoreB, BitVector &DoneT, BitVector &DoneF,
947 BitVector &Path) const {
948 assert(MBB.getNumber() >= 0);
949 unsigned BN = MBB.getNumber();
950 if (Path[BN] || DoneF[BN])
951 return false;
952 if (DoneT[BN])
953 return true;
954
955 auto &CSI = MBB.getParent()->getFrameInfo().getCalleeSavedInfo();
956
957 Path[BN] = true;
958 bool ReachedExit = false;
959 for (auto &SB : MBB.successors())
960 ReachedExit |= updateExitPaths(*SB, RestoreB, DoneT, DoneF, Path);
961
962 if (!MBB.empty() && MBB.back().isReturn()) {
963 // Add implicit uses of all callee-saved registers to the reached
964 // return instructions. This is to prevent the anti-dependency breaker
965 // from renaming these registers.
966 MachineInstr &RetI = MBB.back();
967 if (!isRestoreCall(RetI.getOpcode()))
968 for (auto &R : CSI)
969 RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
970 ReachedExit = true;
971 }
972
973 // We don't want to add unnecessary live-ins to the restore block: since
974 // the callee-saved registers are being defined in it, the entry of the
975 // restore block cannot be on the path from the definitions to any exit.
976 if (ReachedExit && &MBB != &RestoreB) {
977 for (auto &R : CSI)
978 if (!MBB.isLiveIn(R.getReg()))
979 MBB.addLiveIn(R.getReg());
980 DoneT[BN] = true;
981 }
982 if (!ReachedExit)
983 DoneF[BN] = true;
984
985 Path[BN] = false;
986 return ReachedExit;
987 }
988
989 static Optional<MachineBasicBlock::iterator>
findCFILocation(MachineBasicBlock & B)990 findCFILocation(MachineBasicBlock &B) {
991 // The CFI instructions need to be inserted right after allocframe.
992 // An exception to this is a situation where allocframe is bundled
993 // with a call: then the CFI instructions need to be inserted before
994 // the packet with the allocframe+call (in case the call throws an
995 // exception).
996 auto End = B.instr_end();
997
998 for (MachineInstr &I : B) {
999 MachineBasicBlock::iterator It = I.getIterator();
1000 if (!I.isBundle()) {
1001 if (I.getOpcode() == Hexagon::S2_allocframe)
1002 return std::next(It);
1003 continue;
1004 }
1005 // I is a bundle.
1006 bool HasCall = false, HasAllocFrame = false;
1007 auto T = It.getInstrIterator();
1008 while (++T != End && T->isBundled()) {
1009 if (T->getOpcode() == Hexagon::S2_allocframe)
1010 HasAllocFrame = true;
1011 else if (T->isCall())
1012 HasCall = true;
1013 }
1014 if (HasAllocFrame)
1015 return HasCall ? It : std::next(It);
1016 }
1017 return None;
1018 }
1019
insertCFIInstructions(MachineFunction & MF) const1020 void HexagonFrameLowering::insertCFIInstructions(MachineFunction &MF) const {
1021 for (auto &B : MF) {
1022 auto At = findCFILocation(B);
1023 if (At.hasValue())
1024 insertCFIInstructionsAt(B, At.getValue());
1025 }
1026 }
1027
insertCFIInstructionsAt(MachineBasicBlock & MBB,MachineBasicBlock::iterator At) const1028 void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
1029 MachineBasicBlock::iterator At) const {
1030 MachineFunction &MF = *MBB.getParent();
1031 MachineFrameInfo &MFI = MF.getFrameInfo();
1032 MachineModuleInfo &MMI = MF.getMMI();
1033 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1034 auto &HII = *HST.getInstrInfo();
1035 auto &HRI = *HST.getRegisterInfo();
1036
1037 // If CFI instructions have debug information attached, something goes
1038 // wrong with the final assembly generation: the prolog_end is placed
1039 // in a wrong location.
1040 DebugLoc DL;
1041 const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
1042
1043 MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
1044 bool HasFP = hasFP(MF);
1045
1046 if (HasFP) {
1047 unsigned DwFPReg = HRI.getDwarfRegNum(HRI.getFrameRegister(), true);
1048 unsigned DwRAReg = HRI.getDwarfRegNum(HRI.getRARegister(), true);
1049
1050 // Define CFA via an offset from the value of FP.
1051 //
1052 // -8 -4 0 (SP)
1053 // --+----+----+---------------------
1054 // | FP | LR | increasing addresses -->
1055 // --+----+----+---------------------
1056 // | +-- Old SP (before allocframe)
1057 // +-- New FP (after allocframe)
1058 //
1059 // MCCFIInstruction::cfiDefCfa adds the offset from the register.
1060 // MCCFIInstruction::createOffset takes the offset without sign change.
1061 auto DefCfa = MCCFIInstruction::cfiDefCfa(FrameLabel, DwFPReg, 8);
1062 BuildMI(MBB, At, DL, CFID)
1063 .addCFIIndex(MF.addFrameInst(DefCfa));
1064 // R31 (return addr) = CFA - 4
1065 auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
1066 BuildMI(MBB, At, DL, CFID)
1067 .addCFIIndex(MF.addFrameInst(OffR31));
1068 // R30 (frame ptr) = CFA - 8
1069 auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
1070 BuildMI(MBB, At, DL, CFID)
1071 .addCFIIndex(MF.addFrameInst(OffR30));
1072 }
1073
1074 static unsigned int RegsToMove[] = {
1075 Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
1076 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
1077 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
1078 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
1079 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
1080 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
1081 Hexagon::NoRegister
1082 };
1083
1084 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1085
1086 for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
1087 unsigned Reg = RegsToMove[i];
1088 auto IfR = [Reg] (const CalleeSavedInfo &C) -> bool {
1089 return C.getReg() == Reg;
1090 };
1091 auto F = find_if(CSI, IfR);
1092 if (F == CSI.end())
1093 continue;
1094
1095 int64_t Offset;
1096 if (HasFP) {
1097 // If the function has a frame pointer (i.e. has an allocframe),
1098 // then the CFA has been defined in terms of FP. Any offsets in
1099 // the following CFI instructions have to be defined relative
1100 // to FP, which points to the bottom of the stack frame.
1101 // The function getFrameIndexReference can still choose to use SP
1102 // for the offset calculation, so we cannot simply call it here.
1103 // Instead, get the offset (relative to the FP) directly.
1104 Offset = MFI.getObjectOffset(F->getFrameIdx());
1105 } else {
1106 Register FrameReg;
1107 Offset = getFrameIndexReference(MF, F->getFrameIdx(), FrameReg);
1108 }
1109 // Subtract 8 to make room for R30 and R31, which are added above.
1110 Offset -= 8;
1111
1112 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
1113 unsigned DwarfReg = HRI.getDwarfRegNum(Reg, true);
1114 auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
1115 Offset);
1116 BuildMI(MBB, At, DL, CFID)
1117 .addCFIIndex(MF.addFrameInst(OffReg));
1118 } else {
1119 // Split the double regs into subregs, and generate appropriate
1120 // cfi_offsets.
1121 // The only reason, we are split double regs is, llvm-mc does not
1122 // understand paired registers for cfi_offset.
1123 // Eg .cfi_offset r1:0, -64
1124
1125 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
1126 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
1127 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
1128 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
1129 auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
1130 Offset+4);
1131 BuildMI(MBB, At, DL, CFID)
1132 .addCFIIndex(MF.addFrameInst(OffHi));
1133 auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
1134 Offset);
1135 BuildMI(MBB, At, DL, CFID)
1136 .addCFIIndex(MF.addFrameInst(OffLo));
1137 }
1138 }
1139 }
1140
hasFP(const MachineFunction & MF) const1141 bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
1142 if (MF.getFunction().hasFnAttribute(Attribute::Naked))
1143 return false;
1144
1145 auto &MFI = MF.getFrameInfo();
1146 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1147 bool HasExtraAlign = HRI.needsStackRealignment(MF);
1148 bool HasAlloca = MFI.hasVarSizedObjects();
1149
1150 // Insert ALLOCFRAME if we need to or at -O0 for the debugger. Think
1151 // that this shouldn't be required, but doing so now because gcc does and
1152 // gdb can't break at the start of the function without it. Will remove if
1153 // this turns out to be a gdb bug.
1154 //
1155 if (MF.getTarget().getOptLevel() == CodeGenOpt::None)
1156 return true;
1157
1158 // By default we want to use SP (since it's always there). FP requires
1159 // some setup (i.e. ALLOCFRAME).
1160 // Both, alloca and stack alignment modify the stack pointer by an
1161 // undetermined value, so we need to save it at the entry to the function
1162 // (i.e. use allocframe).
1163 if (HasAlloca || HasExtraAlign)
1164 return true;
1165
1166 if (MFI.getStackSize() > 0) {
1167 // If FP-elimination is disabled, we have to use FP at this point.
1168 const TargetMachine &TM = MF.getTarget();
1169 if (TM.Options.DisableFramePointerElim(MF) || !EliminateFramePointer)
1170 return true;
1171 if (EnableStackOVFSanitizer)
1172 return true;
1173 }
1174
1175 const auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1176 if ((MFI.hasCalls() && !enableAllocFrameElim(MF)) || HMFI.hasClobberLR())
1177 return true;
1178
1179 return false;
1180 }
1181
1182 enum SpillKind {
1183 SK_ToMem,
1184 SK_FromMem,
1185 SK_FromMemTailcall
1186 };
1187
getSpillFunctionFor(unsigned MaxReg,SpillKind SpillType,bool Stkchk=false)1188 static const char *getSpillFunctionFor(unsigned MaxReg, SpillKind SpillType,
1189 bool Stkchk = false) {
1190 const char * V4SpillToMemoryFunctions[] = {
1191 "__save_r16_through_r17",
1192 "__save_r16_through_r19",
1193 "__save_r16_through_r21",
1194 "__save_r16_through_r23",
1195 "__save_r16_through_r25",
1196 "__save_r16_through_r27" };
1197
1198 const char * V4SpillToMemoryStkchkFunctions[] = {
1199 "__save_r16_through_r17_stkchk",
1200 "__save_r16_through_r19_stkchk",
1201 "__save_r16_through_r21_stkchk",
1202 "__save_r16_through_r23_stkchk",
1203 "__save_r16_through_r25_stkchk",
1204 "__save_r16_through_r27_stkchk" };
1205
1206 const char * V4SpillFromMemoryFunctions[] = {
1207 "__restore_r16_through_r17_and_deallocframe",
1208 "__restore_r16_through_r19_and_deallocframe",
1209 "__restore_r16_through_r21_and_deallocframe",
1210 "__restore_r16_through_r23_and_deallocframe",
1211 "__restore_r16_through_r25_and_deallocframe",
1212 "__restore_r16_through_r27_and_deallocframe" };
1213
1214 const char * V4SpillFromMemoryTailcallFunctions[] = {
1215 "__restore_r16_through_r17_and_deallocframe_before_tailcall",
1216 "__restore_r16_through_r19_and_deallocframe_before_tailcall",
1217 "__restore_r16_through_r21_and_deallocframe_before_tailcall",
1218 "__restore_r16_through_r23_and_deallocframe_before_tailcall",
1219 "__restore_r16_through_r25_and_deallocframe_before_tailcall",
1220 "__restore_r16_through_r27_and_deallocframe_before_tailcall"
1221 };
1222
1223 const char **SpillFunc = nullptr;
1224
1225 switch(SpillType) {
1226 case SK_ToMem:
1227 SpillFunc = Stkchk ? V4SpillToMemoryStkchkFunctions
1228 : V4SpillToMemoryFunctions;
1229 break;
1230 case SK_FromMem:
1231 SpillFunc = V4SpillFromMemoryFunctions;
1232 break;
1233 case SK_FromMemTailcall:
1234 SpillFunc = V4SpillFromMemoryTailcallFunctions;
1235 break;
1236 }
1237 assert(SpillFunc && "Unknown spill kind");
1238
1239 // Spill all callee-saved registers up to the highest register used.
1240 switch (MaxReg) {
1241 case Hexagon::R17:
1242 return SpillFunc[0];
1243 case Hexagon::R19:
1244 return SpillFunc[1];
1245 case Hexagon::R21:
1246 return SpillFunc[2];
1247 case Hexagon::R23:
1248 return SpillFunc[3];
1249 case Hexagon::R25:
1250 return SpillFunc[4];
1251 case Hexagon::R27:
1252 return SpillFunc[5];
1253 default:
1254 llvm_unreachable("Unhandled maximum callee save register");
1255 }
1256 return nullptr;
1257 }
1258
getFrameIndexReference(const MachineFunction & MF,int FI,Register & FrameReg) const1259 int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF,
1260 int FI,
1261 Register &FrameReg) const {
1262 auto &MFI = MF.getFrameInfo();
1263 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1264
1265 int Offset = MFI.getObjectOffset(FI);
1266 bool HasAlloca = MFI.hasVarSizedObjects();
1267 bool HasExtraAlign = HRI.needsStackRealignment(MF);
1268 bool NoOpt = MF.getTarget().getOptLevel() == CodeGenOpt::None;
1269
1270 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1271 unsigned FrameSize = MFI.getStackSize();
1272 Register SP = HRI.getStackRegister();
1273 Register FP = HRI.getFrameRegister();
1274 Register AP = HMFI.getStackAlignBasePhysReg();
1275 // It may happen that AP will be absent even HasAlloca && HasExtraAlign
1276 // is true. HasExtraAlign may be set because of vector spills, without
1277 // aligned locals or aligned outgoing function arguments. Since vector
1278 // spills will ultimately be "unaligned", it is safe to use FP as the
1279 // base register.
1280 // In fact, in such a scenario the stack is actually not required to be
1281 // aligned, although it may end up being aligned anyway, since this
1282 // particular case is not easily detectable. The alignment will be
1283 // unnecessary, but not incorrect.
1284 // Unfortunately there is no quick way to verify that the above is
1285 // indeed the case (and that it's not a result of an error), so just
1286 // assume that missing AP will be replaced by FP.
1287 // (A better fix would be to rematerialize AP from FP and always align
1288 // vector spills.)
1289 if (AP == 0)
1290 AP = FP;
1291
1292 bool UseFP = false, UseAP = false; // Default: use SP (except at -O0).
1293 // Use FP at -O0, except when there are objects with extra alignment.
1294 // That additional alignment requirement may cause a pad to be inserted,
1295 // which will make it impossible to use FP to access objects located
1296 // past the pad.
1297 if (NoOpt && !HasExtraAlign)
1298 UseFP = true;
1299 if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
1300 // Fixed and preallocated objects will be located before any padding
1301 // so FP must be used to access them.
1302 UseFP |= (HasAlloca || HasExtraAlign);
1303 } else {
1304 if (HasAlloca) {
1305 if (HasExtraAlign)
1306 UseAP = true;
1307 else
1308 UseFP = true;
1309 }
1310 }
1311
1312 // If FP was picked, then there had better be FP.
1313 bool HasFP = hasFP(MF);
1314 assert((HasFP || !UseFP) && "This function must have frame pointer");
1315
1316 // Having FP implies allocframe. Allocframe will store extra 8 bytes:
1317 // FP/LR. If the base register is used to access an object across these
1318 // 8 bytes, then the offset will need to be adjusted by 8.
1319 //
1320 // After allocframe:
1321 // HexagonISelLowering adds 8 to ---+
1322 // the offsets of all stack-based |
1323 // arguments (*) |
1324 // |
1325 // getObjectOffset < 0 0 8 getObjectOffset >= 8
1326 // ------------------------+-----+------------------------> increasing
1327 // <local objects> |FP/LR| <input arguments> addresses
1328 // -----------------+------+-----+------------------------>
1329 // | |
1330 // SP/AP point --+ +-- FP points here (**)
1331 // somewhere on
1332 // this side of FP/LR
1333 //
1334 // (*) See LowerFormalArguments. The FP/LR is assumed to be present.
1335 // (**) *FP == old-FP. FP+0..7 are the bytes of FP/LR.
1336
1337 // The lowering assumes that FP/LR is present, and so the offsets of
1338 // the formal arguments start at 8. If FP/LR is not there we need to
1339 // reduce the offset by 8.
1340 if (Offset > 0 && !HasFP)
1341 Offset -= 8;
1342
1343 if (UseFP)
1344 FrameReg = FP;
1345 else if (UseAP)
1346 FrameReg = AP;
1347 else
1348 FrameReg = SP;
1349
1350 // Calculate the actual offset in the instruction. If there is no FP
1351 // (in other words, no allocframe), then SP will not be adjusted (i.e.
1352 // there will be no SP -= FrameSize), so the frame size should not be
1353 // added to the calculated offset.
1354 int RealOffset = Offset;
1355 if (!UseFP && !UseAP)
1356 RealOffset = FrameSize+Offset;
1357 return RealOffset;
1358 }
1359
insertCSRSpillsInBlock(MachineBasicBlock & MBB,const CSIVect & CSI,const HexagonRegisterInfo & HRI,bool & PrologueStubs) const1360 bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
1361 const CSIVect &CSI, const HexagonRegisterInfo &HRI,
1362 bool &PrologueStubs) const {
1363 if (CSI.empty())
1364 return true;
1365
1366 MachineBasicBlock::iterator MI = MBB.begin();
1367 PrologueStubs = false;
1368 MachineFunction &MF = *MBB.getParent();
1369 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1370 auto &HII = *HST.getInstrInfo();
1371
1372 if (useSpillFunction(MF, CSI)) {
1373 PrologueStubs = true;
1374 unsigned MaxReg = getMaxCalleeSavedReg(CSI, HRI);
1375 bool StkOvrFlowEnabled = EnableStackOVFSanitizer;
1376 const char *SpillFun = getSpillFunctionFor(MaxReg, SK_ToMem,
1377 StkOvrFlowEnabled);
1378 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1379 bool IsPIC = HTM.isPositionIndependent();
1380 bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1381
1382 // Call spill function.
1383 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1384 unsigned SpillOpc;
1385 if (StkOvrFlowEnabled) {
1386 if (LongCalls)
1387 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1388 : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1389 else
1390 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1391 : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1392 } else {
1393 if (LongCalls)
1394 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1395 : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1396 else
1397 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1398 : Hexagon::SAVE_REGISTERS_CALL_V4;
1399 }
1400
1401 MachineInstr *SaveRegsCall =
1402 BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1403 .addExternalSymbol(SpillFun);
1404
1405 // Add callee-saved registers as use.
1406 addCalleeSaveRegistersAsImpOperand(SaveRegsCall, CSI, false, true);
1407 // Add live in registers.
1408 for (unsigned I = 0; I < CSI.size(); ++I)
1409 MBB.addLiveIn(CSI[I].getReg());
1410 return true;
1411 }
1412
1413 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1414 unsigned Reg = CSI[i].getReg();
1415 // Add live in registers. We treat eh_return callee saved register r0 - r3
1416 // specially. They are not really callee saved registers as they are not
1417 // supposed to be killed.
1418 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg);
1419 int FI = CSI[i].getFrameIdx();
1420 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1421 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1422 if (IsKill)
1423 MBB.addLiveIn(Reg);
1424 }
1425 return true;
1426 }
1427
insertCSRRestoresInBlock(MachineBasicBlock & MBB,const CSIVect & CSI,const HexagonRegisterInfo & HRI) const1428 bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
1429 const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
1430 if (CSI.empty())
1431 return false;
1432
1433 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
1434 MachineFunction &MF = *MBB.getParent();
1435 auto &HST = MF.getSubtarget<HexagonSubtarget>();
1436 auto &HII = *HST.getInstrInfo();
1437
1438 if (useRestoreFunction(MF, CSI)) {
1439 bool HasTC = hasTailCall(MBB) || !hasReturn(MBB);
1440 unsigned MaxR = getMaxCalleeSavedReg(CSI, HRI);
1441 SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem;
1442 const char *RestoreFn = getSpillFunctionFor(MaxR, Kind);
1443 auto &HTM = static_cast<const HexagonTargetMachine&>(MF.getTarget());
1444 bool IsPIC = HTM.isPositionIndependent();
1445 bool LongCalls = HST.useLongCalls() || EnableSaveRestoreLong;
1446
1447 // Call spill function.
1448 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1449 : MBB.findDebugLoc(MBB.end());
1450 MachineInstr *DeallocCall = nullptr;
1451
1452 if (HasTC) {
1453 unsigned RetOpc;
1454 if (LongCalls)
1455 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1456 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1457 else
1458 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1459 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1460 DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1461 .addExternalSymbol(RestoreFn);
1462 } else {
1463 // The block has a return.
1464 MachineBasicBlock::iterator It = MBB.getFirstTerminator();
1465 assert(It->isReturn() && std::next(It) == MBB.end());
1466 unsigned RetOpc;
1467 if (LongCalls)
1468 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1469 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1470 else
1471 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1472 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1473 DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1474 .addExternalSymbol(RestoreFn);
1475 // Transfer the function live-out registers.
1476 DeallocCall->copyImplicitOps(MF, *It);
1477 }
1478 addCalleeSaveRegistersAsImpOperand(DeallocCall, CSI, true, false);
1479 return true;
1480 }
1481
1482 for (unsigned i = 0; i < CSI.size(); ++i) {
1483 unsigned Reg = CSI[i].getReg();
1484 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1485 int FI = CSI[i].getFrameIdx();
1486 HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1487 }
1488
1489 return true;
1490 }
1491
eliminateCallFramePseudoInstr(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const1492 MachineBasicBlock::iterator HexagonFrameLowering::eliminateCallFramePseudoInstr(
1493 MachineFunction &MF, MachineBasicBlock &MBB,
1494 MachineBasicBlock::iterator I) const {
1495 MachineInstr &MI = *I;
1496 unsigned Opc = MI.getOpcode();
1497 (void)Opc; // Silence compiler warning.
1498 assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1499 "Cannot handle this call frame pseudo instruction");
1500 return MBB.erase(I);
1501 }
1502
processFunctionBeforeFrameFinalized(MachineFunction & MF,RegScavenger * RS) const1503 void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
1504 MachineFunction &MF, RegScavenger *RS) const {
1505 // If this function has uses aligned stack and also has variable sized stack
1506 // objects, then we need to map all spill slots to fixed positions, so that
1507 // they can be accessed through FP. Otherwise they would have to be accessed
1508 // via AP, which may not be available at the particular place in the program.
1509 MachineFrameInfo &MFI = MF.getFrameInfo();
1510 bool HasAlloca = MFI.hasVarSizedObjects();
1511 bool NeedsAlign = (MFI.getMaxAlign() > getStackAlign());
1512
1513 if (!HasAlloca || !NeedsAlign)
1514 return;
1515
1516 SmallSet<int, 4> DealignSlots;
1517 unsigned LFS = MFI.getLocalFrameSize();
1518 for (int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
1519 if (!MFI.isSpillSlotObjectIndex(i) || MFI.isDeadObjectIndex(i))
1520 continue;
1521 unsigned S = MFI.getObjectSize(i);
1522 // Reduce the alignment to at most 8. This will require unaligned vector
1523 // stores if they happen here.
1524 Align A = std::max(MFI.getObjectAlign(i), Align(8));
1525 MFI.setObjectAlignment(i, Align(8));
1526 LFS = alignTo(LFS+S, A);
1527 MFI.mapLocalFrameObject(i, -static_cast<int64_t>(LFS));
1528 DealignSlots.insert(i);
1529 }
1530
1531 MFI.setLocalFrameSize(LFS);
1532 Align A = MFI.getLocalFrameMaxAlign();
1533 assert(A <= 8 && "Unexpected local frame alignment");
1534 if (A == 1)
1535 MFI.setLocalFrameMaxAlign(Align(8));
1536 MFI.setUseLocalStackAllocationBlock(true);
1537
1538 // Go over all MachineMemOperands in the code, and change the ones that
1539 // refer to the dealigned stack slots to reflect the new alignment.
1540 if (!DealignSlots.empty()) {
1541 for (MachineBasicBlock &BB : MF) {
1542 for (MachineInstr &MI : BB) {
1543 bool KeepOld = true;
1544 ArrayRef<MachineMemOperand*> memops = MI.memoperands();
1545 SmallVector<MachineMemOperand*,1> new_memops;
1546 for (MachineMemOperand *MMO : memops) {
1547 auto *PV = MMO->getPseudoValue();
1548 if (auto *FS = dyn_cast_or_null<FixedStackPseudoSourceValue>(PV)) {
1549 int FI = FS->getFrameIndex();
1550 if (DealignSlots.count(FI)) {
1551 auto *NewMMO = MF.getMachineMemOperand(
1552 MMO->getPointerInfo(), MMO->getFlags(), MMO->getSize(),
1553 MFI.getObjectAlign(FI), MMO->getAAInfo(), MMO->getRanges(),
1554 MMO->getSyncScopeID(), MMO->getOrdering(),
1555 MMO->getFailureOrdering());
1556 new_memops.push_back(NewMMO);
1557 KeepOld = false;
1558 continue;
1559 }
1560 }
1561 new_memops.push_back(MMO);
1562 }
1563 if (!KeepOld)
1564 MI.setMemRefs(MF, new_memops);
1565 }
1566 }
1567 }
1568
1569 // Set the physical aligned-stack base address register.
1570 unsigned AP = 0;
1571 if (const MachineInstr *AI = getAlignaInstr(MF))
1572 AP = AI->getOperand(0).getReg();
1573 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1574 HMFI.setStackAlignBasePhysReg(AP);
1575 }
1576
1577 /// Returns true if there are no caller-saved registers available in class RC.
needToReserveScavengingSpillSlots(MachineFunction & MF,const HexagonRegisterInfo & HRI,const TargetRegisterClass * RC)1578 static bool needToReserveScavengingSpillSlots(MachineFunction &MF,
1579 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1580 MachineRegisterInfo &MRI = MF.getRegInfo();
1581
1582 auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
1583 for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
1584 if (MRI.isPhysRegUsed(*AI))
1585 return true;
1586 return false;
1587 };
1588
1589 // Check for an unused caller-saved register. Callee-saved registers
1590 // have become pristine by now.
1591 for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1592 if (!IsUsed(*P))
1593 return false;
1594
1595 // All caller-saved registers are used.
1596 return true;
1597 }
1598
1599 #ifndef NDEBUG
dump_registers(BitVector & Regs,const TargetRegisterInfo & TRI)1600 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
1601 dbgs() << '{';
1602 for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
1603 unsigned R = x;
1604 dbgs() << ' ' << printReg(R, &TRI);
1605 }
1606 dbgs() << " }";
1607 }
1608 #endif
1609
assignCalleeSavedSpillSlots(MachineFunction & MF,const TargetRegisterInfo * TRI,std::vector<CalleeSavedInfo> & CSI) const1610 bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
1611 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
1612 LLVM_DEBUG(dbgs() << __func__ << " on " << MF.getName() << '\n');
1613 MachineFrameInfo &MFI = MF.getFrameInfo();
1614 BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1615
1616 // Generate a set of unique, callee-saved registers (SRegs), where each
1617 // register in the set is maximal in terms of sub-/super-register relation,
1618 // i.e. for each R in SRegs, no proper super-register of R is also in SRegs.
1619
1620 // (1) For each callee-saved register, add that register and all of its
1621 // sub-registers to SRegs.
1622 LLVM_DEBUG(dbgs() << "Initial CS registers: {");
1623 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1624 unsigned R = CSI[i].getReg();
1625 LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1626 for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1627 SRegs[*SR] = true;
1628 }
1629 LLVM_DEBUG(dbgs() << " }\n");
1630 LLVM_DEBUG(dbgs() << "SRegs.1: "; dump_registers(SRegs, *TRI);
1631 dbgs() << "\n");
1632
1633 // (2) For each reserved register, remove that register and all of its
1634 // sub- and super-registers from SRegs.
1635 BitVector Reserved = TRI->getReservedRegs(MF);
1636 for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) {
1637 unsigned R = x;
1638 for (MCSuperRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
1639 SRegs[*SR] = false;
1640 }
1641 LLVM_DEBUG(dbgs() << "Res: "; dump_registers(Reserved, *TRI);
1642 dbgs() << "\n");
1643 LLVM_DEBUG(dbgs() << "SRegs.2: "; dump_registers(SRegs, *TRI);
1644 dbgs() << "\n");
1645
1646 // (3) Collect all registers that have at least one sub-register in SRegs,
1647 // and also have no sub-registers that are reserved. These will be the can-
1648 // didates for saving as a whole instead of their individual sub-registers.
1649 // (Saving R17:16 instead of R16 is fine, but only if R17 was not reserved.)
1650 BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1651 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1652 unsigned R = x;
1653 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR)
1654 TmpSup[*SR] = true;
1655 }
1656 for (int x = TmpSup.find_first(); x >= 0; x = TmpSup.find_next(x)) {
1657 unsigned R = x;
1658 for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR) {
1659 if (!Reserved[*SR])
1660 continue;
1661 TmpSup[R] = false;
1662 break;
1663 }
1664 }
1665 LLVM_DEBUG(dbgs() << "TmpSup: "; dump_registers(TmpSup, *TRI);
1666 dbgs() << "\n");
1667
1668 // (4) Include all super-registers found in (3) into SRegs.
1669 SRegs |= TmpSup;
1670 LLVM_DEBUG(dbgs() << "SRegs.4: "; dump_registers(SRegs, *TRI);
1671 dbgs() << "\n");
1672
1673 // (5) For each register R in SRegs, if any super-register of R is in SRegs,
1674 // remove R from SRegs.
1675 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1676 unsigned R = x;
1677 for (MCSuperRegIterator SR(R, TRI); SR.isValid(); ++SR) {
1678 if (!SRegs[*SR])
1679 continue;
1680 SRegs[R] = false;
1681 break;
1682 }
1683 }
1684 LLVM_DEBUG(dbgs() << "SRegs.5: "; dump_registers(SRegs, *TRI);
1685 dbgs() << "\n");
1686
1687 // Now, for each register that has a fixed stack slot, create the stack
1688 // object for it.
1689 CSI.clear();
1690
1691 using SpillSlot = TargetFrameLowering::SpillSlot;
1692
1693 unsigned NumFixed;
1694 int MinOffset = 0; // CS offsets are negative.
1695 const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
1696 for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
1697 if (!SRegs[S->Reg])
1698 continue;
1699 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1700 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1701 MinOffset = std::min(MinOffset, S->Offset);
1702 CSI.push_back(CalleeSavedInfo(S->Reg, FI));
1703 SRegs[S->Reg] = false;
1704 }
1705
1706 // There can be some registers that don't have fixed slots. For example,
1707 // we need to store R0-R3 in functions with exception handling. For each
1708 // such register, create a non-fixed stack object.
1709 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1710 unsigned R = x;
1711 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1712 unsigned Size = TRI->getSpillSize(*RC);
1713 int Off = MinOffset - Size;
1714 Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign());
1715 Off &= -Alignment.value();
1716 int FI = MFI.CreateFixedSpillStackObject(Size, Off);
1717 MinOffset = std::min(MinOffset, Off);
1718 CSI.push_back(CalleeSavedInfo(R, FI));
1719 SRegs[R] = false;
1720 }
1721
1722 LLVM_DEBUG({
1723 dbgs() << "CS information: {";
1724 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
1725 int FI = CSI[i].getFrameIdx();
1726 int Off = MFI.getObjectOffset(FI);
1727 dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1728 if (Off >= 0)
1729 dbgs() << '+';
1730 dbgs() << Off;
1731 }
1732 dbgs() << " }\n";
1733 });
1734
1735 #ifndef NDEBUG
1736 // Verify that all registers were handled.
1737 bool MissedReg = false;
1738 for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
1739 unsigned R = x;
1740 dbgs() << printReg(R, TRI) << ' ';
1741 MissedReg = true;
1742 }
1743 if (MissedReg)
1744 llvm_unreachable("...there are unhandled callee-saved registers!");
1745 #endif
1746
1747 return true;
1748 }
1749
expandCopy(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const1750 bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B,
1751 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1752 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1753 MachineInstr *MI = &*It;
1754 DebugLoc DL = MI->getDebugLoc();
1755 Register DstR = MI->getOperand(0).getReg();
1756 Register SrcR = MI->getOperand(1).getReg();
1757 if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1758 !Hexagon::ModRegsRegClass.contains(SrcR))
1759 return false;
1760
1761 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1762 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1763 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1764 .addReg(TmpR, RegState::Kill);
1765
1766 NewRegs.push_back(TmpR);
1767 B.erase(It);
1768 return true;
1769 }
1770
expandStoreInt(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const1771 bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B,
1772 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1773 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1774 MachineInstr *MI = &*It;
1775 if (!MI->getOperand(0).isFI())
1776 return false;
1777
1778 DebugLoc DL = MI->getDebugLoc();
1779 unsigned Opc = MI->getOpcode();
1780 Register SrcR = MI->getOperand(2).getReg();
1781 bool IsKill = MI->getOperand(2).isKill();
1782 int FI = MI->getOperand(0).getIndex();
1783
1784 // TmpR = C2_tfrpr SrcR if SrcR is a predicate register
1785 // TmpR = A2_tfrcrr SrcR if SrcR is a modifier register
1786 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1787 unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1788 : Hexagon::A2_tfrcrr;
1789 BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1790 .addReg(SrcR, getKillRegState(IsKill));
1791
1792 // S2_storeri_io FI, 0, TmpR
1793 BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1794 .addFrameIndex(FI)
1795 .addImm(0)
1796 .addReg(TmpR, RegState::Kill)
1797 .cloneMemRefs(*MI);
1798
1799 NewRegs.push_back(TmpR);
1800 B.erase(It);
1801 return true;
1802 }
1803
expandLoadInt(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const1804 bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B,
1805 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1806 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1807 MachineInstr *MI = &*It;
1808 if (!MI->getOperand(1).isFI())
1809 return false;
1810
1811 DebugLoc DL = MI->getDebugLoc();
1812 unsigned Opc = MI->getOpcode();
1813 Register DstR = MI->getOperand(0).getReg();
1814 int FI = MI->getOperand(1).getIndex();
1815
1816 // TmpR = L2_loadri_io FI, 0
1817 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1818 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1819 .addFrameIndex(FI)
1820 .addImm(0)
1821 .cloneMemRefs(*MI);
1822
1823 // DstR = C2_tfrrp TmpR if DstR is a predicate register
1824 // DstR = A2_tfrrcr TmpR if DstR is a modifier register
1825 unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1826 : Hexagon::A2_tfrrcr;
1827 BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1828 .addReg(TmpR, RegState::Kill);
1829
1830 NewRegs.push_back(TmpR);
1831 B.erase(It);
1832 return true;
1833 }
1834
expandStoreVecPred(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const1835 bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
1836 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1837 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1838 MachineInstr *MI = &*It;
1839 if (!MI->getOperand(0).isFI())
1840 return false;
1841
1842 DebugLoc DL = MI->getDebugLoc();
1843 Register SrcR = MI->getOperand(2).getReg();
1844 bool IsKill = MI->getOperand(2).isKill();
1845 int FI = MI->getOperand(0).getIndex();
1846 auto *RC = &Hexagon::HvxVRRegClass;
1847
1848 // Insert transfer to general vector register.
1849 // TmpR0 = A2_tfrsi 0x01010101
1850 // TmpR1 = V6_vandqrt Qx, TmpR0
1851 // store FI, 0, TmpR1
1852 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1853 Register TmpR1 = MRI.createVirtualRegister(RC);
1854
1855 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1856 .addImm(0x01010101);
1857
1858 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1859 .addReg(SrcR, getKillRegState(IsKill))
1860 .addReg(TmpR0, RegState::Kill);
1861
1862 auto *HRI = B.getParent()->getSubtarget<HexagonSubtarget>().getRegisterInfo();
1863 HII.storeRegToStackSlot(B, It, TmpR1, true, FI, RC, HRI);
1864 expandStoreVec(B, std::prev(It), MRI, HII, NewRegs);
1865
1866 NewRegs.push_back(TmpR0);
1867 NewRegs.push_back(TmpR1);
1868 B.erase(It);
1869 return true;
1870 }
1871
expandLoadVecPred(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const1872 bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B,
1873 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1874 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1875 MachineInstr *MI = &*It;
1876 if (!MI->getOperand(1).isFI())
1877 return false;
1878
1879 DebugLoc DL = MI->getDebugLoc();
1880 Register DstR = MI->getOperand(0).getReg();
1881 int FI = MI->getOperand(1).getIndex();
1882 auto *RC = &Hexagon::HvxVRRegClass;
1883
1884 // TmpR0 = A2_tfrsi 0x01010101
1885 // TmpR1 = load FI, 0
1886 // DstR = V6_vandvrt TmpR1, TmpR0
1887 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1888 Register TmpR1 = MRI.createVirtualRegister(RC);
1889
1890 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1891 .addImm(0x01010101);
1892 MachineFunction &MF = *B.getParent();
1893 auto *HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1894 HII.loadRegFromStackSlot(B, It, TmpR1, FI, RC, HRI);
1895 expandLoadVec(B, std::prev(It), MRI, HII, NewRegs);
1896
1897 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1898 .addReg(TmpR1, RegState::Kill)
1899 .addReg(TmpR0, RegState::Kill);
1900
1901 NewRegs.push_back(TmpR0);
1902 NewRegs.push_back(TmpR1);
1903 B.erase(It);
1904 return true;
1905 }
1906
expandStoreVec2(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const1907 bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
1908 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1909 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1910 MachineFunction &MF = *B.getParent();
1911 auto &MFI = MF.getFrameInfo();
1912 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1913 MachineInstr *MI = &*It;
1914 if (!MI->getOperand(0).isFI())
1915 return false;
1916
1917 // It is possible that the double vector being stored is only partially
1918 // defined. From the point of view of the liveness tracking, it is ok to
1919 // store it as a whole, but if we break it up we may end up storing a
1920 // register that is entirely undefined.
1921 LivePhysRegs LPR(HRI);
1922 LPR.addLiveIns(B);
1923 SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;
1924 for (auto R = B.begin(); R != It; ++R) {
1925 Clobbers.clear();
1926 LPR.stepForward(*R, Clobbers);
1927 }
1928
1929 DebugLoc DL = MI->getDebugLoc();
1930 Register SrcR = MI->getOperand(2).getReg();
1931 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1932 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1933 bool IsKill = MI->getOperand(2).isKill();
1934 int FI = MI->getOperand(0).getIndex();
1935 bool NeedsAligna = needsAligna(MF);
1936
1937 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1938 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1939 Align HasAlign = MFI.getObjectAlign(FI);
1940 unsigned StoreOpc;
1941
1942 auto UseAligned = [&](Align NeedAlign, Align HasAlign) {
1943 return !NeedsAligna && (NeedAlign <= HasAlign);
1944 };
1945
1946 // Store low part.
1947 if (LPR.contains(SrcLo)) {
1948 StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai
1949 : Hexagon::V6_vS32Ub_ai;
1950 BuildMI(B, It, DL, HII.get(StoreOpc))
1951 .addFrameIndex(FI)
1952 .addImm(0)
1953 .addReg(SrcLo, getKillRegState(IsKill))
1954 .cloneMemRefs(*MI);
1955 }
1956
1957 // Store high part.
1958 if (LPR.contains(SrcHi)) {
1959 StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai
1960 : Hexagon::V6_vS32Ub_ai;
1961 BuildMI(B, It, DL, HII.get(StoreOpc))
1962 .addFrameIndex(FI)
1963 .addImm(Size)
1964 .addReg(SrcHi, getKillRegState(IsKill))
1965 .cloneMemRefs(*MI);
1966 }
1967
1968 B.erase(It);
1969 return true;
1970 }
1971
expandLoadVec2(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const1972 bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B,
1973 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
1974 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
1975 MachineFunction &MF = *B.getParent();
1976 auto &MFI = MF.getFrameInfo();
1977 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
1978 MachineInstr *MI = &*It;
1979 if (!MI->getOperand(1).isFI())
1980 return false;
1981
1982 DebugLoc DL = MI->getDebugLoc();
1983 Register DstR = MI->getOperand(0).getReg();
1984 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1985 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1986 int FI = MI->getOperand(1).getIndex();
1987 bool NeedsAligna = needsAligna(MF);
1988
1989 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1990 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1991 Align HasAlign = MFI.getObjectAlign(FI);
1992 unsigned LoadOpc;
1993
1994 auto UseAligned = [&](Align NeedAlign, Align HasAlign) {
1995 return !NeedsAligna && (NeedAlign <= HasAlign);
1996 };
1997
1998 // Load low part.
1999 LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai
2000 : Hexagon::V6_vL32Ub_ai;
2001 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
2002 .addFrameIndex(FI)
2003 .addImm(0)
2004 .cloneMemRefs(*MI);
2005
2006 // Load high part.
2007 LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai
2008 : Hexagon::V6_vL32Ub_ai;
2009 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
2010 .addFrameIndex(FI)
2011 .addImm(Size)
2012 .cloneMemRefs(*MI);
2013
2014 B.erase(It);
2015 return true;
2016 }
2017
expandStoreVec(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const2018 bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B,
2019 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
2020 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
2021 MachineFunction &MF = *B.getParent();
2022 auto &MFI = MF.getFrameInfo();
2023 MachineInstr *MI = &*It;
2024 if (!MI->getOperand(0).isFI())
2025 return false;
2026
2027 bool NeedsAligna = needsAligna(MF);
2028 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2029 DebugLoc DL = MI->getDebugLoc();
2030 Register SrcR = MI->getOperand(2).getReg();
2031 bool IsKill = MI->getOperand(2).isKill();
2032 int FI = MI->getOperand(0).getIndex();
2033
2034 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2035 Align HasAlign = MFI.getObjectAlign(FI);
2036 bool UseAligned = !NeedsAligna && (NeedAlign <= HasAlign);
2037 unsigned StoreOpc = UseAligned ? Hexagon::V6_vS32b_ai
2038 : Hexagon::V6_vS32Ub_ai;
2039 BuildMI(B, It, DL, HII.get(StoreOpc))
2040 .addFrameIndex(FI)
2041 .addImm(0)
2042 .addReg(SrcR, getKillRegState(IsKill))
2043 .cloneMemRefs(*MI);
2044
2045 B.erase(It);
2046 return true;
2047 }
2048
expandLoadVec(MachineBasicBlock & B,MachineBasicBlock::iterator It,MachineRegisterInfo & MRI,const HexagonInstrInfo & HII,SmallVectorImpl<unsigned> & NewRegs) const2049 bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B,
2050 MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
2051 const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
2052 MachineFunction &MF = *B.getParent();
2053 auto &MFI = MF.getFrameInfo();
2054 MachineInstr *MI = &*It;
2055 if (!MI->getOperand(1).isFI())
2056 return false;
2057
2058 bool NeedsAligna = needsAligna(MF);
2059 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2060 DebugLoc DL = MI->getDebugLoc();
2061 Register DstR = MI->getOperand(0).getReg();
2062 int FI = MI->getOperand(1).getIndex();
2063
2064 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2065 Align HasAlign = MFI.getObjectAlign(FI);
2066 bool UseAligned = !NeedsAligna && (NeedAlign <= HasAlign);
2067 unsigned LoadOpc = UseAligned ? Hexagon::V6_vL32b_ai
2068 : Hexagon::V6_vL32Ub_ai;
2069 BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
2070 .addFrameIndex(FI)
2071 .addImm(0)
2072 .cloneMemRefs(*MI);
2073
2074 B.erase(It);
2075 return true;
2076 }
2077
expandSpillMacros(MachineFunction & MF,SmallVectorImpl<unsigned> & NewRegs) const2078 bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
2079 SmallVectorImpl<unsigned> &NewRegs) const {
2080 auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
2081 MachineRegisterInfo &MRI = MF.getRegInfo();
2082 bool Changed = false;
2083
2084 for (auto &B : MF) {
2085 // Traverse the basic block.
2086 MachineBasicBlock::iterator NextI;
2087 for (auto I = B.begin(), E = B.end(); I != E; I = NextI) {
2088 MachineInstr *MI = &*I;
2089 NextI = std::next(I);
2090 unsigned Opc = MI->getOpcode();
2091
2092 switch (Opc) {
2093 case TargetOpcode::COPY:
2094 Changed |= expandCopy(B, I, MRI, HII, NewRegs);
2095 break;
2096 case Hexagon::STriw_pred:
2097 case Hexagon::STriw_ctr:
2098 Changed |= expandStoreInt(B, I, MRI, HII, NewRegs);
2099 break;
2100 case Hexagon::LDriw_pred:
2101 case Hexagon::LDriw_ctr:
2102 Changed |= expandLoadInt(B, I, MRI, HII, NewRegs);
2103 break;
2104 case Hexagon::PS_vstorerq_ai:
2105 Changed |= expandStoreVecPred(B, I, MRI, HII, NewRegs);
2106 break;
2107 case Hexagon::PS_vloadrq_ai:
2108 Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs);
2109 break;
2110 case Hexagon::PS_vloadrw_ai:
2111 Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs);
2112 break;
2113 case Hexagon::PS_vstorerw_ai:
2114 Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs);
2115 break;
2116 }
2117 }
2118 }
2119
2120 return Changed;
2121 }
2122
determineCalleeSaves(MachineFunction & MF,BitVector & SavedRegs,RegScavenger * RS) const2123 void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
2124 BitVector &SavedRegs,
2125 RegScavenger *RS) const {
2126 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2127
2128 SavedRegs.resize(HRI.getNumRegs());
2129
2130 // If we have a function containing __builtin_eh_return we want to spill and
2131 // restore all callee saved registers. Pretend that they are used.
2132 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
2133 for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
2134 SavedRegs.set(*R);
2135
2136 // Replace predicate register pseudo spill code.
2137 SmallVector<unsigned,8> NewRegs;
2138 expandSpillMacros(MF, NewRegs);
2139 if (OptimizeSpillSlots && !isOptNone(MF))
2140 optimizeSpillSlots(MF, NewRegs);
2141
2142 // We need to reserve a spill slot if scavenging could potentially require
2143 // spilling a scavenged register.
2144 if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
2145 MachineFrameInfo &MFI = MF.getFrameInfo();
2146 MachineRegisterInfo &MRI = MF.getRegInfo();
2147 SetVector<const TargetRegisterClass*> SpillRCs;
2148 // Reserve an int register in any case, because it could be used to hold
2149 // the stack offset in case it does not fit into a spill instruction.
2150 SpillRCs.insert(&Hexagon::IntRegsRegClass);
2151
2152 for (unsigned VR : NewRegs)
2153 SpillRCs.insert(MRI.getRegClass(VR));
2154
2155 for (auto *RC : SpillRCs) {
2156 if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
2157 continue;
2158 unsigned Num = 1;
2159 switch (RC->getID()) {
2160 case Hexagon::IntRegsRegClassID:
2161 Num = NumberScavengerSlots;
2162 break;
2163 case Hexagon::HvxQRRegClassID:
2164 Num = 2; // Vector predicate spills also need a vector register.
2165 break;
2166 }
2167 unsigned S = HRI.getSpillSize(*RC);
2168 Align A = HRI.getSpillAlign(*RC);
2169 for (unsigned i = 0; i < Num; i++) {
2170 int NewFI = MFI.CreateSpillStackObject(S, A);
2171 RS->addScavengingFrameIndex(NewFI);
2172 }
2173 }
2174 }
2175
2176 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2177 }
2178
findPhysReg(MachineFunction & MF,HexagonBlockRanges::IndexRange & FIR,HexagonBlockRanges::InstrIndexMap & IndexMap,HexagonBlockRanges::RegToRangeMap & DeadMap,const TargetRegisterClass * RC) const2179 unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
2180 HexagonBlockRanges::IndexRange &FIR,
2181 HexagonBlockRanges::InstrIndexMap &IndexMap,
2182 HexagonBlockRanges::RegToRangeMap &DeadMap,
2183 const TargetRegisterClass *RC) const {
2184 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
2185 auto &MRI = MF.getRegInfo();
2186
2187 auto isDead = [&FIR,&DeadMap] (unsigned Reg) -> bool {
2188 auto F = DeadMap.find({Reg,0});
2189 if (F == DeadMap.end())
2190 return false;
2191 for (auto &DR : F->second)
2192 if (DR.contains(FIR))
2193 return true;
2194 return false;
2195 };
2196
2197 for (unsigned Reg : RC->getRawAllocationOrder(MF)) {
2198 bool Dead = true;
2199 for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
2200 if (isDead(R.Reg))
2201 continue;
2202 Dead = false;
2203 break;
2204 }
2205 if (Dead)
2206 return Reg;
2207 }
2208 return 0;
2209 }
2210
optimizeSpillSlots(MachineFunction & MF,SmallVectorImpl<unsigned> & VRegs) const2211 void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
2212 SmallVectorImpl<unsigned> &VRegs) const {
2213 auto &HST = MF.getSubtarget<HexagonSubtarget>();
2214 auto &HII = *HST.getInstrInfo();
2215 auto &HRI = *HST.getRegisterInfo();
2216 auto &MRI = MF.getRegInfo();
2217 HexagonBlockRanges HBR(MF);
2218
2219 using BlockIndexMap =
2220 std::map<MachineBasicBlock *, HexagonBlockRanges::InstrIndexMap>;
2221 using BlockRangeMap =
2222 std::map<MachineBasicBlock *, HexagonBlockRanges::RangeList>;
2223 using IndexType = HexagonBlockRanges::IndexType;
2224
2225 struct SlotInfo {
2226 BlockRangeMap Map;
2227 unsigned Size = 0;
2228 const TargetRegisterClass *RC = nullptr;
2229
2230 SlotInfo() = default;
2231 };
2232
2233 BlockIndexMap BlockIndexes;
2234 SmallSet<int,4> BadFIs;
2235 std::map<int,SlotInfo> FIRangeMap;
2236
2237 // Accumulate register classes: get a common class for a pre-existing
2238 // class HaveRC and a new class NewRC. Return nullptr if a common class
2239 // cannot be found, otherwise return the resulting class. If HaveRC is
2240 // nullptr, assume that it is still unset.
2241 auto getCommonRC =
2242 [](const TargetRegisterClass *HaveRC,
2243 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * {
2244 if (HaveRC == nullptr || HaveRC == NewRC)
2245 return NewRC;
2246 // Different classes, both non-null. Pick the more general one.
2247 if (HaveRC->hasSubClassEq(NewRC))
2248 return HaveRC;
2249 if (NewRC->hasSubClassEq(HaveRC))
2250 return NewRC;
2251 return nullptr;
2252 };
2253
2254 // Scan all blocks in the function. Check all occurrences of frame indexes,
2255 // and collect relevant information.
2256 for (auto &B : MF) {
2257 std::map<int,IndexType> LastStore, LastLoad;
2258 // Emplace appears not to be supported in gcc 4.7.2-4.
2259 //auto P = BlockIndexes.emplace(&B, HexagonBlockRanges::InstrIndexMap(B));
2260 auto P = BlockIndexes.insert(
2261 std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
2262 auto &IndexMap = P.first->second;
2263 LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
2264 << IndexMap << '\n');
2265
2266 for (auto &In : B) {
2267 int LFI, SFI;
2268 bool Load = HII.isLoadFromStackSlot(In, LFI) && !HII.isPredicated(In);
2269 bool Store = HII.isStoreToStackSlot(In, SFI) && !HII.isPredicated(In);
2270 if (Load && Store) {
2271 // If it's both a load and a store, then we won't handle it.
2272 BadFIs.insert(LFI);
2273 BadFIs.insert(SFI);
2274 continue;
2275 }
2276 // Check for register classes of the register used as the source for
2277 // the store, and the register used as the destination for the load.
2278 // Also, only accept base+imm_offset addressing modes. Other addressing
2279 // modes can have side-effects (post-increments, etc.). For stack
2280 // slots they are very unlikely, so there is not much loss due to
2281 // this restriction.
2282 if (Load || Store) {
2283 int TFI = Load ? LFI : SFI;
2284 unsigned AM = HII.getAddrMode(In);
2285 SlotInfo &SI = FIRangeMap[TFI];
2286 bool Bad = (AM != HexagonII::BaseImmOffset);
2287 if (!Bad) {
2288 // If the addressing mode is ok, check the register class.
2289 unsigned OpNum = Load ? 0 : 2;
2290 auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
2291 RC = getCommonRC(SI.RC, RC);
2292 if (RC == nullptr)
2293 Bad = true;
2294 else
2295 SI.RC = RC;
2296 }
2297 if (!Bad) {
2298 // Check sizes.
2299 unsigned S = HII.getMemAccessSize(In);
2300 if (SI.Size != 0 && SI.Size != S)
2301 Bad = true;
2302 else
2303 SI.Size = S;
2304 }
2305 if (!Bad) {
2306 for (auto *Mo : In.memoperands()) {
2307 if (!Mo->isVolatile() && !Mo->isAtomic())
2308 continue;
2309 Bad = true;
2310 break;
2311 }
2312 }
2313 if (Bad)
2314 BadFIs.insert(TFI);
2315 }
2316
2317 // Locate uses of frame indices.
2318 for (unsigned i = 0, n = In.getNumOperands(); i < n; ++i) {
2319 const MachineOperand &Op = In.getOperand(i);
2320 if (!Op.isFI())
2321 continue;
2322 int FI = Op.getIndex();
2323 // Make sure that the following operand is an immediate and that
2324 // it is 0. This is the offset in the stack object.
2325 if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2326 In.getOperand(i+1).getImm() != 0)
2327 BadFIs.insert(FI);
2328 if (BadFIs.count(FI))
2329 continue;
2330
2331 IndexType Index = IndexMap.getIndex(&In);
2332 if (Load) {
2333 if (LastStore[FI] == IndexType::None)
2334 LastStore[FI] = IndexType::Entry;
2335 LastLoad[FI] = Index;
2336 } else if (Store) {
2337 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2338 if (LastStore[FI] != IndexType::None)
2339 RL.add(LastStore[FI], LastLoad[FI], false, false);
2340 else if (LastLoad[FI] != IndexType::None)
2341 RL.add(IndexType::Entry, LastLoad[FI], false, false);
2342 LastLoad[FI] = IndexType::None;
2343 LastStore[FI] = Index;
2344 } else {
2345 BadFIs.insert(FI);
2346 }
2347 }
2348 }
2349
2350 for (auto &I : LastLoad) {
2351 IndexType LL = I.second;
2352 if (LL == IndexType::None)
2353 continue;
2354 auto &RL = FIRangeMap[I.first].Map[&B];
2355 IndexType &LS = LastStore[I.first];
2356 if (LS != IndexType::None)
2357 RL.add(LS, LL, false, false);
2358 else
2359 RL.add(IndexType::Entry, LL, false, false);
2360 LS = IndexType::None;
2361 }
2362 for (auto &I : LastStore) {
2363 IndexType LS = I.second;
2364 if (LS == IndexType::None)
2365 continue;
2366 auto &RL = FIRangeMap[I.first].Map[&B];
2367 RL.add(LS, IndexType::None, false, false);
2368 }
2369 }
2370
2371 LLVM_DEBUG({
2372 for (auto &P : FIRangeMap) {
2373 dbgs() << "fi#" << P.first;
2374 if (BadFIs.count(P.first))
2375 dbgs() << " (bad)";
2376 dbgs() << " RC: ";
2377 if (P.second.RC != nullptr)
2378 dbgs() << HRI.getRegClassName(P.second.RC) << '\n';
2379 else
2380 dbgs() << "<null>\n";
2381 for (auto &R : P.second.Map)
2382 dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
2383 << "}\n";
2384 }
2385 });
2386
2387 // When a slot is loaded from in a block without being stored to in the
2388 // same block, it is live-on-entry to this block. To avoid CFG analysis,
2389 // consider this slot to be live-on-exit from all blocks.
2390 SmallSet<int,4> LoxFIs;
2391
2392 std::map<MachineBasicBlock*,std::vector<int>> BlockFIMap;
2393
2394 for (auto &P : FIRangeMap) {
2395 // P = pair(FI, map: BB->RangeList)
2396 if (BadFIs.count(P.first))
2397 continue;
2398 for (auto &B : MF) {
2399 auto F = P.second.Map.find(&B);
2400 // F = pair(BB, RangeList)
2401 if (F == P.second.Map.end() || F->second.empty())
2402 continue;
2403 HexagonBlockRanges::IndexRange &IR = F->second.front();
2404 if (IR.start() == IndexType::Entry)
2405 LoxFIs.insert(P.first);
2406 BlockFIMap[&B].push_back(P.first);
2407 }
2408 }
2409
2410 LLVM_DEBUG({
2411 dbgs() << "Block-to-FI map (* -- live-on-exit):\n";
2412 for (auto &P : BlockFIMap) {
2413 auto &FIs = P.second;
2414 if (FIs.empty())
2415 continue;
2416 dbgs() << " " << printMBBReference(*P.first) << ": {";
2417 for (auto I : FIs) {
2418 dbgs() << " fi#" << I;
2419 if (LoxFIs.count(I))
2420 dbgs() << '*';
2421 }
2422 dbgs() << " }\n";
2423 }
2424 });
2425
2426 #ifndef NDEBUG
2427 bool HasOptLimit = SpillOptMax.getPosition();
2428 #endif
2429
2430 // eliminate loads, when all loads eliminated, eliminate all stores.
2431 for (auto &B : MF) {
2432 auto F = BlockIndexes.find(&B);
2433 assert(F != BlockIndexes.end());
2434 HexagonBlockRanges::InstrIndexMap &IM = F->second;
2435 HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
2436 HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
2437 LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
2438 << HexagonBlockRanges::PrintRangeMap(DM, HRI));
2439
2440 for (auto FI : BlockFIMap[&B]) {
2441 if (BadFIs.count(FI))
2442 continue;
2443 LLVM_DEBUG(dbgs() << "Working on fi#" << FI << '\n');
2444 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B];
2445 for (auto &Range : RL) {
2446 LLVM_DEBUG(dbgs() << "--Examining range:" << RL << '\n');
2447 if (!IndexType::isInstr(Range.start()) ||
2448 !IndexType::isInstr(Range.end()))
2449 continue;
2450 MachineInstr &SI = *IM.getInstr(Range.start());
2451 MachineInstr &EI = *IM.getInstr(Range.end());
2452 assert(SI.mayStore() && "Unexpected start instruction");
2453 assert(EI.mayLoad() && "Unexpected end instruction");
2454 MachineOperand &SrcOp = SI.getOperand(2);
2455
2456 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2457 SrcOp.getSubReg() };
2458 auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
2459 // The this-> is needed to unconfuse MSVC.
2460 unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
2461 LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
2462 << '\n');
2463 if (FoundR == 0)
2464 continue;
2465 #ifndef NDEBUG
2466 if (HasOptLimit) {
2467 if (SpillOptCount >= SpillOptMax)
2468 return;
2469 SpillOptCount++;
2470 }
2471 #endif
2472
2473 // Generate the copy-in: "FoundR = COPY SrcR" at the store location.
2474 MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
2475 MachineInstr *CopyIn = nullptr;
2476 if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
2477 const DebugLoc &DL = SI.getDebugLoc();
2478 CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2479 .add(SrcOp);
2480 }
2481
2482 ++StartIt;
2483 // Check if this is a last store and the FI is live-on-exit.
2484 if (LoxFIs.count(FI) && (&Range == &RL.back())) {
2485 // Update store's source register.
2486 if (unsigned SR = SrcOp.getSubReg())
2487 SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2488 else
2489 SrcOp.setReg(FoundR);
2490 SrcOp.setSubReg(0);
2491 // We are keeping this register live.
2492 SrcOp.setIsKill(false);
2493 } else {
2494 B.erase(&SI);
2495 IM.replaceInstr(&SI, CopyIn);
2496 }
2497
2498 auto EndIt = std::next(EI.getIterator());
2499 for (auto It = StartIt; It != EndIt; It = NextIt) {
2500 MachineInstr &MI = *It;
2501 NextIt = std::next(It);
2502 int TFI;
2503 if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
2504 continue;
2505 Register DstR = MI.getOperand(0).getReg();
2506 assert(MI.getOperand(0).getSubReg() == 0);
2507 MachineInstr *CopyOut = nullptr;
2508 if (DstR != FoundR) {
2509 DebugLoc DL = MI.getDebugLoc();
2510 unsigned MemSize = HII.getMemAccessSize(MI);
2511 assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
2512 unsigned CopyOpc = TargetOpcode::COPY;
2513 if (HII.isSignExtendingLoad(MI))
2514 CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2515 else if (HII.isZeroExtendingLoad(MI))
2516 CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2517 CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2518 .addReg(FoundR, getKillRegState(&MI == &EI));
2519 }
2520 IM.replaceInstr(&MI, CopyOut);
2521 B.erase(It);
2522 }
2523
2524 // Update the dead map.
2525 HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };
2526 for (auto RR : HexagonBlockRanges::expandToSubRegs(FoundRR, MRI, HRI))
2527 DM[RR].subtract(Range);
2528 } // for Range in range list
2529 }
2530 }
2531 }
2532
expandAlloca(MachineInstr * AI,const HexagonInstrInfo & HII,unsigned SP,unsigned CF) const2533 void HexagonFrameLowering::expandAlloca(MachineInstr *AI,
2534 const HexagonInstrInfo &HII, unsigned SP, unsigned CF) const {
2535 MachineBasicBlock &MB = *AI->getParent();
2536 DebugLoc DL = AI->getDebugLoc();
2537 unsigned A = AI->getOperand(2).getImm();
2538
2539 // Have
2540 // Rd = alloca Rs, #A
2541 //
2542 // If Rs and Rd are different registers, use this sequence:
2543 // Rd = sub(r29, Rs)
2544 // r29 = sub(r29, Rs)
2545 // Rd = and(Rd, #-A) ; if necessary
2546 // r29 = and(r29, #-A) ; if necessary
2547 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2548 // otherwise, do
2549 // Rd = sub(r29, Rs)
2550 // Rd = and(Rd, #-A) ; if necessary
2551 // r29 = Rd
2552 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2553
2554 MachineOperand &RdOp = AI->getOperand(0);
2555 MachineOperand &RsOp = AI->getOperand(1);
2556 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
2557
2558 // Rd = sub(r29, Rs)
2559 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2560 .addReg(SP)
2561 .addReg(Rs);
2562 if (Rs != Rd) {
2563 // r29 = sub(r29, Rs)
2564 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2565 .addReg(SP)
2566 .addReg(Rs);
2567 }
2568 if (A > 8) {
2569 // Rd = and(Rd, #-A)
2570 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2571 .addReg(Rd)
2572 .addImm(-int64_t(A));
2573 if (Rs != Rd)
2574 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2575 .addReg(SP)
2576 .addImm(-int64_t(A));
2577 }
2578 if (Rs == Rd) {
2579 // r29 = Rd
2580 BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2581 .addReg(Rd);
2582 }
2583 if (CF > 0) {
2584 // Rd = add(Rd, #CF)
2585 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2586 .addReg(Rd)
2587 .addImm(CF);
2588 }
2589 }
2590
needsAligna(const MachineFunction & MF) const2591 bool HexagonFrameLowering::needsAligna(const MachineFunction &MF) const {
2592 const MachineFrameInfo &MFI = MF.getFrameInfo();
2593 if (!MFI.hasVarSizedObjects())
2594 return false;
2595 // Do not check for max stack object alignment here, because the stack
2596 // may not be complete yet. Assume that we will need PS_aligna if there
2597 // are variable-sized objects.
2598 return true;
2599 }
2600
getAlignaInstr(const MachineFunction & MF) const2601 const MachineInstr *HexagonFrameLowering::getAlignaInstr(
2602 const MachineFunction &MF) const {
2603 for (auto &B : MF)
2604 for (auto &I : B)
2605 if (I.getOpcode() == Hexagon::PS_aligna)
2606 return &I;
2607 return nullptr;
2608 }
2609
2610 /// Adds all callee-saved registers as implicit uses or defs to the
2611 /// instruction.
addCalleeSaveRegistersAsImpOperand(MachineInstr * MI,const CSIVect & CSI,bool IsDef,bool IsKill) const2612 void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
2613 const CSIVect &CSI, bool IsDef, bool IsKill) const {
2614 // Add the callee-saved registers as implicit uses.
2615 for (auto &R : CSI)
2616 MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
2617 }
2618
2619 /// Determine whether the callee-saved register saves and restores should
2620 /// be generated via inline code. If this function returns "true", inline
2621 /// code will be generated. If this function returns "false", additional
2622 /// checks are performed, which may still lead to the inline code.
shouldInlineCSR(const MachineFunction & MF,const CSIVect & CSI) const2623 bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
2624 const CSIVect &CSI) const {
2625 if (MF.getSubtarget<HexagonSubtarget>().isEnvironmentMusl())
2626 return true;
2627 if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
2628 return true;
2629 if (!hasFP(MF))
2630 return true;
2631 if (!isOptSize(MF) && !isMinSize(MF))
2632 if (MF.getTarget().getOptLevel() > CodeGenOpt::Default)
2633 return true;
2634
2635 // Check if CSI only has double registers, and if the registers form
2636 // a contiguous block starting from D8.
2637 BitVector Regs(Hexagon::NUM_TARGET_REGS);
2638 for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
2639 unsigned R = CSI[i].getReg();
2640 if (!Hexagon::DoubleRegsRegClass.contains(R))
2641 return true;
2642 Regs[R] = true;
2643 }
2644 int F = Regs.find_first();
2645 if (F != Hexagon::D8)
2646 return true;
2647 while (F >= 0) {
2648 int N = Regs.find_next(F);
2649 if (N >= 0 && N != F+1)
2650 return true;
2651 F = N;
2652 }
2653
2654 return false;
2655 }
2656
useSpillFunction(const MachineFunction & MF,const CSIVect & CSI) const2657 bool HexagonFrameLowering::useSpillFunction(const MachineFunction &MF,
2658 const CSIVect &CSI) const {
2659 if (shouldInlineCSR(MF, CSI))
2660 return false;
2661 unsigned NumCSI = CSI.size();
2662 if (NumCSI <= 1)
2663 return false;
2664
2665 unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs
2666 : SpillFuncThreshold;
2667 return Threshold < NumCSI;
2668 }
2669
useRestoreFunction(const MachineFunction & MF,const CSIVect & CSI) const2670 bool HexagonFrameLowering::useRestoreFunction(const MachineFunction &MF,
2671 const CSIVect &CSI) const {
2672 if (shouldInlineCSR(MF, CSI))
2673 return false;
2674 // The restore functions do a bit more than just restoring registers.
2675 // The non-returning versions will go back directly to the caller's
2676 // caller, others will clean up the stack frame in preparation for
2677 // a tail call. Using them can still save code size even if only one
2678 // register is getting restores. Make the decision based on -Oz:
2679 // using -Os will use inline restore for a single register.
2680 if (isMinSize(MF))
2681 return true;
2682 unsigned NumCSI = CSI.size();
2683 if (NumCSI <= 1)
2684 return false;
2685
2686 unsigned Threshold = isOptSize(MF) ? SpillFuncThresholdOs-1
2687 : SpillFuncThreshold;
2688 return Threshold < NumCSI;
2689 }
2690
mayOverflowFrameOffset(MachineFunction & MF) const2691 bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
2692 unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
2693 auto &HST = MF.getSubtarget<HexagonSubtarget>();
2694 // A fairly simplistic guess as to whether a potential load/store to a
2695 // stack location could require an extra register.
2696 if (HST.useHVXOps() && StackSize > 256)
2697 return true;
2698
2699 // Check if the function has store-immediate instructions that access
2700 // the stack. Since the offset field is not extendable, if the stack
2701 // size exceeds the offset limit (6 bits, shifted), the stores will
2702 // require a new base register.
2703 bool HasImmStack = false;
2704 unsigned MinLS = ~0u; // Log_2 of the memory access size.
2705
2706 for (const MachineBasicBlock &B : MF) {
2707 for (const MachineInstr &MI : B) {
2708 unsigned LS = 0;
2709 switch (MI.getOpcode()) {
2710 case Hexagon::S4_storeirit_io:
2711 case Hexagon::S4_storeirif_io:
2712 case Hexagon::S4_storeiri_io:
2713 ++LS;
2714 LLVM_FALLTHROUGH;
2715 case Hexagon::S4_storeirht_io:
2716 case Hexagon::S4_storeirhf_io:
2717 case Hexagon::S4_storeirh_io:
2718 ++LS;
2719 LLVM_FALLTHROUGH;
2720 case Hexagon::S4_storeirbt_io:
2721 case Hexagon::S4_storeirbf_io:
2722 case Hexagon::S4_storeirb_io:
2723 if (MI.getOperand(0).isFI())
2724 HasImmStack = true;
2725 MinLS = std::min(MinLS, LS);
2726 break;
2727 }
2728 }
2729 }
2730
2731 if (HasImmStack)
2732 return !isUInt<6>(StackSize >> MinLS);
2733
2734 return false;
2735 }
2736