1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonArch.h"
14 #include "HexagonTargetStreamer.h"
15 #include "MCTargetDesc/HexagonInstPrinter.h"
16 #include "MCTargetDesc/HexagonMCAsmInfo.h"
17 #include "MCTargetDesc/HexagonMCELFStreamer.h"
18 #include "MCTargetDesc/HexagonMCInstrInfo.h"
19 #include "MCTargetDesc/HexagonMCTargetDesc.h"
20 #include "TargetInfo/HexagonTargetInfo.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCCodeEmitter.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDwarf.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCInstrAnalysis.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCObjectWriter.h"
32 #include "llvm/MC/MCRegisterInfo.h"
33 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/MC/MCSubtargetInfo.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include <cassert>
39 #include <cstdint>
40 #include <mutex>
41 #include <new>
42 #include <string>
43 #include <unordered_map>
44 
45 using namespace llvm;
46 
47 #define GET_INSTRINFO_MC_DESC
48 #include "HexagonGenInstrInfo.inc"
49 
50 #define GET_SUBTARGETINFO_MC_DESC
51 #include "HexagonGenSubtargetInfo.inc"
52 
53 #define GET_REGINFO_MC_DESC
54 #include "HexagonGenRegisterInfo.inc"
55 
56 cl::opt<bool> llvm::HexagonDisableCompound
57   ("mno-compound",
58    cl::desc("Disable looking for compound instructions for Hexagon"));
59 
60 cl::opt<bool> llvm::HexagonDisableDuplex
61   ("mno-pairing",
62    cl::desc("Disable looking for duplex instructions for Hexagon"));
63 
64 namespace { // These flags are to be deprecated
65 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
66                   cl::init(false));
67 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
68                    cl::init(false));
69 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
70                    cl::init(false));
71 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
72                    cl::init(false));
73 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
74                    cl::init(false));
75 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
76                    cl::init(false));
77 cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
78                    cl::init(false));
79 cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
80                     cl::init(false));
81 
82 cl::opt<Hexagon::ArchEnum>
83     EnableHVX("mhvx",
84       cl::desc("Enable Hexagon Vector eXtensions"),
85       cl::values(
86         clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
87         clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
88         clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
89         clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
90         clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
91         // Sentinel for no value specified.
92         clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
93       // Sentinel for flag not present.
94       cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional);
95 } // namespace
96 
97 static cl::opt<bool>
98   DisableHVX("mno-hvx", cl::Hidden,
99              cl::desc("Disable Hexagon Vector eXtensions"));
100 
101 
102 static StringRef DefaultArch = "hexagonv60";
103 
HexagonGetArchVariant()104 static StringRef HexagonGetArchVariant() {
105   if (MV5)
106     return "hexagonv5";
107   if (MV55)
108     return "hexagonv55";
109   if (MV60)
110     return "hexagonv60";
111   if (MV62)
112     return "hexagonv62";
113   if (MV65)
114     return "hexagonv65";
115   if (MV66)
116     return "hexagonv66";
117   if (MV67)
118     return "hexagonv67";
119   if (MV67T)
120     return "hexagonv67t";
121   return "";
122 }
123 
selectHexagonCPU(StringRef CPU)124 StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
125   StringRef ArchV = HexagonGetArchVariant();
126   if (!ArchV.empty() && !CPU.empty()) {
127     // Tiny cores have a "t" suffix that is discarded when creating a secondary
128     // non-tiny subtarget.  See: addArchSubtarget
129     std::pair<StringRef,StringRef> ArchP = ArchV.split('t');
130     std::pair<StringRef,StringRef> CPUP = CPU.split('t');
131     if (!ArchP.first.equals(CPUP.first))
132         report_fatal_error("conflicting architectures specified.");
133     return CPU;
134   }
135   if (ArchV.empty()) {
136     if (CPU.empty())
137       CPU = DefaultArch;
138     return CPU;
139   }
140   return ArchV;
141 }
142 
HexagonGetLastSlot()143 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
144 
HexagonConvertUnits(unsigned ItinUnits,unsigned * Lanes)145 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
146   enum {
147     CVI_NONE = 0,
148     CVI_XLANE = 1 << 0,
149     CVI_SHIFT = 1 << 1,
150     CVI_MPY0 = 1 << 2,
151     CVI_MPY1 = 1 << 3,
152     CVI_ZW = 1 << 4
153   };
154 
155   if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
156       ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
157     return (*Lanes = 4, CVI_XLANE);
158   else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
159            ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
160     return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
161   else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
162     return (*Lanes = 2, CVI_MPY0);
163   else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
164     return (*Lanes = 2, CVI_XLANE);
165   else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
166            ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
167            ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
168            ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
169     return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
170   else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
171            ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
172     return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
173   else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
174            ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
175     return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
176   else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
177     return (*Lanes = 1, CVI_ZW);
178   else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
179     return (*Lanes = 1, CVI_XLANE);
180   else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
181     return (*Lanes = 1, CVI_SHIFT);
182 
183   return (*Lanes = 0, CVI_NONE);
184 }
185 
186 
187 namespace llvm {
188 namespace HexagonFUnits {
isSlot0Only(unsigned units)189 bool isSlot0Only(unsigned units) {
190   return HexagonItinerariesV62FU::SLOT0 == units;
191 }
192 } // namespace HexagonFUnits
193 } // namespace llvm
194 
195 namespace {
196 
197 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
198 public:
HexagonTargetAsmStreamer(MCStreamer & S,formatted_raw_ostream & OS,bool isVerboseAsm,MCInstPrinter & IP)199   HexagonTargetAsmStreamer(MCStreamer &S,
200                            formatted_raw_ostream &OS,
201                            bool isVerboseAsm,
202                            MCInstPrinter &IP)
203       : HexagonTargetStreamer(S) {}
204 
prettyPrintAsm(MCInstPrinter & InstPrinter,uint64_t Address,const MCInst & Inst,const MCSubtargetInfo & STI,raw_ostream & OS)205   void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
206                       const MCInst &Inst, const MCSubtargetInfo &STI,
207                       raw_ostream &OS) override {
208     assert(HexagonMCInstrInfo::isBundle(Inst));
209     assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
210     std::string Buffer;
211     {
212       raw_string_ostream TempStream(Buffer);
213       InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
214     }
215     StringRef Contents(Buffer);
216     auto PacketBundle = Contents.rsplit('\n');
217     auto HeadTail = PacketBundle.first.split('\n');
218     StringRef Separator = "\n";
219     StringRef Indent = "\t";
220     OS << "\t{\n";
221     while (!HeadTail.first.empty()) {
222       StringRef InstTxt;
223       auto Duplex = HeadTail.first.split('\v');
224       if (!Duplex.second.empty()) {
225         OS << Indent << Duplex.first << Separator;
226         InstTxt = Duplex.second;
227       } else if (!HeadTail.first.trim().startswith("immext")) {
228         InstTxt = Duplex.first;
229       }
230       if (!InstTxt.empty())
231         OS << Indent << InstTxt << Separator;
232       HeadTail = HeadTail.second.split('\n');
233     }
234 
235     if (HexagonMCInstrInfo::isMemReorderDisabled(Inst))
236       OS << "\n\t} :mem_noshuf" << PacketBundle.second;
237     else
238       OS << "\t}" << PacketBundle.second;
239   }
240 };
241 
242 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
243 public:
getStreamer()244   MCELFStreamer &getStreamer() {
245     return static_cast<MCELFStreamer &>(Streamer);
246   }
HexagonTargetELFStreamer(MCStreamer & S,MCSubtargetInfo const & STI)247   HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
248       : HexagonTargetStreamer(S) {
249     MCAssembler &MCA = getStreamer().getAssembler();
250     MCA.setELFHeaderEFlags(Hexagon_MC::GetELFFlags(STI));
251   }
252 
253 
emitCommonSymbolSorted(MCSymbol * Symbol,uint64_t Size,unsigned ByteAlignment,unsigned AccessSize)254   void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
255                               unsigned ByteAlignment,
256                               unsigned AccessSize) override {
257     HexagonMCELFStreamer &HexagonELFStreamer =
258         static_cast<HexagonMCELFStreamer &>(getStreamer());
259     HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
260                                                  AccessSize);
261   }
262 
emitLocalCommonSymbolSorted(MCSymbol * Symbol,uint64_t Size,unsigned ByteAlignment,unsigned AccessSize)263   void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
264                                    unsigned ByteAlignment,
265                                    unsigned AccessSize) override {
266     HexagonMCELFStreamer &HexagonELFStreamer =
267         static_cast<HexagonMCELFStreamer &>(getStreamer());
268     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
269         Symbol, Size, ByteAlignment, AccessSize);
270   }
271 };
272 
273 } // end anonymous namespace
274 
createHexagonMCInstrInfo()275 llvm::MCInstrInfo *llvm::createHexagonMCInstrInfo() {
276   MCInstrInfo *X = new MCInstrInfo();
277   InitHexagonMCInstrInfo(X);
278   return X;
279 }
280 
281 static MCRegisterInfo *
createHexagonMCRegisterInfo(const Triple & TT,const MCTargetOptions & Options)282 createHexagonMCRegisterInfo(const Triple &TT, const MCTargetOptions &Options) {
283   MCRegisterInfo *X = new MCRegisterInfo();
284   InitHexagonMCRegisterInfo(X, Hexagon::R31);
285   return X;
286 }
287 
createHexagonMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT,const MCTargetOptions & Options)288 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
289                                          const Triple &TT,
290                                          const MCTargetOptions &Options) {
291   MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
292 
293   // VirtualFP = (R30 + #0).
294   MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
295       nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
296   MAI->addInitialFrameState(Inst);
297 
298   return MAI;
299 }
300 
createHexagonMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)301 static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
302                                                  unsigned SyntaxVariant,
303                                                  const MCAsmInfo &MAI,
304                                                  const MCInstrInfo &MII,
305                                                  const MCRegisterInfo &MRI)
306 {
307   if (SyntaxVariant == 0)
308     return new HexagonInstPrinter(MAI, MII, MRI);
309   else
310     return nullptr;
311 }
312 
createMCAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * IP,bool IsVerboseAsm)313 static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S,
314                                                    formatted_raw_ostream &OS,
315                                                    MCInstPrinter *IP,
316                                                    bool IsVerboseAsm) {
317   return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
318 }
319 
createMCStreamer(Triple const & T,MCContext & Context,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll)320 static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
321                                     std::unique_ptr<MCAsmBackend> &&MAB,
322                                     std::unique_ptr<MCObjectWriter> &&OW,
323                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
324                                     bool RelaxAll) {
325   return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
326                                   std::move(Emitter));
327 }
328 
329 static MCTargetStreamer *
createHexagonObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)330 createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
331   return new HexagonTargetELFStreamer(S, STI);
332 }
333 
clearFeature(MCSubtargetInfo * STI,uint64_t F)334 static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo* STI, uint64_t F) {
335   if (STI->getFeatureBits()[F])
336     STI->ToggleFeature(F);
337 }
338 
checkFeature(MCSubtargetInfo * STI,uint64_t F)339 static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F) {
340   return STI->getFeatureBits()[F];
341 }
342 
343 namespace {
selectHexagonFS(StringRef CPU,StringRef FS)344 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
345   SmallVector<StringRef, 3> Result;
346   if (!FS.empty())
347     Result.push_back(FS);
348 
349   switch (EnableHVX) {
350   case Hexagon::ArchEnum::V5:
351   case Hexagon::ArchEnum::V55:
352     break;
353   case Hexagon::ArchEnum::V60:
354     Result.push_back("+hvxv60");
355     break;
356   case Hexagon::ArchEnum::V62:
357     Result.push_back("+hvxv62");
358     break;
359   case Hexagon::ArchEnum::V65:
360     Result.push_back("+hvxv65");
361     break;
362   case Hexagon::ArchEnum::V66:
363     Result.push_back("+hvxv66");
364     break;
365   case Hexagon::ArchEnum::V67:
366     Result.push_back("+hvxv67");
367     break;
368   case Hexagon::ArchEnum::Generic:{
369     Result.push_back(StringSwitch<StringRef>(CPU)
370              .Case("hexagonv60", "+hvxv60")
371              .Case("hexagonv62", "+hvxv62")
372              .Case("hexagonv65", "+hvxv65")
373              .Case("hexagonv66", "+hvxv66")
374              .Case("hexagonv67", "+hvxv67")
375              .Case("hexagonv67t", "+hvxv67"));
376     break;
377   }
378   case Hexagon::ArchEnum::NoArch:
379     // Sentinel if -mhvx isn't specified
380     break;
381   }
382   return join(Result.begin(), Result.end(), ",");
383 }
384 }
385 
isCPUValid(const std::string & CPU)386 static bool isCPUValid(const std::string &CPU) {
387   return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend();
388 }
389 
390 namespace {
selectCPUAndFS(StringRef CPU,StringRef FS)391 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
392                                                    StringRef FS) {
393   std::pair<std::string, std::string> Result;
394   Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
395   Result.second = selectHexagonFS(Result.first, FS);
396   return Result;
397 }
398 std::mutex ArchSubtargetMutex;
399 std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
400     ArchSubtarget;
401 } // namespace
402 
403 MCSubtargetInfo const *
getArchSubtarget(MCSubtargetInfo const * STI)404 Hexagon_MC::getArchSubtarget(MCSubtargetInfo const *STI) {
405   std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
406   auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
407   if (Existing == ArchSubtarget.end())
408     return nullptr;
409   return Existing->second.get();
410 }
411 
completeHVXFeatures(const FeatureBitset & S)412 FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
413   using namespace Hexagon;
414   // Make sure that +hvx-length turns hvx on, and that "hvx" alone
415   // turns on hvxvNN, corresponding to the existing ArchVNN.
416   FeatureBitset FB = S;
417   unsigned CpuArch = ArchV5;
418   for (unsigned F : {ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, ArchV55,
419                      ArchV5}) {
420     if (!FB.test(F))
421       continue;
422     CpuArch = F;
423     break;
424   }
425   bool UseHvx = false;
426   for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
427     if (!FB.test(F))
428       continue;
429     UseHvx = true;
430     break;
431   }
432   bool HasHvxVer = false;
433   for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
434                      ExtensionHVXV66, ExtensionHVXV67}) {
435     if (!FB.test(F))
436       continue;
437     HasHvxVer = true;
438     UseHvx = true;
439     break;
440   }
441 
442   if (!UseHvx || HasHvxVer)
443     return FB;
444 
445   // HasHvxVer is false, and UseHvx is true.
446   switch (CpuArch) {
447     case ArchV67:
448       FB.set(ExtensionHVXV67);
449       LLVM_FALLTHROUGH;
450     case ArchV66:
451       FB.set(ExtensionHVXV66);
452       LLVM_FALLTHROUGH;
453     case ArchV65:
454       FB.set(ExtensionHVXV65);
455       LLVM_FALLTHROUGH;
456     case ArchV62:
457       FB.set(ExtensionHVXV62);
458       LLVM_FALLTHROUGH;
459     case ArchV60:
460       FB.set(ExtensionHVXV60);
461       break;
462   }
463   return FB;
464 }
465 
createHexagonMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)466 MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
467                                                           StringRef CPU,
468                                                           StringRef FS) {
469   std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
470   StringRef CPUName = Features.first;
471   StringRef ArchFS = Features.second;
472 
473   MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
474   if (X != nullptr && (CPUName == "hexagonv67t"))
475     addArchSubtarget(X, ArchFS);
476 
477   if (CPU.equals("help"))
478       exit(0);
479 
480   if (!isCPUValid(CPUName.str())) {
481     errs() << "error: invalid CPU \"" << CPUName.str().c_str()
482            << "\" specified\n";
483     return nullptr;
484   }
485 
486   if (HexagonDisableDuplex) {
487     llvm::FeatureBitset Features = X->getFeatureBits();
488     X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
489   }
490 
491   X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
492 
493   // The Z-buffer instructions are grandfathered in for current
494   // architectures but omitted for new ones.  Future instruction
495   // sets may introduce new/conflicting z-buffer instructions.
496   const bool ZRegOnDefault =
497       (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
498   if (ZRegOnDefault) {
499     llvm::FeatureBitset Features = X->getFeatureBits();
500     X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
501   }
502 
503   return X;
504 }
505 
addArchSubtarget(MCSubtargetInfo const * STI,StringRef FS)506 void Hexagon_MC::addArchSubtarget(MCSubtargetInfo const *STI,
507                                   StringRef FS) {
508   assert(STI != nullptr);
509   if (STI->getCPU().contains("t")) {
510     auto ArchSTI = createHexagonMCSubtargetInfo(
511         STI->getTargetTriple(),
512         STI->getCPU().substr(0, STI->getCPU().size() - 1), FS);
513     std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
514     ArchSubtarget[std::string(STI->getCPU())] =
515         std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
516   }
517 }
518 
GetELFFlags(const MCSubtargetInfo & STI)519 unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
520   static std::map<StringRef,unsigned> ElfFlags = {
521     {"hexagonv5",  ELF::EF_HEXAGON_MACH_V5},
522     {"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
523     {"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
524     {"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
525     {"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
526     {"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
527     {"hexagonv67", ELF::EF_HEXAGON_MACH_V67},
528     {"hexagonv67t", ELF::EF_HEXAGON_MACH_V67T},
529   };
530 
531   auto F = ElfFlags.find(STI.getCPU());
532   assert(F != ElfFlags.end() && "Unrecognized Architecture");
533   return F->second;
534 }
535 
GetVectRegRev()536 llvm::ArrayRef<MCPhysReg> Hexagon_MC::GetVectRegRev() {
537   return makeArrayRef(VectRegRev);
538 }
539 
540 namespace {
541 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
542 public:
HexagonMCInstrAnalysis(MCInstrInfo const * Info)543   HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
544 
isUnconditionalBranch(MCInst const & Inst) const545   bool isUnconditionalBranch(MCInst const &Inst) const override {
546     //assert(!HexagonMCInstrInfo::isBundle(Inst));
547     return MCInstrAnalysis::isUnconditionalBranch(Inst);
548   }
549 
isConditionalBranch(MCInst const & Inst) const550   bool isConditionalBranch(MCInst const &Inst) const override {
551     //assert(!HexagonMCInstrInfo::isBundle(Inst));
552     return MCInstrAnalysis::isConditionalBranch(Inst);
553   }
554 
evaluateBranch(MCInst const & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const555   bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
556                       uint64_t Size, uint64_t &Target) const override {
557     if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
558           isConditionalBranch(Inst)))
559       return false;
560 
561     //assert(!HexagonMCInstrInfo::isBundle(Inst));
562     if(!HexagonMCInstrInfo::isExtendable(*Info, Inst))
563       return false;
564     auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
565     assert(Extended.isExpr());
566     int64_t Value;
567     if(!Extended.getExpr()->evaluateAsAbsolute(Value))
568       return false;
569     Target = Value;
570     return true;
571   }
572 };
573 }
574 
createHexagonMCInstrAnalysis(const MCInstrInfo * Info)575 static MCInstrAnalysis *createHexagonMCInstrAnalysis(const MCInstrInfo *Info) {
576   return new HexagonMCInstrAnalysis(Info);
577 }
578 
579 // Force static initialization.
LLVMInitializeHexagonTargetMC()580 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC() {
581   // Register the MC asm info.
582   RegisterMCAsmInfoFn X(getTheHexagonTarget(), createHexagonMCAsmInfo);
583 
584   // Register the MC instruction info.
585   TargetRegistry::RegisterMCInstrInfo(getTheHexagonTarget(),
586                                       createHexagonMCInstrInfo);
587 
588   // Register the MC register info.
589   TargetRegistry::RegisterMCRegInfo(getTheHexagonTarget(),
590                                     createHexagonMCRegisterInfo);
591 
592   // Register the MC subtarget info.
593   TargetRegistry::RegisterMCSubtargetInfo(getTheHexagonTarget(),
594     Hexagon_MC::createHexagonMCSubtargetInfo);
595 
596   // Register the MC Code Emitter
597   TargetRegistry::RegisterMCCodeEmitter(getTheHexagonTarget(),
598                                         createHexagonMCCodeEmitter);
599 
600   // Register the asm backend
601   TargetRegistry::RegisterMCAsmBackend(getTheHexagonTarget(),
602                                        createHexagonAsmBackend);
603 
604 
605   // Register the MC instruction analyzer.
606   TargetRegistry::RegisterMCInstrAnalysis(getTheHexagonTarget(),
607                                           createHexagonMCInstrAnalysis);
608 
609   // Register the obj streamer
610   TargetRegistry::RegisterELFStreamer(getTheHexagonTarget(),
611                                       createMCStreamer);
612 
613   // Register the obj target streamer
614   TargetRegistry::RegisterObjectTargetStreamer(getTheHexagonTarget(),
615                                       createHexagonObjectTargetStreamer);
616 
617   // Register the asm streamer
618   TargetRegistry::RegisterAsmTargetStreamer(getTheHexagonTarget(),
619                                             createMCAsmTargetStreamer);
620 
621   // Register the MC Inst Printer
622   TargetRegistry::RegisterMCInstPrinter(getTheHexagonTarget(),
623                                         createHexagonMCInstPrinter);
624 }
625