1 //===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Subclass of MipsTargetLowering specialized for mips32/64. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 14 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 15 16 #include "MipsISelLowering.h" 17 #include "llvm/CodeGen/SelectionDAGNodes.h" 18 #include "llvm/Support/MachineValueType.h" 19 20 namespace llvm { 21 22 class MachineBasicBlock; 23 class MachineInstr; 24 class MipsSubtarget; 25 class MipsTargetMachine; 26 class SelectionDAG; 27 class TargetRegisterClass; 28 29 class MipsSETargetLowering : public MipsTargetLowering { 30 public: 31 explicit MipsSETargetLowering(const MipsTargetMachine &TM, 32 const MipsSubtarget &STI); 33 34 /// Enable MSA support for the given integer type and Register 35 /// class. 36 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 37 38 /// Enable MSA support for the given floating-point type and 39 /// Register class. 40 void addMSAFloatType(MVT::SimpleValueType Ty, 41 const TargetRegisterClass *RC); 42 43 bool allowsMisalignedMemoryAccesses( 44 EVT VT, unsigned AS = 0, unsigned Align = 1, 45 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 46 bool *Fast = nullptr) const override; 47 48 uint32_t getExceptionPointerAS() const override; 49 50 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 51 52 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 53 54 MachineBasicBlock * 55 EmitInstrWithCustomInserter(MachineInstr &MI, 56 MachineBasicBlock *MBB) const override; 57 isShuffleMaskLegal(ArrayRef<int> Mask,EVT VT)58 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override { 59 return false; 60 } 61 62 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 63 64 private: 65 bool isEligibleForTailCallOptimization( 66 const CCState &CCInfo, unsigned NextStackOffset, 67 const MipsFunctionInfo &FI) const override; 68 69 void 70 getOpndList(SmallVectorImpl<SDValue> &Ops, 71 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 72 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 73 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 74 SDValue Chain) const override; 75 76 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 77 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 78 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 79 80 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, 81 SelectionDAG &DAG) const; 82 83 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 84 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 85 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 86 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 87 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 88 /// Lower VECTOR_SHUFFLE into one of a number of instructions 89 /// depending on the indices in the shuffle. 90 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 91 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 92 93 MachineBasicBlock *emitBPOSGE32(MachineInstr &MI, 94 MachineBasicBlock *BB) const; 95 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI, 96 MachineBasicBlock *BB, 97 unsigned BranchOp) const; 98 /// Emit the COPY_FW pseudo instruction 99 MachineBasicBlock *emitCOPY_FW(MachineInstr &MI, 100 MachineBasicBlock *BB) const; 101 /// Emit the COPY_FD pseudo instruction 102 MachineBasicBlock *emitCOPY_FD(MachineInstr &MI, 103 MachineBasicBlock *BB) const; 104 /// Emit the INSERT_FW pseudo instruction 105 MachineBasicBlock *emitINSERT_FW(MachineInstr &MI, 106 MachineBasicBlock *BB) const; 107 /// Emit the INSERT_FD pseudo instruction 108 MachineBasicBlock *emitINSERT_FD(MachineInstr &MI, 109 MachineBasicBlock *BB) const; 110 /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction 111 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI, 112 MachineBasicBlock *BB, 113 unsigned EltSizeInBytes, 114 bool IsFP) const; 115 /// Emit the FILL_FW pseudo instruction 116 MachineBasicBlock *emitFILL_FW(MachineInstr &MI, 117 MachineBasicBlock *BB) const; 118 /// Emit the FILL_FD pseudo instruction 119 MachineBasicBlock *emitFILL_FD(MachineInstr &MI, 120 MachineBasicBlock *BB) const; 121 /// Emit the FEXP2_W_1 pseudo instructions. 122 MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI, 123 MachineBasicBlock *BB) const; 124 /// Emit the FEXP2_D_1 pseudo instructions. 125 MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI, 126 MachineBasicBlock *BB) const; 127 /// Emit the clwc1 pseudo instructions. 128 MachineBasicBlock *emitCapFloat32Load(MachineInstr &MI, 129 MachineBasicBlock *BB) const; 130 /// Emit the cldc1 pseudo instructions. 131 MachineBasicBlock *emitCapFloat64Load(MachineInstr &MI, 132 MachineBasicBlock *BB) const; 133 /// Emit the cswc1 pseudo instructions. 134 MachineBasicBlock *emitCapFloat32Store(MachineInstr &MI, 135 MachineBasicBlock *BB) const; 136 /// Emit the csdc1 pseudo instructions. 137 MachineBasicBlock *emitCapFloat64Store(MachineInstr &MI, 138 MachineBasicBlock *BB) const; 139 /// Expand a capability-select into a compare and branch 140 MachineBasicBlock *emitCapSelect(MachineInstr &MI, 141 MachineBasicBlock *BB) const; 142 /// Expand a capability equality into exact or inexact comparison 143 /// depending on the current mode. 144 MachineBasicBlock *emitCapEqual(MachineInstr &MI, 145 MachineBasicBlock *BB) const; 146 /// Expand a capability non-equality into exact or inexact 147 /// comparison depending on the current mode. 148 MachineBasicBlock *emitCapNotEqual(MachineInstr &MI, 149 MachineBasicBlock *BB) const; 150 151 /// Emit the FILL_FW pseudo instruction 152 MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI, 153 MachineBasicBlock *BB) const; 154 /// Emit the FILL_FD pseudo instruction 155 MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI, 156 MachineBasicBlock *BB) const; 157 /// Emit the FEXP2_W_1 pseudo instructions. 158 MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI, 159 MachineBasicBlock *BB, 160 bool IsFGR64) const; 161 /// Emit the FEXP2_D_1 pseudo instructions. 162 MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI, 163 MachineBasicBlock *BBi, 164 bool IsFGR64) const; 165 }; 166 167 } // end namespace llvm 168 169 #endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 170