1# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \
2# RUN:     | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s
3# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \
4# RUN:     | llvm-objdump -M no-aliases -d -r - \
5# RUN:     | FileCheck -check-prefix=CHECK-ASM-AND-OBJ %s
6
7# This file provides a basic sanity check for RV32E, checking that the expected
8# set of registers and instructions are accepted.
9
10# CHECK-ASM-AND-OBJ: lui zero, 1
11lui x0, 1
12# CHECK-ASM-AND-OBJ: auipc ra, 2
13auipc x1, 2
14
15# CHECK-ASM-AND-OBJ: jal sp, 4
16jal x2, 4
17# CHECK-ASM-AND-OBJ: jalr gp, 4(gp)
18jalr x3, x3, 4
19
20# CHECK-ASM-AND-OBJ: beq tp, t0, 8
21beq x4, x5, 8
22# CHECK-ASM-AND-OBJ: bne t1, t2, 12
23bne x6, x7, 12
24# CHECK-ASM-AND-OBJ: blt s0, s1, 16
25blt x8, x9, 16
26# CHECK-ASM-AND-OBJ: bge a0, a1, 20
27bge x10, x11, 20
28# CHECK-ASM-AND-OBJ: bgeu a2, a3, 24
29bgeu x12, x13, 24
30
31# CHECK-ASM-AND-OBJ: lb a4, 25(a5)
32lb x14, 25(x15)
33# CHECK-ASM-AND-OBJ: lh zero, 26(ra)
34lh zero, 26(ra)
35# CHECK-ASM-AND-OBJ: lw sp, 28(gp)
36lw sp, 28(gp)
37# CHECK-ASM-AND-OBJ: lbu tp, 29(t0)
38lbu tp, 29(t0)
39# CHECK-ASM-AND-OBJ: lhu t1, 30(t2)
40lhu t1, 30(t2)
41# CHECK-ASM-AND-OBJ: sb s0, 31(s1)
42sb s0, 31(s1)
43# CHECK-ASM-AND-OBJ: sh a0, 32(a1)
44sh a0, 32(a1)
45# CHECK-ASM-AND-OBJ: sw a2, 36(a3)
46sw a2, 36(a3)
47
48# CHECK-ASM-AND-OBJ: addi a4, a5, 37
49addi a4, a5, 37
50# CHECK-ASM-AND-OBJ: slti a0, a2, -20
51slti a0, a2, -20
52# CHECK-ASM-AND-OBJ: xori tp, t1, -99
53xori tp, t1, -99
54# CHECK-ASM-AND-OBJ: ori a0, a1, -2048
55ori a0, a1, -2048
56# CHECK-ASM-AND-OBJ: andi ra, sp, 2047
57andi ra, sp, 2047
58# CHECK-ASM-AND-OBJ: slli t1, t1, 31
59slli t1, t1, 31
60# CHECK-ASM-AND-OBJ: srli a0, a4, 0
61srli a0, a4, 0
62# CHECK-ASM-AND-OBJ: srai a1, sp, 15
63srai a1, sp, 15
64# CHECK-ASM-AND-OBJ: slli t0, t1, 13
65slli t0, t1, 13
66
67# CHECK-ASM-AND-OBJ: add ra, zero, zero
68add ra, zero, zero
69# CHECK-ASM-AND-OBJ: sub t0, t2, t1
70sub t0, t2, t1
71# CHECK-ASM-AND-OBJ: sll a5, a4, a3
72sll a5, a4, a3
73# CHECK-ASM-AND-OBJ: slt s0, s0, s0
74slt s0, s0, s0
75# CHECK-ASM-AND-OBJ: sltu gp, a0, a1
76sltu gp, a0, a1
77# CHECK-ASM-AND-OBJ: xor s1, s0, s1
78xor s1, s0, s1
79# CHECK-ASM-AND-OBJ: srl a0, s0, t0
80srl a0, s0, t0
81# CHECK-ASM-AND-OBJ: sra t0, a3, zero
82sra t0, a3, zero
83# CHECK-ASM-AND-OBJ: or a5, t1, ra
84or a5, t1, ra
85# CHECK-ASM-AND-OBJ: and a0, s1, a3
86and a0, s1, a3
87
88# CHECK-ASM-AND-OBJ: fence iorw, iorw
89fence iorw, iorw
90# CHECK-ASM-AND-OBJ: fence.tso
91fence.tso
92# CHECK-ASM-AND-OBJ: fence.i
93fence.i
94
95# CHECK-ASM-AND-OBJ: ecall
96ecall
97# CHECK-ASM-AND-OBJ: ebreak
98ebreak
99# CHECK-ASM-AND-OBJ: unimp
100unimp
101
102# CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
103csrrw t0, 0xfff, t1
104# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
105csrrs s0, 0xc00, x0
106# CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5
107csrrs s0, 0x001, a5
108# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
109csrrc sp, 0x000, ra
110# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
111csrrwi a5, 0x000, 0
112# CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
113csrrsi t2, 0xfff, 31
114# CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
115csrrci t1, 0x140, 5
116