1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
8
9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK6
12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK8
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10
19
20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12
23
24 // expected-no-diagnostics
25 #ifndef HEADER
26 #define HEADER
27
28 struct St {
29 int a, b;
StSt30 St() : a(0), b(0) {}
StSt31 St(const St &st) : a(st.a + st.b), b(0) {}
~StSt32 ~St() {}
33 };
34
35 volatile int g = 1212;
36 volatile int &g1 = g;
37
38 template <class T>
39 struct S {
40 T f;
SS41 S(T a) : f(a + g) {}
SS42 S() : f(g) {}
SS43 S(const S &s, St t = St()) : f(s.f + t.a) {}
operator TS44 operator T() { return T(); }
~SS45 ~S() {}
46 };
47
48
49 template <typename T>
tmain()50 T tmain() {
51 S<T> test;
52 T t_var = T();
53 T vec[] = {1, 2};
54 S<T> s_arr[] = {1, 2};
55 S<T> &var = test;
56 #pragma omp target
57 #pragma omp teams distribute simd private(t_var, vec, s_arr, var)
58 for (int i = 0; i < 2; ++i) {
59 vec[i] = t_var;
60 s_arr[i] = var;
61 }
62 return T();
63 }
64
65 S<float> test;
66 int t_var = 333;
67 int vec[] = {1, 2};
68 S<float> s_arr[] = {1, 2};
69 S<float> var(3);
70
main()71 int main() {
72 static int sivar;
73 #ifdef LAMBDA
74 [&]() {
75 #pragma omp target
76 #pragma omp teams distribute simd private(g, g1, sivar)
77 for (int i = 0; i < 2; ++i) {
78
79 // Skip global, bound tid and loop vars
80
81 g = 1;
82 g1 = 1;
83 sivar = 2;
84 [&]() {
85 g = 2;
86 g1 = 2;
87 sivar = 4;
88
89 }();
90 }
91 }();
92 return 0;
93 #else
94 #pragma omp target
95 #pragma omp teams distribute simd private(t_var, vec, s_arr, var, sivar)
96 for (int i = 0; i < 2; ++i) {
97 vec[i] = t_var;
98 s_arr[i] = var;
99 sivar += i;
100 }
101 return tmain<int>();
102 #endif
103 }
104
105
106
107 // Skip global, bound tid and loop vars
108
109 // private(s_arr)
110
111 // private(var)
112
113
114
115
116
117 // Skip global, bound tid and loop vars
118
119 // private(s_arr)
120
121
122 // private(var)
123
124
125 #endif
126 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
127 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
128 // CHECK1-NEXT: entry:
129 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
130 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
131 // CHECK1-NEXT: ret void
132 //
133 //
134 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
135 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
136 // CHECK1-NEXT: entry:
137 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
138 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
139 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
140 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
141 // CHECK1-NEXT: ret void
142 //
143 //
144 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
145 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
146 // CHECK1-NEXT: entry:
147 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
148 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
149 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
150 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
151 // CHECK1-NEXT: ret void
152 //
153 //
154 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
155 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
156 // CHECK1-NEXT: entry:
157 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
158 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
159 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
160 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
161 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
162 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
163 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4
164 // CHECK1-NEXT: ret void
165 //
166 //
167 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
168 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
169 // CHECK1-NEXT: entry:
170 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
171 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
172 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
173 // CHECK1-NEXT: ret void
174 //
175 //
176 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
177 // CHECK1-SAME: () #[[ATTR0]] {
178 // CHECK1-NEXT: entry:
179 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
180 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
181 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
182 // CHECK1-NEXT: ret void
183 //
184 //
185 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
186 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
187 // CHECK1-NEXT: entry:
188 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
189 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
190 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
191 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
192 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
193 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
194 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
195 // CHECK1-NEXT: ret void
196 //
197 //
198 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
199 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
200 // CHECK1-NEXT: entry:
201 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
202 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
203 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
204 // CHECK1: arraydestroy.body:
205 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
206 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
207 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
208 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
209 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
210 // CHECK1: arraydestroy.done1:
211 // CHECK1-NEXT: ret void
212 //
213 //
214 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
215 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
216 // CHECK1-NEXT: entry:
217 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
218 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
219 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
220 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4
221 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
222 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
223 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
224 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
225 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
226 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
227 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4
228 // CHECK1-NEXT: ret void
229 //
230 //
231 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
232 // CHECK1-SAME: () #[[ATTR0]] {
233 // CHECK1-NEXT: entry:
234 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
235 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
236 // CHECK1-NEXT: ret void
237 //
238 //
239 // CHECK1-LABEL: define {{[^@]+}}@main
240 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
241 // CHECK1-NEXT: entry:
242 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
243 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
244 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
245 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
246 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
247 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
248 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
249 // CHECK1: omp_offload.failed:
250 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
251 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
252 // CHECK1: omp_offload.cont:
253 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
254 // CHECK1-NEXT: ret i32 [[CALL]]
255 //
256 //
257 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
258 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
259 // CHECK1-NEXT: entry:
260 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
261 // CHECK1-NEXT: ret void
262 //
263 //
264 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
265 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
266 // CHECK1-NEXT: entry:
267 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
268 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
269 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
270 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
271 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
272 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
273 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
274 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
275 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
276 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
277 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
278 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
279 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
280 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
281 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
282 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
283 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
284 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
285 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
286 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
287 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
288 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
289 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
290 // CHECK1: arrayctor.loop:
291 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
292 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
293 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
294 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
295 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
296 // CHECK1: arrayctor.cont:
297 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
298 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
299 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
300 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
301 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
302 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
303 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
304 // CHECK1: cond.true:
305 // CHECK1-NEXT: br label [[COND_END:%.*]]
306 // CHECK1: cond.false:
307 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
308 // CHECK1-NEXT: br label [[COND_END]]
309 // CHECK1: cond.end:
310 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
311 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
312 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
313 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
314 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
315 // CHECK1: omp.inner.for.cond:
316 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
317 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
318 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
319 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
320 // CHECK1: omp.inner.for.cond.cleanup:
321 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
322 // CHECK1: omp.inner.for.body:
323 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
324 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
325 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
326 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
327 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
328 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
329 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
330 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
331 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
332 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4
333 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
334 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]]
335 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8*
336 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
337 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false)
338 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
339 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4
340 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
341 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4
342 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
343 // CHECK1: omp.body.continue:
344 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
345 // CHECK1: omp.inner.for.inc:
346 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
347 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
348 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
349 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
350 // CHECK1: omp.inner.for.end:
351 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
352 // CHECK1: omp.loop.exit:
353 // CHECK1-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
354 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
355 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
356 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
357 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
358 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
359 // CHECK1: .omp.final.then:
360 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
361 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
362 // CHECK1: .omp.final.done:
363 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
364 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
365 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2
366 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
367 // CHECK1: arraydestroy.body:
368 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
369 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
370 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
371 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
372 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
373 // CHECK1: arraydestroy.done7:
374 // CHECK1-NEXT: ret void
375 //
376 //
377 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
378 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
379 // CHECK1-NEXT: entry:
380 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
381 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
382 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
383 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
384 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
385 // CHECK1-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
386 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
387 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
388 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
389 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4
390 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
391 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
392 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
393 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
394 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
395 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
396 // CHECK1-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
397 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
398 // CHECK1-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
399 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
400 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
401 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
402 // CHECK1: omp_offload.failed:
403 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
404 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
405 // CHECK1: omp_offload.cont:
406 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
407 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
408 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
409 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
410 // CHECK1: arraydestroy.body:
411 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
412 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
413 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
414 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
415 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
416 // CHECK1: arraydestroy.done2:
417 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
418 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
419 // CHECK1-NEXT: ret i32 [[TMP4]]
420 //
421 //
422 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
423 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
424 // CHECK1-NEXT: entry:
425 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
426 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
427 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
428 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
429 // CHECK1-NEXT: ret void
430 //
431 //
432 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
433 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
434 // CHECK1-NEXT: entry:
435 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
436 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
437 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
438 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
439 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
440 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
441 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
442 // CHECK1-NEXT: ret void
443 //
444 //
445 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
446 // CHECK1-SAME: () #[[ATTR4]] {
447 // CHECK1-NEXT: entry:
448 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
449 // CHECK1-NEXT: ret void
450 //
451 //
452 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
453 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
454 // CHECK1-NEXT: entry:
455 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
456 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
457 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
458 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
459 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
460 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
461 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
462 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
463 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
464 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
465 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
466 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
467 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
468 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
469 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
470 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
471 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
472 // CHECK1-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
473 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
474 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
475 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
476 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
477 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
478 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
479 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
480 // CHECK1: arrayctor.loop:
481 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
482 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
483 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
484 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
485 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
486 // CHECK1: arrayctor.cont:
487 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
488 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
489 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
490 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
491 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
492 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
493 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
494 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
495 // CHECK1: cond.true:
496 // CHECK1-NEXT: br label [[COND_END:%.*]]
497 // CHECK1: cond.false:
498 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
499 // CHECK1-NEXT: br label [[COND_END]]
500 // CHECK1: cond.end:
501 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
502 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
503 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
504 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
505 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
506 // CHECK1: omp.inner.for.cond:
507 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
508 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
509 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
510 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
511 // CHECK1: omp.inner.for.cond.cleanup:
512 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
513 // CHECK1: omp.inner.for.body:
514 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
515 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
516 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
517 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
518 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
519 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
520 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
521 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
522 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
523 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8
524 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
525 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
526 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
527 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8*
528 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
529 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false)
530 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
531 // CHECK1: omp.body.continue:
532 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
533 // CHECK1: omp.inner.for.inc:
534 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
535 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
536 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
537 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
538 // CHECK1: omp.inner.for.end:
539 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
540 // CHECK1: omp.loop.exit:
541 // CHECK1-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
542 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
543 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
544 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
545 // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
546 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
547 // CHECK1: .omp.final.then:
548 // CHECK1-NEXT: store i32 2, i32* [[I]], align 4
549 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
550 // CHECK1: .omp.final.done:
551 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
552 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
553 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2
554 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
555 // CHECK1: arraydestroy.body:
556 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
557 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
558 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
559 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
560 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
561 // CHECK1: arraydestroy.done8:
562 // CHECK1-NEXT: ret void
563 //
564 //
565 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
566 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
567 // CHECK1-NEXT: entry:
568 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
569 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
570 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
571 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
572 // CHECK1-NEXT: ret void
573 //
574 //
575 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
576 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
577 // CHECK1-NEXT: entry:
578 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
579 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
580 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
581 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
582 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
583 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
584 // CHECK1-NEXT: ret void
585 //
586 //
587 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
588 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
589 // CHECK1-NEXT: entry:
590 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
591 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
592 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
593 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
594 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
595 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
596 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
597 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
598 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
599 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
600 // CHECK1-NEXT: ret void
601 //
602 //
603 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
604 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
605 // CHECK1-NEXT: entry:
606 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
607 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
608 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
609 // CHECK1-NEXT: ret void
610 //
611 //
612 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
613 // CHECK1-SAME: () #[[ATTR0]] {
614 // CHECK1-NEXT: entry:
615 // CHECK1-NEXT: call void @__cxx_global_var_init()
616 // CHECK1-NEXT: call void @__cxx_global_var_init.1()
617 // CHECK1-NEXT: call void @__cxx_global_var_init.2()
618 // CHECK1-NEXT: ret void
619 //
620 //
621 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
622 // CHECK1-SAME: () #[[ATTR0]] {
623 // CHECK1-NEXT: entry:
624 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
625 // CHECK1-NEXT: ret void
626 //
627 //
628 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
629 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
630 // CHECK2-NEXT: entry:
631 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
632 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
633 // CHECK2-NEXT: ret void
634 //
635 //
636 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
637 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
638 // CHECK2-NEXT: entry:
639 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
640 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
641 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
642 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
643 // CHECK2-NEXT: ret void
644 //
645 //
646 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
647 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
648 // CHECK2-NEXT: entry:
649 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
650 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
651 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
652 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
653 // CHECK2-NEXT: ret void
654 //
655 //
656 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
657 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
658 // CHECK2-NEXT: entry:
659 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
660 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
661 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
662 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
663 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
664 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
665 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4
666 // CHECK2-NEXT: ret void
667 //
668 //
669 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
670 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
671 // CHECK2-NEXT: entry:
672 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
673 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
674 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
675 // CHECK2-NEXT: ret void
676 //
677 //
678 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
679 // CHECK2-SAME: () #[[ATTR0]] {
680 // CHECK2-NEXT: entry:
681 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
682 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
683 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
684 // CHECK2-NEXT: ret void
685 //
686 //
687 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
688 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
689 // CHECK2-NEXT: entry:
690 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
691 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
692 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
693 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
694 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
695 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
696 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
697 // CHECK2-NEXT: ret void
698 //
699 //
700 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
701 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
702 // CHECK2-NEXT: entry:
703 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
704 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
705 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
706 // CHECK2: arraydestroy.body:
707 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
708 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
709 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
710 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
711 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
712 // CHECK2: arraydestroy.done1:
713 // CHECK2-NEXT: ret void
714 //
715 //
716 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
717 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
718 // CHECK2-NEXT: entry:
719 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
720 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
721 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
722 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4
723 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
724 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
725 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
726 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
727 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
728 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
729 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4
730 // CHECK2-NEXT: ret void
731 //
732 //
733 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
734 // CHECK2-SAME: () #[[ATTR0]] {
735 // CHECK2-NEXT: entry:
736 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
737 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
738 // CHECK2-NEXT: ret void
739 //
740 //
741 // CHECK2-LABEL: define {{[^@]+}}@main
742 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
743 // CHECK2-NEXT: entry:
744 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
745 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
746 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
747 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
748 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
749 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
750 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
751 // CHECK2: omp_offload.failed:
752 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
753 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
754 // CHECK2: omp_offload.cont:
755 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
756 // CHECK2-NEXT: ret i32 [[CALL]]
757 //
758 //
759 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
760 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] {
761 // CHECK2-NEXT: entry:
762 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
763 // CHECK2-NEXT: ret void
764 //
765 //
766 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
767 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
768 // CHECK2-NEXT: entry:
769 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
770 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
771 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
772 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
773 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
774 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
775 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
776 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
777 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
778 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
779 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
780 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
781 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
782 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
783 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
784 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
785 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
786 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
787 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
788 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
789 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
790 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
791 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
792 // CHECK2: arrayctor.loop:
793 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
794 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
795 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
796 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
797 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
798 // CHECK2: arrayctor.cont:
799 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
800 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
801 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
802 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
803 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
804 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
805 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
806 // CHECK2: cond.true:
807 // CHECK2-NEXT: br label [[COND_END:%.*]]
808 // CHECK2: cond.false:
809 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
810 // CHECK2-NEXT: br label [[COND_END]]
811 // CHECK2: cond.end:
812 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
813 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
814 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
815 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
816 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
817 // CHECK2: omp.inner.for.cond:
818 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
819 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
820 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
821 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
822 // CHECK2: omp.inner.for.cond.cleanup:
823 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
824 // CHECK2: omp.inner.for.body:
825 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
826 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
827 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
828 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
829 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
830 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
831 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
832 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
833 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
834 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4
835 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
836 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM2]]
837 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8*
838 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
839 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false)
840 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
841 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4
842 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
843 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[SIVAR]], align 4
844 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
845 // CHECK2: omp.body.continue:
846 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
847 // CHECK2: omp.inner.for.inc:
848 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
849 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
850 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
851 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
852 // CHECK2: omp.inner.for.end:
853 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
854 // CHECK2: omp.loop.exit:
855 // CHECK2-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
856 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
857 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
858 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
859 // CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
860 // CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
861 // CHECK2: .omp.final.then:
862 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
863 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
864 // CHECK2: .omp.final.done:
865 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
866 // CHECK2-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
867 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN6]], i64 2
868 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
869 // CHECK2: arraydestroy.body:
870 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
871 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
872 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
873 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
874 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
875 // CHECK2: arraydestroy.done7:
876 // CHECK2-NEXT: ret void
877 //
878 //
879 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
880 // CHECK2-SAME: () #[[ATTR6:[0-9]+]] comdat {
881 // CHECK2-NEXT: entry:
882 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
883 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
884 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
885 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
886 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
887 // CHECK2-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
888 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
889 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
890 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
891 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4
892 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
893 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
894 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
895 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
896 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
897 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
898 // CHECK2-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
899 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
900 // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
901 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
902 // CHECK2-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
903 // CHECK2-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
904 // CHECK2: omp_offload.failed:
905 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
906 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
907 // CHECK2: omp_offload.cont:
908 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
909 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
910 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
911 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
912 // CHECK2: arraydestroy.body:
913 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
914 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
915 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
916 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
917 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
918 // CHECK2: arraydestroy.done2:
919 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
920 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
921 // CHECK2-NEXT: ret i32 [[TMP4]]
922 //
923 //
924 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
925 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
926 // CHECK2-NEXT: entry:
927 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
928 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
929 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
930 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
931 // CHECK2-NEXT: ret void
932 //
933 //
934 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
935 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
936 // CHECK2-NEXT: entry:
937 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
938 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
939 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
940 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
941 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
942 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
943 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
944 // CHECK2-NEXT: ret void
945 //
946 //
947 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
948 // CHECK2-SAME: () #[[ATTR4]] {
949 // CHECK2-NEXT: entry:
950 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
951 // CHECK2-NEXT: ret void
952 //
953 //
954 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
955 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
956 // CHECK2-NEXT: entry:
957 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
958 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
959 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
960 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
961 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
962 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
963 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
964 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
965 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
966 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
967 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
968 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
969 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
970 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 8
971 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
972 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
973 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
974 // CHECK2-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
975 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
976 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
977 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
978 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
979 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
980 // CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
981 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
982 // CHECK2: arrayctor.loop:
983 // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
984 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
985 // CHECK2-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
986 // CHECK2-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
987 // CHECK2-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
988 // CHECK2: arrayctor.cont:
989 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
990 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 8
991 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
992 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
993 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
994 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
995 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
996 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
997 // CHECK2: cond.true:
998 // CHECK2-NEXT: br label [[COND_END:%.*]]
999 // CHECK2: cond.false:
1000 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1001 // CHECK2-NEXT: br label [[COND_END]]
1002 // CHECK2: cond.end:
1003 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1004 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1005 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1006 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1007 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1008 // CHECK2: omp.inner.for.cond:
1009 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1010 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1011 // CHECK2-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1012 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1013 // CHECK2: omp.inner.for.cond.cleanup:
1014 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1015 // CHECK2: omp.inner.for.body:
1016 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1017 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1018 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1019 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1020 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
1021 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
1022 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
1023 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
1024 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
1025 // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 8
1026 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1027 // CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
1028 // CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 [[IDXPROM4]]
1029 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5]] to i8*
1030 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
1031 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 4, i1 false)
1032 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1033 // CHECK2: omp.body.continue:
1034 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1035 // CHECK2: omp.inner.for.inc:
1036 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1037 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1
1038 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4
1039 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1040 // CHECK2: omp.inner.for.end:
1041 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1042 // CHECK2: omp.loop.exit:
1043 // CHECK2-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1044 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
1045 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
1046 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1047 // CHECK2-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1048 // CHECK2-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1049 // CHECK2: .omp.final.then:
1050 // CHECK2-NEXT: store i32 2, i32* [[I]], align 4
1051 // CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
1052 // CHECK2: .omp.final.done:
1053 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1054 // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1055 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN7]], i64 2
1056 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1057 // CHECK2: arraydestroy.body:
1058 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1059 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1060 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1061 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1062 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1063 // CHECK2: arraydestroy.done8:
1064 // CHECK2-NEXT: ret void
1065 //
1066 //
1067 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1068 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1069 // CHECK2-NEXT: entry:
1070 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1071 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1072 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1073 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1074 // CHECK2-NEXT: ret void
1075 //
1076 //
1077 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1078 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1079 // CHECK2-NEXT: entry:
1080 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1081 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1082 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1083 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1084 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1085 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1086 // CHECK2-NEXT: ret void
1087 //
1088 //
1089 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1090 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1091 // CHECK2-NEXT: entry:
1092 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1093 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1094 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1095 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1096 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1097 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1098 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1099 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1100 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1101 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1102 // CHECK2-NEXT: ret void
1103 //
1104 //
1105 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1106 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1107 // CHECK2-NEXT: entry:
1108 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1109 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1110 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1111 // CHECK2-NEXT: ret void
1112 //
1113 //
1114 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
1115 // CHECK2-SAME: () #[[ATTR0]] {
1116 // CHECK2-NEXT: entry:
1117 // CHECK2-NEXT: call void @__cxx_global_var_init()
1118 // CHECK2-NEXT: call void @__cxx_global_var_init.1()
1119 // CHECK2-NEXT: call void @__cxx_global_var_init.2()
1120 // CHECK2-NEXT: ret void
1121 //
1122 //
1123 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1124 // CHECK2-SAME: () #[[ATTR0]] {
1125 // CHECK2-NEXT: entry:
1126 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
1127 // CHECK2-NEXT: ret void
1128 //
1129 //
1130 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1131 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1132 // CHECK3-NEXT: entry:
1133 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1134 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1135 // CHECK3-NEXT: ret void
1136 //
1137 //
1138 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1139 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1140 // CHECK3-NEXT: entry:
1141 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1142 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1143 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1144 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1145 // CHECK3-NEXT: ret void
1146 //
1147 //
1148 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1149 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1150 // CHECK3-NEXT: entry:
1151 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1152 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1153 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1154 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1155 // CHECK3-NEXT: ret void
1156 //
1157 //
1158 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1159 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1160 // CHECK3-NEXT: entry:
1161 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1162 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1163 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1164 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1165 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1166 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1167 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4
1168 // CHECK3-NEXT: ret void
1169 //
1170 //
1171 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1172 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1173 // CHECK3-NEXT: entry:
1174 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1175 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1176 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1177 // CHECK3-NEXT: ret void
1178 //
1179 //
1180 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1181 // CHECK3-SAME: () #[[ATTR0]] {
1182 // CHECK3-NEXT: entry:
1183 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
1184 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
1185 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1186 // CHECK3-NEXT: ret void
1187 //
1188 //
1189 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1190 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1191 // CHECK3-NEXT: entry:
1192 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1193 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1194 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1195 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1196 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1197 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1198 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1199 // CHECK3-NEXT: ret void
1200 //
1201 //
1202 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1203 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1204 // CHECK3-NEXT: entry:
1205 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1206 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1207 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1208 // CHECK3: arraydestroy.body:
1209 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1210 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1211 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1212 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1213 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1214 // CHECK3: arraydestroy.done1:
1215 // CHECK3-NEXT: ret void
1216 //
1217 //
1218 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1219 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1220 // CHECK3-NEXT: entry:
1221 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1222 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1223 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1224 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1225 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1226 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1227 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1228 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1229 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1230 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1231 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4
1232 // CHECK3-NEXT: ret void
1233 //
1234 //
1235 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1236 // CHECK3-SAME: () #[[ATTR0]] {
1237 // CHECK3-NEXT: entry:
1238 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1239 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1240 // CHECK3-NEXT: ret void
1241 //
1242 //
1243 // CHECK3-LABEL: define {{[^@]+}}@main
1244 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1245 // CHECK3-NEXT: entry:
1246 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1247 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1248 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1249 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
1250 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
1251 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
1252 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1253 // CHECK3: omp_offload.failed:
1254 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
1255 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1256 // CHECK3: omp_offload.cont:
1257 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1258 // CHECK3-NEXT: ret i32 [[CALL]]
1259 //
1260 //
1261 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
1262 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
1263 // CHECK3-NEXT: entry:
1264 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1265 // CHECK3-NEXT: ret void
1266 //
1267 //
1268 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1269 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1270 // CHECK3-NEXT: entry:
1271 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1272 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1273 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1274 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1275 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1276 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1277 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1278 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1279 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1280 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1281 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1282 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1283 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1284 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1285 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1286 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1287 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1288 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1289 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1290 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1291 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1292 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1293 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1294 // CHECK3: arrayctor.loop:
1295 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1296 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1297 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1298 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1299 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1300 // CHECK3: arrayctor.cont:
1301 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1302 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1303 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1304 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1305 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1306 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1307 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1308 // CHECK3: cond.true:
1309 // CHECK3-NEXT: br label [[COND_END:%.*]]
1310 // CHECK3: cond.false:
1311 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1312 // CHECK3-NEXT: br label [[COND_END]]
1313 // CHECK3: cond.end:
1314 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1315 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1316 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1317 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1318 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1319 // CHECK3: omp.inner.for.cond:
1320 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1321 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1322 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1323 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1324 // CHECK3: omp.inner.for.cond.cleanup:
1325 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1326 // CHECK3: omp.inner.for.body:
1327 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1328 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1329 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1330 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1331 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
1332 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
1333 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1334 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
1335 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4
1336 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]]
1337 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1338 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1339 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false)
1340 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
1341 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4
1342 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
1343 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4
1344 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1345 // CHECK3: omp.body.continue:
1346 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1347 // CHECK3: omp.inner.for.inc:
1348 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1349 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
1350 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
1351 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
1352 // CHECK3: omp.inner.for.end:
1353 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1354 // CHECK3: omp.loop.exit:
1355 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1356 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
1357 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
1358 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1359 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1360 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1361 // CHECK3: .omp.final.then:
1362 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1363 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1364 // CHECK3: .omp.final.done:
1365 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1366 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1367 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
1368 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1369 // CHECK3: arraydestroy.body:
1370 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1371 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1372 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1373 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1374 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1375 // CHECK3: arraydestroy.done6:
1376 // CHECK3-NEXT: ret void
1377 //
1378 //
1379 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1380 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
1381 // CHECK3-NEXT: entry:
1382 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1383 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1384 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1385 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1386 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1387 // CHECK3-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1388 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1389 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1390 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1391 // CHECK3-NEXT: store i32 0, i32* [[T_VAR]], align 4
1392 // CHECK3-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1393 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1394 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1395 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
1396 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1397 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1398 // CHECK3-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1399 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1400 // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
1401 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
1402 // CHECK3-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
1403 // CHECK3-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1404 // CHECK3: omp_offload.failed:
1405 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1406 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
1407 // CHECK3: omp_offload.cont:
1408 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4
1409 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1410 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1411 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1412 // CHECK3: arraydestroy.body:
1413 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1414 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1415 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1416 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1417 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1418 // CHECK3: arraydestroy.done2:
1419 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1420 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
1421 // CHECK3-NEXT: ret i32 [[TMP4]]
1422 //
1423 //
1424 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1425 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1426 // CHECK3-NEXT: entry:
1427 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1428 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1429 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1430 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1431 // CHECK3-NEXT: ret void
1432 //
1433 //
1434 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1435 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1436 // CHECK3-NEXT: entry:
1437 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1438 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1439 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1440 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1441 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1442 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1443 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1444 // CHECK3-NEXT: ret void
1445 //
1446 //
1447 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1448 // CHECK3-SAME: () #[[ATTR4]] {
1449 // CHECK3-NEXT: entry:
1450 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
1451 // CHECK3-NEXT: ret void
1452 //
1453 //
1454 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
1455 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1456 // CHECK3-NEXT: entry:
1457 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1458 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1459 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1460 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
1461 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1462 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1463 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1464 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1465 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1466 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1467 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1468 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1469 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1470 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1471 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
1472 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1473 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1474 // CHECK3-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1475 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1476 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1477 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1478 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1479 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1480 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1481 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1482 // CHECK3: arrayctor.loop:
1483 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1484 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1485 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1486 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1487 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1488 // CHECK3: arrayctor.cont:
1489 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1490 // CHECK3-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1491 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1492 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1493 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1494 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1495 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1496 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1497 // CHECK3: cond.true:
1498 // CHECK3-NEXT: br label [[COND_END:%.*]]
1499 // CHECK3: cond.false:
1500 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1501 // CHECK3-NEXT: br label [[COND_END]]
1502 // CHECK3: cond.end:
1503 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1504 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1505 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1506 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1507 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1508 // CHECK3: omp.inner.for.cond:
1509 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1510 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1511 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1512 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1513 // CHECK3: omp.inner.for.cond.cleanup:
1514 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1515 // CHECK3: omp.inner.for.body:
1516 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1517 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1518 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1519 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1520 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
1521 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
1522 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1523 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
1524 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4
1525 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
1526 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
1527 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
1528 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
1529 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false)
1530 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1531 // CHECK3: omp.body.continue:
1532 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1533 // CHECK3: omp.inner.for.inc:
1534 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1535 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1536 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
1537 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
1538 // CHECK3: omp.inner.for.end:
1539 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1540 // CHECK3: omp.loop.exit:
1541 // CHECK3-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1542 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
1543 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
1544 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1545 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1546 // CHECK3-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1547 // CHECK3: .omp.final.then:
1548 // CHECK3-NEXT: store i32 2, i32* [[I]], align 4
1549 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
1550 // CHECK3: .omp.final.done:
1551 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1552 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1553 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
1554 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1555 // CHECK3: arraydestroy.body:
1556 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1557 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1558 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1559 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1560 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1561 // CHECK3: arraydestroy.done7:
1562 // CHECK3-NEXT: ret void
1563 //
1564 //
1565 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1566 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1567 // CHECK3-NEXT: entry:
1568 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1569 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1570 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1571 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1572 // CHECK3-NEXT: ret void
1573 //
1574 //
1575 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1576 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1577 // CHECK3-NEXT: entry:
1578 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1579 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1580 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1581 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1582 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1583 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
1584 // CHECK3-NEXT: ret void
1585 //
1586 //
1587 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1588 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1589 // CHECK3-NEXT: entry:
1590 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1591 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1592 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1593 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1594 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1595 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1596 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1597 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1598 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1599 // CHECK3-NEXT: store i32 [[ADD]], i32* [[F]], align 4
1600 // CHECK3-NEXT: ret void
1601 //
1602 //
1603 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1604 // CHECK3-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1605 // CHECK3-NEXT: entry:
1606 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1607 // CHECK3-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1608 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1609 // CHECK3-NEXT: ret void
1610 //
1611 //
1612 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
1613 // CHECK3-SAME: () #[[ATTR0]] {
1614 // CHECK3-NEXT: entry:
1615 // CHECK3-NEXT: call void @__cxx_global_var_init()
1616 // CHECK3-NEXT: call void @__cxx_global_var_init.1()
1617 // CHECK3-NEXT: call void @__cxx_global_var_init.2()
1618 // CHECK3-NEXT: ret void
1619 //
1620 //
1621 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1622 // CHECK3-SAME: () #[[ATTR0]] {
1623 // CHECK3-NEXT: entry:
1624 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
1625 // CHECK3-NEXT: ret void
1626 //
1627 //
1628 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init
1629 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
1630 // CHECK4-NEXT: entry:
1631 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
1632 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
1633 // CHECK4-NEXT: ret void
1634 //
1635 //
1636 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1637 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1638 // CHECK4-NEXT: entry:
1639 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1640 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1641 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1642 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1643 // CHECK4-NEXT: ret void
1644 //
1645 //
1646 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1647 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1648 // CHECK4-NEXT: entry:
1649 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1650 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1651 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1652 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1653 // CHECK4-NEXT: ret void
1654 //
1655 //
1656 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1657 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1658 // CHECK4-NEXT: entry:
1659 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1660 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1661 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1662 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1663 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
1664 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1665 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4
1666 // CHECK4-NEXT: ret void
1667 //
1668 //
1669 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1670 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1671 // CHECK4-NEXT: entry:
1672 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1673 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1674 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1675 // CHECK4-NEXT: ret void
1676 //
1677 //
1678 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1679 // CHECK4-SAME: () #[[ATTR0]] {
1680 // CHECK4-NEXT: entry:
1681 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
1682 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
1683 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
1684 // CHECK4-NEXT: ret void
1685 //
1686 //
1687 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1688 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1689 // CHECK4-NEXT: entry:
1690 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1691 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1692 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1693 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1694 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1695 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1696 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1697 // CHECK4-NEXT: ret void
1698 //
1699 //
1700 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1701 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
1702 // CHECK4-NEXT: entry:
1703 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
1704 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
1705 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1706 // CHECK4: arraydestroy.body:
1707 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1708 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1709 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1710 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
1711 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1712 // CHECK4: arraydestroy.done1:
1713 // CHECK4-NEXT: ret void
1714 //
1715 //
1716 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1717 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1718 // CHECK4-NEXT: entry:
1719 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
1720 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1721 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
1722 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4
1723 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
1724 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1725 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1726 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
1727 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1728 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1729 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4
1730 // CHECK4-NEXT: ret void
1731 //
1732 //
1733 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1734 // CHECK4-SAME: () #[[ATTR0]] {
1735 // CHECK4-NEXT: entry:
1736 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
1737 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
1738 // CHECK4-NEXT: ret void
1739 //
1740 //
1741 // CHECK4-LABEL: define {{[^@]+}}@main
1742 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
1743 // CHECK4-NEXT: entry:
1744 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1745 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1746 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
1747 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2)
1748 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
1749 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0
1750 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1751 // CHECK4: omp_offload.failed:
1752 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]]
1753 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
1754 // CHECK4: omp_offload.cont:
1755 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
1756 // CHECK4-NEXT: ret i32 [[CALL]]
1757 //
1758 //
1759 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94
1760 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] {
1761 // CHECK4-NEXT: entry:
1762 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1763 // CHECK4-NEXT: ret void
1764 //
1765 //
1766 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
1767 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1768 // CHECK4-NEXT: entry:
1769 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1770 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1771 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1772 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1773 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1774 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1775 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1776 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1777 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1778 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1779 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1780 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1781 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
1782 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
1783 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1784 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1785 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1786 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1787 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1788 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1789 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1790 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
1791 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1792 // CHECK4: arrayctor.loop:
1793 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1794 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1795 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
1796 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1797 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1798 // CHECK4: arrayctor.cont:
1799 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
1800 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1801 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1802 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1803 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1804 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1805 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1806 // CHECK4: cond.true:
1807 // CHECK4-NEXT: br label [[COND_END:%.*]]
1808 // CHECK4: cond.false:
1809 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1810 // CHECK4-NEXT: br label [[COND_END]]
1811 // CHECK4: cond.end:
1812 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1813 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1814 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1815 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1816 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1817 // CHECK4: omp.inner.for.cond:
1818 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1819 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1820 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1821 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1822 // CHECK4: omp.inner.for.cond.cleanup:
1823 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1824 // CHECK4: omp.inner.for.body:
1825 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1826 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1827 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1828 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
1829 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
1830 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
1831 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
1832 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
1833 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4
1834 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP10]]
1835 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
1836 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[VAR]] to i8*
1837 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false)
1838 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
1839 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[SIVAR]], align 4
1840 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
1841 // CHECK4-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4
1842 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1843 // CHECK4: omp.body.continue:
1844 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1845 // CHECK4: omp.inner.for.inc:
1846 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1847 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
1848 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
1849 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
1850 // CHECK4: omp.inner.for.end:
1851 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1852 // CHECK4: omp.loop.exit:
1853 // CHECK4-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1854 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
1855 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP17]])
1856 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
1857 // CHECK4-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1858 // CHECK4-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1859 // CHECK4: .omp.final.then:
1860 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
1861 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
1862 // CHECK4: .omp.final.done:
1863 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1864 // CHECK4-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
1865 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i32 2
1866 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1867 // CHECK4: arraydestroy.body:
1868 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1869 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1870 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1871 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1872 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1873 // CHECK4: arraydestroy.done6:
1874 // CHECK4-NEXT: ret void
1875 //
1876 //
1877 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1878 // CHECK4-SAME: () #[[ATTR6:[0-9]+]] comdat {
1879 // CHECK4-NEXT: entry:
1880 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1881 // CHECK4-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1882 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1883 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1884 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1885 // CHECK4-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
1886 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1887 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1888 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1889 // CHECK4-NEXT: store i32 0, i32* [[T_VAR]], align 4
1890 // CHECK4-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
1891 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
1892 // CHECK4-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1893 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
1894 // CHECK4-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
1895 // CHECK4-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1896 // CHECK4-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
1897 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1898 // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2)
1899 // CHECK4-NEXT: [[TMP1:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 0, i32 1)
1900 // CHECK4-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
1901 // CHECK4-NEXT: br i1 [[TMP2]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1902 // CHECK4: omp_offload.failed:
1903 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1904 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
1905 // CHECK4: omp_offload.cont:
1906 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4
1907 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1908 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1909 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1910 // CHECK4: arraydestroy.body:
1911 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1912 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1913 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1914 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1915 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1916 // CHECK4: arraydestroy.done2:
1917 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1918 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
1919 // CHECK4-NEXT: ret i32 [[TMP4]]
1920 //
1921 //
1922 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1923 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1924 // CHECK4-NEXT: entry:
1925 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1926 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1927 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1928 // CHECK4-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1929 // CHECK4-NEXT: ret void
1930 //
1931 //
1932 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1933 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1934 // CHECK4-NEXT: entry:
1935 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
1936 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1937 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
1938 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
1939 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
1940 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1941 // CHECK4-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1942 // CHECK4-NEXT: ret void
1943 //
1944 //
1945 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1946 // CHECK4-SAME: () #[[ATTR4]] {
1947 // CHECK4-NEXT: entry:
1948 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
1949 // CHECK4-NEXT: ret void
1950 //
1951 //
1952 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
1953 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1954 // CHECK4-NEXT: entry:
1955 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1956 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1957 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1958 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
1959 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
1960 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1961 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1962 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1963 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1964 // CHECK4-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1965 // CHECK4-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1966 // CHECK4-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1967 // CHECK4-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1968 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca %struct.S.0*, align 4
1969 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
1970 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1971 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1972 // CHECK4-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
1973 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1974 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
1975 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1976 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1977 // CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
1978 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
1979 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1980 // CHECK4: arrayctor.loop:
1981 // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1982 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1983 // CHECK4-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
1984 // CHECK4-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1985 // CHECK4-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1986 // CHECK4: arrayctor.cont:
1987 // CHECK4-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]])
1988 // CHECK4-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[_TMP2]], align 4
1989 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
1990 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1991 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1992 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1993 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1994 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1995 // CHECK4: cond.true:
1996 // CHECK4-NEXT: br label [[COND_END:%.*]]
1997 // CHECK4: cond.false:
1998 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1999 // CHECK4-NEXT: br label [[COND_END]]
2000 // CHECK4: cond.end:
2001 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2002 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
2003 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2004 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
2005 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2006 // CHECK4: omp.inner.for.cond:
2007 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2008 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
2009 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2010 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2011 // CHECK4: omp.inner.for.cond.cleanup:
2012 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2013 // CHECK4: omp.inner.for.body:
2014 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2015 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2016 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2017 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
2018 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[T_VAR]], align 4
2019 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4
2020 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP9]]
2021 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[ARRAYIDX]], align 4
2022 // CHECK4-NEXT: [[TMP10:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP2]], align 4
2023 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4
2024 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 [[TMP11]]
2025 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8*
2026 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[TMP10]] to i8*
2027 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 4, i1 false)
2028 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2029 // CHECK4: omp.body.continue:
2030 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2031 // CHECK4: omp.inner.for.inc:
2032 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
2033 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
2034 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4
2035 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2036 // CHECK4: omp.inner.for.end:
2037 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2038 // CHECK4: omp.loop.exit:
2039 // CHECK4-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2040 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4
2041 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]])
2042 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
2043 // CHECK4-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
2044 // CHECK4-NEXT: br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2045 // CHECK4: .omp.final.then:
2046 // CHECK4-NEXT: store i32 2, i32* [[I]], align 4
2047 // CHECK4-NEXT: br label [[DOTOMP_FINAL_DONE]]
2048 // CHECK4: .omp.final.done:
2049 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2050 // CHECK4-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2051 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN6]], i32 2
2052 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2053 // CHECK4: arraydestroy.body:
2054 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2055 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2056 // CHECK4-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2057 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
2058 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2059 // CHECK4: arraydestroy.done7:
2060 // CHECK4-NEXT: ret void
2061 //
2062 //
2063 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2064 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2065 // CHECK4-NEXT: entry:
2066 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2067 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2068 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2069 // CHECK4-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2070 // CHECK4-NEXT: ret void
2071 //
2072 //
2073 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2074 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2075 // CHECK4-NEXT: entry:
2076 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2077 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2078 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2079 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2080 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2081 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2082 // CHECK4-NEXT: ret void
2083 //
2084 //
2085 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2086 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2087 // CHECK4-NEXT: entry:
2088 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2089 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2090 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2091 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2092 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2093 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2094 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2095 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2096 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2097 // CHECK4-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2098 // CHECK4-NEXT: ret void
2099 //
2100 //
2101 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2102 // CHECK4-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2103 // CHECK4-NEXT: entry:
2104 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
2105 // CHECK4-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
2106 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
2107 // CHECK4-NEXT: ret void
2108 //
2109 //
2110 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
2111 // CHECK4-SAME: () #[[ATTR0]] {
2112 // CHECK4-NEXT: entry:
2113 // CHECK4-NEXT: call void @__cxx_global_var_init()
2114 // CHECK4-NEXT: call void @__cxx_global_var_init.1()
2115 // CHECK4-NEXT: call void @__cxx_global_var_init.2()
2116 // CHECK4-NEXT: ret void
2117 //
2118 //
2119 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2120 // CHECK4-SAME: () #[[ATTR0]] {
2121 // CHECK4-NEXT: entry:
2122 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
2123 // CHECK4-NEXT: ret void
2124 //
2125 //
2126 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
2127 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
2128 // CHECK5-NEXT: entry:
2129 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2130 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2131 // CHECK5-NEXT: ret void
2132 //
2133 //
2134 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2135 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2136 // CHECK5-NEXT: entry:
2137 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2138 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2139 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2140 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2141 // CHECK5-NEXT: ret void
2142 //
2143 //
2144 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2145 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2146 // CHECK5-NEXT: entry:
2147 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2148 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2149 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2150 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2151 // CHECK5-NEXT: ret void
2152 //
2153 //
2154 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2155 // CHECK5-SAME: () #[[ATTR0]] {
2156 // CHECK5-NEXT: entry:
2157 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
2158 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
2159 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2160 // CHECK5-NEXT: ret void
2161 //
2162 //
2163 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2164 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2165 // CHECK5-NEXT: entry:
2166 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2167 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2168 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2169 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2170 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2171 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2172 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2173 // CHECK5-NEXT: ret void
2174 //
2175 //
2176 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2177 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2178 // CHECK5-NEXT: entry:
2179 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2180 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2181 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2182 // CHECK5: arraydestroy.body:
2183 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2184 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2185 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2186 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2187 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2188 // CHECK5: arraydestroy.done1:
2189 // CHECK5-NEXT: ret void
2190 //
2191 //
2192 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2193 // CHECK5-SAME: () #[[ATTR0]] {
2194 // CHECK5-NEXT: entry:
2195 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2196 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2197 // CHECK5-NEXT: ret void
2198 //
2199 //
2200 // CHECK5-LABEL: define {{[^@]+}}@main
2201 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
2202 // CHECK5-NEXT: entry:
2203 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2204 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2205 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2206 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2207 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2208 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2209 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2210 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2211 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2212 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2213 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2214 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
2215 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2216 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2217 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2218 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
2219 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2220 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
2221 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2222 // CHECK5: arrayctor.loop:
2223 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2224 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2225 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
2226 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2227 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2228 // CHECK5: arrayctor.cont:
2229 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2230 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2231 // CHECK5: omp.inner.for.cond:
2232 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2233 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
2234 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2235 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2236 // CHECK5: omp.inner.for.cond.cleanup:
2237 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2238 // CHECK5: omp.inner.for.body:
2239 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2240 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2241 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2242 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
2243 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
2244 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2245 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
2246 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
2247 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
2248 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2249 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
2250 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
2251 // CHECK5-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
2252 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
2253 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
2254 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2255 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
2256 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
2257 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
2258 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2259 // CHECK5: omp.body.continue:
2260 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2261 // CHECK5: omp.inner.for.inc:
2262 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2263 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
2264 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2265 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2266 // CHECK5: omp.inner.for.end:
2267 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
2268 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2269 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2270 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
2271 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2272 // CHECK5: arraydestroy.body:
2273 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2274 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2275 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2276 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
2277 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2278 // CHECK5: arraydestroy.done6:
2279 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
2280 // CHECK5-NEXT: ret i32 [[CALL]]
2281 //
2282 //
2283 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2284 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
2285 // CHECK5-NEXT: entry:
2286 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2287 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2288 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2289 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2290 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2291 // CHECK5-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
2292 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
2293 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
2294 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2295 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2296 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2297 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
2298 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2299 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2300 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2301 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
2302 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
2303 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2304 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4
2305 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2306 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
2307 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
2308 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
2309 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
2310 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
2311 // CHECK5-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
2312 // CHECK5-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
2313 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2314 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2315 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2316 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
2317 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2318 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2319 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2320 // CHECK5: arrayctor.loop:
2321 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2322 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2323 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
2324 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2325 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2326 // CHECK5: arrayctor.cont:
2327 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
2328 // CHECK5-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
2329 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2330 // CHECK5: omp.inner.for.cond:
2331 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2332 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
2333 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
2334 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2335 // CHECK5: omp.inner.for.cond.cleanup:
2336 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2337 // CHECK5: omp.inner.for.body:
2338 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2339 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
2340 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2341 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
2342 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
2343 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2344 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
2345 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
2346 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
2347 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
2348 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2349 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
2350 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
2351 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
2352 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
2353 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
2354 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2355 // CHECK5: omp.body.continue:
2356 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2357 // CHECK5: omp.inner.for.inc:
2358 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2359 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
2360 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2361 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2362 // CHECK5: omp.inner.for.end:
2363 // CHECK5-NEXT: store i32 2, i32* [[I]], align 4
2364 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2365 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2366 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
2367 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2368 // CHECK5: arraydestroy.body:
2369 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2370 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2371 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2372 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2373 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2374 // CHECK5: arraydestroy.done11:
2375 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
2376 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2377 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
2378 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
2379 // CHECK5: arraydestroy.body13:
2380 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
2381 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
2382 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
2383 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
2384 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
2385 // CHECK5: arraydestroy.done17:
2386 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2387 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
2388 // CHECK5-NEXT: ret i32 [[TMP14]]
2389 //
2390 //
2391 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2392 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2393 // CHECK5-NEXT: entry:
2394 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2395 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2396 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2397 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2398 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2399 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2400 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4
2401 // CHECK5-NEXT: ret void
2402 //
2403 //
2404 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2405 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2406 // CHECK5-NEXT: entry:
2407 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2408 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2409 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2410 // CHECK5-NEXT: ret void
2411 //
2412 //
2413 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2414 // CHECK5-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2415 // CHECK5-NEXT: entry:
2416 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2417 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2418 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2419 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2420 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2421 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2422 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2423 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2424 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2425 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2426 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4
2427 // CHECK5-NEXT: ret void
2428 //
2429 //
2430 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2431 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2432 // CHECK5-NEXT: entry:
2433 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2434 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2435 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2436 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2437 // CHECK5-NEXT: ret void
2438 //
2439 //
2440 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2441 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2442 // CHECK5-NEXT: entry:
2443 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2444 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2445 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2446 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2447 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2448 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2449 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
2450 // CHECK5-NEXT: ret void
2451 //
2452 //
2453 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2454 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2455 // CHECK5-NEXT: entry:
2456 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2457 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2458 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2459 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2460 // CHECK5-NEXT: ret void
2461 //
2462 //
2463 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2464 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2465 // CHECK5-NEXT: entry:
2466 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2467 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2468 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2469 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2470 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2471 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2472 // CHECK5-NEXT: ret void
2473 //
2474 //
2475 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2476 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2477 // CHECK5-NEXT: entry:
2478 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2479 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2480 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2481 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2482 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2483 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2484 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2485 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2486 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2487 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2488 // CHECK5-NEXT: ret void
2489 //
2490 //
2491 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2492 // CHECK5-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2493 // CHECK5-NEXT: entry:
2494 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2495 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2496 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2497 // CHECK5-NEXT: ret void
2498 //
2499 //
2500 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
2501 // CHECK5-SAME: () #[[ATTR0]] {
2502 // CHECK5-NEXT: entry:
2503 // CHECK5-NEXT: call void @__cxx_global_var_init()
2504 // CHECK5-NEXT: call void @__cxx_global_var_init.1()
2505 // CHECK5-NEXT: call void @__cxx_global_var_init.2()
2506 // CHECK5-NEXT: ret void
2507 //
2508 //
2509 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init
2510 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
2511 // CHECK6-NEXT: entry:
2512 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2513 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2514 // CHECK6-NEXT: ret void
2515 //
2516 //
2517 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2518 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2519 // CHECK6-NEXT: entry:
2520 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2521 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2522 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2523 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2524 // CHECK6-NEXT: ret void
2525 //
2526 //
2527 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2528 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2529 // CHECK6-NEXT: entry:
2530 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2531 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2532 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2533 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2534 // CHECK6-NEXT: ret void
2535 //
2536 //
2537 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2538 // CHECK6-SAME: () #[[ATTR0]] {
2539 // CHECK6-NEXT: entry:
2540 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
2541 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
2542 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2543 // CHECK6-NEXT: ret void
2544 //
2545 //
2546 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2547 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2548 // CHECK6-NEXT: entry:
2549 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2550 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2551 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2552 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2553 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2554 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2555 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2556 // CHECK6-NEXT: ret void
2557 //
2558 //
2559 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2560 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2561 // CHECK6-NEXT: entry:
2562 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
2563 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2564 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2565 // CHECK6: arraydestroy.body:
2566 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2567 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2568 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2569 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2570 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2571 // CHECK6: arraydestroy.done1:
2572 // CHECK6-NEXT: ret void
2573 //
2574 //
2575 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2576 // CHECK6-SAME: () #[[ATTR0]] {
2577 // CHECK6-NEXT: entry:
2578 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2579 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2580 // CHECK6-NEXT: ret void
2581 //
2582 //
2583 // CHECK6-LABEL: define {{[^@]+}}@main
2584 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] {
2585 // CHECK6-NEXT: entry:
2586 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2587 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
2588 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2589 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2590 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2591 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
2592 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2593 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2594 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2595 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2596 // CHECK6-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2597 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
2598 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2599 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2600 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2601 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
2602 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2603 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
2604 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2605 // CHECK6: arrayctor.loop:
2606 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2607 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2608 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i64 1
2609 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2610 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2611 // CHECK6: arrayctor.cont:
2612 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2613 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2614 // CHECK6: omp.inner.for.cond:
2615 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2616 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2
2617 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2618 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2619 // CHECK6: omp.inner.for.cond.cleanup:
2620 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2621 // CHECK6: omp.inner.for.body:
2622 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2623 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2624 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2625 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2
2626 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !2
2627 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2628 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
2629 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 [[IDXPROM]]
2630 // CHECK6-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !2
2631 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2632 // CHECK6-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
2633 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 [[IDXPROM1]]
2634 // CHECK6-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
2635 // CHECK6-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
2636 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 4, i1 false), !llvm.access.group !2
2637 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !2
2638 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !2
2639 // CHECK6-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
2640 // CHECK6-NEXT: store i32 [[ADD3]], i32* [[SIVAR]], align 4, !llvm.access.group !2
2641 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2642 // CHECK6: omp.body.continue:
2643 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2644 // CHECK6: omp.inner.for.inc:
2645 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2646 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
2647 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2
2648 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2649 // CHECK6: omp.inner.for.end:
2650 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
2651 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2652 // CHECK6-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2653 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN5]], i64 2
2654 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2655 // CHECK6: arraydestroy.body:
2656 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2657 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2658 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2659 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
2660 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2661 // CHECK6: arraydestroy.done6:
2662 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v()
2663 // CHECK6-NEXT: ret i32 [[CALL]]
2664 //
2665 //
2666 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2667 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] comdat {
2668 // CHECK6-NEXT: entry:
2669 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2670 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2671 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2672 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2673 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2674 // CHECK6-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8
2675 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4
2676 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8
2677 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2678 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2679 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2680 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4
2681 // CHECK6-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2682 // CHECK6-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2683 // CHECK6-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2684 // CHECK6-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
2685 // CHECK6-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 8
2686 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2687 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4
2688 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
2689 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
2690 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
2691 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1)
2692 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
2693 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
2694 // CHECK6-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8
2695 // CHECK6-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 8
2696 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2697 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2698 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2699 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
2700 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2701 // CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
2702 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2703 // CHECK6: arrayctor.loop:
2704 // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2705 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2706 // CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i64 1
2707 // CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2708 // CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2709 // CHECK6: arrayctor.cont:
2710 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
2711 // CHECK6-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 8
2712 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2713 // CHECK6: omp.inner.for.cond:
2714 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2715 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !6
2716 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
2717 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2718 // CHECK6: omp.inner.for.cond.cleanup:
2719 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2720 // CHECK6: omp.inner.for.body:
2721 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2722 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
2723 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2724 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !6
2725 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !6
2726 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2727 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
2728 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i64 0, i64 [[IDXPROM]]
2729 // CHECK6-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !6
2730 // CHECK6-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 8, !llvm.access.group !6
2731 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !6
2732 // CHECK6-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP8]] to i64
2733 // CHECK6-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
2734 // CHECK6-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8*
2735 // CHECK6-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
2736 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group !6
2737 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2738 // CHECK6: omp.body.continue:
2739 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2740 // CHECK6: omp.inner.for.inc:
2741 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2742 // CHECK6-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], 1
2743 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !6
2744 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2745 // CHECK6: omp.inner.for.end:
2746 // CHECK6-NEXT: store i32 2, i32* [[I]], align 4
2747 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2748 // CHECK6-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
2749 // CHECK6-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN10]], i64 2
2750 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2751 // CHECK6: arraydestroy.body:
2752 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2753 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2754 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2755 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2756 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2757 // CHECK6: arraydestroy.done11:
2758 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
2759 // CHECK6-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
2760 // CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i64 2
2761 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]]
2762 // CHECK6: arraydestroy.body13:
2763 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
2764 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
2765 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
2766 // CHECK6-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
2767 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
2768 // CHECK6: arraydestroy.done17:
2769 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2770 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
2771 // CHECK6-NEXT: ret i32 [[TMP14]]
2772 //
2773 //
2774 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2775 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2776 // CHECK6-NEXT: entry:
2777 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2778 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2779 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2780 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2781 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2782 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2783 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4
2784 // CHECK6-NEXT: ret void
2785 //
2786 //
2787 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2788 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2789 // CHECK6-NEXT: entry:
2790 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2791 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2792 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2793 // CHECK6-NEXT: ret void
2794 //
2795 //
2796 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2797 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2798 // CHECK6-NEXT: entry:
2799 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2800 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2801 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2802 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2803 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2804 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2805 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2806 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2807 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2808 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2809 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4
2810 // CHECK6-NEXT: ret void
2811 //
2812 //
2813 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2814 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2815 // CHECK6-NEXT: entry:
2816 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2817 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2818 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2819 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2820 // CHECK6-NEXT: ret void
2821 //
2822 //
2823 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2824 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2825 // CHECK6-NEXT: entry:
2826 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2827 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2828 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2829 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2830 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2831 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2832 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]])
2833 // CHECK6-NEXT: ret void
2834 //
2835 //
2836 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2837 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2838 // CHECK6-NEXT: entry:
2839 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2840 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2841 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2842 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2843 // CHECK6-NEXT: ret void
2844 //
2845 //
2846 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2847 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2848 // CHECK6-NEXT: entry:
2849 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2850 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2851 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2852 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2853 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
2854 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
2855 // CHECK6-NEXT: ret void
2856 //
2857 //
2858 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2859 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2860 // CHECK6-NEXT: entry:
2861 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2862 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2863 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2864 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
2865 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2866 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2867 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2868 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
2869 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2870 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4
2871 // CHECK6-NEXT: ret void
2872 //
2873 //
2874 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2875 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2876 // CHECK6-NEXT: entry:
2877 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2878 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2879 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2880 // CHECK6-NEXT: ret void
2881 //
2882 //
2883 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
2884 // CHECK6-SAME: () #[[ATTR0]] {
2885 // CHECK6-NEXT: entry:
2886 // CHECK6-NEXT: call void @__cxx_global_var_init()
2887 // CHECK6-NEXT: call void @__cxx_global_var_init.1()
2888 // CHECK6-NEXT: call void @__cxx_global_var_init.2()
2889 // CHECK6-NEXT: ret void
2890 //
2891 //
2892 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
2893 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
2894 // CHECK7-NEXT: entry:
2895 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
2896 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
2897 // CHECK7-NEXT: ret void
2898 //
2899 //
2900 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2901 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2902 // CHECK7-NEXT: entry:
2903 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2904 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2905 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2906 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2907 // CHECK7-NEXT: ret void
2908 //
2909 //
2910 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2911 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2912 // CHECK7-NEXT: entry:
2913 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2914 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2915 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2916 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2917 // CHECK7-NEXT: ret void
2918 //
2919 //
2920 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2921 // CHECK7-SAME: () #[[ATTR0]] {
2922 // CHECK7-NEXT: entry:
2923 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
2924 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
2925 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
2926 // CHECK7-NEXT: ret void
2927 //
2928 //
2929 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2930 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2931 // CHECK7-NEXT: entry:
2932 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
2933 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2934 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
2935 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
2936 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
2937 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2938 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2939 // CHECK7-NEXT: ret void
2940 //
2941 //
2942 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2943 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
2944 // CHECK7-NEXT: entry:
2945 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
2946 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
2947 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2948 // CHECK7: arraydestroy.body:
2949 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2950 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2951 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2952 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
2953 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2954 // CHECK7: arraydestroy.done1:
2955 // CHECK7-NEXT: ret void
2956 //
2957 //
2958 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2959 // CHECK7-SAME: () #[[ATTR0]] {
2960 // CHECK7-NEXT: entry:
2961 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
2962 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
2963 // CHECK7-NEXT: ret void
2964 //
2965 //
2966 // CHECK7-LABEL: define {{[^@]+}}@main
2967 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
2968 // CHECK7-NEXT: entry:
2969 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2970 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
2971 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2972 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2973 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2974 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2975 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2976 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2977 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2978 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2979 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
2980 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
2981 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
2982 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
2983 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
2984 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
2985 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
2986 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
2987 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2988 // CHECK7: arrayctor.loop:
2989 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2990 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2991 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
2992 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2993 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2994 // CHECK7: arrayctor.cont:
2995 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
2996 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2997 // CHECK7: omp.inner.for.cond:
2998 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
2999 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
3000 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3001 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3002 // CHECK7: omp.inner.for.cond.cleanup:
3003 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3004 // CHECK7: omp.inner.for.body:
3005 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3006 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3007 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3008 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
3009 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
3010 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3011 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
3012 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
3013 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3014 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
3015 // CHECK7-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
3016 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
3017 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
3018 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3019 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
3020 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
3021 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
3022 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3023 // CHECK7: omp.body.continue:
3024 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3025 // CHECK7: omp.inner.for.inc:
3026 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3027 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
3028 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3029 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
3030 // CHECK7: omp.inner.for.end:
3031 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
3032 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
3033 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3034 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
3035 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3036 // CHECK7: arraydestroy.body:
3037 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3038 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3039 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3040 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
3041 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
3042 // CHECK7: arraydestroy.done5:
3043 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
3044 // CHECK7-NEXT: ret i32 [[CALL]]
3045 //
3046 //
3047 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3048 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
3049 // CHECK7-NEXT: entry:
3050 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3051 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3052 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3053 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3054 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3055 // CHECK7-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
3056 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
3057 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
3058 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3059 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3060 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3061 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
3062 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3063 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3064 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
3065 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
3066 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
3067 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3068 // CHECK7-NEXT: store i32 0, i32* [[T_VAR]], align 4
3069 // CHECK7-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3070 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3071 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3072 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
3073 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3074 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
3075 // CHECK7-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3076 // CHECK7-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
3077 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3078 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3079 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3080 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
3081 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3082 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3083 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3084 // CHECK7: arrayctor.loop:
3085 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3086 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3087 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
3088 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3089 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3090 // CHECK7: arrayctor.cont:
3091 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
3092 // CHECK7-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
3093 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3094 // CHECK7: omp.inner.for.cond:
3095 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3096 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
3097 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
3098 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3099 // CHECK7: omp.inner.for.cond.cleanup:
3100 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3101 // CHECK7: omp.inner.for.body:
3102 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3103 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3104 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3105 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
3106 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
3107 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3108 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
3109 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
3110 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
3111 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3112 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
3113 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
3114 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
3115 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
3116 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3117 // CHECK7: omp.body.continue:
3118 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3119 // CHECK7: omp.inner.for.inc:
3120 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3121 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
3122 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3123 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
3124 // CHECK7: omp.inner.for.end:
3125 // CHECK7-NEXT: store i32 2, i32* [[I]], align 4
3126 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3127 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3128 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
3129 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3130 // CHECK7: arraydestroy.body:
3131 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3132 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3133 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3134 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
3135 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
3136 // CHECK7: arraydestroy.done10:
3137 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
3138 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3139 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
3140 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
3141 // CHECK7: arraydestroy.body12:
3142 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
3143 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
3144 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
3145 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
3146 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
3147 // CHECK7: arraydestroy.done16:
3148 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3149 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
3150 // CHECK7-NEXT: ret i32 [[TMP14]]
3151 //
3152 //
3153 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3154 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3155 // CHECK7-NEXT: entry:
3156 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3157 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3158 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3159 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3160 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3161 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3162 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4
3163 // CHECK7-NEXT: ret void
3164 //
3165 //
3166 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3167 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3168 // CHECK7-NEXT: entry:
3169 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3170 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3171 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3172 // CHECK7-NEXT: ret void
3173 //
3174 //
3175 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3176 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3177 // CHECK7-NEXT: entry:
3178 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3179 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3180 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3181 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3182 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3183 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3184 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3185 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3186 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3187 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3188 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4
3189 // CHECK7-NEXT: ret void
3190 //
3191 //
3192 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3193 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3194 // CHECK7-NEXT: entry:
3195 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3196 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3197 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3198 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3199 // CHECK7-NEXT: ret void
3200 //
3201 //
3202 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3203 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3204 // CHECK7-NEXT: entry:
3205 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3206 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3207 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3208 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3209 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3210 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3211 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
3212 // CHECK7-NEXT: ret void
3213 //
3214 //
3215 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3216 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3217 // CHECK7-NEXT: entry:
3218 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3219 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3220 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3221 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3222 // CHECK7-NEXT: ret void
3223 //
3224 //
3225 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3226 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3227 // CHECK7-NEXT: entry:
3228 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3229 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3230 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3231 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3232 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3233 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3234 // CHECK7-NEXT: ret void
3235 //
3236 //
3237 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3238 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3239 // CHECK7-NEXT: entry:
3240 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3241 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3242 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3243 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3244 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3245 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3246 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3247 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3248 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3249 // CHECK7-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3250 // CHECK7-NEXT: ret void
3251 //
3252 //
3253 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3254 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3255 // CHECK7-NEXT: entry:
3256 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3257 // CHECK7-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3258 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3259 // CHECK7-NEXT: ret void
3260 //
3261 //
3262 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
3263 // CHECK7-SAME: () #[[ATTR0]] {
3264 // CHECK7-NEXT: entry:
3265 // CHECK7-NEXT: call void @__cxx_global_var_init()
3266 // CHECK7-NEXT: call void @__cxx_global_var_init.1()
3267 // CHECK7-NEXT: call void @__cxx_global_var_init.2()
3268 // CHECK7-NEXT: ret void
3269 //
3270 //
3271 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init
3272 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
3273 // CHECK8-NEXT: entry:
3274 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3275 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3276 // CHECK8-NEXT: ret void
3277 //
3278 //
3279 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3280 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3281 // CHECK8-NEXT: entry:
3282 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3283 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3284 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3285 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3286 // CHECK8-NEXT: ret void
3287 //
3288 //
3289 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3290 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3291 // CHECK8-NEXT: entry:
3292 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3293 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3294 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3295 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3296 // CHECK8-NEXT: ret void
3297 //
3298 //
3299 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3300 // CHECK8-SAME: () #[[ATTR0]] {
3301 // CHECK8-NEXT: entry:
3302 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), float 1.000000e+00)
3303 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 1), float 2.000000e+00)
3304 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3305 // CHECK8-NEXT: ret void
3306 //
3307 //
3308 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3309 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3310 // CHECK8-NEXT: entry:
3311 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3312 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3313 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3314 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3315 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3316 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3317 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3318 // CHECK8-NEXT: ret void
3319 //
3320 //
3321 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3322 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3323 // CHECK8-NEXT: entry:
3324 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 4
3325 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 4
3326 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3327 // CHECK8: arraydestroy.body:
3328 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3329 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3330 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3331 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3332 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3333 // CHECK8: arraydestroy.done1:
3334 // CHECK8-NEXT: ret void
3335 //
3336 //
3337 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3338 // CHECK8-SAME: () #[[ATTR0]] {
3339 // CHECK8-NEXT: entry:
3340 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3341 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3342 // CHECK8-NEXT: ret void
3343 //
3344 //
3345 // CHECK8-LABEL: define {{[^@]+}}@main
3346 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] {
3347 // CHECK8-NEXT: entry:
3348 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3349 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
3350 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3351 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3352 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3353 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
3354 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3355 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3356 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
3357 // CHECK8-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3358 // CHECK8-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3359 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
3360 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3361 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3362 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3363 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTOMP_IV]], align 4
3364 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3365 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2
3366 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3367 // CHECK8: arrayctor.loop:
3368 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3369 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3370 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYCTOR_CUR]], i32 1
3371 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3372 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3373 // CHECK8: arrayctor.cont:
3374 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]])
3375 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3376 // CHECK8: omp.inner.for.cond:
3377 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3378 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3
3379 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
3380 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3381 // CHECK8: omp.inner.for.cond.cleanup:
3382 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3383 // CHECK8: omp.inner.for.body:
3384 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3385 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
3386 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3387 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3
3388 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group !3
3389 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3390 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i32 0, i32 [[TMP5]]
3391 // CHECK8-NEXT: store i32 [[TMP4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !3
3392 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3393 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 [[TMP6]]
3394 // CHECK8-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
3395 // CHECK8-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[VAR]] to i8*
3396 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 4, i1 false), !llvm.access.group !3
3397 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !3
3398 // CHECK8-NEXT: [[TMP10:%.*]] = load i32, i32* [[SIVAR]], align 4, !llvm.access.group !3
3399 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
3400 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[SIVAR]], align 4, !llvm.access.group !3
3401 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3402 // CHECK8: omp.body.continue:
3403 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3404 // CHECK8: omp.inner.for.inc:
3405 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3406 // CHECK8-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
3407 // CHECK8-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3
3408 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
3409 // CHECK8: omp.inner.for.end:
3410 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
3411 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
3412 // CHECK8-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
3413 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i32 2
3414 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3415 // CHECK8: arraydestroy.body:
3416 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3417 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3418 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3419 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
3420 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
3421 // CHECK8: arraydestroy.done5:
3422 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v()
3423 // CHECK8-NEXT: ret i32 [[CALL]]
3424 //
3425 //
3426 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3427 // CHECK8-SAME: () #[[ATTR5:[0-9]+]] comdat {
3428 // CHECK8-NEXT: entry:
3429 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3430 // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3431 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
3432 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
3433 // CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
3434 // CHECK8-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4
3435 // CHECK8-NEXT: [[TMP:%.*]] = alloca i32, align 4
3436 // CHECK8-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4
3437 // CHECK8-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3438 // CHECK8-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3439 // CHECK8-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3440 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4
3441 // CHECK8-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
3442 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
3443 // CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
3444 // CHECK8-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
3445 // CHECK8-NEXT: [[_TMP6:%.*]] = alloca %struct.S.0*, align 4
3446 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3447 // CHECK8-NEXT: store i32 0, i32* [[T_VAR]], align 4
3448 // CHECK8-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
3449 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false)
3450 // CHECK8-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3451 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
3452 // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1
3453 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
3454 // CHECK8-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4
3455 // CHECK8-NEXT: store %struct.S.0* undef, %struct.S.0** [[_TMP1]], align 4
3456 // CHECK8-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3457 // CHECK8-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3458 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3459 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[DOTOMP_IV]], align 4
3460 // CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3461 // CHECK8-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2
3462 // CHECK8-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
3463 // CHECK8: arrayctor.loop:
3464 // CHECK8-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3465 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
3466 // CHECK8-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYCTOR_CUR]], i32 1
3467 // CHECK8-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
3468 // CHECK8-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3469 // CHECK8: arrayctor.cont:
3470 // CHECK8-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]])
3471 // CHECK8-NEXT: store %struct.S.0* [[VAR5]], %struct.S.0** [[_TMP6]], align 4
3472 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3473 // CHECK8: omp.inner.for.cond:
3474 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3475 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !7
3476 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
3477 // CHECK8-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
3478 // CHECK8: omp.inner.for.cond.cleanup:
3479 // CHECK8-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
3480 // CHECK8: omp.inner.for.body:
3481 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3482 // CHECK8-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
3483 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3484 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !7
3485 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR2]], align 4, !llvm.access.group !7
3486 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3487 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC3]], i32 0, i32 [[TMP6]]
3488 // CHECK8-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !7
3489 // CHECK8-NEXT: [[TMP7:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP6]], align 4, !llvm.access.group !7
3490 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group !7
3491 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 [[TMP8]]
3492 // CHECK8-NEXT: [[TMP9:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8*
3493 // CHECK8-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[TMP7]] to i8*
3494 // CHECK8-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group !7
3495 // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3496 // CHECK8: omp.body.continue:
3497 // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3498 // CHECK8: omp.inner.for.inc:
3499 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3500 // CHECK8-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 1
3501 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !7
3502 // CHECK8-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
3503 // CHECK8: omp.inner.for.end:
3504 // CHECK8-NEXT: store i32 2, i32* [[I]], align 4
3505 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
3506 // CHECK8-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR4]], i32 0, i32 0
3507 // CHECK8-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i32 2
3508 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3509 // CHECK8: arraydestroy.body:
3510 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3511 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
3512 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3513 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
3514 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
3515 // CHECK8: arraydestroy.done10:
3516 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4
3517 // CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
3518 // CHECK8-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN11]], i32 2
3519 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]]
3520 // CHECK8: arraydestroy.body12:
3521 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
3522 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
3523 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
3524 // CHECK8-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
3525 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
3526 // CHECK8: arraydestroy.done16:
3527 // CHECK8-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
3528 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[RETVAL]], align 4
3529 // CHECK8-NEXT: ret i32 [[TMP14]]
3530 //
3531 //
3532 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3533 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3534 // CHECK8-NEXT: entry:
3535 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3536 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3537 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3538 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3539 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3540 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3541 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4
3542 // CHECK8-NEXT: ret void
3543 //
3544 //
3545 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3546 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3547 // CHECK8-NEXT: entry:
3548 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3549 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3550 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3551 // CHECK8-NEXT: ret void
3552 //
3553 //
3554 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3555 // CHECK8-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3556 // CHECK8-NEXT: entry:
3557 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4
3558 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3559 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4
3560 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3561 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4
3562 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3563 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3564 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3565 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3566 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3567 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4
3568 // CHECK8-NEXT: ret void
3569 //
3570 //
3571 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3572 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3573 // CHECK8-NEXT: entry:
3574 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3575 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3576 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3577 // CHECK8-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3578 // CHECK8-NEXT: ret void
3579 //
3580 //
3581 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3582 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3583 // CHECK8-NEXT: entry:
3584 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3585 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3586 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3587 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3588 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3589 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3590 // CHECK8-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
3591 // CHECK8-NEXT: ret void
3592 //
3593 //
3594 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3595 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3596 // CHECK8-NEXT: entry:
3597 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3598 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3599 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3600 // CHECK8-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3601 // CHECK8-NEXT: ret void
3602 //
3603 //
3604 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3605 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3606 // CHECK8-NEXT: entry:
3607 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3608 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3609 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3610 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3611 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3612 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
3613 // CHECK8-NEXT: ret void
3614 //
3615 //
3616 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3617 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3618 // CHECK8-NEXT: entry:
3619 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3620 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3621 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3622 // CHECK8-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
3623 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3624 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3625 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3626 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3627 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3628 // CHECK8-NEXT: store i32 [[ADD]], i32* [[F]], align 4
3629 // CHECK8-NEXT: ret void
3630 //
3631 //
3632 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3633 // CHECK8-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3634 // CHECK8-NEXT: entry:
3635 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4
3636 // CHECK8-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4
3637 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4
3638 // CHECK8-NEXT: ret void
3639 //
3640 //
3641 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
3642 // CHECK8-SAME: () #[[ATTR0]] {
3643 // CHECK8-NEXT: entry:
3644 // CHECK8-NEXT: call void @__cxx_global_var_init()
3645 // CHECK8-NEXT: call void @__cxx_global_var_init.1()
3646 // CHECK8-NEXT: call void @__cxx_global_var_init.2()
3647 // CHECK8-NEXT: ret void
3648 //
3649 //
3650 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
3651 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
3652 // CHECK9-NEXT: entry:
3653 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3654 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3655 // CHECK9-NEXT: ret void
3656 //
3657 //
3658 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3659 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3660 // CHECK9-NEXT: entry:
3661 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3662 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3663 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3664 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3665 // CHECK9-NEXT: ret void
3666 //
3667 //
3668 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3669 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3670 // CHECK9-NEXT: entry:
3671 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3672 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3673 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3674 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3675 // CHECK9-NEXT: ret void
3676 //
3677 //
3678 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3679 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3680 // CHECK9-NEXT: entry:
3681 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3682 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3683 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3684 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3685 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3686 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3687 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4
3688 // CHECK9-NEXT: ret void
3689 //
3690 //
3691 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3692 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3693 // CHECK9-NEXT: entry:
3694 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3695 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3696 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3697 // CHECK9-NEXT: ret void
3698 //
3699 //
3700 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3701 // CHECK9-SAME: () #[[ATTR0]] {
3702 // CHECK9-NEXT: entry:
3703 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3704 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3705 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3706 // CHECK9-NEXT: ret void
3707 //
3708 //
3709 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3710 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3711 // CHECK9-NEXT: entry:
3712 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3713 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3714 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3715 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3716 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3717 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3718 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3719 // CHECK9-NEXT: ret void
3720 //
3721 //
3722 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3723 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3724 // CHECK9-NEXT: entry:
3725 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3726 // CHECK9-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3727 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3728 // CHECK9: arraydestroy.body:
3729 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3730 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3731 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3732 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3733 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3734 // CHECK9: arraydestroy.done1:
3735 // CHECK9-NEXT: ret void
3736 //
3737 //
3738 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3739 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3740 // CHECK9-NEXT: entry:
3741 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3742 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3743 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3744 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3745 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3746 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3747 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3748 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3749 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3750 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3751 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4
3752 // CHECK9-NEXT: ret void
3753 //
3754 //
3755 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3756 // CHECK9-SAME: () #[[ATTR0]] {
3757 // CHECK9-NEXT: entry:
3758 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3759 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3760 // CHECK9-NEXT: ret void
3761 //
3762 //
3763 // CHECK9-LABEL: define {{[^@]+}}@main
3764 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
3765 // CHECK9-NEXT: entry:
3766 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
3767 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3768 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4
3769 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
3770 // CHECK9-NEXT: ret i32 0
3771 //
3772 //
3773 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
3774 // CHECK9-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
3775 // CHECK9-NEXT: entry:
3776 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
3777 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8
3778 // CHECK9-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
3779 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
3780 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
3781 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3782 // CHECK9-NEXT: ret void
3783 //
3784 //
3785 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
3786 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
3787 // CHECK9-NEXT: entry:
3788 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3789 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3790 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3791 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
3792 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
3793 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3794 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3795 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3796 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3797 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4
3798 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4
3799 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
3800 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
3801 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
3802 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
3803 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3804 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3805 // CHECK9-NEXT: store i32* undef, i32** [[_TMP1]], align 8
3806 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
3807 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
3808 // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
3809 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
3810 // CHECK9-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
3811 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3812 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
3813 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
3814 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3815 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
3816 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3817 // CHECK9: cond.true:
3818 // CHECK9-NEXT: br label [[COND_END:%.*]]
3819 // CHECK9: cond.false:
3820 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3821 // CHECK9-NEXT: br label [[COND_END]]
3822 // CHECK9: cond.end:
3823 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3824 // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
3825 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
3826 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
3827 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3828 // CHECK9: omp.inner.for.cond:
3829 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3830 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
3831 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3832 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3833 // CHECK9: omp.inner.for.body:
3834 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3835 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
3836 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3837 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
3838 // CHECK9-NEXT: store i32 1, i32* [[G]], align 4
3839 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8
3840 // CHECK9-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
3841 // CHECK9-NEXT: store i32 2, i32* [[SIVAR]], align 4
3842 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
3843 // CHECK9-NEXT: store i32* [[G]], i32** [[TMP9]], align 8
3844 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
3845 // CHECK9-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8
3846 // CHECK9-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
3847 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
3848 // CHECK9-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8
3849 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
3850 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3851 // CHECK9: omp.body.continue:
3852 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3853 // CHECK9: omp.inner.for.inc:
3854 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
3855 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
3856 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
3857 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
3858 // CHECK9: omp.inner.for.end:
3859 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3860 // CHECK9: omp.loop.exit:
3861 // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
3862 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
3863 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
3864 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3865 // CHECK9: .omp.final.then:
3866 // CHECK9-NEXT: store i32 2, i32* [[I]], align 4
3867 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
3868 // CHECK9: .omp.final.done:
3869 // CHECK9-NEXT: ret void
3870 //
3871 //
3872 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
3873 // CHECK9-SAME: () #[[ATTR0]] {
3874 // CHECK9-NEXT: entry:
3875 // CHECK9-NEXT: call void @__cxx_global_var_init()
3876 // CHECK9-NEXT: call void @__cxx_global_var_init.1()
3877 // CHECK9-NEXT: call void @__cxx_global_var_init.2()
3878 // CHECK9-NEXT: ret void
3879 //
3880 //
3881 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3882 // CHECK9-SAME: () #[[ATTR0]] {
3883 // CHECK9-NEXT: entry:
3884 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
3885 // CHECK9-NEXT: ret void
3886 //
3887 //
3888 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init
3889 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
3890 // CHECK10-NEXT: entry:
3891 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
3892 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
3893 // CHECK10-NEXT: ret void
3894 //
3895 //
3896 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3897 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3898 // CHECK10-NEXT: entry:
3899 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3900 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3901 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3902 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3903 // CHECK10-NEXT: ret void
3904 //
3905 //
3906 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3907 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3908 // CHECK10-NEXT: entry:
3909 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3910 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3911 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3912 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3913 // CHECK10-NEXT: ret void
3914 //
3915 //
3916 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3917 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3918 // CHECK10-NEXT: entry:
3919 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3920 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3921 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3922 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3923 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
3924 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3925 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4
3926 // CHECK10-NEXT: ret void
3927 //
3928 //
3929 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3930 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3931 // CHECK10-NEXT: entry:
3932 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3933 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3934 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3935 // CHECK10-NEXT: ret void
3936 //
3937 //
3938 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3939 // CHECK10-SAME: () #[[ATTR0]] {
3940 // CHECK10-NEXT: entry:
3941 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
3942 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
3943 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
3944 // CHECK10-NEXT: ret void
3945 //
3946 //
3947 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3948 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3949 // CHECK10-NEXT: entry:
3950 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3951 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3952 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3953 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3954 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3955 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3956 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3957 // CHECK10-NEXT: ret void
3958 //
3959 //
3960 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3961 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
3962 // CHECK10-NEXT: entry:
3963 // CHECK10-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
3964 // CHECK10-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3965 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
3966 // CHECK10: arraydestroy.body:
3967 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3968 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3969 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3970 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
3971 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3972 // CHECK10: arraydestroy.done1:
3973 // CHECK10-NEXT: ret void
3974 //
3975 //
3976 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3977 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3978 // CHECK10-NEXT: entry:
3979 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3980 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
3981 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3982 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4
3983 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3984 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3985 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3986 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
3987 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3988 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3989 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4
3990 // CHECK10-NEXT: ret void
3991 //
3992 //
3993 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3994 // CHECK10-SAME: () #[[ATTR0]] {
3995 // CHECK10-NEXT: entry:
3996 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
3997 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
3998 // CHECK10-NEXT: ret void
3999 //
4000 //
4001 // CHECK10-LABEL: define {{[^@]+}}@main
4002 // CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
4003 // CHECK10-NEXT: entry:
4004 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4005 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4006 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4
4007 // CHECK10-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4008 // CHECK10-NEXT: ret i32 0
4009 //
4010 //
4011 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
4012 // CHECK10-SAME: (i64 [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
4013 // CHECK10-NEXT: entry:
4014 // CHECK10-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
4015 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8
4016 // CHECK10-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8
4017 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[G1_ADDR]] to i32*
4018 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8
4019 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
4020 // CHECK10-NEXT: ret void
4021 //
4022 //
4023 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
4024 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
4025 // CHECK10-NEXT: entry:
4026 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4027 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4028 // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4029 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
4030 // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8
4031 // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4032 // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4033 // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4034 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4035 // CHECK10-NEXT: [[G:%.*]] = alloca i32, align 4
4036 // CHECK10-NEXT: [[G1:%.*]] = alloca i32, align 4
4037 // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32*, align 8
4038 // CHECK10-NEXT: [[SIVAR:%.*]] = alloca i32, align 4
4039 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
4040 // CHECK10-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
4041 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4042 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4043 // CHECK10-NEXT: store i32* undef, i32** [[_TMP1]], align 8
4044 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
4045 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4
4046 // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
4047 // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
4048 // CHECK10-NEXT: store i32* [[G1]], i32** [[_TMP2]], align 8
4049 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
4050 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
4051 // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
4052 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4053 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
4054 // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4055 // CHECK10: cond.true:
4056 // CHECK10-NEXT: br label [[COND_END:%.*]]
4057 // CHECK10: cond.false:
4058 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4059 // CHECK10-NEXT: br label [[COND_END]]
4060 // CHECK10: cond.end:
4061 // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4062 // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
4063 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
4064 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
4065 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4066 // CHECK10: omp.inner.for.cond:
4067 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4068 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
4069 // CHECK10-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4070 // CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4071 // CHECK10: omp.inner.for.body:
4072 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4073 // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4074 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4075 // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
4076 // CHECK10-NEXT: store i32 1, i32* [[G]], align 4
4077 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP2]], align 8
4078 // CHECK10-NEXT: store volatile i32 1, i32* [[TMP8]], align 4
4079 // CHECK10-NEXT: store i32 2, i32* [[SIVAR]], align 4
4080 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0
4081 // CHECK10-NEXT: store i32* [[G]], i32** [[TMP9]], align 8
4082 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1
4083 // CHECK10-NEXT: [[TMP11:%.*]] = load i32*, i32** [[_TMP2]], align 8
4084 // CHECK10-NEXT: store i32* [[TMP11]], i32** [[TMP10]], align 8
4085 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2
4086 // CHECK10-NEXT: store i32* [[SIVAR]], i32** [[TMP12]], align 8
4087 // CHECK10-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(24) [[REF_TMP]])
4088 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4089 // CHECK10: omp.body.continue:
4090 // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4091 // CHECK10: omp.inner.for.inc:
4092 // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
4093 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
4094 // CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
4095 // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
4096 // CHECK10: omp.inner.for.end:
4097 // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4098 // CHECK10: omp.loop.exit:
4099 // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
4100 // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
4101 // CHECK10-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
4102 // CHECK10-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4103 // CHECK10: .omp.final.then:
4104 // CHECK10-NEXT: store i32 2, i32* [[I]], align 4
4105 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]]
4106 // CHECK10: .omp.final.done:
4107 // CHECK10-NEXT: ret void
4108 //
4109 //
4110 // CHECK10-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
4111 // CHECK10-SAME: () #[[ATTR0]] {
4112 // CHECK10-NEXT: entry:
4113 // CHECK10-NEXT: call void @__cxx_global_var_init()
4114 // CHECK10-NEXT: call void @__cxx_global_var_init.1()
4115 // CHECK10-NEXT: call void @__cxx_global_var_init.2()
4116 // CHECK10-NEXT: ret void
4117 //
4118 //
4119 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4120 // CHECK10-SAME: () #[[ATTR0]] {
4121 // CHECK10-NEXT: entry:
4122 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1)
4123 // CHECK10-NEXT: ret void
4124 //
4125 //
4126 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
4127 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
4128 // CHECK11-NEXT: entry:
4129 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4130 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4131 // CHECK11-NEXT: ret void
4132 //
4133 //
4134 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4135 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4136 // CHECK11-NEXT: entry:
4137 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4138 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4139 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4140 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4141 // CHECK11-NEXT: ret void
4142 //
4143 //
4144 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4145 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4146 // CHECK11-NEXT: entry:
4147 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4148 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4149 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4150 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4151 // CHECK11-NEXT: ret void
4152 //
4153 //
4154 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4155 // CHECK11-SAME: () #[[ATTR0]] {
4156 // CHECK11-NEXT: entry:
4157 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4158 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4159 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4160 // CHECK11-NEXT: ret void
4161 //
4162 //
4163 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4164 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4165 // CHECK11-NEXT: entry:
4166 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4167 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4168 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4169 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4170 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4171 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4172 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4173 // CHECK11-NEXT: ret void
4174 //
4175 //
4176 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4177 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4178 // CHECK11-NEXT: entry:
4179 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4180 // CHECK11-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4181 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4182 // CHECK11: arraydestroy.body:
4183 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4184 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4185 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4186 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4187 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4188 // CHECK11: arraydestroy.done1:
4189 // CHECK11-NEXT: ret void
4190 //
4191 //
4192 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4193 // CHECK11-SAME: () #[[ATTR0]] {
4194 // CHECK11-NEXT: entry:
4195 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4196 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4197 // CHECK11-NEXT: ret void
4198 //
4199 //
4200 // CHECK11-LABEL: define {{[^@]+}}@main
4201 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
4202 // CHECK11-NEXT: entry:
4203 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4204 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4205 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4
4206 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4207 // CHECK11-NEXT: ret i32 0
4208 //
4209 //
4210 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4211 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4212 // CHECK11-NEXT: entry:
4213 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4214 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4215 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4216 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4217 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4218 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4219 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4
4220 // CHECK11-NEXT: ret void
4221 //
4222 //
4223 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4224 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4225 // CHECK11-NEXT: entry:
4226 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4227 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4228 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4229 // CHECK11-NEXT: ret void
4230 //
4231 //
4232 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4233 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4234 // CHECK11-NEXT: entry:
4235 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4236 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4237 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4238 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4239 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4240 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4241 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4242 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4243 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4244 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4245 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4
4246 // CHECK11-NEXT: ret void
4247 //
4248 //
4249 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
4250 // CHECK11-SAME: () #[[ATTR0]] {
4251 // CHECK11-NEXT: entry:
4252 // CHECK11-NEXT: call void @__cxx_global_var_init()
4253 // CHECK11-NEXT: call void @__cxx_global_var_init.1()
4254 // CHECK11-NEXT: call void @__cxx_global_var_init.2()
4255 // CHECK11-NEXT: ret void
4256 //
4257 //
4258 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init
4259 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
4260 // CHECK12-NEXT: entry:
4261 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test)
4262 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]]
4263 // CHECK12-NEXT: ret void
4264 //
4265 //
4266 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
4267 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
4268 // CHECK12-NEXT: entry:
4269 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4270 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4271 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4272 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
4273 // CHECK12-NEXT: ret void
4274 //
4275 //
4276 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
4277 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4278 // CHECK12-NEXT: entry:
4279 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4280 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4281 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4282 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
4283 // CHECK12-NEXT: ret void
4284 //
4285 //
4286 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4287 // CHECK12-SAME: () #[[ATTR0]] {
4288 // CHECK12-NEXT: entry:
4289 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00)
4290 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00)
4291 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]]
4292 // CHECK12-NEXT: ret void
4293 //
4294 //
4295 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
4296 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4297 // CHECK12-NEXT: entry:
4298 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4299 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4300 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4301 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4302 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4303 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4304 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
4305 // CHECK12-NEXT: ret void
4306 //
4307 //
4308 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4309 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] {
4310 // CHECK12-NEXT: entry:
4311 // CHECK12-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8
4312 // CHECK12-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4313 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
4314 // CHECK12: arraydestroy.body:
4315 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4316 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4317 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
4318 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0)
4319 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4320 // CHECK12: arraydestroy.done1:
4321 // CHECK12-NEXT: ret void
4322 //
4323 //
4324 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4325 // CHECK12-SAME: () #[[ATTR0]] {
4326 // CHECK12-NEXT: entry:
4327 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00)
4328 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]]
4329 // CHECK12-NEXT: ret void
4330 //
4331 //
4332 // CHECK12-LABEL: define {{[^@]+}}@main
4333 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] {
4334 // CHECK12-NEXT: entry:
4335 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
4336 // CHECK12-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4337 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4
4338 // CHECK12-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4339 // CHECK12-NEXT: ret i32 0
4340 //
4341 //
4342 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
4343 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4344 // CHECK12-NEXT: entry:
4345 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4346 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4347 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4348 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4349 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4
4350 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
4351 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4
4352 // CHECK12-NEXT: ret void
4353 //
4354 //
4355 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4356 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4357 // CHECK12-NEXT: entry:
4358 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4359 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4360 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4361 // CHECK12-NEXT: ret void
4362 //
4363 //
4364 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4365 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4366 // CHECK12-NEXT: entry:
4367 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4368 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
4369 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4370 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4
4371 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4372 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4373 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4374 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4
4375 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4376 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4377 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4
4378 // CHECK12-NEXT: ret void
4379 //
4380 //
4381 // CHECK12-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp
4382 // CHECK12-SAME: () #[[ATTR0]] {
4383 // CHECK12-NEXT: entry:
4384 // CHECK12-NEXT: call void @__cxx_global_var_init()
4385 // CHECK12-NEXT: call void @__cxx_global_var_init.1()
4386 // CHECK12-NEXT: call void @__cxx_global_var_init.2()
4387 // CHECK12-NEXT: ret void
4388 //
4389