1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Check code generation
3 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=51 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
4
5 // Check same results after serialization round-trip
6 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=51 -emit-pch -o %t %s
7 // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-version=51 -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2
8 // expected-no-diagnostics
9
10 #ifndef HEADER
11 #define HEADER
12
13 // placeholder for loop body code.
body(...)14 extern "C" void body(...) {}
15
16
17 struct S {
18 int i;
SS19 S() {
20 #pragma omp tile sizes(5)
21 for (i = 7; i < 17; i += 3)
22 body(i);
23 }
24 } s;
25
foo1(int start,int end,int step)26 extern "C" void foo1(int start, int end, int step) {
27 int i;
28 #pragma omp tile sizes(5)
29 for (i = start; i < end; i += step)
30 body(i);
31 }
32
foo2(int start,int end,int step)33 extern "C" void foo2(int start, int end, int step) {
34 #pragma omp tile sizes(5,5)
35 for (int i = 7; i < 17; i+=3)
36 for (int j = 7; j < 17; j+=3)
37 body(i,j);
38 }
39
foo3()40 extern "C" void foo3() {
41 #pragma omp for
42 #pragma omp tile sizes(5,5)
43 for (int i = 7; i < 17; i += 3)
44 for (int j = 7; j < 17; j += 3)
45 body(i, j);
46 }
47
foo4()48 extern "C" void foo4() {
49 #pragma omp for collapse(2)
50 for (int k = 7; k < 17; k += 3)
51 #pragma omp tile sizes(5,5)
52 for (int i = 7; i < 17; i += 3)
53 for (int j = 7; j < 17; j += 3)
54 body(i, j);
55 }
56
57
foo5()58 extern "C" void foo5() {
59 #pragma omp for collapse(3)
60 #pragma omp tile sizes(5)
61 for (int i = 7; i < 17; i += 3)
62 for (int j = 7; j < 17; j += 3)
63 body(i, j);
64 }
65
66
foo6()67 extern "C" void foo6() {
68 #pragma omp parallel for
69 #pragma omp tile sizes(5)
70 for (int i = 7; i < 17; i += 3)
71 body(i);
72 }
73
74
75 template<typename T, T Step, T Tile>
foo7(T start,T end)76 void foo7(T start, T end) {
77 #pragma omp tile sizes(Tile)
78 for (T i = start; i < end; i += Step)
79 body(i);
80 }
81
tfoo7()82 extern "C" void tfoo7() {
83 foo7<int,3,5>(0, 42);
84 }
85
86 #endif /* HEADER */
87 // CHECK1-LABEL: define {{[^@]+}}@body
88 // CHECK1-SAME: (...) #[[ATTR0:[0-9]+]] {
89 // CHECK1-NEXT: entry:
90 // CHECK1-NEXT: ret void
91 //
92 //
93 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
94 // CHECK1-SAME: () #[[ATTR1:[0-9]+]] section ".text.startup" {
95 // CHECK1-NEXT: entry:
96 // CHECK1-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @s)
97 // CHECK1-NEXT: ret void
98 //
99 //
100 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC1Ev
101 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
102 // CHECK1-NEXT: entry:
103 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
104 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
105 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
106 // CHECK1-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
107 // CHECK1-NEXT: ret void
108 //
109 //
110 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SC2Ev
111 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
112 // CHECK1-NEXT: entry:
113 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
114 // CHECK1-NEXT: [[I:%.*]] = alloca i32*, align 8
115 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
116 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
117 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
118 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
119 // CHECK1-NEXT: [[I2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
120 // CHECK1-NEXT: store i32* [[I2]], i32** [[I]], align 8
121 // CHECK1-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
122 // CHECK1-NEXT: br label [[FOR_COND:%.*]]
123 // CHECK1: for.cond:
124 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
125 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4
126 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END11:%.*]]
127 // CHECK1: for.body:
128 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
129 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTTILE_0_IV_I]], align 4
130 // CHECK1-NEXT: br label [[FOR_COND3:%.*]]
131 // CHECK1: for.cond3:
132 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
133 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
134 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 5
135 // CHECK1-NEXT: [[CMP4:%.*]] = icmp slt i32 4, [[ADD]]
136 // CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
137 // CHECK1: cond.true:
138 // CHECK1-NEXT: br label [[COND_END:%.*]]
139 // CHECK1: cond.false:
140 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
141 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP4]], 5
142 // CHECK1-NEXT: br label [[COND_END]]
143 // CHECK1: cond.end:
144 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD5]], [[COND_FALSE]] ]
145 // CHECK1-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP2]], [[COND]]
146 // CHECK1-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END:%.*]]
147 // CHECK1: for.body7:
148 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
149 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 3
150 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL]]
151 // CHECK1-NEXT: [[TMP6:%.*]] = load i32*, i32** [[I]], align 8
152 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[TMP6]], align 4
153 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[I]], align 8
154 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
155 // CHECK1-NEXT: call void (...) @body(i32 [[TMP8]])
156 // CHECK1-NEXT: br label [[FOR_INC:%.*]]
157 // CHECK1: for.inc:
158 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
159 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
160 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
161 // CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP2:![0-9]+]]
162 // CHECK1: for.end:
163 // CHECK1-NEXT: br label [[FOR_INC9:%.*]]
164 // CHECK1: for.inc9:
165 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
166 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP10]], 5
167 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTFLOOR_0_IV_I]], align 4
168 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
169 // CHECK1: for.end11:
170 // CHECK1-NEXT: ret void
171 //
172 //
173 // CHECK1-LABEL: define {{[^@]+}}@foo1
174 // CHECK1-SAME: (i32 [[START:%.*]], i32 [[END:%.*]], i32 [[STEP:%.*]]) #[[ATTR0]] {
175 // CHECK1-NEXT: entry:
176 // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
177 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
178 // CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
179 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
180 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
181 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
182 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
183 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
184 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
185 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
186 // CHECK1-NEXT: store i32 [[START]], i32* [[START_ADDR]], align 4
187 // CHECK1-NEXT: store i32 [[END]], i32* [[END_ADDR]], align 4
188 // CHECK1-NEXT: store i32 [[STEP]], i32* [[STEP_ADDR]], align 4
189 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[START_ADDR]], align 4
190 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
191 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[END_ADDR]], align 4
192 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
193 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[STEP_ADDR]], align 4
194 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
195 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
196 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
197 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
198 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
199 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
200 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], [[TMP5]]
201 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
202 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP6]]
203 // CHECK1-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1
204 // CHECK1-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
205 // CHECK1-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
206 // CHECK1-NEXT: br label [[FOR_COND:%.*]]
207 // CHECK1: for.cond:
208 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
209 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
210 // CHECK1-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1
211 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]
212 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END18:%.*]]
213 // CHECK1: for.body:
214 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
215 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[DOTTILE_0_IV_I]], align 4
216 // CHECK1-NEXT: br label [[FOR_COND7:%.*]]
217 // CHECK1: for.cond7:
218 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
219 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
220 // CHECK1-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 1
221 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
222 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 5
223 // CHECK1-NEXT: [[CMP10:%.*]] = icmp ult i32 [[ADD8]], [[ADD9]]
224 // CHECK1-NEXT: br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
225 // CHECK1: cond.true:
226 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
227 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP13]], 1
228 // CHECK1-NEXT: br label [[COND_END:%.*]]
229 // CHECK1: cond.false:
230 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
231 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP14]], 5
232 // CHECK1-NEXT: br label [[COND_END]]
233 // CHECK1: cond.end:
234 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD11]], [[COND_TRUE]] ], [ [[ADD12]], [[COND_FALSE]] ]
235 // CHECK1-NEXT: [[CMP13:%.*]] = icmp ult i32 [[TMP10]], [[COND]]
236 // CHECK1-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END:%.*]]
237 // CHECK1: for.body14:
238 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
239 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
240 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
241 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP16]], [[TMP17]]
242 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], [[MUL]]
243 // CHECK1-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
244 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
245 // CHECK1-NEXT: call void (...) @body(i32 [[TMP18]])
246 // CHECK1-NEXT: br label [[FOR_INC:%.*]]
247 // CHECK1: for.inc:
248 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
249 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1
250 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
251 // CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP5:![0-9]+]]
252 // CHECK1: for.end:
253 // CHECK1-NEXT: br label [[FOR_INC16:%.*]]
254 // CHECK1: for.inc16:
255 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
256 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 5
257 // CHECK1-NEXT: store i32 [[ADD17]], i32* [[DOTFLOOR_0_IV_I]], align 4
258 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
259 // CHECK1: for.end18:
260 // CHECK1-NEXT: ret void
261 //
262 //
263 // CHECK1-LABEL: define {{[^@]+}}@foo2
264 // CHECK1-SAME: (i32 [[START:%.*]], i32 [[END:%.*]], i32 [[STEP:%.*]]) #[[ATTR0]] {
265 // CHECK1-NEXT: entry:
266 // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
267 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
268 // CHECK1-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
269 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
270 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
271 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
272 // CHECK1-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4
273 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
274 // CHECK1-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4
275 // CHECK1-NEXT: store i32 [[START]], i32* [[START_ADDR]], align 4
276 // CHECK1-NEXT: store i32 [[END]], i32* [[END_ADDR]], align 4
277 // CHECK1-NEXT: store i32 [[STEP]], i32* [[STEP_ADDR]], align 4
278 // CHECK1-NEXT: store i32 7, i32* [[I]], align 4
279 // CHECK1-NEXT: store i32 7, i32* [[J]], align 4
280 // CHECK1-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
281 // CHECK1-NEXT: br label [[FOR_COND:%.*]]
282 // CHECK1: for.cond:
283 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
284 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4
285 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END30:%.*]]
286 // CHECK1: for.body:
287 // CHECK1-NEXT: store i32 0, i32* [[DOTFLOOR_1_IV_J]], align 4
288 // CHECK1-NEXT: br label [[FOR_COND1:%.*]]
289 // CHECK1: for.cond1:
290 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
291 // CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 4
292 // CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END27:%.*]]
293 // CHECK1: for.body3:
294 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
295 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTTILE_0_IV_I]], align 4
296 // CHECK1-NEXT: br label [[FOR_COND4:%.*]]
297 // CHECK1: for.cond4:
298 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
299 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
300 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 5
301 // CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD]]
302 // CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
303 // CHECK1: cond.true:
304 // CHECK1-NEXT: br label [[COND_END:%.*]]
305 // CHECK1: cond.false:
306 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
307 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 5
308 // CHECK1-NEXT: br label [[COND_END]]
309 // CHECK1: cond.end:
310 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD6]], [[COND_FALSE]] ]
311 // CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP3]], [[COND]]
312 // CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END24:%.*]]
313 // CHECK1: for.body8:
314 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
315 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 3
316 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]]
317 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[I]], align 4
318 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
319 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTTILE_1_IV_J]], align 4
320 // CHECK1-NEXT: br label [[FOR_COND10:%.*]]
321 // CHECK1: for.cond10:
322 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
323 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
324 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP9]], 5
325 // CHECK1-NEXT: [[CMP12:%.*]] = icmp slt i32 4, [[ADD11]]
326 // CHECK1-NEXT: br i1 [[CMP12]], label [[COND_TRUE13:%.*]], label [[COND_FALSE14:%.*]]
327 // CHECK1: cond.true13:
328 // CHECK1-NEXT: br label [[COND_END16:%.*]]
329 // CHECK1: cond.false14:
330 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
331 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP10]], 5
332 // CHECK1-NEXT: br label [[COND_END16]]
333 // CHECK1: cond.end16:
334 // CHECK1-NEXT: [[COND17:%.*]] = phi i32 [ 4, [[COND_TRUE13]] ], [ [[ADD15]], [[COND_FALSE14]] ]
335 // CHECK1-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP8]], [[COND17]]
336 // CHECK1-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]]
337 // CHECK1: for.body19:
338 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
339 // CHECK1-NEXT: [[MUL20:%.*]] = mul nsw i32 [[TMP11]], 3
340 // CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 7, [[MUL20]]
341 // CHECK1-NEXT: store i32 [[ADD21]], i32* [[J]], align 4
342 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
343 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4
344 // CHECK1-NEXT: call void (...) @body(i32 [[TMP12]], i32 [[TMP13]])
345 // CHECK1-NEXT: br label [[FOR_INC:%.*]]
346 // CHECK1: for.inc:
347 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
348 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
349 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
350 // CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]
351 // CHECK1: for.end:
352 // CHECK1-NEXT: br label [[FOR_INC22:%.*]]
353 // CHECK1: for.inc22:
354 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
355 // CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
356 // CHECK1-NEXT: store i32 [[INC23]], i32* [[DOTTILE_0_IV_I]], align 4
357 // CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP8:![0-9]+]]
358 // CHECK1: for.end24:
359 // CHECK1-NEXT: br label [[FOR_INC25:%.*]]
360 // CHECK1: for.inc25:
361 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
362 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5
363 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTFLOOR_1_IV_J]], align 4
364 // CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP9:![0-9]+]]
365 // CHECK1: for.end27:
366 // CHECK1-NEXT: br label [[FOR_INC28:%.*]]
367 // CHECK1: for.inc28:
368 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
369 // CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5
370 // CHECK1-NEXT: store i32 [[ADD29]], i32* [[DOTFLOOR_0_IV_I]], align 4
371 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
372 // CHECK1: for.end30:
373 // CHECK1-NEXT: ret void
374 //
375 //
376 // CHECK1-LABEL: define {{[^@]+}}@foo3
377 // CHECK1-SAME: () #[[ATTR0]] {
378 // CHECK1-NEXT: entry:
379 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
380 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
381 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
382 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
383 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
384 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
385 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
386 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
387 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
388 // CHECK1-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4
389 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
390 // CHECK1-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4
391 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
392 // CHECK1-NEXT: store i32 7, i32* [[I]], align 4
393 // CHECK1-NEXT: store i32 7, i32* [[J]], align 4
394 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
395 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_UB]], align 4
396 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
397 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
398 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
399 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
400 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 0
401 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
402 // CHECK1: cond.true:
403 // CHECK1-NEXT: br label [[COND_END:%.*]]
404 // CHECK1: cond.false:
405 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
406 // CHECK1-NEXT: br label [[COND_END]]
407 // CHECK1: cond.end:
408 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
409 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
410 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
411 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4
412 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
413 // CHECK1: omp.inner.for.cond:
414 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
415 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
416 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
417 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
418 // CHECK1: omp.inner.for.body:
419 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
420 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 5
421 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
422 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTFLOOR_0_IV_I]], align 4
423 // CHECK1-NEXT: store i32 0, i32* [[DOTFLOOR_1_IV_J]], align 4
424 // CHECK1-NEXT: br label [[FOR_COND:%.*]]
425 // CHECK1: for.cond:
426 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
427 // CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP7]], 4
428 // CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END32:%.*]]
429 // CHECK1: for.body:
430 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
431 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTTILE_0_IV_I]], align 4
432 // CHECK1-NEXT: br label [[FOR_COND3:%.*]]
433 // CHECK1: for.cond3:
434 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
435 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
436 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 5
437 // CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD4]]
438 // CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
439 // CHECK1: cond.true6:
440 // CHECK1-NEXT: br label [[COND_END9:%.*]]
441 // CHECK1: cond.false7:
442 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
443 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 5
444 // CHECK1-NEXT: br label [[COND_END9]]
445 // CHECK1: cond.end9:
446 // CHECK1-NEXT: [[COND10:%.*]] = phi i32 [ 4, [[COND_TRUE6]] ], [ [[ADD8]], [[COND_FALSE7]] ]
447 // CHECK1-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP9]], [[COND10]]
448 // CHECK1-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END29:%.*]]
449 // CHECK1: for.body12:
450 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
451 // CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP12]], 3
452 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 7, [[MUL13]]
453 // CHECK1-NEXT: store i32 [[ADD14]], i32* [[I]], align 4
454 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
455 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTTILE_1_IV_J]], align 4
456 // CHECK1-NEXT: br label [[FOR_COND15:%.*]]
457 // CHECK1: for.cond15:
458 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
459 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
460 // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP15]], 5
461 // CHECK1-NEXT: [[CMP17:%.*]] = icmp slt i32 4, [[ADD16]]
462 // CHECK1-NEXT: br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]]
463 // CHECK1: cond.true18:
464 // CHECK1-NEXT: br label [[COND_END21:%.*]]
465 // CHECK1: cond.false19:
466 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
467 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 5
468 // CHECK1-NEXT: br label [[COND_END21]]
469 // CHECK1: cond.end21:
470 // CHECK1-NEXT: [[COND22:%.*]] = phi i32 [ 4, [[COND_TRUE18]] ], [ [[ADD20]], [[COND_FALSE19]] ]
471 // CHECK1-NEXT: [[CMP23:%.*]] = icmp slt i32 [[TMP14]], [[COND22]]
472 // CHECK1-NEXT: br i1 [[CMP23]], label [[FOR_BODY24:%.*]], label [[FOR_END:%.*]]
473 // CHECK1: for.body24:
474 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
475 // CHECK1-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP17]], 3
476 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 7, [[MUL25]]
477 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[J]], align 4
478 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
479 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[J]], align 4
480 // CHECK1-NEXT: call void (...) @body(i32 [[TMP18]], i32 [[TMP19]])
481 // CHECK1-NEXT: br label [[FOR_INC:%.*]]
482 // CHECK1: for.inc:
483 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
484 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1
485 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
486 // CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP11:![0-9]+]]
487 // CHECK1: for.end:
488 // CHECK1-NEXT: br label [[FOR_INC27:%.*]]
489 // CHECK1: for.inc27:
490 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
491 // CHECK1-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1
492 // CHECK1-NEXT: store i32 [[INC28]], i32* [[DOTTILE_0_IV_I]], align 4
493 // CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP12:![0-9]+]]
494 // CHECK1: for.end29:
495 // CHECK1-NEXT: br label [[FOR_INC30:%.*]]
496 // CHECK1: for.inc30:
497 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
498 // CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5
499 // CHECK1-NEXT: store i32 [[ADD31]], i32* [[DOTFLOOR_1_IV_J]], align 4
500 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
501 // CHECK1: for.end32:
502 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
503 // CHECK1: omp.body.continue:
504 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
505 // CHECK1: omp.inner.for.inc:
506 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
507 // CHECK1-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1
508 // CHECK1-NEXT: store i32 [[ADD33]], i32* [[DOTOMP_IV]], align 4
509 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
510 // CHECK1: omp.inner.for.end:
511 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
512 // CHECK1: omp.loop.exit:
513 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
514 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]])
515 // CHECK1-NEXT: ret void
516 //
517 //
518 // CHECK1-LABEL: define {{[^@]+}}@foo4
519 // CHECK1-SAME: () #[[ATTR0]] {
520 // CHECK1-NEXT: entry:
521 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
522 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
523 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
524 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
525 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
526 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
527 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
528 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
529 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
530 // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4
531 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
532 // CHECK1-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4
533 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
534 // CHECK1-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4
535 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
536 // CHECK1-NEXT: store i32 7, i32* [[I]], align 4
537 // CHECK1-NEXT: store i32 7, i32* [[J]], align 4
538 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
539 // CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
540 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
541 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
542 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
543 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
544 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 3
545 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
546 // CHECK1: cond.true:
547 // CHECK1-NEXT: br label [[COND_END:%.*]]
548 // CHECK1: cond.false:
549 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
550 // CHECK1-NEXT: br label [[COND_END]]
551 // CHECK1: cond.end:
552 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
553 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
554 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
555 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4
556 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
557 // CHECK1: omp.inner.for.cond:
558 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
559 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
560 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
561 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
562 // CHECK1: omp.inner.for.body:
563 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
564 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 1
565 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3
566 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
567 // CHECK1-NEXT: store i32 [[ADD]], i32* [[K]], align 4
568 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
569 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
570 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 1
571 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 1
572 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]]
573 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 5
574 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
575 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[DOTFLOOR_0_IV_I]], align 4
576 // CHECK1-NEXT: store i32 0, i32* [[DOTFLOOR_1_IV_J]], align 4
577 // CHECK1-NEXT: br label [[FOR_COND:%.*]]
578 // CHECK1: for.cond:
579 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
580 // CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP9]], 4
581 // CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY:%.*]], label [[FOR_END37:%.*]]
582 // CHECK1: for.body:
583 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
584 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[DOTTILE_0_IV_I]], align 4
585 // CHECK1-NEXT: br label [[FOR_COND8:%.*]]
586 // CHECK1: for.cond8:
587 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
588 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
589 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 5
590 // CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 4, [[ADD9]]
591 // CHECK1-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
592 // CHECK1: cond.true11:
593 // CHECK1-NEXT: br label [[COND_END14:%.*]]
594 // CHECK1: cond.false12:
595 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
596 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP13]], 5
597 // CHECK1-NEXT: br label [[COND_END14]]
598 // CHECK1: cond.end14:
599 // CHECK1-NEXT: [[COND15:%.*]] = phi i32 [ 4, [[COND_TRUE11]] ], [ [[ADD13]], [[COND_FALSE12]] ]
600 // CHECK1-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP11]], [[COND15]]
601 // CHECK1-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END34:%.*]]
602 // CHECK1: for.body17:
603 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
604 // CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i32 [[TMP14]], 3
605 // CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]]
606 // CHECK1-NEXT: store i32 [[ADD19]], i32* [[I]], align 4
607 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
608 // CHECK1-NEXT: store i32 [[TMP15]], i32* [[DOTTILE_1_IV_J]], align 4
609 // CHECK1-NEXT: br label [[FOR_COND20:%.*]]
610 // CHECK1: for.cond20:
611 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
612 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
613 // CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP17]], 5
614 // CHECK1-NEXT: [[CMP22:%.*]] = icmp slt i32 4, [[ADD21]]
615 // CHECK1-NEXT: br i1 [[CMP22]], label [[COND_TRUE23:%.*]], label [[COND_FALSE24:%.*]]
616 // CHECK1: cond.true23:
617 // CHECK1-NEXT: br label [[COND_END26:%.*]]
618 // CHECK1: cond.false24:
619 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
620 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP18]], 5
621 // CHECK1-NEXT: br label [[COND_END26]]
622 // CHECK1: cond.end26:
623 // CHECK1-NEXT: [[COND27:%.*]] = phi i32 [ 4, [[COND_TRUE23]] ], [ [[ADD25]], [[COND_FALSE24]] ]
624 // CHECK1-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP16]], [[COND27]]
625 // CHECK1-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END:%.*]]
626 // CHECK1: for.body29:
627 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
628 // CHECK1-NEXT: [[MUL30:%.*]] = mul nsw i32 [[TMP19]], 3
629 // CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 7, [[MUL30]]
630 // CHECK1-NEXT: store i32 [[ADD31]], i32* [[J]], align 4
631 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
632 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[J]], align 4
633 // CHECK1-NEXT: call void (...) @body(i32 [[TMP20]], i32 [[TMP21]])
634 // CHECK1-NEXT: br label [[FOR_INC:%.*]]
635 // CHECK1: for.inc:
636 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
637 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1
638 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
639 // CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP14:![0-9]+]]
640 // CHECK1: for.end:
641 // CHECK1-NEXT: br label [[FOR_INC32:%.*]]
642 // CHECK1: for.inc32:
643 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
644 // CHECK1-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1
645 // CHECK1-NEXT: store i32 [[INC33]], i32* [[DOTTILE_0_IV_I]], align 4
646 // CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP15:![0-9]+]]
647 // CHECK1: for.end34:
648 // CHECK1-NEXT: br label [[FOR_INC35:%.*]]
649 // CHECK1: for.inc35:
650 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
651 // CHECK1-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5
652 // CHECK1-NEXT: store i32 [[ADD36]], i32* [[DOTFLOOR_1_IV_J]], align 4
653 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
654 // CHECK1: for.end37:
655 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
656 // CHECK1: omp.body.continue:
657 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
658 // CHECK1: omp.inner.for.inc:
659 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
660 // CHECK1-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1
661 // CHECK1-NEXT: store i32 [[ADD38]], i32* [[DOTOMP_IV]], align 4
662 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
663 // CHECK1: omp.inner.for.end:
664 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
665 // CHECK1: omp.loop.exit:
666 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
667 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]])
668 // CHECK1-NEXT: ret void
669 //
670 //
671 // CHECK1-LABEL: define {{[^@]+}}@foo5
672 // CHECK1-SAME: () #[[ATTR0]] {
673 // CHECK1-NEXT: entry:
674 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
675 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
676 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
677 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
678 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
679 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
680 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
681 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
682 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
683 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
684 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
685 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
686 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
687 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
688 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
689 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 4
690 // CHECK1-NEXT: [[DOTTILE_0_IV_I12:%.*]] = alloca i32, align 4
691 // CHECK1-NEXT: [[J13:%.*]] = alloca i32, align 4
692 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
693 // CHECK1-NEXT: store i32 7, i32* [[I]], align 4
694 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 4
695 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
696 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP]], align 4
697 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5
698 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 4, [[ADD]]
699 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
700 // CHECK1: cond.true:
701 // CHECK1-NEXT: br label [[COND_END:%.*]]
702 // CHECK1: cond.false:
703 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP]], align 4
704 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 5
705 // CHECK1-NEXT: br label [[COND_END]]
706 // CHECK1: cond.end:
707 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD4]], [[COND_FALSE]] ]
708 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTCAPTURE_EXPR_3]], align 4
709 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
710 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
711 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]
712 // CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
713 // CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[SUB6]], 1
714 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD7]], 1
715 // CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV]] to i64
716 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 1, [[CONV]]
717 // CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i64 [[MUL]], 4
718 // CHECK1-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL8]], 1
719 // CHECK1-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
720 // CHECK1-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
721 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
722 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[DOTTILE_0_IV_I]], align 4
723 // CHECK1-NEXT: store i32 7, i32* [[J]], align 4
724 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
725 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
726 // CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]
727 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
728 // CHECK1: omp.precond.then:
729 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
730 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
731 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8
732 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
733 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
734 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
735 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
736 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
737 // CHECK1-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
738 // CHECK1-NEXT: br i1 [[CMP14]], label [[COND_TRUE15:%.*]], label [[COND_FALSE16:%.*]]
739 // CHECK1: cond.true15:
740 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
741 // CHECK1-NEXT: br label [[COND_END17:%.*]]
742 // CHECK1: cond.false16:
743 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
744 // CHECK1-NEXT: br label [[COND_END17]]
745 // CHECK1: cond.end17:
746 // CHECK1-NEXT: [[COND18:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE15]] ], [ [[TMP13]], [[COND_FALSE16]] ]
747 // CHECK1-NEXT: store i64 [[COND18]], i64* [[DOTOMP_UB]], align 8
748 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
749 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8
750 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
751 // CHECK1: omp.inner.for.cond:
752 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
753 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
754 // CHECK1-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP15]], [[TMP16]]
755 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
756 // CHECK1: omp.inner.for.body:
757 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
758 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
759 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
760 // CHECK1-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]
761 // CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1
762 // CHECK1-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1
763 // CHECK1-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
764 // CHECK1-NEXT: [[MUL24:%.*]] = mul i32 1, [[DIV23]]
765 // CHECK1-NEXT: [[MUL25:%.*]] = mul i32 [[MUL24]], 4
766 // CHECK1-NEXT: [[CONV26:%.*]] = zext i32 [[MUL25]] to i64
767 // CHECK1-NEXT: [[DIV27:%.*]] = sdiv i64 [[TMP17]], [[CONV26]]
768 // CHECK1-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV27]], 5
769 // CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 0, [[MUL28]]
770 // CHECK1-NEXT: [[CONV30:%.*]] = trunc i64 [[ADD29]] to i32
771 // CHECK1-NEXT: store i32 [[CONV30]], i32* [[DOTFLOOR_0_IV_I11]], align 4
772 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
773 // CHECK1-NEXT: [[CONV31:%.*]] = sext i32 [[TMP20]] to i64
774 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
775 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
776 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
777 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
778 // CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP23]], [[TMP24]]
779 // CHECK1-NEXT: [[SUB33:%.*]] = sub i32 [[SUB32]], 1
780 // CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[SUB33]], 1
781 // CHECK1-NEXT: [[DIV35:%.*]] = udiv i32 [[ADD34]], 1
782 // CHECK1-NEXT: [[MUL36:%.*]] = mul i32 1, [[DIV35]]
783 // CHECK1-NEXT: [[MUL37:%.*]] = mul i32 [[MUL36]], 4
784 // CHECK1-NEXT: [[CONV38:%.*]] = zext i32 [[MUL37]] to i64
785 // CHECK1-NEXT: [[DIV39:%.*]] = sdiv i64 [[TMP22]], [[CONV38]]
786 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
787 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
788 // CHECK1-NEXT: [[SUB40:%.*]] = sub i32 [[TMP25]], [[TMP26]]
789 // CHECK1-NEXT: [[SUB41:%.*]] = sub i32 [[SUB40]], 1
790 // CHECK1-NEXT: [[ADD42:%.*]] = add i32 [[SUB41]], 1
791 // CHECK1-NEXT: [[DIV43:%.*]] = udiv i32 [[ADD42]], 1
792 // CHECK1-NEXT: [[MUL44:%.*]] = mul i32 1, [[DIV43]]
793 // CHECK1-NEXT: [[MUL45:%.*]] = mul i32 [[MUL44]], 4
794 // CHECK1-NEXT: [[CONV46:%.*]] = zext i32 [[MUL45]] to i64
795 // CHECK1-NEXT: [[MUL47:%.*]] = mul nsw i64 [[DIV39]], [[CONV46]]
796 // CHECK1-NEXT: [[SUB48:%.*]] = sub nsw i64 [[TMP21]], [[MUL47]]
797 // CHECK1-NEXT: [[DIV49:%.*]] = sdiv i64 [[SUB48]], 4
798 // CHECK1-NEXT: [[MUL50:%.*]] = mul nsw i64 [[DIV49]], 1
799 // CHECK1-NEXT: [[ADD51:%.*]] = add nsw i64 [[CONV31]], [[MUL50]]
800 // CHECK1-NEXT: [[CONV52:%.*]] = trunc i64 [[ADD51]] to i32
801 // CHECK1-NEXT: store i32 [[CONV52]], i32* [[DOTTILE_0_IV_I12]], align 4
802 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
803 // CHECK1-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
804 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
805 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
806 // CHECK1-NEXT: [[SUB53:%.*]] = sub i32 [[TMP29]], [[TMP30]]
807 // CHECK1-NEXT: [[SUB54:%.*]] = sub i32 [[SUB53]], 1
808 // CHECK1-NEXT: [[ADD55:%.*]] = add i32 [[SUB54]], 1
809 // CHECK1-NEXT: [[DIV56:%.*]] = udiv i32 [[ADD55]], 1
810 // CHECK1-NEXT: [[MUL57:%.*]] = mul i32 1, [[DIV56]]
811 // CHECK1-NEXT: [[MUL58:%.*]] = mul i32 [[MUL57]], 4
812 // CHECK1-NEXT: [[CONV59:%.*]] = zext i32 [[MUL58]] to i64
813 // CHECK1-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP28]], [[CONV59]]
814 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
815 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
816 // CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[TMP31]], [[TMP32]]
817 // CHECK1-NEXT: [[SUB62:%.*]] = sub i32 [[SUB61]], 1
818 // CHECK1-NEXT: [[ADD63:%.*]] = add i32 [[SUB62]], 1
819 // CHECK1-NEXT: [[DIV64:%.*]] = udiv i32 [[ADD63]], 1
820 // CHECK1-NEXT: [[MUL65:%.*]] = mul i32 1, [[DIV64]]
821 // CHECK1-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 4
822 // CHECK1-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
823 // CHECK1-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[CONV67]]
824 // CHECK1-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP27]], [[MUL68]]
825 // CHECK1-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
826 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
827 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
828 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
829 // CHECK1-NEXT: [[SUB70:%.*]] = sub i32 [[TMP35]], [[TMP36]]
830 // CHECK1-NEXT: [[SUB71:%.*]] = sub i32 [[SUB70]], 1
831 // CHECK1-NEXT: [[ADD72:%.*]] = add i32 [[SUB71]], 1
832 // CHECK1-NEXT: [[DIV73:%.*]] = udiv i32 [[ADD72]], 1
833 // CHECK1-NEXT: [[MUL74:%.*]] = mul i32 1, [[DIV73]]
834 // CHECK1-NEXT: [[MUL75:%.*]] = mul i32 [[MUL74]], 4
835 // CHECK1-NEXT: [[CONV76:%.*]] = zext i32 [[MUL75]] to i64
836 // CHECK1-NEXT: [[DIV77:%.*]] = sdiv i64 [[TMP34]], [[CONV76]]
837 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
838 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
839 // CHECK1-NEXT: [[SUB78:%.*]] = sub i32 [[TMP37]], [[TMP38]]
840 // CHECK1-NEXT: [[SUB79:%.*]] = sub i32 [[SUB78]], 1
841 // CHECK1-NEXT: [[ADD80:%.*]] = add i32 [[SUB79]], 1
842 // CHECK1-NEXT: [[DIV81:%.*]] = udiv i32 [[ADD80]], 1
843 // CHECK1-NEXT: [[MUL82:%.*]] = mul i32 1, [[DIV81]]
844 // CHECK1-NEXT: [[MUL83:%.*]] = mul i32 [[MUL82]], 4
845 // CHECK1-NEXT: [[CONV84:%.*]] = zext i32 [[MUL83]] to i64
846 // CHECK1-NEXT: [[MUL85:%.*]] = mul nsw i64 [[DIV77]], [[CONV84]]
847 // CHECK1-NEXT: [[SUB86:%.*]] = sub nsw i64 [[TMP33]], [[MUL85]]
848 // CHECK1-NEXT: [[DIV87:%.*]] = sdiv i64 [[SUB86]], 4
849 // CHECK1-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV87]], 4
850 // CHECK1-NEXT: [[SUB89:%.*]] = sub nsw i64 [[SUB69]], [[MUL88]]
851 // CHECK1-NEXT: [[MUL90:%.*]] = mul nsw i64 [[SUB89]], 3
852 // CHECK1-NEXT: [[ADD91:%.*]] = add nsw i64 7, [[MUL90]]
853 // CHECK1-NEXT: [[CONV92:%.*]] = trunc i64 [[ADD91]] to i32
854 // CHECK1-NEXT: store i32 [[CONV92]], i32* [[J13]], align 4
855 // CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTTILE_0_IV_I12]], align 4
856 // CHECK1-NEXT: [[MUL93:%.*]] = mul nsw i32 [[TMP39]], 3
857 // CHECK1-NEXT: [[ADD94:%.*]] = add nsw i32 7, [[MUL93]]
858 // CHECK1-NEXT: store i32 [[ADD94]], i32* [[I]], align 4
859 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[I]], align 4
860 // CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[J13]], align 4
861 // CHECK1-NEXT: call void (...) @body(i32 [[TMP40]], i32 [[TMP41]])
862 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
863 // CHECK1: omp.body.continue:
864 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
865 // CHECK1: omp.inner.for.inc:
866 // CHECK1-NEXT: [[TMP42:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
867 // CHECK1-NEXT: [[ADD95:%.*]] = add nsw i64 [[TMP42]], 1
868 // CHECK1-NEXT: store i64 [[ADD95]], i64* [[DOTOMP_IV]], align 8
869 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
870 // CHECK1: omp.inner.for.end:
871 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
872 // CHECK1: omp.loop.exit:
873 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
874 // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
875 // CHECK1: omp.precond.end:
876 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]])
877 // CHECK1-NEXT: ret void
878 //
879 //
880 // CHECK1-LABEL: define {{[^@]+}}@foo6
881 // CHECK1-SAME: () #[[ATTR0]] {
882 // CHECK1-NEXT: entry:
883 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
884 // CHECK1-NEXT: ret void
885 //
886 //
887 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
888 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
889 // CHECK1-NEXT: entry:
890 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
891 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
892 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
893 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
894 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
895 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
896 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
897 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
898 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
899 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
900 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
901 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
902 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
903 // CHECK1-NEXT: store i32 7, i32* [[I]], align 4
904 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
905 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_UB]], align 4
906 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
907 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
908 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
909 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
910 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
911 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
912 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 0
913 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
914 // CHECK1: cond.true:
915 // CHECK1-NEXT: br label [[COND_END:%.*]]
916 // CHECK1: cond.false:
917 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
918 // CHECK1-NEXT: br label [[COND_END]]
919 // CHECK1: cond.end:
920 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
921 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
922 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
923 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
924 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
925 // CHECK1: omp.inner.for.cond:
926 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
927 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
928 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
929 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
930 // CHECK1: omp.inner.for.body:
931 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
932 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
933 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
934 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTFLOOR_0_IV_I]], align 4
935 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
936 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTTILE_0_IV_I]], align 4
937 // CHECK1-NEXT: br label [[FOR_COND:%.*]]
938 // CHECK1: for.cond:
939 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
940 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
941 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 5
942 // CHECK1-NEXT: [[CMP3:%.*]] = icmp slt i32 4, [[ADD2]]
943 // CHECK1-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]]
944 // CHECK1: cond.true4:
945 // CHECK1-NEXT: br label [[COND_END7:%.*]]
946 // CHECK1: cond.false5:
947 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
948 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 5
949 // CHECK1-NEXT: br label [[COND_END7]]
950 // CHECK1: cond.end7:
951 // CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 4, [[COND_TRUE4]] ], [ [[ADD6]], [[COND_FALSE5]] ]
952 // CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP9]], [[COND8]]
953 // CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
954 // CHECK1: for.body:
955 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
956 // CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP12]], 3
957 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]]
958 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[I]], align 4
959 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
960 // CHECK1-NEXT: call void (...) @body(i32 [[TMP13]])
961 // CHECK1-NEXT: br label [[FOR_INC:%.*]]
962 // CHECK1: for.inc:
963 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
964 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
965 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
966 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
967 // CHECK1: for.end:
968 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
969 // CHECK1: omp.body.continue:
970 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
971 // CHECK1: omp.inner.for.inc:
972 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
973 // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1
974 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
975 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
976 // CHECK1: omp.inner.for.end:
977 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
978 // CHECK1: omp.loop.exit:
979 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
980 // CHECK1-NEXT: ret void
981 //
982 //
983 // CHECK1-LABEL: define {{[^@]+}}@tfoo7
984 // CHECK1-SAME: () #[[ATTR0]] {
985 // CHECK1-NEXT: entry:
986 // CHECK1-NEXT: call void @_Z4foo7IiLi3ELi5EEvT_S0_(i32 0, i32 42)
987 // CHECK1-NEXT: ret void
988 //
989 //
990 // CHECK1-LABEL: define {{[^@]+}}@_Z4foo7IiLi3ELi5EEvT_S0_
991 // CHECK1-SAME: (i32 [[START:%.*]], i32 [[END:%.*]]) #[[ATTR0]] comdat {
992 // CHECK1-NEXT: entry:
993 // CHECK1-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
994 // CHECK1-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
995 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
996 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
997 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
998 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
999 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1000 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1001 // CHECK1-NEXT: store i32 [[START]], i32* [[START_ADDR]], align 4
1002 // CHECK1-NEXT: store i32 [[END]], i32* [[END_ADDR]], align 4
1003 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[START_ADDR]], align 4
1004 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[I]], align 4
1005 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[START_ADDR]], align 4
1006 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
1007 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[END_ADDR]], align 4
1008 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
1009 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1010 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1011 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1012 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
1013 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 3
1014 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 3
1015 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
1016 // CHECK1-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1017 // CHECK1-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
1018 // CHECK1-NEXT: br label [[FOR_COND:%.*]]
1019 // CHECK1: for.cond:
1020 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1021 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1022 // CHECK1-NEXT: [[ADD5:%.*]] = add i32 [[TMP6]], 1
1023 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP5]], [[ADD5]]
1024 // CHECK1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END17:%.*]]
1025 // CHECK1: for.body:
1026 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1027 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTTILE_0_IV_I]], align 4
1028 // CHECK1-NEXT: br label [[FOR_COND6:%.*]]
1029 // CHECK1: for.cond6:
1030 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1031 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1032 // CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP9]], 1
1033 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1034 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 5
1035 // CHECK1-NEXT: [[CMP9:%.*]] = icmp ult i32 [[ADD7]], [[ADD8]]
1036 // CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1037 // CHECK1: cond.true:
1038 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1039 // CHECK1-NEXT: [[ADD10:%.*]] = add i32 [[TMP11]], 1
1040 // CHECK1-NEXT: br label [[COND_END:%.*]]
1041 // CHECK1: cond.false:
1042 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1043 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP12]], 5
1044 // CHECK1-NEXT: br label [[COND_END]]
1045 // CHECK1: cond.end:
1046 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD10]], [[COND_TRUE]] ], [ [[ADD11]], [[COND_FALSE]] ]
1047 // CHECK1-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP8]], [[COND]]
1048 // CHECK1-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]
1049 // CHECK1: for.body13:
1050 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1051 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1052 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP14]], 3
1053 // CHECK1-NEXT: [[ADD14:%.*]] = add i32 [[TMP13]], [[MUL]]
1054 // CHECK1-NEXT: store i32 [[ADD14]], i32* [[I]], align 4
1055 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
1056 // CHECK1-NEXT: call void (...) @body(i32 [[TMP15]])
1057 // CHECK1-NEXT: br label [[FOR_INC:%.*]]
1058 // CHECK1: for.inc:
1059 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1060 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1
1061 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
1062 // CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP20:![0-9]+]]
1063 // CHECK1: for.end:
1064 // CHECK1-NEXT: br label [[FOR_INC15:%.*]]
1065 // CHECK1: for.inc15:
1066 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1067 // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP17]], 5
1068 // CHECK1-NEXT: store i32 [[ADD16]], i32* [[DOTFLOOR_0_IV_I]], align 4
1069 // CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
1070 // CHECK1: for.end17:
1071 // CHECK1-NEXT: ret void
1072 //
1073 //
1074 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_tile_codegen.cpp
1075 // CHECK1-SAME: () #[[ATTR1]] section ".text.startup" {
1076 // CHECK1-NEXT: entry:
1077 // CHECK1-NEXT: call void @__cxx_global_var_init()
1078 // CHECK1-NEXT: ret void
1079 //
1080 //
1081 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
1082 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] section ".text.startup" {
1083 // CHECK2-NEXT: entry:
1084 // CHECK2-NEXT: call void @_ZN1SC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @s)
1085 // CHECK2-NEXT: ret void
1086 //
1087 //
1088 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC1Ev
1089 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1090 // CHECK2-NEXT: entry:
1091 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1092 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1093 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1094 // CHECK2-NEXT: call void @_ZN1SC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1095 // CHECK2-NEXT: ret void
1096 //
1097 //
1098 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SC2Ev
1099 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1100 // CHECK2-NEXT: entry:
1101 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1102 // CHECK2-NEXT: [[I:%.*]] = alloca i32*, align 8
1103 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1104 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1105 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1106 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1107 // CHECK2-NEXT: [[I2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1108 // CHECK2-NEXT: store i32* [[I2]], i32** [[I]], align 8
1109 // CHECK2-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
1110 // CHECK2-NEXT: br label [[FOR_COND:%.*]]
1111 // CHECK2: for.cond:
1112 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1113 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4
1114 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END11:%.*]]
1115 // CHECK2: for.body:
1116 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1117 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTTILE_0_IV_I]], align 4
1118 // CHECK2-NEXT: br label [[FOR_COND3:%.*]]
1119 // CHECK2: for.cond3:
1120 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1121 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1122 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 5
1123 // CHECK2-NEXT: [[CMP4:%.*]] = icmp slt i32 4, [[ADD]]
1124 // CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1125 // CHECK2: cond.true:
1126 // CHECK2-NEXT: br label [[COND_END:%.*]]
1127 // CHECK2: cond.false:
1128 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1129 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP4]], 5
1130 // CHECK2-NEXT: br label [[COND_END]]
1131 // CHECK2: cond.end:
1132 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD5]], [[COND_FALSE]] ]
1133 // CHECK2-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP2]], [[COND]]
1134 // CHECK2-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END:%.*]]
1135 // CHECK2: for.body7:
1136 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1137 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 3
1138 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL]]
1139 // CHECK2-NEXT: [[TMP6:%.*]] = load i32*, i32** [[I]], align 8
1140 // CHECK2-NEXT: store i32 [[ADD8]], i32* [[TMP6]], align 4
1141 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[I]], align 8
1142 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4
1143 // CHECK2-NEXT: call void (...) @body(i32 [[TMP8]])
1144 // CHECK2-NEXT: br label [[FOR_INC:%.*]]
1145 // CHECK2: for.inc:
1146 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1147 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1
1148 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
1149 // CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP2:![0-9]+]]
1150 // CHECK2: for.end:
1151 // CHECK2-NEXT: br label [[FOR_INC9:%.*]]
1152 // CHECK2: for.inc9:
1153 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1154 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP10]], 5
1155 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTFLOOR_0_IV_I]], align 4
1156 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1157 // CHECK2: for.end11:
1158 // CHECK2-NEXT: ret void
1159 //
1160 //
1161 // CHECK2-LABEL: define {{[^@]+}}@body
1162 // CHECK2-SAME: (...) #[[ATTR2:[0-9]+]] {
1163 // CHECK2-NEXT: entry:
1164 // CHECK2-NEXT: ret void
1165 //
1166 //
1167 // CHECK2-LABEL: define {{[^@]+}}@foo1
1168 // CHECK2-SAME: (i32 [[START:%.*]], i32 [[END:%.*]], i32 [[STEP:%.*]]) #[[ATTR2]] {
1169 // CHECK2-NEXT: entry:
1170 // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
1171 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
1172 // CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
1173 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1174 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1175 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1176 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1177 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
1178 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1179 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1180 // CHECK2-NEXT: store i32 [[START]], i32* [[START_ADDR]], align 4
1181 // CHECK2-NEXT: store i32 [[END]], i32* [[END_ADDR]], align 4
1182 // CHECK2-NEXT: store i32 [[STEP]], i32* [[STEP_ADDR]], align 4
1183 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[START_ADDR]], align 4
1184 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4
1185 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[END_ADDR]], align 4
1186 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_1]], align 4
1187 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[STEP_ADDR]], align 4
1188 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_2]], align 4
1189 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
1190 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1191 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1192 // CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[SUB]], 1
1193 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1194 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB4]], [[TMP5]]
1195 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1196 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP6]]
1197 // CHECK2-NEXT: [[SUB5:%.*]] = sub i32 [[DIV]], 1
1198 // CHECK2-NEXT: store i32 [[SUB5]], i32* [[DOTCAPTURE_EXPR_3]], align 4
1199 // CHECK2-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
1200 // CHECK2-NEXT: br label [[FOR_COND:%.*]]
1201 // CHECK2: for.cond:
1202 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1203 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1204 // CHECK2-NEXT: [[ADD6:%.*]] = add i32 [[TMP8]], 1
1205 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]
1206 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END18:%.*]]
1207 // CHECK2: for.body:
1208 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1209 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[DOTTILE_0_IV_I]], align 4
1210 // CHECK2-NEXT: br label [[FOR_COND7:%.*]]
1211 // CHECK2: for.cond7:
1212 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1213 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1214 // CHECK2-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 1
1215 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1216 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 5
1217 // CHECK2-NEXT: [[CMP10:%.*]] = icmp ult i32 [[ADD8]], [[ADD9]]
1218 // CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1219 // CHECK2: cond.true:
1220 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1221 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP13]], 1
1222 // CHECK2-NEXT: br label [[COND_END:%.*]]
1223 // CHECK2: cond.false:
1224 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1225 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP14]], 5
1226 // CHECK2-NEXT: br label [[COND_END]]
1227 // CHECK2: cond.end:
1228 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD11]], [[COND_TRUE]] ], [ [[ADD12]], [[COND_FALSE]] ]
1229 // CHECK2-NEXT: [[CMP13:%.*]] = icmp ult i32 [[TMP10]], [[COND]]
1230 // CHECK2-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END:%.*]]
1231 // CHECK2: for.body14:
1232 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1233 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1234 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
1235 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP16]], [[TMP17]]
1236 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], [[MUL]]
1237 // CHECK2-NEXT: store i32 [[ADD15]], i32* [[I]], align 4
1238 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
1239 // CHECK2-NEXT: call void (...) @body(i32 [[TMP18]])
1240 // CHECK2-NEXT: br label [[FOR_INC:%.*]]
1241 // CHECK2: for.inc:
1242 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1243 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1
1244 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
1245 // CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP5:![0-9]+]]
1246 // CHECK2: for.end:
1247 // CHECK2-NEXT: br label [[FOR_INC16:%.*]]
1248 // CHECK2: for.inc16:
1249 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1250 // CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP20]], 5
1251 // CHECK2-NEXT: store i32 [[ADD17]], i32* [[DOTFLOOR_0_IV_I]], align 4
1252 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
1253 // CHECK2: for.end18:
1254 // CHECK2-NEXT: ret void
1255 //
1256 //
1257 // CHECK2-LABEL: define {{[^@]+}}@foo2
1258 // CHECK2-SAME: (i32 [[START:%.*]], i32 [[END:%.*]], i32 [[STEP:%.*]]) #[[ATTR2]] {
1259 // CHECK2-NEXT: entry:
1260 // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
1261 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
1262 // CHECK2-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4
1263 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1264 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
1265 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1266 // CHECK2-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4
1267 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1268 // CHECK2-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4
1269 // CHECK2-NEXT: store i32 [[START]], i32* [[START_ADDR]], align 4
1270 // CHECK2-NEXT: store i32 [[END]], i32* [[END_ADDR]], align 4
1271 // CHECK2-NEXT: store i32 [[STEP]], i32* [[STEP_ADDR]], align 4
1272 // CHECK2-NEXT: store i32 7, i32* [[I]], align 4
1273 // CHECK2-NEXT: store i32 7, i32* [[J]], align 4
1274 // CHECK2-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
1275 // CHECK2-NEXT: br label [[FOR_COND:%.*]]
1276 // CHECK2: for.cond:
1277 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1278 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 4
1279 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END30:%.*]]
1280 // CHECK2: for.body:
1281 // CHECK2-NEXT: store i32 0, i32* [[DOTFLOOR_1_IV_J]], align 4
1282 // CHECK2-NEXT: br label [[FOR_COND1:%.*]]
1283 // CHECK2: for.cond1:
1284 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1285 // CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 4
1286 // CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END27:%.*]]
1287 // CHECK2: for.body3:
1288 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1289 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTTILE_0_IV_I]], align 4
1290 // CHECK2-NEXT: br label [[FOR_COND4:%.*]]
1291 // CHECK2: for.cond4:
1292 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1293 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1294 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 5
1295 // CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD]]
1296 // CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1297 // CHECK2: cond.true:
1298 // CHECK2-NEXT: br label [[COND_END:%.*]]
1299 // CHECK2: cond.false:
1300 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1301 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 5
1302 // CHECK2-NEXT: br label [[COND_END]]
1303 // CHECK2: cond.end:
1304 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD6]], [[COND_FALSE]] ]
1305 // CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP3]], [[COND]]
1306 // CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY8:%.*]], label [[FOR_END24:%.*]]
1307 // CHECK2: for.body8:
1308 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1309 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 3
1310 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]]
1311 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[I]], align 4
1312 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1313 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTTILE_1_IV_J]], align 4
1314 // CHECK2-NEXT: br label [[FOR_COND10:%.*]]
1315 // CHECK2: for.cond10:
1316 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1317 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1318 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP9]], 5
1319 // CHECK2-NEXT: [[CMP12:%.*]] = icmp slt i32 4, [[ADD11]]
1320 // CHECK2-NEXT: br i1 [[CMP12]], label [[COND_TRUE13:%.*]], label [[COND_FALSE14:%.*]]
1321 // CHECK2: cond.true13:
1322 // CHECK2-NEXT: br label [[COND_END16:%.*]]
1323 // CHECK2: cond.false14:
1324 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1325 // CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP10]], 5
1326 // CHECK2-NEXT: br label [[COND_END16]]
1327 // CHECK2: cond.end16:
1328 // CHECK2-NEXT: [[COND17:%.*]] = phi i32 [ 4, [[COND_TRUE13]] ], [ [[ADD15]], [[COND_FALSE14]] ]
1329 // CHECK2-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP8]], [[COND17]]
1330 // CHECK2-NEXT: br i1 [[CMP18]], label [[FOR_BODY19:%.*]], label [[FOR_END:%.*]]
1331 // CHECK2: for.body19:
1332 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1333 // CHECK2-NEXT: [[MUL20:%.*]] = mul nsw i32 [[TMP11]], 3
1334 // CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 7, [[MUL20]]
1335 // CHECK2-NEXT: store i32 [[ADD21]], i32* [[J]], align 4
1336 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4
1337 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4
1338 // CHECK2-NEXT: call void (...) @body(i32 [[TMP12]], i32 [[TMP13]])
1339 // CHECK2-NEXT: br label [[FOR_INC:%.*]]
1340 // CHECK2: for.inc:
1341 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1342 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
1343 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
1344 // CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]
1345 // CHECK2: for.end:
1346 // CHECK2-NEXT: br label [[FOR_INC22:%.*]]
1347 // CHECK2: for.inc22:
1348 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1349 // CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1
1350 // CHECK2-NEXT: store i32 [[INC23]], i32* [[DOTTILE_0_IV_I]], align 4
1351 // CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP8:![0-9]+]]
1352 // CHECK2: for.end24:
1353 // CHECK2-NEXT: br label [[FOR_INC25:%.*]]
1354 // CHECK2: for.inc25:
1355 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1356 // CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5
1357 // CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTFLOOR_1_IV_J]], align 4
1358 // CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP9:![0-9]+]]
1359 // CHECK2: for.end27:
1360 // CHECK2-NEXT: br label [[FOR_INC28:%.*]]
1361 // CHECK2: for.inc28:
1362 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1363 // CHECK2-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5
1364 // CHECK2-NEXT: store i32 [[ADD29]], i32* [[DOTFLOOR_0_IV_I]], align 4
1365 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
1366 // CHECK2: for.end30:
1367 // CHECK2-NEXT: ret void
1368 //
1369 //
1370 // CHECK2-LABEL: define {{[^@]+}}@foo3
1371 // CHECK2-SAME: () #[[ATTR2]] {
1372 // CHECK2-NEXT: entry:
1373 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1374 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1375 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1376 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
1377 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1378 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1379 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1380 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1381 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1382 // CHECK2-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4
1383 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1384 // CHECK2-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4
1385 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
1386 // CHECK2-NEXT: store i32 7, i32* [[I]], align 4
1387 // CHECK2-NEXT: store i32 7, i32* [[J]], align 4
1388 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1389 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_UB]], align 4
1390 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1391 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1392 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1393 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1394 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 0
1395 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1396 // CHECK2: cond.true:
1397 // CHECK2-NEXT: br label [[COND_END:%.*]]
1398 // CHECK2: cond.false:
1399 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1400 // CHECK2-NEXT: br label [[COND_END]]
1401 // CHECK2: cond.end:
1402 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
1403 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1404 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1405 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4
1406 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1407 // CHECK2: omp.inner.for.cond:
1408 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1409 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1410 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
1411 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1412 // CHECK2: omp.inner.for.body:
1413 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1414 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 5
1415 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1416 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTFLOOR_0_IV_I]], align 4
1417 // CHECK2-NEXT: store i32 0, i32* [[DOTFLOOR_1_IV_J]], align 4
1418 // CHECK2-NEXT: br label [[FOR_COND:%.*]]
1419 // CHECK2: for.cond:
1420 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1421 // CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP7]], 4
1422 // CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END32:%.*]]
1423 // CHECK2: for.body:
1424 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1425 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTTILE_0_IV_I]], align 4
1426 // CHECK2-NEXT: br label [[FOR_COND3:%.*]]
1427 // CHECK2: for.cond3:
1428 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1429 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1430 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 5
1431 // CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD4]]
1432 // CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
1433 // CHECK2: cond.true6:
1434 // CHECK2-NEXT: br label [[COND_END9:%.*]]
1435 // CHECK2: cond.false7:
1436 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1437 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 5
1438 // CHECK2-NEXT: br label [[COND_END9]]
1439 // CHECK2: cond.end9:
1440 // CHECK2-NEXT: [[COND10:%.*]] = phi i32 [ 4, [[COND_TRUE6]] ], [ [[ADD8]], [[COND_FALSE7]] ]
1441 // CHECK2-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP9]], [[COND10]]
1442 // CHECK2-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END29:%.*]]
1443 // CHECK2: for.body12:
1444 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1445 // CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP12]], 3
1446 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 7, [[MUL13]]
1447 // CHECK2-NEXT: store i32 [[ADD14]], i32* [[I]], align 4
1448 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1449 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTTILE_1_IV_J]], align 4
1450 // CHECK2-NEXT: br label [[FOR_COND15:%.*]]
1451 // CHECK2: for.cond15:
1452 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1453 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1454 // CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP15]], 5
1455 // CHECK2-NEXT: [[CMP17:%.*]] = icmp slt i32 4, [[ADD16]]
1456 // CHECK2-NEXT: br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]]
1457 // CHECK2: cond.true18:
1458 // CHECK2-NEXT: br label [[COND_END21:%.*]]
1459 // CHECK2: cond.false19:
1460 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1461 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 5
1462 // CHECK2-NEXT: br label [[COND_END21]]
1463 // CHECK2: cond.end21:
1464 // CHECK2-NEXT: [[COND22:%.*]] = phi i32 [ 4, [[COND_TRUE18]] ], [ [[ADD20]], [[COND_FALSE19]] ]
1465 // CHECK2-NEXT: [[CMP23:%.*]] = icmp slt i32 [[TMP14]], [[COND22]]
1466 // CHECK2-NEXT: br i1 [[CMP23]], label [[FOR_BODY24:%.*]], label [[FOR_END:%.*]]
1467 // CHECK2: for.body24:
1468 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1469 // CHECK2-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP17]], 3
1470 // CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 7, [[MUL25]]
1471 // CHECK2-NEXT: store i32 [[ADD26]], i32* [[J]], align 4
1472 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4
1473 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[J]], align 4
1474 // CHECK2-NEXT: call void (...) @body(i32 [[TMP18]], i32 [[TMP19]])
1475 // CHECK2-NEXT: br label [[FOR_INC:%.*]]
1476 // CHECK2: for.inc:
1477 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1478 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1
1479 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
1480 // CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP11:![0-9]+]]
1481 // CHECK2: for.end:
1482 // CHECK2-NEXT: br label [[FOR_INC27:%.*]]
1483 // CHECK2: for.inc27:
1484 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1485 // CHECK2-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1
1486 // CHECK2-NEXT: store i32 [[INC28]], i32* [[DOTTILE_0_IV_I]], align 4
1487 // CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP12:![0-9]+]]
1488 // CHECK2: for.end29:
1489 // CHECK2-NEXT: br label [[FOR_INC30:%.*]]
1490 // CHECK2: for.inc30:
1491 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1492 // CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5
1493 // CHECK2-NEXT: store i32 [[ADD31]], i32* [[DOTFLOOR_1_IV_J]], align 4
1494 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1495 // CHECK2: for.end32:
1496 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1497 // CHECK2: omp.body.continue:
1498 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1499 // CHECK2: omp.inner.for.inc:
1500 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1501 // CHECK2-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1
1502 // CHECK2-NEXT: store i32 [[ADD33]], i32* [[DOTOMP_IV]], align 4
1503 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1504 // CHECK2: omp.inner.for.end:
1505 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1506 // CHECK2: omp.loop.exit:
1507 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1508 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]])
1509 // CHECK2-NEXT: ret void
1510 //
1511 //
1512 // CHECK2-LABEL: define {{[^@]+}}@foo4
1513 // CHECK2-SAME: () #[[ATTR2]] {
1514 // CHECK2-NEXT: entry:
1515 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1516 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1517 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1518 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1519 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
1520 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1521 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1522 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1523 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1524 // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4
1525 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1526 // CHECK2-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4
1527 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1528 // CHECK2-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4
1529 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
1530 // CHECK2-NEXT: store i32 7, i32* [[I]], align 4
1531 // CHECK2-NEXT: store i32 7, i32* [[J]], align 4
1532 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1533 // CHECK2-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
1534 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1535 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1536 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1537 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1538 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 3
1539 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1540 // CHECK2: cond.true:
1541 // CHECK2-NEXT: br label [[COND_END:%.*]]
1542 // CHECK2: cond.false:
1543 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1544 // CHECK2-NEXT: br label [[COND_END]]
1545 // CHECK2: cond.end:
1546 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
1547 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1548 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1549 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4
1550 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1551 // CHECK2: omp.inner.for.cond:
1552 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1553 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1554 // CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
1555 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1556 // CHECK2: omp.inner.for.body:
1557 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1558 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 1
1559 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 3
1560 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 7, [[MUL]]
1561 // CHECK2-NEXT: store i32 [[ADD]], i32* [[K]], align 4
1562 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1563 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1564 // CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 1
1565 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 1
1566 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]]
1567 // CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 5
1568 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1569 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[DOTFLOOR_0_IV_I]], align 4
1570 // CHECK2-NEXT: store i32 0, i32* [[DOTFLOOR_1_IV_J]], align 4
1571 // CHECK2-NEXT: br label [[FOR_COND:%.*]]
1572 // CHECK2: for.cond:
1573 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1574 // CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP9]], 4
1575 // CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY:%.*]], label [[FOR_END37:%.*]]
1576 // CHECK2: for.body:
1577 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1578 // CHECK2-NEXT: store i32 [[TMP10]], i32* [[DOTTILE_0_IV_I]], align 4
1579 // CHECK2-NEXT: br label [[FOR_COND8:%.*]]
1580 // CHECK2: for.cond8:
1581 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1582 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1583 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 5
1584 // CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 4, [[ADD9]]
1585 // CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]]
1586 // CHECK2: cond.true11:
1587 // CHECK2-NEXT: br label [[COND_END14:%.*]]
1588 // CHECK2: cond.false12:
1589 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1590 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP13]], 5
1591 // CHECK2-NEXT: br label [[COND_END14]]
1592 // CHECK2: cond.end14:
1593 // CHECK2-NEXT: [[COND15:%.*]] = phi i32 [ 4, [[COND_TRUE11]] ], [ [[ADD13]], [[COND_FALSE12]] ]
1594 // CHECK2-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP11]], [[COND15]]
1595 // CHECK2-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END34:%.*]]
1596 // CHECK2: for.body17:
1597 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1598 // CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i32 [[TMP14]], 3
1599 // CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]]
1600 // CHECK2-NEXT: store i32 [[ADD19]], i32* [[I]], align 4
1601 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1602 // CHECK2-NEXT: store i32 [[TMP15]], i32* [[DOTTILE_1_IV_J]], align 4
1603 // CHECK2-NEXT: br label [[FOR_COND20:%.*]]
1604 // CHECK2: for.cond20:
1605 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1606 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1607 // CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP17]], 5
1608 // CHECK2-NEXT: [[CMP22:%.*]] = icmp slt i32 4, [[ADD21]]
1609 // CHECK2-NEXT: br i1 [[CMP22]], label [[COND_TRUE23:%.*]], label [[COND_FALSE24:%.*]]
1610 // CHECK2: cond.true23:
1611 // CHECK2-NEXT: br label [[COND_END26:%.*]]
1612 // CHECK2: cond.false24:
1613 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1614 // CHECK2-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP18]], 5
1615 // CHECK2-NEXT: br label [[COND_END26]]
1616 // CHECK2: cond.end26:
1617 // CHECK2-NEXT: [[COND27:%.*]] = phi i32 [ 4, [[COND_TRUE23]] ], [ [[ADD25]], [[COND_FALSE24]] ]
1618 // CHECK2-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP16]], [[COND27]]
1619 // CHECK2-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END:%.*]]
1620 // CHECK2: for.body29:
1621 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1622 // CHECK2-NEXT: [[MUL30:%.*]] = mul nsw i32 [[TMP19]], 3
1623 // CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 7, [[MUL30]]
1624 // CHECK2-NEXT: store i32 [[ADD31]], i32* [[J]], align 4
1625 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4
1626 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[J]], align 4
1627 // CHECK2-NEXT: call void (...) @body(i32 [[TMP20]], i32 [[TMP21]])
1628 // CHECK2-NEXT: br label [[FOR_INC:%.*]]
1629 // CHECK2: for.inc:
1630 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTTILE_1_IV_J]], align 4
1631 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1
1632 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_1_IV_J]], align 4
1633 // CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP14:![0-9]+]]
1634 // CHECK2: for.end:
1635 // CHECK2-NEXT: br label [[FOR_INC32:%.*]]
1636 // CHECK2: for.inc32:
1637 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1638 // CHECK2-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1
1639 // CHECK2-NEXT: store i32 [[INC33]], i32* [[DOTTILE_0_IV_I]], align 4
1640 // CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP15:![0-9]+]]
1641 // CHECK2: for.end34:
1642 // CHECK2-NEXT: br label [[FOR_INC35:%.*]]
1643 // CHECK2: for.inc35:
1644 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTFLOOR_1_IV_J]], align 4
1645 // CHECK2-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5
1646 // CHECK2-NEXT: store i32 [[ADD36]], i32* [[DOTFLOOR_1_IV_J]], align 4
1647 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
1648 // CHECK2: for.end37:
1649 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1650 // CHECK2: omp.body.continue:
1651 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1652 // CHECK2: omp.inner.for.inc:
1653 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1654 // CHECK2-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1
1655 // CHECK2-NEXT: store i32 [[ADD38]], i32* [[DOTOMP_IV]], align 4
1656 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1657 // CHECK2: omp.inner.for.end:
1658 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1659 // CHECK2: omp.loop.exit:
1660 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1661 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]])
1662 // CHECK2-NEXT: ret void
1663 //
1664 //
1665 // CHECK2-LABEL: define {{[^@]+}}@foo5
1666 // CHECK2-SAME: () #[[ATTR2]] {
1667 // CHECK2-NEXT: entry:
1668 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1669 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1670 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1671 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
1672 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1673 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1674 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
1675 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
1676 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1677 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1678 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4
1679 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1680 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1681 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1682 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1683 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 4
1684 // CHECK2-NEXT: [[DOTTILE_0_IV_I12:%.*]] = alloca i32, align 4
1685 // CHECK2-NEXT: [[J13:%.*]] = alloca i32, align 4
1686 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
1687 // CHECK2-NEXT: store i32 7, i32* [[I]], align 4
1688 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 4
1689 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
1690 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP]], align 4
1691 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5
1692 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 4, [[ADD]]
1693 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1694 // CHECK2: cond.true:
1695 // CHECK2-NEXT: br label [[COND_END:%.*]]
1696 // CHECK2: cond.false:
1697 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP]], align 4
1698 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 5
1699 // CHECK2-NEXT: br label [[COND_END]]
1700 // CHECK2: cond.end:
1701 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD4]], [[COND_FALSE]] ]
1702 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTCAPTURE_EXPR_3]], align 4
1703 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1704 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1705 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]]
1706 // CHECK2-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1
1707 // CHECK2-NEXT: [[ADD7:%.*]] = add i32 [[SUB6]], 1
1708 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD7]], 1
1709 // CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV]] to i64
1710 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 1, [[CONV]]
1711 // CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i64 [[MUL]], 4
1712 // CHECK2-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL8]], 1
1713 // CHECK2-NEXT: store i64 [[SUB9]], i64* [[DOTCAPTURE_EXPR_5]], align 8
1714 // CHECK2-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
1715 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1716 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[DOTTILE_0_IV_I]], align 4
1717 // CHECK2-NEXT: store i32 7, i32* [[J]], align 4
1718 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1719 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1720 // CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]]
1721 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1722 // CHECK2: omp.precond.then:
1723 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
1724 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1725 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8
1726 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
1727 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1728 // CHECK2-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
1729 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1730 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1731 // CHECK2-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
1732 // CHECK2-NEXT: br i1 [[CMP14]], label [[COND_TRUE15:%.*]], label [[COND_FALSE16:%.*]]
1733 // CHECK2: cond.true15:
1734 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_5]], align 8
1735 // CHECK2-NEXT: br label [[COND_END17:%.*]]
1736 // CHECK2: cond.false16:
1737 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1738 // CHECK2-NEXT: br label [[COND_END17]]
1739 // CHECK2: cond.end17:
1740 // CHECK2-NEXT: [[COND18:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE15]] ], [ [[TMP13]], [[COND_FALSE16]] ]
1741 // CHECK2-NEXT: store i64 [[COND18]], i64* [[DOTOMP_UB]], align 8
1742 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
1743 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8
1744 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1745 // CHECK2: omp.inner.for.cond:
1746 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1747 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
1748 // CHECK2-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP15]], [[TMP16]]
1749 // CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1750 // CHECK2: omp.inner.for.body:
1751 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1752 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1753 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1754 // CHECK2-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]]
1755 // CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1
1756 // CHECK2-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1
1757 // CHECK2-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1
1758 // CHECK2-NEXT: [[MUL24:%.*]] = mul i32 1, [[DIV23]]
1759 // CHECK2-NEXT: [[MUL25:%.*]] = mul i32 [[MUL24]], 4
1760 // CHECK2-NEXT: [[CONV26:%.*]] = zext i32 [[MUL25]] to i64
1761 // CHECK2-NEXT: [[DIV27:%.*]] = sdiv i64 [[TMP17]], [[CONV26]]
1762 // CHECK2-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV27]], 5
1763 // CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 0, [[MUL28]]
1764 // CHECK2-NEXT: [[CONV30:%.*]] = trunc i64 [[ADD29]] to i32
1765 // CHECK2-NEXT: store i32 [[CONV30]], i32* [[DOTFLOOR_0_IV_I11]], align 4
1766 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1767 // CHECK2-NEXT: [[CONV31:%.*]] = sext i32 [[TMP20]] to i64
1768 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1769 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1770 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1771 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1772 // CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP23]], [[TMP24]]
1773 // CHECK2-NEXT: [[SUB33:%.*]] = sub i32 [[SUB32]], 1
1774 // CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[SUB33]], 1
1775 // CHECK2-NEXT: [[DIV35:%.*]] = udiv i32 [[ADD34]], 1
1776 // CHECK2-NEXT: [[MUL36:%.*]] = mul i32 1, [[DIV35]]
1777 // CHECK2-NEXT: [[MUL37:%.*]] = mul i32 [[MUL36]], 4
1778 // CHECK2-NEXT: [[CONV38:%.*]] = zext i32 [[MUL37]] to i64
1779 // CHECK2-NEXT: [[DIV39:%.*]] = sdiv i64 [[TMP22]], [[CONV38]]
1780 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1781 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1782 // CHECK2-NEXT: [[SUB40:%.*]] = sub i32 [[TMP25]], [[TMP26]]
1783 // CHECK2-NEXT: [[SUB41:%.*]] = sub i32 [[SUB40]], 1
1784 // CHECK2-NEXT: [[ADD42:%.*]] = add i32 [[SUB41]], 1
1785 // CHECK2-NEXT: [[DIV43:%.*]] = udiv i32 [[ADD42]], 1
1786 // CHECK2-NEXT: [[MUL44:%.*]] = mul i32 1, [[DIV43]]
1787 // CHECK2-NEXT: [[MUL45:%.*]] = mul i32 [[MUL44]], 4
1788 // CHECK2-NEXT: [[CONV46:%.*]] = zext i32 [[MUL45]] to i64
1789 // CHECK2-NEXT: [[MUL47:%.*]] = mul nsw i64 [[DIV39]], [[CONV46]]
1790 // CHECK2-NEXT: [[SUB48:%.*]] = sub nsw i64 [[TMP21]], [[MUL47]]
1791 // CHECK2-NEXT: [[DIV49:%.*]] = sdiv i64 [[SUB48]], 4
1792 // CHECK2-NEXT: [[MUL50:%.*]] = mul nsw i64 [[DIV49]], 1
1793 // CHECK2-NEXT: [[ADD51:%.*]] = add nsw i64 [[CONV31]], [[MUL50]]
1794 // CHECK2-NEXT: [[CONV52:%.*]] = trunc i64 [[ADD51]] to i32
1795 // CHECK2-NEXT: store i32 [[CONV52]], i32* [[DOTTILE_0_IV_I12]], align 4
1796 // CHECK2-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1797 // CHECK2-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1798 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1799 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1800 // CHECK2-NEXT: [[SUB53:%.*]] = sub i32 [[TMP29]], [[TMP30]]
1801 // CHECK2-NEXT: [[SUB54:%.*]] = sub i32 [[SUB53]], 1
1802 // CHECK2-NEXT: [[ADD55:%.*]] = add i32 [[SUB54]], 1
1803 // CHECK2-NEXT: [[DIV56:%.*]] = udiv i32 [[ADD55]], 1
1804 // CHECK2-NEXT: [[MUL57:%.*]] = mul i32 1, [[DIV56]]
1805 // CHECK2-NEXT: [[MUL58:%.*]] = mul i32 [[MUL57]], 4
1806 // CHECK2-NEXT: [[CONV59:%.*]] = zext i32 [[MUL58]] to i64
1807 // CHECK2-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP28]], [[CONV59]]
1808 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1809 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1810 // CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[TMP31]], [[TMP32]]
1811 // CHECK2-NEXT: [[SUB62:%.*]] = sub i32 [[SUB61]], 1
1812 // CHECK2-NEXT: [[ADD63:%.*]] = add i32 [[SUB62]], 1
1813 // CHECK2-NEXT: [[DIV64:%.*]] = udiv i32 [[ADD63]], 1
1814 // CHECK2-NEXT: [[MUL65:%.*]] = mul i32 1, [[DIV64]]
1815 // CHECK2-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 4
1816 // CHECK2-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64
1817 // CHECK2-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[CONV67]]
1818 // CHECK2-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP27]], [[MUL68]]
1819 // CHECK2-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1820 // CHECK2-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1821 // CHECK2-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1822 // CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1823 // CHECK2-NEXT: [[SUB70:%.*]] = sub i32 [[TMP35]], [[TMP36]]
1824 // CHECK2-NEXT: [[SUB71:%.*]] = sub i32 [[SUB70]], 1
1825 // CHECK2-NEXT: [[ADD72:%.*]] = add i32 [[SUB71]], 1
1826 // CHECK2-NEXT: [[DIV73:%.*]] = udiv i32 [[ADD72]], 1
1827 // CHECK2-NEXT: [[MUL74:%.*]] = mul i32 1, [[DIV73]]
1828 // CHECK2-NEXT: [[MUL75:%.*]] = mul i32 [[MUL74]], 4
1829 // CHECK2-NEXT: [[CONV76:%.*]] = zext i32 [[MUL75]] to i64
1830 // CHECK2-NEXT: [[DIV77:%.*]] = sdiv i64 [[TMP34]], [[CONV76]]
1831 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4
1832 // CHECK2-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
1833 // CHECK2-NEXT: [[SUB78:%.*]] = sub i32 [[TMP37]], [[TMP38]]
1834 // CHECK2-NEXT: [[SUB79:%.*]] = sub i32 [[SUB78]], 1
1835 // CHECK2-NEXT: [[ADD80:%.*]] = add i32 [[SUB79]], 1
1836 // CHECK2-NEXT: [[DIV81:%.*]] = udiv i32 [[ADD80]], 1
1837 // CHECK2-NEXT: [[MUL82:%.*]] = mul i32 1, [[DIV81]]
1838 // CHECK2-NEXT: [[MUL83:%.*]] = mul i32 [[MUL82]], 4
1839 // CHECK2-NEXT: [[CONV84:%.*]] = zext i32 [[MUL83]] to i64
1840 // CHECK2-NEXT: [[MUL85:%.*]] = mul nsw i64 [[DIV77]], [[CONV84]]
1841 // CHECK2-NEXT: [[SUB86:%.*]] = sub nsw i64 [[TMP33]], [[MUL85]]
1842 // CHECK2-NEXT: [[DIV87:%.*]] = sdiv i64 [[SUB86]], 4
1843 // CHECK2-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV87]], 4
1844 // CHECK2-NEXT: [[SUB89:%.*]] = sub nsw i64 [[SUB69]], [[MUL88]]
1845 // CHECK2-NEXT: [[MUL90:%.*]] = mul nsw i64 [[SUB89]], 3
1846 // CHECK2-NEXT: [[ADD91:%.*]] = add nsw i64 7, [[MUL90]]
1847 // CHECK2-NEXT: [[CONV92:%.*]] = trunc i64 [[ADD91]] to i32
1848 // CHECK2-NEXT: store i32 [[CONV92]], i32* [[J13]], align 4
1849 // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTTILE_0_IV_I12]], align 4
1850 // CHECK2-NEXT: [[MUL93:%.*]] = mul nsw i32 [[TMP39]], 3
1851 // CHECK2-NEXT: [[ADD94:%.*]] = add nsw i32 7, [[MUL93]]
1852 // CHECK2-NEXT: store i32 [[ADD94]], i32* [[I]], align 4
1853 // CHECK2-NEXT: [[TMP40:%.*]] = load i32, i32* [[I]], align 4
1854 // CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[J13]], align 4
1855 // CHECK2-NEXT: call void (...) @body(i32 [[TMP40]], i32 [[TMP41]])
1856 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1857 // CHECK2: omp.body.continue:
1858 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1859 // CHECK2: omp.inner.for.inc:
1860 // CHECK2-NEXT: [[TMP42:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
1861 // CHECK2-NEXT: [[ADD95:%.*]] = add nsw i64 [[TMP42]], 1
1862 // CHECK2-NEXT: store i64 [[ADD95]], i64* [[DOTOMP_IV]], align 8
1863 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1864 // CHECK2: omp.inner.for.end:
1865 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1866 // CHECK2: omp.loop.exit:
1867 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1868 // CHECK2-NEXT: br label [[OMP_PRECOND_END]]
1869 // CHECK2: omp.precond.end:
1870 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]])
1871 // CHECK2-NEXT: ret void
1872 //
1873 //
1874 // CHECK2-LABEL: define {{[^@]+}}@foo6
1875 // CHECK2-SAME: () #[[ATTR2]] {
1876 // CHECK2-NEXT: entry:
1877 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1878 // CHECK2-NEXT: ret void
1879 //
1880 //
1881 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1882 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
1883 // CHECK2-NEXT: entry:
1884 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1885 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1886 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1887 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
1888 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1889 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1890 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1891 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1892 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1893 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1894 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1895 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1896 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1897 // CHECK2-NEXT: store i32 7, i32* [[I]], align 4
1898 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
1899 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_UB]], align 4
1900 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
1901 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
1902 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1903 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1904 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
1905 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1906 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 0
1907 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1908 // CHECK2: cond.true:
1909 // CHECK2-NEXT: br label [[COND_END:%.*]]
1910 // CHECK2: cond.false:
1911 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1912 // CHECK2-NEXT: br label [[COND_END]]
1913 // CHECK2: cond.end:
1914 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 0, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1915 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
1916 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
1917 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
1918 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1919 // CHECK2: omp.inner.for.cond:
1920 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1921 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
1922 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1923 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1924 // CHECK2: omp.inner.for.body:
1925 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1926 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
1927 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1928 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTFLOOR_0_IV_I]], align 4
1929 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1930 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTTILE_0_IV_I]], align 4
1931 // CHECK2-NEXT: br label [[FOR_COND:%.*]]
1932 // CHECK2: for.cond:
1933 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1934 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1935 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 5
1936 // CHECK2-NEXT: [[CMP3:%.*]] = icmp slt i32 4, [[ADD2]]
1937 // CHECK2-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]]
1938 // CHECK2: cond.true4:
1939 // CHECK2-NEXT: br label [[COND_END7:%.*]]
1940 // CHECK2: cond.false5:
1941 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
1942 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 5
1943 // CHECK2-NEXT: br label [[COND_END7]]
1944 // CHECK2: cond.end7:
1945 // CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 4, [[COND_TRUE4]] ], [ [[ADD6]], [[COND_FALSE5]] ]
1946 // CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP9]], [[COND8]]
1947 // CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
1948 // CHECK2: for.body:
1949 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1950 // CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP12]], 3
1951 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]]
1952 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[I]], align 4
1953 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4
1954 // CHECK2-NEXT: call void (...) @body(i32 [[TMP13]])
1955 // CHECK2-NEXT: br label [[FOR_INC:%.*]]
1956 // CHECK2: for.inc:
1957 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
1958 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1
1959 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
1960 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
1961 // CHECK2: for.end:
1962 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1963 // CHECK2: omp.body.continue:
1964 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1965 // CHECK2: omp.inner.for.inc:
1966 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
1967 // CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1
1968 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4
1969 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
1970 // CHECK2: omp.inner.for.end:
1971 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1972 // CHECK2: omp.loop.exit:
1973 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
1974 // CHECK2-NEXT: ret void
1975 //
1976 //
1977 // CHECK2-LABEL: define {{[^@]+}}@tfoo7
1978 // CHECK2-SAME: () #[[ATTR2]] {
1979 // CHECK2-NEXT: entry:
1980 // CHECK2-NEXT: call void @_Z4foo7IiLi3ELi5EEvT_S0_(i32 0, i32 42)
1981 // CHECK2-NEXT: ret void
1982 //
1983 //
1984 // CHECK2-LABEL: define {{[^@]+}}@_Z4foo7IiLi3ELi5EEvT_S0_
1985 // CHECK2-SAME: (i32 [[START:%.*]], i32 [[END:%.*]]) #[[ATTR2]] comdat {
1986 // CHECK2-NEXT: entry:
1987 // CHECK2-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4
1988 // CHECK2-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4
1989 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
1990 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1991 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1992 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1993 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4
1994 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4
1995 // CHECK2-NEXT: store i32 [[START]], i32* [[START_ADDR]], align 4
1996 // CHECK2-NEXT: store i32 [[END]], i32* [[END_ADDR]], align 4
1997 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[START_ADDR]], align 4
1998 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[I]], align 4
1999 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[START_ADDR]], align 4
2000 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4
2001 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[END_ADDR]], align 4
2002 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4
2003 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4
2004 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2005 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
2006 // CHECK2-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
2007 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 3
2008 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 3
2009 // CHECK2-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
2010 // CHECK2-NEXT: store i32 [[SUB4]], i32* [[DOTCAPTURE_EXPR_2]], align 4
2011 // CHECK2-NEXT: store i32 0, i32* [[DOTFLOOR_0_IV_I]], align 4
2012 // CHECK2-NEXT: br label [[FOR_COND:%.*]]
2013 // CHECK2: for.cond:
2014 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
2015 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2016 // CHECK2-NEXT: [[ADD5:%.*]] = add i32 [[TMP6]], 1
2017 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP5]], [[ADD5]]
2018 // CHECK2-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END17:%.*]]
2019 // CHECK2: for.body:
2020 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
2021 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTTILE_0_IV_I]], align 4
2022 // CHECK2-NEXT: br label [[FOR_COND6:%.*]]
2023 // CHECK2: for.cond6:
2024 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
2025 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2026 // CHECK2-NEXT: [[ADD7:%.*]] = add i32 [[TMP9]], 1
2027 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
2028 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 5
2029 // CHECK2-NEXT: [[CMP9:%.*]] = icmp ult i32 [[ADD7]], [[ADD8]]
2030 // CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2031 // CHECK2: cond.true:
2032 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4
2033 // CHECK2-NEXT: [[ADD10:%.*]] = add i32 [[TMP11]], 1
2034 // CHECK2-NEXT: br label [[COND_END:%.*]]
2035 // CHECK2: cond.false:
2036 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
2037 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP12]], 5
2038 // CHECK2-NEXT: br label [[COND_END]]
2039 // CHECK2: cond.end:
2040 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD10]], [[COND_TRUE]] ], [ [[ADD11]], [[COND_FALSE]] ]
2041 // CHECK2-NEXT: [[CMP12:%.*]] = icmp ult i32 [[TMP8]], [[COND]]
2042 // CHECK2-NEXT: br i1 [[CMP12]], label [[FOR_BODY13:%.*]], label [[FOR_END:%.*]]
2043 // CHECK2: for.body13:
2044 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
2045 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
2046 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP14]], 3
2047 // CHECK2-NEXT: [[ADD14:%.*]] = add i32 [[TMP13]], [[MUL]]
2048 // CHECK2-NEXT: store i32 [[ADD14]], i32* [[I]], align 4
2049 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4
2050 // CHECK2-NEXT: call void (...) @body(i32 [[TMP15]])
2051 // CHECK2-NEXT: br label [[FOR_INC:%.*]]
2052 // CHECK2: for.inc:
2053 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTTILE_0_IV_I]], align 4
2054 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1
2055 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTTILE_0_IV_I]], align 4
2056 // CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP20:![0-9]+]]
2057 // CHECK2: for.end:
2058 // CHECK2-NEXT: br label [[FOR_INC15:%.*]]
2059 // CHECK2: for.inc15:
2060 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTFLOOR_0_IV_I]], align 4
2061 // CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP17]], 5
2062 // CHECK2-NEXT: store i32 [[ADD16]], i32* [[DOTFLOOR_0_IV_I]], align 4
2063 // CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
2064 // CHECK2: for.end17:
2065 // CHECK2-NEXT: ret void
2066 //
2067 //
2068 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_tile_codegen.cpp
2069 // CHECK2-SAME: () #[[ATTR0]] section ".text.startup" {
2070 // CHECK2-NEXT: entry:
2071 // CHECK2-NEXT: call void @__cxx_global_var_init()
2072 // CHECK2-NEXT: ret void
2073 //
2074