1//===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file describes the RISC-V instructions from the standard 'V' Vector 10/// extension, version 0.10. 11/// This version is still experimental as the 'V' extension hasn't been 12/// ratified yet. 13/// 14//===----------------------------------------------------------------------===// 15 16include "RISCVInstrFormatsV.td" 17 18//===----------------------------------------------------------------------===// 19// Operand and SDNode transformation definitions. 20//===----------------------------------------------------------------------===// 21 22def VTypeIAsmOperand : AsmOperandClass { 23 let Name = "VTypeI"; 24 let ParserMethod = "parseVTypeI"; 25 let DiagnosticType = "InvalidVTypeI"; 26} 27 28def VTypeIOp : Operand<XLenVT> { 29 let ParserMatchClass = VTypeIAsmOperand; 30 let PrintMethod = "printVTypeI"; 31 let DecoderMethod = "decodeUImmOperand<11>"; 32} 33 34def VMaskAsmOperand : AsmOperandClass { 35 let Name = "RVVMaskRegOpOperand"; 36 let RenderMethod = "addRegOperands"; 37 let PredicateMethod = "isV0Reg"; 38 let ParserMethod = "parseMaskReg"; 39 let IsOptional = 1; 40 let DefaultMethod = "defaultMaskRegOp"; 41 let DiagnosticType = "InvalidVMaskRegister"; 42} 43 44def VMaskOp : RegisterOperand<VMV0> { 45 let ParserMatchClass = VMaskAsmOperand; 46 let PrintMethod = "printVMaskReg"; 47 let EncoderMethod = "getVMaskReg"; 48 let DecoderMethod = "decodeVMaskReg"; 49} 50 51def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> { 52 let ParserMatchClass = SImmAsmOperand<5>; 53 let EncoderMethod = "getImmOpValue"; 54 let DecoderMethod = "decodeSImmOperand<5>"; 55 let MCOperandPredicate = [{ 56 int64_t Imm; 57 if (MCOp.evaluateAsConstantImm(Imm)) 58 return isInt<5>(Imm); 59 return MCOp.isBareSymbolRef(); 60 }]; 61} 62 63def SImm5Plus1AsmOperand : AsmOperandClass { 64 let Name = "SImm5Plus1"; 65 let RenderMethod = "addImmOperands"; 66 let DiagnosticType = "InvalidSImm5Plus1"; 67} 68 69def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT, 70 [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> { 71 let ParserMatchClass = SImm5Plus1AsmOperand; 72 let MCOperandPredicate = [{ 73 int64_t Imm; 74 if (MCOp.evaluateAsConstantImm(Imm)) 75 return (isInt<5>(Imm) && Imm != -16) || Imm == 16; 76 return MCOp.isBareSymbolRef(); 77 }]; 78} 79 80//===----------------------------------------------------------------------===// 81// Scheduling definitions. 82//===----------------------------------------------------------------------===// 83 84class VMVRSched<int n>: Sched <[!cast<SchedReadWrite>("WriteVMov" # n # "V"), 85 !cast<SchedReadWrite>("ReadVMov" # n # "V")]>; 86 87class VLESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDE" # n), 88 ReadVLDX, ReadVMask]>; 89 90class VSESched<int n> : Sched <[!cast<SchedReadWrite>("WriteVSTE" # n), 91 !cast<SchedReadWrite>("ReadVSTE" # n # "V"), 92 ReadVSTX, ReadVMask]>; 93 94class VLSSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDS" # n), 95 ReadVLDX, ReadVLDSX, ReadVMask]>; 96 97class VSSSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVSTS" # n), 98 !cast<SchedReadWrite>("ReadVSTS" # n # "V"), 99 ReadVSTX, ReadVSTSX, ReadVMask]>; 100 101class VLXSched<int n, string o> : 102 Sched <[!cast<SchedReadWrite>("WriteVLD" # o # "X" # n), 103 ReadVLDX, !cast<SchedReadWrite>("ReadVLD" # o # "XV"), ReadVMask]>; 104 105class VSXSched<int n, string o> : 106 Sched <[!cast<SchedReadWrite>("WriteVST" # o # "X" # n), 107 !cast<SchedReadWrite>("ReadVST" # o # "X" # n), 108 ReadVSTX, !cast<SchedReadWrite>("ReadVST" # o # "XV"), ReadVMask]>; 109 110class VLFSched<int n> : Sched <[!cast<SchedReadWrite>("WriteVLDFF" # n), 111 ReadVLDX, ReadVMask]>; 112 113//===----------------------------------------------------------------------===// 114// Instruction class templates 115//===----------------------------------------------------------------------===// 116 117let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { 118// load vd, (rs1) 119class VUnitStrideLoadMask<string opcodestr> 120 : RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0}, 121 (outs VR:$vd), 122 (ins GPR:$rs1), opcodestr, "$vd, (${rs1})"> { 123 let vm = 1; 124 let RVVConstraint = NoConstraint; 125} 126 127// load vd, (rs1), vm 128class VUnitStrideLoad<RISCVLSUMOP lumop, RISCVWidth width, 129 string opcodestr> 130 : RVInstVLU<0b000, width.Value{3}, lumop, width.Value{2-0}, 131 (outs VR:$vd), 132 (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; 133 134// load vd, (rs1), rs2, vm 135class VStridedLoad<RISCVWidth width, string opcodestr> 136 : RVInstVLS<0b000, width.Value{3}, width.Value{2-0}, 137 (outs VR:$vd), 138 (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, 139 "$vd, (${rs1}), $rs2$vm">; 140 141// load vd, (rs1), vs2, vm 142class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr> 143 : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0}, 144 (outs VR:$vd), 145 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, 146 "$vd, (${rs1}), $vs2$vm">; 147 148// vl<nf>r.v vd, (rs1) 149class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC> 150 : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg, 151 width.Value{2-0}, (outs VRC:$vd), (ins GPR:$rs1), 152 opcodestr, "$vd, (${rs1})"> { 153 let vm = 1; 154 let Uses = []; 155 let RVVConstraint = NoConstraint; 156} 157 158// segment load vd, (rs1), vm 159class VUnitStrideSegmentLoad<bits<3> nf, RISCVLSUMOP lumop, 160 RISCVWidth width, string opcodestr> 161 : RVInstVLU<nf, width.Value{3}, lumop, width.Value{2-0}, 162 (outs VR:$vd), 163 (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; 164 165// segment load vd, (rs1), rs2, vm 166class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr> 167 : RVInstVLS<nf, width.Value{3}, width.Value{2-0}, 168 (outs VR:$vd), 169 (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, 170 "$vd, (${rs1}), $rs2$vm">; 171 172// segment load vd, (rs1), vs2, vm 173class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width, 174 string opcodestr> 175 : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0}, 176 (outs VR:$vd), 177 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, 178 "$vd, (${rs1}), $vs2$vm">; 179} // hasSideEffects = 0, mayLoad = 1, mayStore = 0 180 181let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { 182// store vd, vs3, (rs1) 183class VUnitStrideStoreMask<string opcodestr> 184 : RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0}, 185 (outs), (ins VR:$vs3, GPR:$rs1), opcodestr, 186 "$vs3, (${rs1})"> { 187 let vm = 1; 188} 189 190// store vd, vs3, (rs1), vm 191class VUnitStrideStore<RISCVLSUMOP sumop, RISCVWidth width, 192 string opcodestr> 193 : RVInstVSU<0b000, width.Value{3}, sumop, width.Value{2-0}, 194 (outs), (ins VR:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr, 195 "$vs3, (${rs1})$vm">; 196 197// store vd, vs3, (rs1), rs2, vm 198class VStridedStore<RISCVWidth width, string opcodestr> 199 : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs), 200 (ins VR:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm), 201 opcodestr, "$vs3, (${rs1}), $rs2$vm">; 202 203// store vd, vs3, (rs1), vs2, vm 204class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr> 205 : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs), 206 (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm), 207 opcodestr, "$vs3, (${rs1}), $vs2$vm">; 208 209// vs<nf>r.v vd, (rs1) 210class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC> 211 : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg, 212 0b000, (outs), (ins VRC:$vs3, GPR:$rs1), 213 opcodestr, "$vs3, (${rs1})"> { 214 let vm = 1; 215 let Uses = []; 216} 217 218// segment store vd, vs3, (rs1), vm 219class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> 220 : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0}, 221 (outs), (ins VR:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr, 222 "$vs3, (${rs1})$vm">; 223 224// segment store vd, vs3, (rs1), rs2, vm 225class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> 226 : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs), 227 (ins VR:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm), 228 opcodestr, "$vs3, (${rs1}), $rs2$vm">; 229 230// segment store vd, vs3, (rs1), vs2, vm 231class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width, 232 string opcodestr> 233 : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs), 234 (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm), 235 opcodestr, "$vs3, (${rs1}), $vs2$vm">; 236} // hasSideEffects = 0, mayLoad = 0, mayStore = 1 237 238let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 239// op vd, vs2, vs1, vm 240class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> 241 : RVInstVV<funct6, opv, (outs VR:$vd), 242 (ins VR:$vs2, VR:$vs1, VMaskOp:$vm), 243 opcodestr, "$vd, $vs2, $vs1$vm">; 244 245// op vd, vs2, vs1, v0 (without mask, use v0 as carry input) 246class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> 247 : RVInstVV<funct6, opv, (outs VR:$vd), 248 (ins VR:$vs2, VR:$vs1, VMV0:$v0), 249 opcodestr, "$vd, $vs2, $vs1, v0"> { 250 let vm = 0; 251} 252 253// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2) 254class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> 255 : RVInstVV<funct6, opv, (outs VR:$vd), 256 (ins VR:$vs1, VR:$vs2, VMaskOp:$vm), 257 opcodestr, "$vd, $vs1, $vs2$vm">; 258 259// op vd, vs2, vs1 260class VALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr> 261 : RVInstVV<funct6, opv, (outs VR:$vd), 262 (ins VR:$vs2, VR:$vs1), 263 opcodestr, "$vd, $vs2, $vs1"> { 264 let vm = 1; 265} 266 267// op vd, vs2, rs1, vm 268class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> 269 : RVInstVX<funct6, opv, (outs VR:$vd), 270 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 271 opcodestr, "$vd, $vs2, $rs1$vm">; 272 273// op vd, vs2, rs1, v0 (without mask, use v0 as carry input) 274class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> 275 : RVInstVX<funct6, opv, (outs VR:$vd), 276 (ins VR:$vs2, GPR:$rs1, VMV0:$v0), 277 opcodestr, "$vd, $vs2, $rs1, v0"> { 278 let vm = 0; 279} 280 281// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2) 282class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> 283 : RVInstVX<funct6, opv, (outs VR:$vd), 284 (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), 285 opcodestr, "$vd, $rs1, $vs2$vm">; 286 287// op vd, vs1, vs2 288class VALUVXNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr> 289 : RVInstVX<funct6, opv, (outs VR:$vd), 290 (ins VR:$vs2, GPR:$rs1), 291 opcodestr, "$vd, $vs2, $rs1"> { 292 let vm = 1; 293} 294 295// op vd, vs2, imm, vm 296class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5> 297 : RVInstIVI<funct6, (outs VR:$vd), 298 (ins VR:$vs2, optype:$imm, VMaskOp:$vm), 299 opcodestr, "$vd, $vs2, $imm$vm">; 300 301// op vd, vs2, imm, v0 (without mask, use v0 as carry input) 302class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5> 303 : RVInstIVI<funct6, (outs VR:$vd), 304 (ins VR:$vs2, optype:$imm, VMV0:$v0), 305 opcodestr, "$vd, $vs2, $imm, v0"> { 306 let vm = 0; 307} 308 309// op vd, vs2, imm, vm 310class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5> 311 : RVInstIVI<funct6, (outs VR:$vd), 312 (ins VR:$vs2, optype:$imm), 313 opcodestr, "$vd, $vs2, $imm"> { 314 let vm = 1; 315} 316 317// op vd, vs2, rs1, vm (Float) 318class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr> 319 : RVInstVX<funct6, opv, (outs VR:$vd), 320 (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm), 321 opcodestr, "$vd, $vs2, $rs1$vm">; 322 323// op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2) 324class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr> 325 : RVInstVX<funct6, opv, (outs VR:$vd), 326 (ins FPR32:$rs1, VR:$vs2, VMaskOp:$vm), 327 opcodestr, "$vd, $rs1, $vs2$vm">; 328 329// op vd, vs2, vm (use vs1 as instruction encoding) 330class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> 331 : RVInstV<funct6, vs1, opv, (outs VR:$vd), 332 (ins VR:$vs2, VMaskOp:$vm), 333 opcodestr, "$vd, $vs2$vm">; 334} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 335 336let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 337// vamo vd, (rs1), vs2, vd, vm 338class VAMOWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> 339 : RVInstVAMO<amoop, width.Value{2-0}, (outs VR:$vd_wd), 340 (ins GPR:$rs1, VR:$vs2, VR:$vd, VMaskOp:$vm), 341 opcodestr, "$vd_wd, (${rs1}), $vs2, $vd$vm"> { 342 let Constraints = "$vd_wd = $vd"; 343 let wd = 1; 344 bits<5> vd; 345 let Inst{11-7} = vd; 346} 347 348// vamo x0, (rs1), vs2, vs3, vm 349class VAMONoWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> 350 : RVInstVAMO<amoop, width.Value{2-0}, (outs), 351 (ins GPR:$rs1, VR:$vs2, VR:$vs3, VMaskOp:$vm), 352 opcodestr, "x0, (${rs1}), $vs2, $vs3$vm"> { 353 bits<5> vs3; 354 let Inst{11-7} = vs3; 355} 356 357} // hasSideEffects = 0, mayLoad = 1, mayStore = 1 358 359//===----------------------------------------------------------------------===// 360// Combination of instruction classes. 361// Use these multiclasses to define instructions more easily. 362//===----------------------------------------------------------------------===// 363multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 364 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 365 Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>; 366 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 367 Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>; 368 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 369 Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>; 370} 371 372multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 373 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 374 Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUV, ReadVMask]>; 375 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 376 Sched<[WriteVIALUX, ReadVIALUV, ReadVIALUX, ReadVMask]>; 377} 378 379multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 380 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 381 Sched<[WriteVIALUV, ReadVIALUV, ReadVIALUX, ReadVMask]>; 382 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 383 Sched<[WriteVIALUI, ReadVIALUV, ReadVMask]>; 384} 385 386multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 387 def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 388 Sched<[WriteVIWALUV, ReadVIWALUV, ReadVIWALUV, ReadVMask]>; 389 def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 390 Sched<[WriteVIWALUX, ReadVIWALUV, ReadVIWALUX, ReadVMask]>; 391} 392 393multiclass VMAC_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 394 def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 395 Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>; 396 def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 397 Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>; 398} 399 400multiclass VWMAC_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 401 def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 402 Sched<[WriteVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVMask]>; 403 def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 404 Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>; 405} 406 407multiclass VWMAC_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> { 408 def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 409 Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>; 410} 411 412multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 413 def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 414 Sched<[WriteVExtV, ReadVExtV, ReadVMask]>; 415} 416 417multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> { 418 def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">, 419 Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>; 420 def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">, 421 Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>; 422 def IM : VALUmVI<funct6, opcodestr # ".vim">, 423 Sched<[WriteVICALUI, ReadVIALUCV, ReadVMask]>; 424} 425 426multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> { 427 def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">, 428 Sched<[WriteVIMergeV, ReadVIMergeV, ReadVIMergeV, ReadVMask]>; 429 def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">, 430 Sched<[WriteVIMergeX, ReadVIMergeV, ReadVIMergeX, ReadVMask]>; 431 def IM : VALUmVI<funct6, opcodestr # ".vim">, 432 Sched<[WriteVIMergeI, ReadVIMergeV, ReadVMask]>; 433} 434 435multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> { 436 def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">, 437 Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV, ReadVMask]>; 438 def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">, 439 Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX, ReadVMask]>; 440} 441 442multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> { 443 def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">, 444 Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>; 445 def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">, 446 Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>; 447 def I : VALUVINoVm<funct6, opcodestr # ".vi", optype>, 448 Sched<[WriteVICALUI, ReadVIALUCV]>; 449} 450 451multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> { 452 def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">, 453 Sched<[WriteVICALUV, ReadVIALUCV, ReadVIALUCV]>; 454 def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">, 455 Sched<[WriteVICALUX, ReadVIALUCV, ReadVIALUCX]>; 456} 457 458multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 459 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 460 Sched<[WriteVFALUV, ReadVFALUV, ReadVFALUV, ReadVMask]>; 461 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 462 Sched<[WriteVFALUF, ReadVFALUV, ReadVFALUF, ReadVMask]>; 463} 464 465multiclass VALU_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> { 466 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 467 Sched<[WriteVFALUF, ReadVFALUV, ReadVFALUF, ReadVMask]>; 468} 469 470multiclass VWALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 471 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 472 Sched<[WriteVFWALUV, ReadVFWALUV, ReadVFWALUV, ReadVMask]>; 473 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 474 Sched<[WriteVFWALUF, ReadVFWALUV, ReadVFWALUF, ReadVMask]>; 475} 476 477multiclass VMUL_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 478 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 479 Sched<[WriteVFMulV, ReadVFMulV, ReadVFMulV, ReadVMask]>; 480 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 481 Sched<[WriteVFMulF, ReadVFMulV, ReadVFMulF, ReadVMask]>; 482} 483 484multiclass VDIV_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 485 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 486 Sched<[WriteVFDivV, ReadVFDivV, ReadVFDivV, ReadVMask]>; 487 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 488 Sched<[WriteVFDivF, ReadVFDivV, ReadVFDivF, ReadVMask]>; 489} 490 491multiclass VRDIV_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> { 492 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 493 Sched<[WriteVFDivF, ReadVFDivV, ReadVFDivF, ReadVMask]>; 494} 495 496multiclass VWMUL_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 497 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 498 Sched<[WriteVFWMulV, ReadVFWMulV, ReadVFWMulV, ReadVMask]>; 499 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 500 Sched<[WriteVFWMulF, ReadVFWMulV, ReadVFWMulF, ReadVMask]>; 501} 502 503multiclass VMAC_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 504 def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 505 Sched<[WriteVFMulAddV, ReadVFMulAddV, ReadVFMulAddV, ReadVMask]>; 506 def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 507 Sched<[WriteVFMulAddF, ReadVFMulAddV, ReadVFMulAddF, ReadVMask]>; 508} 509 510multiclass VWMAC_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 511 def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 512 Sched<[WriteVFWMulAddV, ReadVFWMulAddV, ReadVFWMulAddV, ReadVMask]>; 513 def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 514 Sched<[WriteVFWMulAddF, ReadVFWMulAddV, ReadVFWMulAddF, ReadVMask]>; 515} 516 517multiclass VSQR_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 518 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 519 Sched<[WriteVFSqrtV, ReadVFSqrtV, ReadVMask]>; 520} 521 522multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 523 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 524 Sched<[WriteVFRecpV, ReadVFRecpV, ReadVMask]>; 525} 526 527multiclass VCMP_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 528 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 529 Sched<[WriteVFCmpV, ReadVFCmpV, ReadVFCmpV, ReadVMask]>; 530 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 531 Sched<[WriteVFCmpF, ReadVFCmpV, ReadVFCmpF, ReadVMask]>; 532} 533 534multiclass VCMP_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> { 535 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 536 Sched<[WriteVFCmpF, ReadVFCmpV, ReadVFCmpF, ReadVMask]>; 537} 538 539multiclass VSGNJ_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> { 540 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 541 Sched<[WriteVFSgnjV, ReadVFSgnjV, ReadVFSgnjV, ReadVMask]>; 542 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 543 Sched<[WriteVFSgnjF, ReadVFSgnjV, ReadVFSgnjF, ReadVMask]>; 544} 545 546multiclass VCLS_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 547 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 548 Sched<[WriteVFClassV, ReadVFClassV, ReadVMask]>; 549} 550 551multiclass VCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 552 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 553 Sched<[WriteVFCvtIToFV, ReadVFCvtIToFV, ReadVMask]>; 554} 555 556multiclass VCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 557 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 558 Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>; 559} 560 561multiclass VWCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 562 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 563 Sched<[WriteVFWCvtIToFV, ReadVFWCvtIToFV, ReadVMask]>; 564} 565 566multiclass VWCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 567 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 568 Sched<[WriteVFWCvtFToIV, ReadVFWCvtFToIV, ReadVMask]>; 569} 570 571multiclass VWCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 572 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 573 Sched<[WriteVFWCvtFToFV, ReadVFWCvtFToFV, ReadVMask]>; 574} 575 576multiclass VNCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 577 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 578 Sched<[WriteVFNCvtIToFV, ReadVFNCvtIToFV, ReadVMask]>; 579} 580 581multiclass VNCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 582 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 583 Sched<[WriteVFNCvtFToIV, ReadVFNCvtFToIV, ReadVMask]>; 584} 585 586multiclass VNCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 587 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 588 Sched<[WriteVFNCvtFToFV, ReadVFNCvtFToFV, ReadVMask]>; 589} 590 591multiclass VRED_MV_V<string opcodestr, bits<6> funct6> { 592 def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">, 593 Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV0, ReadVMask]>; 594} 595 596multiclass VWRED_IV_V<string opcodestr, bits<6> funct6> { 597 def _VS : VALUVV<funct6, OPIVV, opcodestr # ".vs">, 598 Sched<[WriteVIWRedV, ReadVIWRedV, ReadVIWRedV0, ReadVMask]>; 599} 600 601multiclass VRED_FV_V<string opcodestr, bits<6> funct6> { 602 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 603 Sched<[WriteVFRedV, ReadVFRedV, ReadVFRedV0, ReadVMask]>; 604} 605 606multiclass VREDO_FV_V<string opcodestr, bits<6> funct6> { 607 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 608 Sched<[WriteVFRedOV, ReadVFRedOV, ReadVFRedOV0, ReadVMask]>; 609} 610 611multiclass VWRED_FV_V<string opcodestr, bits<6> funct6> { 612 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 613 Sched<[WriteVFWRedV, ReadVFWRedV, ReadVFWRedV0, ReadVMask]>; 614} 615 616multiclass VWREDO_FV_V<string opcodestr, bits<6> funct6> { 617 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 618 Sched<[WriteVFWRedOV, ReadVFWRedOV, ReadVFWRedOV0, ReadVMask]>; 619} 620 621multiclass VMALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> { 622 def M : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">, 623 Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>; 624} 625 626multiclass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> { 627 def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 628 Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>; 629} 630 631multiclass VMIOT_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> { 632 def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 633 Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; 634} 635 636multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 637 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 638 Sched<[WriteVShiftV, ReadVShiftV, ReadVShiftV, ReadVMask]>; 639 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 640 Sched<[WriteVShiftX, ReadVShiftV, ReadVShiftX, ReadVMask]>; 641 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 642 Sched<[WriteVShiftI, ReadVShiftV, ReadVMask]>; 643} 644 645multiclass VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 646 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 647 Sched<[WriteVNShiftV, ReadVNShiftV, ReadVNShiftV, ReadVMask]>; 648 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 649 Sched<[WriteVNShiftX, ReadVNShiftV, ReadVNShiftX, ReadVMask]>; 650 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 651 Sched<[WriteVNShiftI, ReadVNShiftV, ReadVMask]>; 652} 653 654multiclass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 655 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 656 Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>; 657 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 658 Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>; 659 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 660 Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>; 661} 662 663multiclass VCMP_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 664 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 665 Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpX, ReadVMask]>; 666 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 667 Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>; 668} 669 670multiclass VCMP_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 671 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 672 Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>; 673 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 674 Sched<[WriteVICmpX, ReadVICmpV, ReadVICmpX, ReadVMask]>; 675} 676 677multiclass VMUL_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 678 def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 679 Sched<[WriteVIMulV, ReadVIMulV, ReadVIMulV, ReadVMask]>; 680 def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 681 Sched<[WriteVIMulX, ReadVIMulV, ReadVIMulX, ReadVMask]>; 682} 683 684multiclass VWMUL_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 685 def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 686 Sched<[WriteVIWMulV, ReadVIWMulV, ReadVIWMulV, ReadVMask]>; 687 def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 688 Sched<[WriteVIWMulX, ReadVIWMulV, ReadVIWMulX, ReadVMask]>; 689} 690 691multiclass VDIV_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 692 def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 693 Sched<[WriteVIDivV, ReadVIDivV, ReadVIDivV, ReadVMask]>; 694 def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 695 Sched<[WriteVIDivX, ReadVIDivV, ReadVIDivX, ReadVMask]>; 696} 697 698multiclass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 699 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 700 Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>; 701 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 702 Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>; 703 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 704 Sched<[WriteVSALUI, ReadVSALUV, ReadVMask]>; 705} 706 707multiclass VSALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 708 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 709 Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>; 710 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 711 Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>; 712} 713 714multiclass VAALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 715 def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 716 Sched<[WriteVAALUV, ReadVAALUV, ReadVAALUV, ReadVMask]>; 717 def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 718 Sched<[WriteVAALUX, ReadVAALUV, ReadVAALUX, ReadVMask]>; 719} 720 721multiclass VSMUL_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> { 722 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 723 Sched<[WriteVSMulV, ReadVSMulV, ReadVSMulV, ReadVMask]>; 724 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 725 Sched<[WriteVSMulX, ReadVSMulV, ReadVSMulX, ReadVMask]>; 726} 727 728multiclass VSSHF_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 729 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 730 Sched<[WriteVSShiftV, ReadVSShiftV, ReadVSShiftV, ReadVMask]>; 731 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 732 Sched<[WriteVSShiftX, ReadVSShiftV, ReadVSShiftX, ReadVMask]>; 733 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 734 Sched<[WriteVSShiftI, ReadVSShiftV, ReadVMask]>; 735} 736 737multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 738 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 739 Sched<[WriteVNClipV, ReadVNClipV, ReadVNClipV, ReadVMask]>; 740 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 741 Sched<[WriteVNClipX, ReadVNClipV, ReadVNClipX, ReadVMask]>; 742 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 743 Sched<[WriteVNClipI, ReadVNClipV, ReadVMask]>; 744} 745 746multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 747 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 748 Sched<[WriteVISlideX, ReadVISlideV, ReadVISlideX, ReadVMask]>; 749 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 750 Sched<[WriteVISlideI, ReadVISlideV, ReadVMask]>; 751} 752 753multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> { 754 def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 755 Sched<[WriteVISlide1X, ReadVISlideV, ReadVISlideX, ReadVMask]>; 756} 757 758multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> { 759 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 760 Sched<[WriteVFSlide1F, ReadVFSlideV, ReadVFSlideF, ReadVMask]>; 761} 762 763multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> { 764 def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">, 765 Sched<[WriteVGatherV, ReadVGatherV, ReadVGatherV, ReadVMask]>; 766 def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">, 767 Sched<[WriteVGatherX, ReadVGatherV, ReadVGatherX, ReadVMask]>; 768 def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>, 769 Sched<[WriteVGatherI, ReadVGatherV, ReadVMask]>; 770} 771 772multiclass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> { 773 def M : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">, 774 Sched<[WriteVCompressV, ReadVCompressV, ReadVCompressV]>; 775} 776 777multiclass VAMO<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> { 778 def _WD : VAMOWd<amoop, width, opcodestr>; 779 def _UNWD : VAMONoWd<amoop, width, opcodestr>; 780} 781 782multiclass VWholeLoad1<string opcodestr, RegisterClass VRC> { 783 def E8_V : VWholeLoad<0, LSWidth8, opcodestr # "e8.v", VRC>, 784 Sched<[WriteVLD1R8, ReadVLDX]>; 785 def E16_V : VWholeLoad<0, LSWidth16, opcodestr # "e16.v", VRC>, 786 Sched<[WriteVLD1R16, ReadVLDX]>; 787 def E32_V : VWholeLoad<0, LSWidth32, opcodestr # "e32.v", VRC>, 788 Sched<[WriteVLD1R32, ReadVLDX]>; 789 def E64_V : VWholeLoad<0, LSWidth64, opcodestr # "e64.v", VRC>, 790 Sched<[WriteVLD1R64, ReadVLDX]>; 791} 792 793multiclass VWholeLoad2<string opcodestr, RegisterClass VRC> { 794 def E8_V : VWholeLoad<1, LSWidth8, opcodestr # "e8.v", VRC>, 795 Sched<[WriteVLD2R8, ReadVLDX]>; 796 def E16_V : VWholeLoad<1, LSWidth16, opcodestr # "e16.v", VRC>, 797 Sched<[WriteVLD2R16, ReadVLDX]>; 798 def E32_V : VWholeLoad<1, LSWidth32, opcodestr # "e32.v", VRC>, 799 Sched<[WriteVLD2R32, ReadVLDX]>; 800 def E64_V : VWholeLoad<1, LSWidth64, opcodestr # "e64.v", VRC>, 801 Sched<[WriteVLD2R64, ReadVLDX]>; 802} 803 804multiclass VWholeLoad4<string opcodestr, RegisterClass VRC> { 805 def E8_V : VWholeLoad<3, LSWidth8, opcodestr # "e8.v", VRC>, 806 Sched<[WriteVLD4R8, ReadVLDX]>; 807 def E16_V : VWholeLoad<3, LSWidth16, opcodestr # "e16.v", VRC>, 808 Sched<[WriteVLD4R16, ReadVLDX]>; 809 def E32_V : VWholeLoad<3, LSWidth32, opcodestr # "e32.v", VRC>, 810 Sched<[WriteVLD4R32, ReadVLDX]>; 811 def E64_V : VWholeLoad<3, LSWidth64, opcodestr # "e64.v", VRC>, 812 Sched<[WriteVLD1R64, ReadVLDX]>; 813} 814 815multiclass VWholeLoad8<string opcodestr, RegisterClass VRC> { 816 def E8_V : VWholeLoad<7, LSWidth8, opcodestr # "e8.v", VRC>, 817 Sched<[WriteVLD8R8, ReadVLDX]>; 818 def E16_V : VWholeLoad<7, LSWidth16, opcodestr # "e16.v", VRC>, 819 Sched<[WriteVLD8R16, ReadVLDX]>; 820 def E32_V : VWholeLoad<7, LSWidth32, opcodestr # "e32.v", VRC>, 821 Sched<[WriteVLD8R32, ReadVLDX]>; 822 def E64_V : VWholeLoad<7, LSWidth64, opcodestr # "e64.v", VRC>, 823 Sched<[WriteVLD8R64, ReadVLDX]>; 824} 825 826//===----------------------------------------------------------------------===// 827// Instructions 828//===----------------------------------------------------------------------===// 829 830let Predicates = [HasStdExtV] in { 831let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { 832def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei), 833 "vsetvli", "$rd, $rs1, $vtypei">; 834 835def VSETIVLI : RVInstSetiVLi<(outs GPR:$rd), (ins uimm5:$uimm, VTypeIOp:$vtypei), 836 "vsetivli", "$rd, $uimm, $vtypei">; 837 838def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), 839 "vsetvl", "$rd, $rs1, $rs2">; 840} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 841 842// Vector Unit-Stride Instructions 843def VLE8_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth8, "vle8.v">, 844 VLESched<8>; 845def VLE16_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth16, "vle16.v">, 846 VLESched<16>; 847def VLE32_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth32, "vle32.v">, 848 VLESched<32>; 849def VLE64_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth64, "vle64.v">, 850 VLESched<64>; 851 852def VLE8FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth8, "vle8ff.v">, 853 VLFSched<8>; 854def VLE16FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth16, "vle16ff.v">, 855 VLFSched<16>; 856def VLE32FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth32, "vle32ff.v">, 857 VLFSched<32>; 858def VLE64FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth64, "vle64ff.v">, 859 VLFSched<64>; 860 861def VLM_V : VUnitStrideLoadMask<"vlm.v">, 862 Sched<[WriteVLDM, ReadVLDX]>; 863def VSM_V : VUnitStrideStoreMask<"vsm.v">, 864 Sched<[WriteVSTM, ReadVSTM, ReadVSTX]>; 865def : InstAlias<"vle1.v $vd, (${rs1})", 866 (VLM_V VR:$vd, GPR:$rs1), 0>; 867def : InstAlias<"vse1.v $vs3, (${rs1})", 868 (VSM_V VR:$vs3, GPR:$rs1), 0>; 869 870def VSE8_V : VUnitStrideStore<SUMOPUnitStride, LSWidth8, "vse8.v">, 871 VSESched<8>; 872def VSE16_V : VUnitStrideStore<SUMOPUnitStride, LSWidth16, "vse16.v">, 873 VSESched<16>; 874def VSE32_V : VUnitStrideStore<SUMOPUnitStride, LSWidth32, "vse32.v">, 875 VSESched<32>; 876def VSE64_V : VUnitStrideStore<SUMOPUnitStride, LSWidth64, "vse64.v">, 877 VSESched<64>; 878 879// Vector Strided Instructions 880def VLSE8_V : VStridedLoad<LSWidth8, "vlse8.v">, 881 VLSSched<8>; 882def VLSE16_V : VStridedLoad<LSWidth16, "vlse16.v">, 883 VLSSched<16>; 884def VLSE32_V : VStridedLoad<LSWidth32, "vlse32.v">, 885 VLSSched<32>; 886def VLSE64_V : VStridedLoad<LSWidth64, "vlse64.v">, 887 VLSSched<32>; 888 889def VSSE8_V : VStridedStore<LSWidth8, "vsse8.v">, 890 VSSSched<8>; 891def VSSE16_V : VStridedStore<LSWidth16, "vsse16.v">, 892 VSSSched<16>; 893def VSSE32_V : VStridedStore<LSWidth32, "vsse32.v">, 894 VSSSched<32>; 895def VSSE64_V : VStridedStore<LSWidth64, "vsse64.v">, 896 VSSSched<64>; 897 898// Vector Indexed Instructions 899foreach n = [8, 16, 32, 64] in { 900defvar w = !cast<RISCVWidth>("LSWidth" # n); 901 902def VLUXEI # n # _V : 903 VIndexedLoad<MOPLDIndexedUnord, w, "vluxei" # n # ".v">, 904 VLXSched<n, "U">; 905def VLOXEI # n # _V : 906 VIndexedLoad<MOPLDIndexedOrder, w, "vloxei" # n # ".v">, 907 VLXSched<n, "O">; 908 909def VSUXEI # n # _V : 910 VIndexedStore<MOPSTIndexedUnord, w, "vsuxei" # n # ".v">, 911 VSXSched<n, "U">; 912def VSOXEI # n # _V : 913 VIndexedStore<MOPSTIndexedOrder, w, "vsoxei" # n # ".v">, 914 VSXSched<n, "O">; 915} 916 917defm VL1R : VWholeLoad1<"vl1r", VR>; 918defm VL2R : VWholeLoad2<"vl2r", VRM2>; 919defm VL4R : VWholeLoad4<"vl4r", VRM4>; 920defm VL8R : VWholeLoad8<"vl8r", VRM8>; 921 922def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; 923def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>; 924def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>; 925def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>; 926 927def VS1R_V : VWholeStore<0, "vs1r.v", VR>, 928 Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>; 929def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>, 930 Sched<[WriteVST2R, ReadVST2R, ReadVSTX]>; 931def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>, 932 Sched<[WriteVST4R, ReadVST4R, ReadVSTX]>; 933def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>, 934 Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>; 935 936// Vector Single-Width Integer Add and Subtract 937defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; 938defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>; 939defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>; 940 941def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 942 943// Vector Widening Integer Add/Subtract 944// Refer to 11.2 Widening Vector Arithmetic Instructions 945// The destination vector register group cannot overlap a source vector 946// register group of a different element width (including the mask register 947// if masked), otherwise an illegal instruction exception is raised. 948let Constraints = "@earlyclobber $vd" in { 949let RVVConstraint = WidenV in { 950defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000>; 951defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010>; 952defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001>; 953defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011>; 954} // RVVConstraint = WidenV 955// Set earlyclobber for following instructions for second and mask operands. 956// This has the downside that the earlyclobber constraint is too coarse and 957// will impose unnecessary restrictions by not allowing the destination to 958// overlap with the first (wide) operand. 959let RVVConstraint = WidenW in { 960defm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">; 961defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">; 962defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">; 963defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">; 964} // RVVConstraint = WidenW 965} // Constraints = "@earlyclobber $vd" 966 967def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm", 968 (VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 969def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm", 970 (VWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 971 972// Vector Integer Extension 973defm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>; 974defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>; 975defm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>; 976defm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>; 977defm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>; 978defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>; 979 980// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions 981defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>; 982let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 983defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>; 984defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>; 985} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 986defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>; 987let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 988defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>; 989defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>; 990} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 991 992// Vector Bitwise Logical Instructions 993defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>; 994defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>; 995defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>; 996 997def : InstAlias<"vnot.v $vd, $vs$vm", 998 (VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>; 999 1000// Vector Single-Width Bit Shift Instructions 1001defm VSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101, uimm5>; 1002defm VSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000, uimm5>; 1003defm VSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001, uimm5>; 1004 1005// Vector Narrowing Integer Right Shift Instructions 1006// Refer to 11.3. Narrowing Vector Arithmetic Instructions 1007// The destination vector register group cannot overlap the first source 1008// vector register group (specified by vs2). The destination vector register 1009// group cannot overlap the mask register if used, unless LMUL=1. 1010let Constraints = "@earlyclobber $vd" in { 1011defm VNSRL_W : VNSHT_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">; 1012defm VNSRA_W : VNSHT_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">; 1013} // Constraints = "@earlyclobber $vd" 1014 1015def : InstAlias<"vncvt.x.x.w $vd, $vs$vm", 1016 (VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 1017 1018// Vector Integer Comparison Instructions 1019let RVVConstraint = NoConstraint in { 1020defm VMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>; 1021defm VMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>; 1022defm VMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>; 1023defm VMSLT_V : VCMP_IV_V_X<"vmslt", 0b011011>; 1024defm VMSLEU_V : VCMP_IV_V_X_I<"vmsleu", 0b011100>; 1025defm VMSLE_V : VCMP_IV_V_X_I<"vmsle", 0b011101>; 1026defm VMSGTU_V : VCMP_IV_X_I<"vmsgtu", 0b011110>; 1027defm VMSGT_V : VCMP_IV_X_I<"vmsgt", 0b011111>; 1028} // RVVConstraint = NoConstraint 1029 1030def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm", 1031 (VMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1032def : InstAlias<"vmsgt.vv $vd, $va, $vb$vm", 1033 (VMSLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1034def : InstAlias<"vmsgeu.vv $vd, $va, $vb$vm", 1035 (VMSLEU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1036def : InstAlias<"vmsge.vv $vd, $va, $vb$vm", 1037 (VMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1038 1039let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, 1040 mayStore = 0 in { 1041// For unsigned comparisons we need to special case 0 immediate to maintain 1042// the always true/false semantics we would invert if we just decremented the 1043// immediate like we do for signed. To match the GNU assembler we will use 1044// vmseq/vmsne.vv with the same register for both operands which we can't do 1045// from an InstAlias. 1046def PseudoVMSGEU_VI : Pseudo<(outs VR:$vd), 1047 (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1048 [], "vmsgeu.vi", "$vd, $vs2, $imm$vm">; 1049def PseudoVMSLTU_VI : Pseudo<(outs VR:$vd), 1050 (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1051 [], "vmsltu.vi", "$vd, $vs2, $imm$vm">; 1052// Handle signed with pseudos as well for more consistency in the 1053// implementation. 1054def PseudoVMSGE_VI : Pseudo<(outs VR:$vd), 1055 (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1056 [], "vmsge.vi", "$vd, $vs2, $imm$vm">; 1057def PseudoVMSLT_VI : Pseudo<(outs VR:$vd), 1058 (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1059 [], "vmslt.vi", "$vd, $vs2, $imm$vm">; 1060} 1061 1062let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, 1063 mayStore = 0 in { 1064def PseudoVMSGEU_VX : Pseudo<(outs VR:$vd), 1065 (ins VR:$vs2, GPR:$rs1), 1066 [], "vmsgeu.vx", "$vd, $vs2, $rs1">; 1067def PseudoVMSGE_VX : Pseudo<(outs VR:$vd), 1068 (ins VR:$vs2, GPR:$rs1), 1069 [], "vmsge.vx", "$vd, $vs2, $rs1">; 1070def PseudoVMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd), 1071 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1072 [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm">; 1073def PseudoVMSGE_VX_M : Pseudo<(outs VRNoV0:$vd), 1074 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1075 [], "vmsge.vx", "$vd, $vs2, $rs1$vm">; 1076def PseudoVMSGEU_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), 1077 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1078 [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">; 1079def PseudoVMSGE_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), 1080 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1081 [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">; 1082} 1083 1084// Vector Integer Min/Max Instructions 1085defm VMINU_V : VCMP_IV_V_X<"vminu", 0b000100>; 1086defm VMIN_V : VCMP_IV_V_X<"vmin", 0b000101>; 1087defm VMAXU_V : VCMP_IV_V_X<"vmaxu", 0b000110>; 1088defm VMAX_V : VCMP_IV_V_X<"vmax", 0b000111>; 1089 1090// Vector Single-Width Integer Multiply Instructions 1091defm VMUL_V : VMUL_MV_V_X<"vmul", 0b100101>; 1092defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>; 1093defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>; 1094defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>; 1095 1096// Vector Integer Divide Instructions 1097defm VDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>; 1098defm VDIV_V : VDIV_MV_V_X<"vdiv", 0b100001>; 1099defm VREMU_V : VDIV_MV_V_X<"vremu", 0b100010>; 1100defm VREM_V : VDIV_MV_V_X<"vrem", 0b100011>; 1101 1102// Vector Widening Integer Multiply Instructions 1103let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1104defm VWMUL_V : VWMUL_MV_V_X<"vwmul", 0b111011>; 1105defm VWMULU_V : VWMUL_MV_V_X<"vwmulu", 0b111000>; 1106defm VWMULSU_V : VWMUL_MV_V_X<"vwmulsu", 0b111010>; 1107} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 1108 1109// Vector Single-Width Integer Multiply-Add Instructions 1110defm VMACC_V : VMAC_MV_V_X<"vmacc", 0b101101>; 1111defm VNMSAC_V : VMAC_MV_V_X<"vnmsac", 0b101111>; 1112defm VMADD_V : VMAC_MV_V_X<"vmadd", 0b101001>; 1113defm VNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>; 1114 1115// Vector Widening Integer Multiply-Add Instructions 1116let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1117defm VWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>; 1118defm VWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>; 1119defm VWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111111>; 1120defm VWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>; 1121} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 1122 1123// Vector Integer Merge Instructions 1124defm VMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>; 1125 1126// Vector Integer Move Instructions 1127let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1, 1128 RVVConstraint = NoConstraint in { 1129// op vd, vs1 1130def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd), 1131 (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">, 1132 Sched<[WriteVIMovV, ReadVIMovV]>; 1133// op vd, rs1 1134def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd), 1135 (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">, 1136 Sched<[WriteVIMovX, ReadVIMovX]>; 1137// op vd, imm 1138def VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd), 1139 (ins simm5:$imm), "vmv.v.i", "$vd, $imm">, 1140 Sched<[WriteVIMovI]>; 1141} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1142 1143// Vector Fixed-Point Arithmetic Instructions 1144defm VSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>; 1145defm VSADD_V : VSALU_IV_V_X_I<"vsadd", 0b100001>; 1146defm VSSUBU_V : VSALU_IV_V_X<"vssubu", 0b100010>; 1147defm VSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>; 1148 1149// Vector Single-Width Averaging Add and Subtract 1150defm VAADDU_V : VAALU_MV_V_X<"vaaddu", 0b001000>; 1151defm VAADD_V : VAALU_MV_V_X<"vaadd", 0b001001>; 1152defm VASUBU_V : VAALU_MV_V_X<"vasubu", 0b001010>; 1153defm VASUB_V : VAALU_MV_V_X<"vasub", 0b001011>; 1154 1155// Vector Single-Width Fractional Multiply with Rounding and Saturation 1156defm VSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>; 1157 1158// Vector Single-Width Scaling Shift Instructions 1159defm VSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010, uimm5>; 1160defm VSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011, uimm5>; 1161 1162// Vector Narrowing Fixed-Point Clip Instructions 1163let Constraints = "@earlyclobber $vd" in { 1164defm VNCLIPU_W : VNCLP_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">; 1165defm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">; 1166} // Constraints = "@earlyclobber $vd" 1167} // Predicates = [HasStdExtV] 1168 1169let Predicates = [HasStdExtV, HasStdExtF] in { 1170// Vector Single-Width Floating-Point Add/Subtract Instructions 1171defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>; 1172defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>; 1173defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>; 1174 1175// Vector Widening Floating-Point Add/Subtract Instructions 1176let Constraints = "@earlyclobber $vd" in { 1177let RVVConstraint = WidenV in { 1178defm VFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000>; 1179defm VFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010>; 1180} // RVVConstraint = WidenV 1181// Set earlyclobber for following instructions for second and mask operands. 1182// This has the downside that the earlyclobber constraint is too coarse and 1183// will impose unnecessary restrictions by not allowing the destination to 1184// overlap with the first (wide) operand. 1185let RVVConstraint = WidenW in { 1186defm VFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">; 1187defm VFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">; 1188} // RVVConstraint = WidenW 1189} // Constraints = "@earlyclobber $vd" 1190 1191// Vector Single-Width Floating-Point Multiply/Divide Instructions 1192defm VFMUL_V : VMUL_FV_V_F<"vfmul", 0b100100>; 1193defm VFDIV_V : VDIV_FV_V_F<"vfdiv", 0b100000>; 1194defm VFRDIV_V : VRDIV_FV_F<"vfrdiv", 0b100001>; 1195 1196// Vector Widening Floating-Point Multiply 1197let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1198defm VFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>; 1199} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 1200 1201// Vector Single-Width Floating-Point Fused Multiply-Add Instructions 1202defm VFMACC_V : VMAC_FV_V_F<"vfmacc", 0b101100>; 1203defm VFNMACC_V : VMAC_FV_V_F<"vfnmacc", 0b101101>; 1204defm VFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>; 1205defm VFNMSAC_V : VMAC_FV_V_F<"vfnmsac", 0b101111>; 1206defm VFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>; 1207defm VFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>; 1208defm VFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>; 1209defm VFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>; 1210 1211// Vector Widening Floating-Point Fused Multiply-Add Instructions 1212let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1213defm VFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>; 1214defm VFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>; 1215defm VFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>; 1216defm VFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>; 1217} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 1218 1219// Vector Floating-Point Square-Root Instruction 1220defm VFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>; 1221defm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>; 1222defm VFREC7_V : VRCP_FV_VS2<"vfrec7.v", 0b010011, 0b00101>; 1223 1224// Vector Floating-Point MIN/MAX Instructions 1225defm VFMIN_V : VCMP_FV_V_F<"vfmin", 0b000100>; 1226defm VFMAX_V : VCMP_FV_V_F<"vfmax", 0b000110>; 1227 1228// Vector Floating-Point Sign-Injection Instructions 1229defm VFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>; 1230defm VFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>; 1231defm VFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>; 1232 1233def : InstAlias<"vfneg.v $vd, $vs$vm", 1234 (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>; 1235def : InstAlias<"vfabs.v $vd, $vs$vm", 1236 (VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>; 1237 1238// Vector Floating-Point Compare Instructions 1239let RVVConstraint = NoConstraint in { 1240defm VMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>; 1241defm VMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>; 1242defm VMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>; 1243defm VMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>; 1244defm VMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>; 1245defm VMFGE_V : VCMP_FV_F<"vmfge", 0b011111>; 1246} // RVVConstraint = NoConstraint 1247 1248def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm", 1249 (VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1250def : InstAlias<"vmfge.vv $vd, $va, $vb$vm", 1251 (VMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1252 1253// Vector Floating-Point Classify Instruction 1254defm VFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b010011, 0b10000>; 1255 1256let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 1257 1258// Vector Floating-Point Merge Instruction 1259let vm = 0 in 1260def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd), 1261 (ins VR:$vs2, FPR32:$rs1, VMV0:$v0), 1262 "vfmerge.vfm", "$vd, $vs2, $rs1, v0">, 1263 Sched<[WriteVFMergeV, ReadVFMergeV, ReadVFMergeF, ReadVMask]>; 1264 1265// Vector Floating-Point Move Instruction 1266let RVVConstraint = NoConstraint in 1267let vm = 1, vs2 = 0 in 1268def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd), 1269 (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">, 1270 Sched<[WriteVFMovV, ReadVFMovF]>; 1271 1272} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1273 1274// Single-Width Floating-Point/Integer Type-Convert Instructions 1275defm VFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>; 1276defm VFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>; 1277defm VFCVT_RTZ_XU_F_V : VCVTI_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>; 1278defm VFCVT_RTZ_X_F_V : VCVTI_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>; 1279defm VFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>; 1280defm VFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>; 1281 1282// Widening Floating-Point/Integer Type-Convert Instructions 1283let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in { 1284defm VFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>; 1285defm VFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>; 1286defm VFWCVT_RTZ_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>; 1287defm VFWCVT_RTZ_X_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>; 1288defm VFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>; 1289defm VFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>; 1290defm VFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>; 1291} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt 1292 1293// Narrowing Floating-Point/Integer Type-Convert Instructions 1294let Constraints = "@earlyclobber $vd" in { 1295defm VFNCVT_XU_F_W : VNCVTI_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>; 1296defm VFNCVT_X_F_W : VNCVTI_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>; 1297defm VFNCVT_RTZ_XU_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>; 1298defm VFNCVT_RTZ_X_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>; 1299defm VFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>; 1300defm VFNCVT_F_X_W : VNCVTF_IV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>; 1301defm VFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>; 1302defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>; 1303} // Constraints = "@earlyclobber $vd" 1304} // Predicates = [HasStdExtV, HasStdExtF] 1305 1306let Predicates = [HasStdExtV] in { 1307 1308// Vector Single-Width Integer Reduction Instructions 1309let RVVConstraint = NoConstraint in { 1310defm VREDSUM : VRED_MV_V<"vredsum", 0b000000>; 1311defm VREDMAXU : VRED_MV_V<"vredmaxu", 0b000110>; 1312defm VREDMAX : VRED_MV_V<"vredmax", 0b000111>; 1313defm VREDMINU : VRED_MV_V<"vredminu", 0b000100>; 1314defm VREDMIN : VRED_MV_V<"vredmin", 0b000101>; 1315defm VREDAND : VRED_MV_V<"vredand", 0b000001>; 1316defm VREDOR : VRED_MV_V<"vredor", 0b000010>; 1317defm VREDXOR : VRED_MV_V<"vredxor", 0b000011>; 1318} // RVVConstraint = NoConstraint 1319 1320// Vector Widening Integer Reduction Instructions 1321let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 1322// Set earlyclobber for following instructions for second and mask operands. 1323// This has the downside that the earlyclobber constraint is too coarse and 1324// will impose unnecessary restrictions by not allowing the destination to 1325// overlap with the first (wide) operand. 1326defm VWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>; 1327defm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>; 1328} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 1329 1330} // Predicates = [HasStdExtV] 1331 1332let Predicates = [HasStdExtV, HasStdExtF] in { 1333// Vector Single-Width Floating-Point Reduction Instructions 1334let RVVConstraint = NoConstraint in { 1335defm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>; 1336defm VFREDUSUM : VRED_FV_V<"vfredusum", 0b000001>; 1337defm VFREDMAX : VRED_FV_V<"vfredmax", 0b000111>; 1338defm VFREDMIN : VRED_FV_V<"vfredmin", 0b000101>; 1339} // RVVConstraint = NoConstraint 1340 1341def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm", 1342 (VFREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>; 1343 1344// Vector Widening Floating-Point Reduction Instructions 1345let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 1346// Set earlyclobber for following instructions for second and mask operands. 1347// This has the downside that the earlyclobber constraint is too coarse and 1348// will impose unnecessary restrictions by not allowing the destination to 1349// overlap with the first (wide) operand. 1350defm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>; 1351defm VFWREDUSUM : VWRED_FV_V<"vfwredusum", 0b110001>; 1352} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 1353} // Predicates = [HasStdExtV, HasStdExtF] 1354 1355def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm", 1356 (VFWREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>; 1357 1358 1359let Predicates = [HasStdExtV] in { 1360// Vector Mask-Register Logical Instructions 1361let RVVConstraint = NoConstraint in { 1362defm VMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">; 1363defm VMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">; 1364defm VMANDNOT_M : VMALU_MV_Mask<"vmandnot", 0b011000, "m">; 1365defm VMXOR_M : VMALU_MV_Mask<"vmxor", 0b011011, "m">; 1366defm VMOR_M : VMALU_MV_Mask<"vmor", 0b011010, "m">; 1367defm VMNOR_M : VMALU_MV_Mask<"vmnor", 0b011110, "m">; 1368defm VMORNOT_M : VMALU_MV_Mask<"vmornot", 0b011100, "m">; 1369defm VMXNOR_M : VMALU_MV_Mask<"vmxnor", 0b011111, "m">; 1370} 1371 1372def : InstAlias<"vmmv.m $vd, $vs", 1373 (VMAND_MM VR:$vd, VR:$vs, VR:$vs)>; 1374def : InstAlias<"vmclr.m $vd", 1375 (VMXOR_MM VR:$vd, VR:$vd, VR:$vd)>; 1376def : InstAlias<"vmset.m $vd", 1377 (VMXNOR_MM VR:$vd, VR:$vd, VR:$vd)>; 1378def : InstAlias<"vmnot.m $vd, $vs", 1379 (VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>; 1380 1381let hasSideEffects = 0, mayLoad = 0, mayStore = 0, 1382 RVVConstraint = NoConstraint in { 1383 1384// Vector mask population count vpopc 1385def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd), 1386 (ins VR:$vs2, VMaskOp:$vm), 1387 "vpopc.m", "$vd, $vs2$vm">, 1388 Sched<[WriteVMPopV, ReadVMPopV, ReadVMask]>; 1389 1390// vfirst find-first-set mask bit 1391def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd), 1392 (ins VR:$vs2, VMaskOp:$vm), 1393 "vfirst.m", "$vd, $vs2$vm">, 1394 Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMask]>; 1395 1396} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1397 1398let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { 1399 1400// vmsbf.m set-before-first mask bit 1401defm VMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010100, 0b00001>; 1402// vmsif.m set-including-first mask bit 1403defm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>; 1404// vmsof.m set-only-first mask bit 1405defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>; 1406// Vector Iota Instruction 1407defm VIOTA_M : VMIOT_MV_V<"viota.m", 0b010100, 0b10000>; 1408 1409} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota 1410 1411// Vector Element Index Instruction 1412let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 1413 1414let vs2 = 0 in 1415def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd), 1416 (ins VMaskOp:$vm), "vid.v", "$vd$vm">, 1417 Sched<[WriteVMIdxV, ReadVMask]>; 1418 1419// Integer Scalar Move Instructions 1420let vm = 1, RVVConstraint = NoConstraint in { 1421def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd), 1422 (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">, 1423 Sched<[WriteVIMovVX, ReadVIMovVX]>; 1424let Constraints = "$vd = $vd_wb" in 1425def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb), 1426 (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">, 1427 Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>; 1428} 1429 1430} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1431 1432} // Predicates = [HasStdExtV] 1433 1434let Predicates = [HasStdExtV, HasStdExtF] in { 1435 1436let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1, 1437 RVVConstraint = NoConstraint in { 1438// Floating-Point Scalar Move Instructions 1439def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd), 1440 (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">, 1441 Sched<[WriteVFMovVF, ReadVFMovVF]>; 1442let Constraints = "$vd = $vd_wb" in 1443def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb), 1444 (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">, 1445 Sched<[WriteVFMovFV, ReadVFMovFV, ReadVFMovFX]>; 1446 1447} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 1448 1449} // Predicates = [HasStdExtV, HasStdExtF] 1450 1451let Predicates = [HasStdExtV] in { 1452// Vector Slide Instructions 1453let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { 1454defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, uimm5>; 1455defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>; 1456} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp 1457defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, uimm5>; 1458defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>; 1459} // Predicates = [HasStdExtV] 1460 1461let Predicates = [HasStdExtV, HasStdExtF] in { 1462let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { 1463defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>; 1464} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp 1465defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>; 1466} // Predicates = [HasStdExtV, HasStdExtF] 1467 1468let Predicates = [HasStdExtV] in { 1469// Vector Register Gather Instruction 1470let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in { 1471defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100, uimm5>; 1472def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">, 1473 Sched<[WriteVGatherV, ReadVGatherV, ReadVGatherV]>; 1474} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather 1475 1476// Vector Compress Instruction 1477let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in { 1478defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>; 1479} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress 1480 1481let hasSideEffects = 0, mayLoad = 0, mayStore = 0, 1482 RVVConstraint = NoConstraint in { 1483foreach n = [1, 2, 4, 8] in { 1484 def VMV#n#R_V : RVInstV<0b100111, !add(n, -1), OPIVI, (outs VR:$vd), 1485 (ins VR:$vs2), "vmv" # n # "r.v", "$vd, $vs2">, 1486 VMVRSched<n> { 1487 let Uses = []; 1488 let vm = 1; 1489} 1490} 1491} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1492} // Predicates = [HasStdExtV] 1493 1494let Predicates = [HasStdExtZvlsseg] in { 1495 foreach nf=2-8 in { 1496 def VLSEG#nf#E8_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth8, "vlseg"#nf#"e8.v">; 1497 def VLSEG#nf#E16_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth16, "vlseg"#nf#"e16.v">; 1498 def VLSEG#nf#E32_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth32, "vlseg"#nf#"e32.v">; 1499 def VLSEG#nf#E64_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth64, "vlseg"#nf#"e64.v">; 1500 1501 def VLSEG#nf#E8FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth8, "vlseg"#nf#"e8ff.v">; 1502 def VLSEG#nf#E16FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth16, "vlseg"#nf#"e16ff.v">; 1503 def VLSEG#nf#E32FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth32, "vlseg"#nf#"e32ff.v">; 1504 def VLSEG#nf#E64FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth64, "vlseg"#nf#"e64ff.v">; 1505 1506 def VSSEG#nf#E8_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth8, "vsseg"#nf#"e8.v">; 1507 def VSSEG#nf#E16_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth16, "vsseg"#nf#"e16.v">; 1508 def VSSEG#nf#E32_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth32, "vsseg"#nf#"e32.v">; 1509 def VSSEG#nf#E64_V : VUnitStrideSegmentStore<!add(nf, -1), LSWidth64, "vsseg"#nf#"e64.v">; 1510 1511 // Vector Strided Instructions 1512 def VLSSEG#nf#E8_V : VStridedSegmentLoad<!add(nf, -1), LSWidth8, "vlsseg"#nf#"e8.v">; 1513 def VLSSEG#nf#E16_V : VStridedSegmentLoad<!add(nf, -1), LSWidth16, "vlsseg"#nf#"e16.v">; 1514 def VLSSEG#nf#E32_V : VStridedSegmentLoad<!add(nf, -1), LSWidth32, "vlsseg"#nf#"e32.v">; 1515 def VLSSEG#nf#E64_V : VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">; 1516 1517 def VSSSEG#nf#E8_V : VStridedSegmentStore<!add(nf, -1), LSWidth8, "vssseg"#nf#"e8.v">; 1518 def VSSSEG#nf#E16_V : VStridedSegmentStore<!add(nf, -1), LSWidth16, "vssseg"#nf#"e16.v">; 1519 def VSSSEG#nf#E32_V : VStridedSegmentStore<!add(nf, -1), LSWidth32, "vssseg"#nf#"e32.v">; 1520 def VSSSEG#nf#E64_V : VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">; 1521 1522 // Vector Indexed Instructions 1523 def VLUXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, 1524 LSWidth8, "vluxseg"#nf#"ei8.v">; 1525 def VLUXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, 1526 LSWidth16, "vluxseg"#nf#"ei16.v">; 1527 def VLUXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, 1528 LSWidth32, "vluxseg"#nf#"ei32.v">; 1529 def VLUXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, 1530 LSWidth64, "vluxseg"#nf#"ei64.v">; 1531 1532 def VLOXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, 1533 LSWidth8, "vloxseg"#nf#"ei8.v">; 1534 def VLOXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, 1535 LSWidth16, "vloxseg"#nf#"ei16.v">; 1536 def VLOXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, 1537 LSWidth32, "vloxseg"#nf#"ei32.v">; 1538 def VLOXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, 1539 LSWidth64, "vloxseg"#nf#"ei64.v">; 1540 1541 def VSUXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, 1542 LSWidth8, "vsuxseg"#nf#"ei8.v">; 1543 def VSUXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, 1544 LSWidth16, "vsuxseg"#nf#"ei16.v">; 1545 def VSUXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, 1546 LSWidth32, "vsuxseg"#nf#"ei32.v">; 1547 def VSUXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, 1548 LSWidth64, "vsuxseg"#nf#"ei64.v">; 1549 1550 def VSOXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, 1551 LSWidth8, "vsoxseg"#nf#"ei8.v">; 1552 def VSOXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, 1553 LSWidth16, "vsoxseg"#nf#"ei16.v">; 1554 def VSOXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, 1555 LSWidth32, "vsoxseg"#nf#"ei32.v">; 1556 def VSOXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, 1557 LSWidth64, "vsoxseg"#nf#"ei64.v">; 1558 } 1559} // Predicates = [HasStdExtZvlsseg] 1560 1561let Predicates = [HasStdExtZvamo, HasStdExtA] in { 1562 defm VAMOSWAPEI8 : VAMO<AMOOPVamoSwap, LSWidth8, "vamoswapei8.v">; 1563 defm VAMOSWAPEI16 : VAMO<AMOOPVamoSwap, LSWidth16, "vamoswapei16.v">; 1564 defm VAMOSWAPEI32 : VAMO<AMOOPVamoSwap, LSWidth32, "vamoswapei32.v">; 1565 1566 defm VAMOADDEI8 : VAMO<AMOOPVamoAdd, LSWidth8, "vamoaddei8.v">; 1567 defm VAMOADDEI16 : VAMO<AMOOPVamoAdd, LSWidth16, "vamoaddei16.v">; 1568 defm VAMOADDEI32 : VAMO<AMOOPVamoAdd, LSWidth32, "vamoaddei32.v">; 1569 1570 defm VAMOXOREI8 : VAMO<AMOOPVamoXor, LSWidth8, "vamoxorei8.v">; 1571 defm VAMOXOREI16 : VAMO<AMOOPVamoXor, LSWidth16, "vamoxorei16.v">; 1572 defm VAMOXOREI32 : VAMO<AMOOPVamoXor, LSWidth32, "vamoxorei32.v">; 1573 1574 defm VAMOANDEI8 : VAMO<AMOOPVamoAnd, LSWidth8, "vamoandei8.v">; 1575 defm VAMOANDEI16 : VAMO<AMOOPVamoAnd, LSWidth16, "vamoandei16.v">; 1576 defm VAMOANDEI32 : VAMO<AMOOPVamoAnd, LSWidth32, "vamoandei32.v">; 1577 1578 defm VAMOOREI8 : VAMO<AMOOPVamoOr, LSWidth8, "vamoorei8.v">; 1579 defm VAMOOREI16 : VAMO<AMOOPVamoOr, LSWidth16, "vamoorei16.v">; 1580 defm VAMOOREI32 : VAMO<AMOOPVamoOr, LSWidth32, "vamoorei32.v">; 1581 1582 defm VAMOMINEI8 : VAMO<AMOOPVamoMin, LSWidth8, "vamominei8.v">; 1583 defm VAMOMINEI16 : VAMO<AMOOPVamoMin, LSWidth16, "vamominei16.v">; 1584 defm VAMOMINEI32 : VAMO<AMOOPVamoMin, LSWidth32, "vamominei32.v">; 1585 1586 defm VAMOMAXEI8 : VAMO<AMOOPVamoMax, LSWidth8, "vamomaxei8.v">; 1587 defm VAMOMAXEI16 : VAMO<AMOOPVamoMax, LSWidth16, "vamomaxei16.v">; 1588 defm VAMOMAXEI32 : VAMO<AMOOPVamoMax, LSWidth32, "vamomaxei32.v">; 1589 1590 defm VAMOMINUEI8 : VAMO<AMOOPVamoMinu, LSWidth8, "vamominuei8.v">; 1591 defm VAMOMINUEI16 : VAMO<AMOOPVamoMinu, LSWidth16, "vamominuei16.v">; 1592 defm VAMOMINUEI32 : VAMO<AMOOPVamoMinu, LSWidth32, "vamominuei32.v">; 1593 1594 defm VAMOMAXUEI8 : VAMO<AMOOPVamoMaxu, LSWidth8, "vamomaxuei8.v">; 1595 defm VAMOMAXUEI16 : VAMO<AMOOPVamoMaxu, LSWidth16, "vamomaxuei16.v">; 1596 defm VAMOMAXUEI32 : VAMO<AMOOPVamoMaxu, LSWidth32, "vamomaxuei32.v">; 1597} // Predicates = [HasStdExtZvamo, HasStdExtA] 1598 1599let Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64] in { 1600 defm VAMOSWAPEI64 : VAMO<AMOOPVamoSwap, LSWidth64, "vamoswapei64.v">; 1601 defm VAMOADDEI64 : VAMO<AMOOPVamoAdd, LSWidth64, "vamoaddei64.v">; 1602 defm VAMOXOREI64 : VAMO<AMOOPVamoXor, LSWidth64, "vamoxorei64.v">; 1603 defm VAMOANDEI64 : VAMO<AMOOPVamoAnd, LSWidth64, "vamoandei64.v">; 1604 defm VAMOOREI64 : VAMO<AMOOPVamoOr, LSWidth64, "vamoorei64.v">; 1605 defm VAMOMINEI64 : VAMO<AMOOPVamoMin, LSWidth64, "vamominei64.v">; 1606 defm VAMOMAXEI64 : VAMO<AMOOPVamoMax, LSWidth64, "vamomaxei64.v">; 1607 defm VAMOMINUEI64 : VAMO<AMOOPVamoMinu, LSWidth64, "vamominuei64.v">; 1608 defm VAMOMAXUEI64 : VAMO<AMOOPVamoMaxu, LSWidth64, "vamomaxuei64.v">; 1609} // Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64] 1610 1611include "RISCVInstrInfoVPseudos.td" 1612