1; RUN: opt -mtriple=arm-none-none-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
2;
3; The loads are not consecutive: check that the rewrite isn't triggered.
4;
5; CHECK-NOT:  call i32 @llvm.arm.smlad
6;
7define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
8entry:
9  %cmp24 = icmp sgt i32 %arg, 0
10  br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
11
12for.body.preheader:
13  %.pre = load i16, i16* %arg3, align 2
14  %.pre27 = load i16, i16* %arg2, align 2
15  br label %for.body
16
17for.cond.cleanup:
18  %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
19  ret i32 %mac1.0.lcssa
20
21for.body:
22  %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
23  %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
24  %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
25  %0 = load i16, i16* %arrayidx, align 2
26  %add = add nuw nsw i32 %i.025, 1
27  %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
28  %1 = load i16, i16* %arrayidx1, align 2
29  %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
30  %2 = load i16, i16* %arrayidx3, align 2
31  %conv = sext i16 %2 to i32
32  %conv4 = sext i16 %0 to i32
33  %mul = mul nsw i32 %conv, %conv4
34
35; Here we add another constants offset of 2, to make sure the
36; loads to %3 and %2 are not consecutive:
37
38  %add5 = add nuw nsw i32 %i.025, 2
39  %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add5
40  %3 = load i16, i16* %arrayidx6, align 2
41
42  %conv7 = sext i16 %3 to i32
43  %conv8 = sext i16 %1 to i32
44  %mul9 = mul nsw i32 %conv7, %conv8
45  %add10 = add i32 %mul, %mac1.026
46  %add11 = add i32 %add10, %mul9
47  %exitcond = icmp ne i32 %add, %arg
48  br i1 %exitcond, label %for.body, label %for.cond.cleanup
49}
50
51