1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64IM
4
5; The patterns for the 'W' suffixed RV64M instructions have the potential of
6; missing cases. This file checks all the variants of
7; sign-extended/zero-extended/any-extended inputs and outputs.
8
9define i32 @aext_mulw_aext_aext(i32 %a, i32 %b) nounwind {
10; RV64IM-LABEL: aext_mulw_aext_aext:
11; RV64IM:       # %bb.0:
12; RV64IM-NEXT:    mulw a0, a0, a1
13; RV64IM-NEXT:    ret
14  %1 = mul i32 %a, %b
15  ret i32 %1
16}
17
18define i32 @aext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {
19; RV64IM-LABEL: aext_mulw_aext_sext:
20; RV64IM:       # %bb.0:
21; RV64IM-NEXT:    mulw a0, a0, a1
22; RV64IM-NEXT:    ret
23  %1 = mul i32 %a, %b
24  ret i32 %1
25}
26
27define i32 @aext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
28; RV64IM-LABEL: aext_mulw_aext_zext:
29; RV64IM:       # %bb.0:
30; RV64IM-NEXT:    mulw a0, a0, a1
31; RV64IM-NEXT:    ret
32  %1 = mul i32 %a, %b
33  ret i32 %1
34}
35
36define i32 @aext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {
37; RV64IM-LABEL: aext_mulw_sext_aext:
38; RV64IM:       # %bb.0:
39; RV64IM-NEXT:    mulw a0, a0, a1
40; RV64IM-NEXT:    ret
41  %1 = mul i32 %a, %b
42  ret i32 %1
43}
44
45define i32 @aext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
46; RV64IM-LABEL: aext_mulw_sext_sext:
47; RV64IM:       # %bb.0:
48; RV64IM-NEXT:    mulw a0, a0, a1
49; RV64IM-NEXT:    ret
50  %1 = mul i32 %a, %b
51  ret i32 %1
52}
53
54define i32 @aext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
55; RV64IM-LABEL: aext_mulw_sext_zext:
56; RV64IM:       # %bb.0:
57; RV64IM-NEXT:    mulw a0, a0, a1
58; RV64IM-NEXT:    ret
59  %1 = mul i32 %a, %b
60  ret i32 %1
61}
62
63define i32 @aext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
64; RV64IM-LABEL: aext_mulw_zext_aext:
65; RV64IM:       # %bb.0:
66; RV64IM-NEXT:    mulw a0, a0, a1
67; RV64IM-NEXT:    ret
68  %1 = mul i32 %a, %b
69  ret i32 %1
70}
71
72define i32 @aext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
73; RV64IM-LABEL: aext_mulw_zext_sext:
74; RV64IM:       # %bb.0:
75; RV64IM-NEXT:    mulw a0, a0, a1
76; RV64IM-NEXT:    ret
77  %1 = mul i32 %a, %b
78  ret i32 %1
79}
80
81define i32 @aext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
82; RV64IM-LABEL: aext_mulw_zext_zext:
83; RV64IM:       # %bb.0:
84; RV64IM-NEXT:    mulw a0, a0, a1
85; RV64IM-NEXT:    ret
86  %1 = mul i32 %a, %b
87  ret i32 %1
88}
89
90define signext i32 @sext_mulw_aext_aext(i32 %a, i32 %b) nounwind {
91; RV64IM-LABEL: sext_mulw_aext_aext:
92; RV64IM:       # %bb.0:
93; RV64IM-NEXT:    mulw a0, a0, a1
94; RV64IM-NEXT:    ret
95  %1 = mul i32 %a, %b
96  ret i32 %1
97}
98
99define signext i32 @sext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {
100; RV64IM-LABEL: sext_mulw_aext_sext:
101; RV64IM:       # %bb.0:
102; RV64IM-NEXT:    mulw a0, a0, a1
103; RV64IM-NEXT:    ret
104  %1 = mul i32 %a, %b
105  ret i32 %1
106}
107
108define signext i32 @sext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
109; RV64IM-LABEL: sext_mulw_aext_zext:
110; RV64IM:       # %bb.0:
111; RV64IM-NEXT:    mulw a0, a0, a1
112; RV64IM-NEXT:    ret
113  %1 = mul i32 %a, %b
114  ret i32 %1
115}
116
117define signext i32 @sext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {
118; RV64IM-LABEL: sext_mulw_sext_aext:
119; RV64IM:       # %bb.0:
120; RV64IM-NEXT:    mulw a0, a0, a1
121; RV64IM-NEXT:    ret
122  %1 = mul i32 %a, %b
123  ret i32 %1
124}
125
126define signext i32 @sext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
127; RV64IM-LABEL: sext_mulw_sext_sext:
128; RV64IM:       # %bb.0:
129; RV64IM-NEXT:    mulw a0, a0, a1
130; RV64IM-NEXT:    ret
131  %1 = mul i32 %a, %b
132  ret i32 %1
133}
134
135define signext i32 @sext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
136; RV64IM-LABEL: sext_mulw_sext_zext:
137; RV64IM:       # %bb.0:
138; RV64IM-NEXT:    mulw a0, a0, a1
139; RV64IM-NEXT:    ret
140  %1 = mul i32 %a, %b
141  ret i32 %1
142}
143
144define signext i32 @sext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
145; RV64IM-LABEL: sext_mulw_zext_aext:
146; RV64IM:       # %bb.0:
147; RV64IM-NEXT:    mulw a0, a0, a1
148; RV64IM-NEXT:    ret
149  %1 = mul i32 %a, %b
150  ret i32 %1
151}
152
153define signext i32 @sext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
154; RV64IM-LABEL: sext_mulw_zext_sext:
155; RV64IM:       # %bb.0:
156; RV64IM-NEXT:    mulw a0, a0, a1
157; RV64IM-NEXT:    ret
158  %1 = mul i32 %a, %b
159  ret i32 %1
160}
161
162define signext i32 @sext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
163; RV64IM-LABEL: sext_mulw_zext_zext:
164; RV64IM:       # %bb.0:
165; RV64IM-NEXT:    mulw a0, a0, a1
166; RV64IM-NEXT:    ret
167  %1 = mul i32 %a, %b
168  ret i32 %1
169}
170
171define zeroext i32 @zext_mulw_aext_aext(i32 %a, i32 %b) nounwind {
172; RV64IM-LABEL: zext_mulw_aext_aext:
173; RV64IM:       # %bb.0:
174; RV64IM-NEXT:    mulw a0, a0, a1
175; RV64IM-NEXT:    slli a0, a0, 32
176; RV64IM-NEXT:    srli a0, a0, 32
177; RV64IM-NEXT:    ret
178  %1 = mul i32 %a, %b
179  ret i32 %1
180}
181
182define zeroext i32 @zext_mulw_aext_sext(i32 %a, i32 signext %b) nounwind {
183; RV64IM-LABEL: zext_mulw_aext_sext:
184; RV64IM:       # %bb.0:
185; RV64IM-NEXT:    mulw a0, a0, a1
186; RV64IM-NEXT:    slli a0, a0, 32
187; RV64IM-NEXT:    srli a0, a0, 32
188; RV64IM-NEXT:    ret
189  %1 = mul i32 %a, %b
190  ret i32 %1
191}
192
193define zeroext i32 @zext_mulw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
194; RV64IM-LABEL: zext_mulw_aext_zext:
195; RV64IM:       # %bb.0:
196; RV64IM-NEXT:    mulw a0, a0, a1
197; RV64IM-NEXT:    slli a0, a0, 32
198; RV64IM-NEXT:    srli a0, a0, 32
199; RV64IM-NEXT:    ret
200  %1 = mul i32 %a, %b
201  ret i32 %1
202}
203
204define zeroext i32 @zext_mulw_sext_aext(i32 signext %a, i32 %b) nounwind {
205; RV64IM-LABEL: zext_mulw_sext_aext:
206; RV64IM:       # %bb.0:
207; RV64IM-NEXT:    mulw a0, a0, a1
208; RV64IM-NEXT:    slli a0, a0, 32
209; RV64IM-NEXT:    srli a0, a0, 32
210; RV64IM-NEXT:    ret
211  %1 = mul i32 %a, %b
212  ret i32 %1
213}
214
215define zeroext i32 @zext_mulw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
216; RV64IM-LABEL: zext_mulw_sext_sext:
217; RV64IM:       # %bb.0:
218; RV64IM-NEXT:    mulw a0, a0, a1
219; RV64IM-NEXT:    slli a0, a0, 32
220; RV64IM-NEXT:    srli a0, a0, 32
221; RV64IM-NEXT:    ret
222  %1 = mul i32 %a, %b
223  ret i32 %1
224}
225
226define zeroext i32 @zext_mulw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
227; RV64IM-LABEL: zext_mulw_sext_zext:
228; RV64IM:       # %bb.0:
229; RV64IM-NEXT:    mulw a0, a0, a1
230; RV64IM-NEXT:    slli a0, a0, 32
231; RV64IM-NEXT:    srli a0, a0, 32
232; RV64IM-NEXT:    ret
233  %1 = mul i32 %a, %b
234  ret i32 %1
235}
236
237define zeroext i32 @zext_mulw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
238; RV64IM-LABEL: zext_mulw_zext_aext:
239; RV64IM:       # %bb.0:
240; RV64IM-NEXT:    mulw a0, a0, a1
241; RV64IM-NEXT:    slli a0, a0, 32
242; RV64IM-NEXT:    srli a0, a0, 32
243; RV64IM-NEXT:    ret
244  %1 = mul i32 %a, %b
245  ret i32 %1
246}
247
248define zeroext i32 @zext_mulw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
249; RV64IM-LABEL: zext_mulw_zext_sext:
250; RV64IM:       # %bb.0:
251; RV64IM-NEXT:    mulw a0, a0, a1
252; RV64IM-NEXT:    slli a0, a0, 32
253; RV64IM-NEXT:    srli a0, a0, 32
254; RV64IM-NEXT:    ret
255  %1 = mul i32 %a, %b
256  ret i32 %1
257}
258
259define zeroext i32 @zext_mulw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
260; RV64IM-LABEL: zext_mulw_zext_zext:
261; RV64IM:       # %bb.0:
262; RV64IM-NEXT:    mulw a0, a0, a1
263; RV64IM-NEXT:    slli a0, a0, 32
264; RV64IM-NEXT:    srli a0, a0, 32
265; RV64IM-NEXT:    ret
266  %1 = mul i32 %a, %b
267  ret i32 %1
268}
269
270define i32 @aext_divuw_aext_aext(i32 %a, i32 %b) nounwind {
271; RV64IM-LABEL: aext_divuw_aext_aext:
272; RV64IM:       # %bb.0:
273; RV64IM-NEXT:    divuw a0, a0, a1
274; RV64IM-NEXT:    ret
275  %1 = udiv i32 %a, %b
276  ret i32 %1
277}
278
279define i32 @aext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {
280; RV64IM-LABEL: aext_divuw_aext_sext:
281; RV64IM:       # %bb.0:
282; RV64IM-NEXT:    divuw a0, a0, a1
283; RV64IM-NEXT:    ret
284  %1 = udiv i32 %a, %b
285  ret i32 %1
286}
287
288define i32 @aext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
289; RV64IM-LABEL: aext_divuw_aext_zext:
290; RV64IM:       # %bb.0:
291; RV64IM-NEXT:    divuw a0, a0, a1
292; RV64IM-NEXT:    ret
293  %1 = udiv i32 %a, %b
294  ret i32 %1
295}
296
297define i32 @aext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {
298; RV64IM-LABEL: aext_divuw_sext_aext:
299; RV64IM:       # %bb.0:
300; RV64IM-NEXT:    divuw a0, a0, a1
301; RV64IM-NEXT:    ret
302  %1 = udiv i32 %a, %b
303  ret i32 %1
304}
305
306define i32 @aext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
307; RV64IM-LABEL: aext_divuw_sext_sext:
308; RV64IM:       # %bb.0:
309; RV64IM-NEXT:    divuw a0, a0, a1
310; RV64IM-NEXT:    ret
311  %1 = udiv i32 %a, %b
312  ret i32 %1
313}
314
315define i32 @aext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
316; RV64IM-LABEL: aext_divuw_sext_zext:
317; RV64IM:       # %bb.0:
318; RV64IM-NEXT:    divuw a0, a0, a1
319; RV64IM-NEXT:    ret
320  %1 = udiv i32 %a, %b
321  ret i32 %1
322}
323
324define i32 @aext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
325; RV64IM-LABEL: aext_divuw_zext_aext:
326; RV64IM:       # %bb.0:
327; RV64IM-NEXT:    divuw a0, a0, a1
328; RV64IM-NEXT:    ret
329  %1 = udiv i32 %a, %b
330  ret i32 %1
331}
332
333define i32 @aext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
334; RV64IM-LABEL: aext_divuw_zext_sext:
335; RV64IM:       # %bb.0:
336; RV64IM-NEXT:    divuw a0, a0, a1
337; RV64IM-NEXT:    ret
338  %1 = udiv i32 %a, %b
339  ret i32 %1
340}
341
342define i32 @aext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
343; RV64IM-LABEL: aext_divuw_zext_zext:
344; RV64IM:       # %bb.0:
345; RV64IM-NEXT:    divuw a0, a0, a1
346; RV64IM-NEXT:    ret
347  %1 = udiv i32 %a, %b
348  ret i32 %1
349}
350
351define signext i32 @sext_divuw_aext_aext(i32 %a, i32 %b) nounwind {
352; RV64IM-LABEL: sext_divuw_aext_aext:
353; RV64IM:       # %bb.0:
354; RV64IM-NEXT:    divuw a0, a0, a1
355; RV64IM-NEXT:    ret
356  %1 = udiv i32 %a, %b
357  ret i32 %1
358}
359
360define signext i32 @sext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {
361; RV64IM-LABEL: sext_divuw_aext_sext:
362; RV64IM:       # %bb.0:
363; RV64IM-NEXT:    divuw a0, a0, a1
364; RV64IM-NEXT:    ret
365  %1 = udiv i32 %a, %b
366  ret i32 %1
367}
368
369define signext i32 @sext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
370; RV64IM-LABEL: sext_divuw_aext_zext:
371; RV64IM:       # %bb.0:
372; RV64IM-NEXT:    divuw a0, a0, a1
373; RV64IM-NEXT:    ret
374  %1 = udiv i32 %a, %b
375  ret i32 %1
376}
377
378define signext i32 @sext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {
379; RV64IM-LABEL: sext_divuw_sext_aext:
380; RV64IM:       # %bb.0:
381; RV64IM-NEXT:    divuw a0, a0, a1
382; RV64IM-NEXT:    ret
383  %1 = udiv i32 %a, %b
384  ret i32 %1
385}
386
387define signext i32 @sext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
388; RV64IM-LABEL: sext_divuw_sext_sext:
389; RV64IM:       # %bb.0:
390; RV64IM-NEXT:    divuw a0, a0, a1
391; RV64IM-NEXT:    ret
392  %1 = udiv i32 %a, %b
393  ret i32 %1
394}
395
396define signext i32 @sext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
397; RV64IM-LABEL: sext_divuw_sext_zext:
398; RV64IM:       # %bb.0:
399; RV64IM-NEXT:    divuw a0, a0, a1
400; RV64IM-NEXT:    ret
401  %1 = udiv i32 %a, %b
402  ret i32 %1
403}
404
405define signext i32 @sext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
406; RV64IM-LABEL: sext_divuw_zext_aext:
407; RV64IM:       # %bb.0:
408; RV64IM-NEXT:    divuw a0, a0, a1
409; RV64IM-NEXT:    ret
410  %1 = udiv i32 %a, %b
411  ret i32 %1
412}
413
414define signext i32 @sext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
415; RV64IM-LABEL: sext_divuw_zext_sext:
416; RV64IM:       # %bb.0:
417; RV64IM-NEXT:    divuw a0, a0, a1
418; RV64IM-NEXT:    ret
419  %1 = udiv i32 %a, %b
420  ret i32 %1
421}
422
423define signext i32 @sext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
424; RV64IM-LABEL: sext_divuw_zext_zext:
425; RV64IM:       # %bb.0:
426; RV64IM-NEXT:    divuw a0, a0, a1
427; RV64IM-NEXT:    ret
428  %1 = udiv i32 %a, %b
429  ret i32 %1
430}
431
432define zeroext i32 @zext_divuw_aext_aext(i32 %a, i32 %b) nounwind {
433; RV64IM-LABEL: zext_divuw_aext_aext:
434; RV64IM:       # %bb.0:
435; RV64IM-NEXT:    divuw a0, a0, a1
436; RV64IM-NEXT:    slli a0, a0, 32
437; RV64IM-NEXT:    srli a0, a0, 32
438; RV64IM-NEXT:    ret
439  %1 = udiv i32 %a, %b
440  ret i32 %1
441}
442
443define zeroext i32 @zext_divuw_aext_sext(i32 %a, i32 signext %b) nounwind {
444; RV64IM-LABEL: zext_divuw_aext_sext:
445; RV64IM:       # %bb.0:
446; RV64IM-NEXT:    divuw a0, a0, a1
447; RV64IM-NEXT:    slli a0, a0, 32
448; RV64IM-NEXT:    srli a0, a0, 32
449; RV64IM-NEXT:    ret
450  %1 = udiv i32 %a, %b
451  ret i32 %1
452}
453
454define zeroext i32 @zext_divuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
455; RV64IM-LABEL: zext_divuw_aext_zext:
456; RV64IM:       # %bb.0:
457; RV64IM-NEXT:    divuw a0, a0, a1
458; RV64IM-NEXT:    slli a0, a0, 32
459; RV64IM-NEXT:    srli a0, a0, 32
460; RV64IM-NEXT:    ret
461  %1 = udiv i32 %a, %b
462  ret i32 %1
463}
464
465define zeroext i32 @zext_divuw_sext_aext(i32 signext %a, i32 %b) nounwind {
466; RV64IM-LABEL: zext_divuw_sext_aext:
467; RV64IM:       # %bb.0:
468; RV64IM-NEXT:    divuw a0, a0, a1
469; RV64IM-NEXT:    slli a0, a0, 32
470; RV64IM-NEXT:    srli a0, a0, 32
471; RV64IM-NEXT:    ret
472  %1 = udiv i32 %a, %b
473  ret i32 %1
474}
475
476define zeroext i32 @zext_divuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
477; RV64IM-LABEL: zext_divuw_sext_sext:
478; RV64IM:       # %bb.0:
479; RV64IM-NEXT:    divuw a0, a0, a1
480; RV64IM-NEXT:    slli a0, a0, 32
481; RV64IM-NEXT:    srli a0, a0, 32
482; RV64IM-NEXT:    ret
483  %1 = udiv i32 %a, %b
484  ret i32 %1
485}
486
487define zeroext i32 @zext_divuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
488; RV64IM-LABEL: zext_divuw_sext_zext:
489; RV64IM:       # %bb.0:
490; RV64IM-NEXT:    divuw a0, a0, a1
491; RV64IM-NEXT:    slli a0, a0, 32
492; RV64IM-NEXT:    srli a0, a0, 32
493; RV64IM-NEXT:    ret
494  %1 = udiv i32 %a, %b
495  ret i32 %1
496}
497
498define zeroext i32 @zext_divuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
499; RV64IM-LABEL: zext_divuw_zext_aext:
500; RV64IM:       # %bb.0:
501; RV64IM-NEXT:    divuw a0, a0, a1
502; RV64IM-NEXT:    slli a0, a0, 32
503; RV64IM-NEXT:    srli a0, a0, 32
504; RV64IM-NEXT:    ret
505  %1 = udiv i32 %a, %b
506  ret i32 %1
507}
508
509define zeroext i32 @zext_divuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
510; RV64IM-LABEL: zext_divuw_zext_sext:
511; RV64IM:       # %bb.0:
512; RV64IM-NEXT:    divuw a0, a0, a1
513; RV64IM-NEXT:    slli a0, a0, 32
514; RV64IM-NEXT:    srli a0, a0, 32
515; RV64IM-NEXT:    ret
516  %1 = udiv i32 %a, %b
517  ret i32 %1
518}
519
520define zeroext i32 @zext_divuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
521; RV64IM-LABEL: zext_divuw_zext_zext:
522; RV64IM:       # %bb.0:
523; RV64IM-NEXT:    divu a0, a0, a1
524; RV64IM-NEXT:    ret
525  %1 = udiv i32 %a, %b
526  ret i32 %1
527}
528
529define zeroext i8 @zext_divuw_zext_zext_i8(i8 zeroext %a, i8 zeroext %b) nounwind {
530; RV64IM-LABEL: zext_divuw_zext_zext_i8:
531; RV64IM:       # %bb.0:
532; RV64IM-NEXT:    divuw a0, a0, a1
533; RV64IM-NEXT:    ret
534  %1 = udiv i8 %a, %b
535  ret i8 %1
536}
537
538define zeroext i16 @zext_divuw_zext_zext_i16(i16 zeroext %a, i16 zeroext %b) nounwind {
539; RV64IM-LABEL: zext_divuw_zext_zext_i16:
540; RV64IM:       # %bb.0:
541; RV64IM-NEXT:    divuw a0, a0, a1
542; RV64IM-NEXT:    ret
543  %1 = udiv i16 %a, %b
544  ret i16 %1
545}
546
547define i32 @aext_divw_aext_aext(i32 %a, i32 %b) nounwind {
548; RV64IM-LABEL: aext_divw_aext_aext:
549; RV64IM:       # %bb.0:
550; RV64IM-NEXT:    divw a0, a0, a1
551; RV64IM-NEXT:    ret
552  %1 = sdiv i32 %a, %b
553  ret i32 %1
554}
555
556define i32 @aext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {
557; RV64IM-LABEL: aext_divw_aext_sext:
558; RV64IM:       # %bb.0:
559; RV64IM-NEXT:    divw a0, a0, a1
560; RV64IM-NEXT:    ret
561  %1 = sdiv i32 %a, %b
562  ret i32 %1
563}
564
565define i32 @aext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
566; RV64IM-LABEL: aext_divw_aext_zext:
567; RV64IM:       # %bb.0:
568; RV64IM-NEXT:    divw a0, a0, a1
569; RV64IM-NEXT:    ret
570  %1 = sdiv i32 %a, %b
571  ret i32 %1
572}
573
574define i32 @aext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {
575; RV64IM-LABEL: aext_divw_sext_aext:
576; RV64IM:       # %bb.0:
577; RV64IM-NEXT:    divw a0, a0, a1
578; RV64IM-NEXT:    ret
579  %1 = sdiv i32 %a, %b
580  ret i32 %1
581}
582
583define i32 @aext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
584; RV64IM-LABEL: aext_divw_sext_sext:
585; RV64IM:       # %bb.0:
586; RV64IM-NEXT:    divw a0, a0, a1
587; RV64IM-NEXT:    ret
588  %1 = sdiv i32 %a, %b
589  ret i32 %1
590}
591
592define i32 @aext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
593; RV64IM-LABEL: aext_divw_sext_zext:
594; RV64IM:       # %bb.0:
595; RV64IM-NEXT:    divw a0, a0, a1
596; RV64IM-NEXT:    ret
597  %1 = sdiv i32 %a, %b
598  ret i32 %1
599}
600
601define i32 @aext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
602; RV64IM-LABEL: aext_divw_zext_aext:
603; RV64IM:       # %bb.0:
604; RV64IM-NEXT:    divw a0, a0, a1
605; RV64IM-NEXT:    ret
606  %1 = sdiv i32 %a, %b
607  ret i32 %1
608}
609
610define i32 @aext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
611; RV64IM-LABEL: aext_divw_zext_sext:
612; RV64IM:       # %bb.0:
613; RV64IM-NEXT:    divw a0, a0, a1
614; RV64IM-NEXT:    ret
615  %1 = sdiv i32 %a, %b
616  ret i32 %1
617}
618
619define i32 @aext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
620; RV64IM-LABEL: aext_divw_zext_zext:
621; RV64IM:       # %bb.0:
622; RV64IM-NEXT:    divw a0, a0, a1
623; RV64IM-NEXT:    ret
624  %1 = sdiv i32 %a, %b
625  ret i32 %1
626}
627
628define signext i32 @sext_divw_aext_aext(i32 %a, i32 %b) nounwind {
629; RV64IM-LABEL: sext_divw_aext_aext:
630; RV64IM:       # %bb.0:
631; RV64IM-NEXT:    divw a0, a0, a1
632; RV64IM-NEXT:    ret
633  %1 = sdiv i32 %a, %b
634  ret i32 %1
635}
636
637define signext i32 @sext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {
638; RV64IM-LABEL: sext_divw_aext_sext:
639; RV64IM:       # %bb.0:
640; RV64IM-NEXT:    divw a0, a0, a1
641; RV64IM-NEXT:    ret
642  %1 = sdiv i32 %a, %b
643  ret i32 %1
644}
645
646define signext i32 @sext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
647; RV64IM-LABEL: sext_divw_aext_zext:
648; RV64IM:       # %bb.0:
649; RV64IM-NEXT:    divw a0, a0, a1
650; RV64IM-NEXT:    ret
651  %1 = sdiv i32 %a, %b
652  ret i32 %1
653}
654
655define signext i32 @sext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {
656; RV64IM-LABEL: sext_divw_sext_aext:
657; RV64IM:       # %bb.0:
658; RV64IM-NEXT:    divw a0, a0, a1
659; RV64IM-NEXT:    ret
660  %1 = sdiv i32 %a, %b
661  ret i32 %1
662}
663
664define signext i32 @sext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
665; RV64IM-LABEL: sext_divw_sext_sext:
666; RV64IM:       # %bb.0:
667; RV64IM-NEXT:    divw a0, a0, a1
668; RV64IM-NEXT:    ret
669  %1 = sdiv i32 %a, %b
670  ret i32 %1
671}
672
673define signext i32 @sext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
674; RV64IM-LABEL: sext_divw_sext_zext:
675; RV64IM:       # %bb.0:
676; RV64IM-NEXT:    divw a0, a0, a1
677; RV64IM-NEXT:    ret
678  %1 = sdiv i32 %a, %b
679  ret i32 %1
680}
681
682define signext i32 @sext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
683; RV64IM-LABEL: sext_divw_zext_aext:
684; RV64IM:       # %bb.0:
685; RV64IM-NEXT:    divw a0, a0, a1
686; RV64IM-NEXT:    ret
687  %1 = sdiv i32 %a, %b
688  ret i32 %1
689}
690
691define signext i32 @sext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
692; RV64IM-LABEL: sext_divw_zext_sext:
693; RV64IM:       # %bb.0:
694; RV64IM-NEXT:    divw a0, a0, a1
695; RV64IM-NEXT:    ret
696  %1 = sdiv i32 %a, %b
697  ret i32 %1
698}
699
700define signext i32 @sext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
701; RV64IM-LABEL: sext_divw_zext_zext:
702; RV64IM:       # %bb.0:
703; RV64IM-NEXT:    divw a0, a0, a1
704; RV64IM-NEXT:    ret
705  %1 = sdiv i32 %a, %b
706  ret i32 %1
707}
708
709define zeroext i32 @zext_divw_aext_aext(i32 %a, i32 %b) nounwind {
710; RV64IM-LABEL: zext_divw_aext_aext:
711; RV64IM:       # %bb.0:
712; RV64IM-NEXT:    divw a0, a0, a1
713; RV64IM-NEXT:    slli a0, a0, 32
714; RV64IM-NEXT:    srli a0, a0, 32
715; RV64IM-NEXT:    ret
716  %1 = sdiv i32 %a, %b
717  ret i32 %1
718}
719
720define zeroext i32 @zext_divw_aext_sext(i32 %a, i32 signext %b) nounwind {
721; RV64IM-LABEL: zext_divw_aext_sext:
722; RV64IM:       # %bb.0:
723; RV64IM-NEXT:    divw a0, a0, a1
724; RV64IM-NEXT:    slli a0, a0, 32
725; RV64IM-NEXT:    srli a0, a0, 32
726; RV64IM-NEXT:    ret
727  %1 = sdiv i32 %a, %b
728  ret i32 %1
729}
730
731define zeroext i32 @zext_divw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
732; RV64IM-LABEL: zext_divw_aext_zext:
733; RV64IM:       # %bb.0:
734; RV64IM-NEXT:    divw a0, a0, a1
735; RV64IM-NEXT:    slli a0, a0, 32
736; RV64IM-NEXT:    srli a0, a0, 32
737; RV64IM-NEXT:    ret
738  %1 = sdiv i32 %a, %b
739  ret i32 %1
740}
741
742define zeroext i32 @zext_divw_sext_aext(i32 signext %a, i32 %b) nounwind {
743; RV64IM-LABEL: zext_divw_sext_aext:
744; RV64IM:       # %bb.0:
745; RV64IM-NEXT:    divw a0, a0, a1
746; RV64IM-NEXT:    slli a0, a0, 32
747; RV64IM-NEXT:    srli a0, a0, 32
748; RV64IM-NEXT:    ret
749  %1 = sdiv i32 %a, %b
750  ret i32 %1
751}
752
753define zeroext i32 @zext_divw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
754; RV64IM-LABEL: zext_divw_sext_sext:
755; RV64IM:       # %bb.0:
756; RV64IM-NEXT:    divw a0, a0, a1
757; RV64IM-NEXT:    slli a0, a0, 32
758; RV64IM-NEXT:    srli a0, a0, 32
759; RV64IM-NEXT:    ret
760  %1 = sdiv i32 %a, %b
761  ret i32 %1
762}
763
764define zeroext i32 @zext_divw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
765; RV64IM-LABEL: zext_divw_sext_zext:
766; RV64IM:       # %bb.0:
767; RV64IM-NEXT:    divw a0, a0, a1
768; RV64IM-NEXT:    slli a0, a0, 32
769; RV64IM-NEXT:    srli a0, a0, 32
770; RV64IM-NEXT:    ret
771  %1 = sdiv i32 %a, %b
772  ret i32 %1
773}
774
775define zeroext i32 @zext_divw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
776; RV64IM-LABEL: zext_divw_zext_aext:
777; RV64IM:       # %bb.0:
778; RV64IM-NEXT:    divw a0, a0, a1
779; RV64IM-NEXT:    slli a0, a0, 32
780; RV64IM-NEXT:    srli a0, a0, 32
781; RV64IM-NEXT:    ret
782  %1 = sdiv i32 %a, %b
783  ret i32 %1
784}
785
786define zeroext i32 @zext_divw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
787; RV64IM-LABEL: zext_divw_zext_sext:
788; RV64IM:       # %bb.0:
789; RV64IM-NEXT:    divw a0, a0, a1
790; RV64IM-NEXT:    slli a0, a0, 32
791; RV64IM-NEXT:    srli a0, a0, 32
792; RV64IM-NEXT:    ret
793  %1 = sdiv i32 %a, %b
794  ret i32 %1
795}
796
797define zeroext i32 @zext_divw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
798; RV64IM-LABEL: zext_divw_zext_zext:
799; RV64IM:       # %bb.0:
800; RV64IM-NEXT:    divw a0, a0, a1
801; RV64IM-NEXT:    slli a0, a0, 32
802; RV64IM-NEXT:    srli a0, a0, 32
803; RV64IM-NEXT:    ret
804  %1 = sdiv i32 %a, %b
805  ret i32 %1
806}
807
808define signext i8 @sext_divw_sext_sext_i8(i8 signext %a, i8 signext %b) nounwind {
809; RV64IM-LABEL: sext_divw_sext_sext_i8:
810; RV64IM:       # %bb.0:
811; RV64IM-NEXT:    divw a0, a0, a1
812; RV64IM-NEXT:    slli a0, a0, 56
813; RV64IM-NEXT:    srai a0, a0, 56
814; RV64IM-NEXT:    ret
815  %1 = sdiv i8 %a, %b
816  ret i8 %1
817}
818
819define signext i16 @sext_divw_sext_sext_i16(i16 signext %a, i16 signext %b) nounwind {
820; RV64IM-LABEL: sext_divw_sext_sext_i16:
821; RV64IM:       # %bb.0:
822; RV64IM-NEXT:    divw a0, a0, a1
823; RV64IM-NEXT:    slli a0, a0, 48
824; RV64IM-NEXT:    srai a0, a0, 48
825; RV64IM-NEXT:    ret
826  %1 = sdiv i16 %a, %b
827  ret i16 %1
828}
829
830define i32 @aext_remw_aext_aext(i32 %a, i32 %b) nounwind {
831; RV64IM-LABEL: aext_remw_aext_aext:
832; RV64IM:       # %bb.0:
833; RV64IM-NEXT:    remw a0, a0, a1
834; RV64IM-NEXT:    ret
835  %1 = srem i32 %a, %b
836  ret i32 %1
837}
838
839define i32 @aext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {
840; RV64IM-LABEL: aext_remw_aext_sext:
841; RV64IM:       # %bb.0:
842; RV64IM-NEXT:    remw a0, a0, a1
843; RV64IM-NEXT:    ret
844  %1 = srem i32 %a, %b
845  ret i32 %1
846}
847
848define i32 @aext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
849; RV64IM-LABEL: aext_remw_aext_zext:
850; RV64IM:       # %bb.0:
851; RV64IM-NEXT:    remw a0, a0, a1
852; RV64IM-NEXT:    ret
853  %1 = srem i32 %a, %b
854  ret i32 %1
855}
856
857define i32 @aext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {
858; RV64IM-LABEL: aext_remw_sext_aext:
859; RV64IM:       # %bb.0:
860; RV64IM-NEXT:    remw a0, a0, a1
861; RV64IM-NEXT:    ret
862  %1 = srem i32 %a, %b
863  ret i32 %1
864}
865
866define i32 @aext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
867; RV64IM-LABEL: aext_remw_sext_sext:
868; RV64IM:       # %bb.0:
869; RV64IM-NEXT:    remw a0, a0, a1
870; RV64IM-NEXT:    ret
871  %1 = srem i32 %a, %b
872  ret i32 %1
873}
874
875define i32 @aext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
876; RV64IM-LABEL: aext_remw_sext_zext:
877; RV64IM:       # %bb.0:
878; RV64IM-NEXT:    remw a0, a0, a1
879; RV64IM-NEXT:    ret
880  %1 = srem i32 %a, %b
881  ret i32 %1
882}
883
884define i32 @aext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
885; RV64IM-LABEL: aext_remw_zext_aext:
886; RV64IM:       # %bb.0:
887; RV64IM-NEXT:    remw a0, a0, a1
888; RV64IM-NEXT:    ret
889  %1 = srem i32 %a, %b
890  ret i32 %1
891}
892
893define i32 @aext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
894; RV64IM-LABEL: aext_remw_zext_sext:
895; RV64IM:       # %bb.0:
896; RV64IM-NEXT:    remw a0, a0, a1
897; RV64IM-NEXT:    ret
898  %1 = srem i32 %a, %b
899  ret i32 %1
900}
901
902define i32 @aext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
903; RV64IM-LABEL: aext_remw_zext_zext:
904; RV64IM:       # %bb.0:
905; RV64IM-NEXT:    remw a0, a0, a1
906; RV64IM-NEXT:    ret
907  %1 = srem i32 %a, %b
908  ret i32 %1
909}
910
911define signext i32 @sext_remw_aext_aext(i32 %a, i32 %b) nounwind {
912; RV64IM-LABEL: sext_remw_aext_aext:
913; RV64IM:       # %bb.0:
914; RV64IM-NEXT:    remw a0, a0, a1
915; RV64IM-NEXT:    ret
916  %1 = srem i32 %a, %b
917  ret i32 %1
918}
919
920define signext i32 @sext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {
921; RV64IM-LABEL: sext_remw_aext_sext:
922; RV64IM:       # %bb.0:
923; RV64IM-NEXT:    remw a0, a0, a1
924; RV64IM-NEXT:    ret
925  %1 = srem i32 %a, %b
926  ret i32 %1
927}
928
929define signext i32 @sext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
930; RV64IM-LABEL: sext_remw_aext_zext:
931; RV64IM:       # %bb.0:
932; RV64IM-NEXT:    remw a0, a0, a1
933; RV64IM-NEXT:    ret
934  %1 = srem i32 %a, %b
935  ret i32 %1
936}
937
938define signext i32 @sext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {
939; RV64IM-LABEL: sext_remw_sext_aext:
940; RV64IM:       # %bb.0:
941; RV64IM-NEXT:    remw a0, a0, a1
942; RV64IM-NEXT:    ret
943  %1 = srem i32 %a, %b
944  ret i32 %1
945}
946
947define signext i32 @sext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
948; RV64IM-LABEL: sext_remw_sext_sext:
949; RV64IM:       # %bb.0:
950; RV64IM-NEXT:    remw a0, a0, a1
951; RV64IM-NEXT:    ret
952  %1 = srem i32 %a, %b
953  ret i32 %1
954}
955
956define signext i32 @sext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
957; RV64IM-LABEL: sext_remw_sext_zext:
958; RV64IM:       # %bb.0:
959; RV64IM-NEXT:    remw a0, a0, a1
960; RV64IM-NEXT:    ret
961  %1 = srem i32 %a, %b
962  ret i32 %1
963}
964
965define signext i32 @sext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
966; RV64IM-LABEL: sext_remw_zext_aext:
967; RV64IM:       # %bb.0:
968; RV64IM-NEXT:    remw a0, a0, a1
969; RV64IM-NEXT:    ret
970  %1 = srem i32 %a, %b
971  ret i32 %1
972}
973
974define signext i32 @sext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
975; RV64IM-LABEL: sext_remw_zext_sext:
976; RV64IM:       # %bb.0:
977; RV64IM-NEXT:    remw a0, a0, a1
978; RV64IM-NEXT:    ret
979  %1 = srem i32 %a, %b
980  ret i32 %1
981}
982
983define signext i32 @sext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
984; RV64IM-LABEL: sext_remw_zext_zext:
985; RV64IM:       # %bb.0:
986; RV64IM-NEXT:    remw a0, a0, a1
987; RV64IM-NEXT:    ret
988  %1 = srem i32 %a, %b
989  ret i32 %1
990}
991
992define zeroext i32 @zext_remw_aext_aext(i32 %a, i32 %b) nounwind {
993; RV64IM-LABEL: zext_remw_aext_aext:
994; RV64IM:       # %bb.0:
995; RV64IM-NEXT:    remw a0, a0, a1
996; RV64IM-NEXT:    slli a0, a0, 32
997; RV64IM-NEXT:    srli a0, a0, 32
998; RV64IM-NEXT:    ret
999  %1 = srem i32 %a, %b
1000  ret i32 %1
1001}
1002
1003define zeroext i32 @zext_remw_aext_sext(i32 %a, i32 signext %b) nounwind {
1004; RV64IM-LABEL: zext_remw_aext_sext:
1005; RV64IM:       # %bb.0:
1006; RV64IM-NEXT:    remw a0, a0, a1
1007; RV64IM-NEXT:    slli a0, a0, 32
1008; RV64IM-NEXT:    srli a0, a0, 32
1009; RV64IM-NEXT:    ret
1010  %1 = srem i32 %a, %b
1011  ret i32 %1
1012}
1013
1014define zeroext i32 @zext_remw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1015; RV64IM-LABEL: zext_remw_aext_zext:
1016; RV64IM:       # %bb.0:
1017; RV64IM-NEXT:    remw a0, a0, a1
1018; RV64IM-NEXT:    slli a0, a0, 32
1019; RV64IM-NEXT:    srli a0, a0, 32
1020; RV64IM-NEXT:    ret
1021  %1 = srem i32 %a, %b
1022  ret i32 %1
1023}
1024
1025define zeroext i32 @zext_remw_sext_aext(i32 signext %a, i32 %b) nounwind {
1026; RV64IM-LABEL: zext_remw_sext_aext:
1027; RV64IM:       # %bb.0:
1028; RV64IM-NEXT:    remw a0, a0, a1
1029; RV64IM-NEXT:    slli a0, a0, 32
1030; RV64IM-NEXT:    srli a0, a0, 32
1031; RV64IM-NEXT:    ret
1032  %1 = srem i32 %a, %b
1033  ret i32 %1
1034}
1035
1036define zeroext i32 @zext_remw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1037; RV64IM-LABEL: zext_remw_sext_sext:
1038; RV64IM:       # %bb.0:
1039; RV64IM-NEXT:    remw a0, a0, a1
1040; RV64IM-NEXT:    slli a0, a0, 32
1041; RV64IM-NEXT:    srli a0, a0, 32
1042; RV64IM-NEXT:    ret
1043  %1 = srem i32 %a, %b
1044  ret i32 %1
1045}
1046
1047define zeroext i32 @zext_remw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1048; RV64IM-LABEL: zext_remw_sext_zext:
1049; RV64IM:       # %bb.0:
1050; RV64IM-NEXT:    remw a0, a0, a1
1051; RV64IM-NEXT:    slli a0, a0, 32
1052; RV64IM-NEXT:    srli a0, a0, 32
1053; RV64IM-NEXT:    ret
1054  %1 = srem i32 %a, %b
1055  ret i32 %1
1056}
1057
1058define zeroext i32 @zext_remw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1059; RV64IM-LABEL: zext_remw_zext_aext:
1060; RV64IM:       # %bb.0:
1061; RV64IM-NEXT:    remw a0, a0, a1
1062; RV64IM-NEXT:    slli a0, a0, 32
1063; RV64IM-NEXT:    srli a0, a0, 32
1064; RV64IM-NEXT:    ret
1065  %1 = srem i32 %a, %b
1066  ret i32 %1
1067}
1068
1069define zeroext i32 @zext_remw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1070; RV64IM-LABEL: zext_remw_zext_sext:
1071; RV64IM:       # %bb.0:
1072; RV64IM-NEXT:    remw a0, a0, a1
1073; RV64IM-NEXT:    slli a0, a0, 32
1074; RV64IM-NEXT:    srli a0, a0, 32
1075; RV64IM-NEXT:    ret
1076  %1 = srem i32 %a, %b
1077  ret i32 %1
1078}
1079
1080define zeroext i32 @zext_remw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1081; RV64IM-LABEL: zext_remw_zext_zext:
1082; RV64IM:       # %bb.0:
1083; RV64IM-NEXT:    remw a0, a0, a1
1084; RV64IM-NEXT:    slli a0, a0, 32
1085; RV64IM-NEXT:    srli a0, a0, 32
1086; RV64IM-NEXT:    ret
1087  %1 = srem i32 %a, %b
1088  ret i32 %1
1089}
1090
1091define signext i8 @sext_remw_sext_sext_i8(i8 signext %a, i8 signext %b) nounwind {
1092; RV64IM-LABEL: sext_remw_sext_sext_i8:
1093; RV64IM:       # %bb.0:
1094; RV64IM-NEXT:    remw a0, a0, a1
1095; RV64IM-NEXT:    ret
1096  %1 = srem i8 %a, %b
1097  ret i8 %1
1098}
1099
1100define signext i16 @sext_remw_sext_sext_i16(i16 signext %a, i16 signext %b) nounwind {
1101; RV64IM-LABEL: sext_remw_sext_sext_i16:
1102; RV64IM:       # %bb.0:
1103; RV64IM-NEXT:    remw a0, a0, a1
1104; RV64IM-NEXT:    ret
1105  %1 = srem i16 %a, %b
1106  ret i16 %1
1107}
1108
1109define signext i32 @sext_i32_remw_zext_sext_i16(i16 zeroext %0, i16 signext %1) nounwind {
1110; RV64IM-LABEL: sext_i32_remw_zext_sext_i16:
1111; RV64IM:       # %bb.0:
1112; RV64IM-NEXT:    remw a0, a0, a1
1113; RV64IM-NEXT:    ret
1114  %3 = sext i16 %1 to i32
1115  %4 = zext i16 %0 to i32
1116  %5 = srem i32 %4, %3
1117  ret i32 %5
1118}
1119
1120define signext i32 @sext_i32_remw_sext_zext_i16(i16 signext %a, i16 zeroext %b) nounwind {
1121; RV64IM-LABEL: sext_i32_remw_sext_zext_i16:
1122; RV64IM:       # %bb.0:
1123; RV64IM-NEXT:    remw a0, a0, a1
1124; RV64IM-NEXT:    ret
1125  %1 = sext i16 %a to i32
1126  %2 = zext i16 %b to i32
1127  %3 = srem i32 %1, %2
1128  ret i32 %3
1129}
1130
1131define i32 @aext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
1132; RV64IM-LABEL: aext_remuw_aext_aext:
1133; RV64IM:       # %bb.0:
1134; RV64IM-NEXT:    remuw a0, a0, a1
1135; RV64IM-NEXT:    ret
1136  %1 = urem i32 %a, %b
1137  ret i32 %1
1138}
1139
1140define i32 @aext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {
1141; RV64IM-LABEL: aext_remuw_aext_sext:
1142; RV64IM:       # %bb.0:
1143; RV64IM-NEXT:    remuw a0, a0, a1
1144; RV64IM-NEXT:    ret
1145  %1 = urem i32 %a, %b
1146  ret i32 %1
1147}
1148
1149define i32 @aext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1150; RV64IM-LABEL: aext_remuw_aext_zext:
1151; RV64IM:       # %bb.0:
1152; RV64IM-NEXT:    remuw a0, a0, a1
1153; RV64IM-NEXT:    ret
1154  %1 = urem i32 %a, %b
1155  ret i32 %1
1156}
1157
1158define i32 @aext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {
1159; RV64IM-LABEL: aext_remuw_sext_aext:
1160; RV64IM:       # %bb.0:
1161; RV64IM-NEXT:    remuw a0, a0, a1
1162; RV64IM-NEXT:    ret
1163  %1 = urem i32 %a, %b
1164  ret i32 %1
1165}
1166
1167define i32 @aext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1168; RV64IM-LABEL: aext_remuw_sext_sext:
1169; RV64IM:       # %bb.0:
1170; RV64IM-NEXT:    remuw a0, a0, a1
1171; RV64IM-NEXT:    ret
1172  %1 = urem i32 %a, %b
1173  ret i32 %1
1174}
1175
1176define i32 @aext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1177; RV64IM-LABEL: aext_remuw_sext_zext:
1178; RV64IM:       # %bb.0:
1179; RV64IM-NEXT:    remuw a0, a0, a1
1180; RV64IM-NEXT:    ret
1181  %1 = urem i32 %a, %b
1182  ret i32 %1
1183}
1184
1185define i32 @aext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1186; RV64IM-LABEL: aext_remuw_zext_aext:
1187; RV64IM:       # %bb.0:
1188; RV64IM-NEXT:    remuw a0, a0, a1
1189; RV64IM-NEXT:    ret
1190  %1 = urem i32 %a, %b
1191  ret i32 %1
1192}
1193
1194define i32 @aext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1195; RV64IM-LABEL: aext_remuw_zext_sext:
1196; RV64IM:       # %bb.0:
1197; RV64IM-NEXT:    remuw a0, a0, a1
1198; RV64IM-NEXT:    ret
1199  %1 = urem i32 %a, %b
1200  ret i32 %1
1201}
1202
1203define i32 @aext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1204; RV64IM-LABEL: aext_remuw_zext_zext:
1205; RV64IM:       # %bb.0:
1206; RV64IM-NEXT:    remuw a0, a0, a1
1207; RV64IM-NEXT:    ret
1208  %1 = urem i32 %a, %b
1209  ret i32 %1
1210}
1211
1212define signext i32 @sext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
1213; RV64IM-LABEL: sext_remuw_aext_aext:
1214; RV64IM:       # %bb.0:
1215; RV64IM-NEXT:    remuw a0, a0, a1
1216; RV64IM-NEXT:    ret
1217  %1 = urem i32 %a, %b
1218  ret i32 %1
1219}
1220
1221define signext i32 @sext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {
1222; RV64IM-LABEL: sext_remuw_aext_sext:
1223; RV64IM:       # %bb.0:
1224; RV64IM-NEXT:    remuw a0, a0, a1
1225; RV64IM-NEXT:    ret
1226  %1 = urem i32 %a, %b
1227  ret i32 %1
1228}
1229
1230define signext i32 @sext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1231; RV64IM-LABEL: sext_remuw_aext_zext:
1232; RV64IM:       # %bb.0:
1233; RV64IM-NEXT:    remuw a0, a0, a1
1234; RV64IM-NEXT:    ret
1235  %1 = urem i32 %a, %b
1236  ret i32 %1
1237}
1238
1239define signext i32 @sext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {
1240; RV64IM-LABEL: sext_remuw_sext_aext:
1241; RV64IM:       # %bb.0:
1242; RV64IM-NEXT:    remuw a0, a0, a1
1243; RV64IM-NEXT:    ret
1244  %1 = urem i32 %a, %b
1245  ret i32 %1
1246}
1247
1248define signext i32 @sext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1249; RV64IM-LABEL: sext_remuw_sext_sext:
1250; RV64IM:       # %bb.0:
1251; RV64IM-NEXT:    remuw a0, a0, a1
1252; RV64IM-NEXT:    ret
1253  %1 = urem i32 %a, %b
1254  ret i32 %1
1255}
1256
1257define signext i32 @sext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1258; RV64IM-LABEL: sext_remuw_sext_zext:
1259; RV64IM:       # %bb.0:
1260; RV64IM-NEXT:    remuw a0, a0, a1
1261; RV64IM-NEXT:    ret
1262  %1 = urem i32 %a, %b
1263  ret i32 %1
1264}
1265
1266define signext i32 @sext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1267; RV64IM-LABEL: sext_remuw_zext_aext:
1268; RV64IM:       # %bb.0:
1269; RV64IM-NEXT:    remuw a0, a0, a1
1270; RV64IM-NEXT:    ret
1271  %1 = urem i32 %a, %b
1272  ret i32 %1
1273}
1274
1275define signext i32 @sext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1276; RV64IM-LABEL: sext_remuw_zext_sext:
1277; RV64IM:       # %bb.0:
1278; RV64IM-NEXT:    remuw a0, a0, a1
1279; RV64IM-NEXT:    ret
1280  %1 = urem i32 %a, %b
1281  ret i32 %1
1282}
1283
1284define signext i32 @sext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1285; RV64IM-LABEL: sext_remuw_zext_zext:
1286; RV64IM:       # %bb.0:
1287; RV64IM-NEXT:    remuw a0, a0, a1
1288; RV64IM-NEXT:    ret
1289  %1 = urem i32 %a, %b
1290  ret i32 %1
1291}
1292
1293define zeroext i32 @zext_remuw_aext_aext(i32 %a, i32 %b) nounwind {
1294; RV64IM-LABEL: zext_remuw_aext_aext:
1295; RV64IM:       # %bb.0:
1296; RV64IM-NEXT:    remuw a0, a0, a1
1297; RV64IM-NEXT:    slli a0, a0, 32
1298; RV64IM-NEXT:    srli a0, a0, 32
1299; RV64IM-NEXT:    ret
1300  %1 = urem i32 %a, %b
1301  ret i32 %1
1302}
1303
1304define zeroext i32 @zext_remuw_aext_sext(i32 %a, i32 signext %b) nounwind {
1305; RV64IM-LABEL: zext_remuw_aext_sext:
1306; RV64IM:       # %bb.0:
1307; RV64IM-NEXT:    remuw a0, a0, a1
1308; RV64IM-NEXT:    slli a0, a0, 32
1309; RV64IM-NEXT:    srli a0, a0, 32
1310; RV64IM-NEXT:    ret
1311  %1 = urem i32 %a, %b
1312  ret i32 %1
1313}
1314
1315define zeroext i32 @zext_remuw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1316; RV64IM-LABEL: zext_remuw_aext_zext:
1317; RV64IM:       # %bb.0:
1318; RV64IM-NEXT:    remuw a0, a0, a1
1319; RV64IM-NEXT:    slli a0, a0, 32
1320; RV64IM-NEXT:    srli a0, a0, 32
1321; RV64IM-NEXT:    ret
1322  %1 = urem i32 %a, %b
1323  ret i32 %1
1324}
1325
1326define zeroext i32 @zext_remuw_sext_aext(i32 signext %a, i32 %b) nounwind {
1327; RV64IM-LABEL: zext_remuw_sext_aext:
1328; RV64IM:       # %bb.0:
1329; RV64IM-NEXT:    remuw a0, a0, a1
1330; RV64IM-NEXT:    slli a0, a0, 32
1331; RV64IM-NEXT:    srli a0, a0, 32
1332; RV64IM-NEXT:    ret
1333  %1 = urem i32 %a, %b
1334  ret i32 %1
1335}
1336
1337define zeroext i32 @zext_remuw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1338; RV64IM-LABEL: zext_remuw_sext_sext:
1339; RV64IM:       # %bb.0:
1340; RV64IM-NEXT:    remuw a0, a0, a1
1341; RV64IM-NEXT:    slli a0, a0, 32
1342; RV64IM-NEXT:    srli a0, a0, 32
1343; RV64IM-NEXT:    ret
1344  %1 = urem i32 %a, %b
1345  ret i32 %1
1346}
1347
1348define zeroext i32 @zext_remuw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1349; RV64IM-LABEL: zext_remuw_sext_zext:
1350; RV64IM:       # %bb.0:
1351; RV64IM-NEXT:    remuw a0, a0, a1
1352; RV64IM-NEXT:    slli a0, a0, 32
1353; RV64IM-NEXT:    srli a0, a0, 32
1354; RV64IM-NEXT:    ret
1355  %1 = urem i32 %a, %b
1356  ret i32 %1
1357}
1358
1359define zeroext i32 @zext_remuw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1360; RV64IM-LABEL: zext_remuw_zext_aext:
1361; RV64IM:       # %bb.0:
1362; RV64IM-NEXT:    remuw a0, a0, a1
1363; RV64IM-NEXT:    slli a0, a0, 32
1364; RV64IM-NEXT:    srli a0, a0, 32
1365; RV64IM-NEXT:    ret
1366  %1 = urem i32 %a, %b
1367  ret i32 %1
1368}
1369
1370define zeroext i32 @zext_remuw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1371; RV64IM-LABEL: zext_remuw_zext_sext:
1372; RV64IM:       # %bb.0:
1373; RV64IM-NEXT:    remuw a0, a0, a1
1374; RV64IM-NEXT:    slli a0, a0, 32
1375; RV64IM-NEXT:    srli a0, a0, 32
1376; RV64IM-NEXT:    ret
1377  %1 = urem i32 %a, %b
1378  ret i32 %1
1379}
1380
1381define zeroext i32 @zext_remuw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1382; RV64IM-LABEL: zext_remuw_zext_zext:
1383; RV64IM:       # %bb.0:
1384; RV64IM-NEXT:    remu a0, a0, a1
1385; RV64IM-NEXT:    ret
1386  %1 = urem i32 %a, %b
1387  ret i32 %1
1388}
1389
1390define zeroext i8 @zext_remuw_zext_zext_i8(i8 zeroext %a, i8 zeroext %b) nounwind {
1391; RV64IM-LABEL: zext_remuw_zext_zext_i8:
1392; RV64IM:       # %bb.0:
1393; RV64IM-NEXT:    remuw a0, a0, a1
1394; RV64IM-NEXT:    ret
1395  %1 = urem i8 %a, %b
1396  ret i8 %1
1397}
1398
1399define zeroext i16 @zext_remuw_zext_zext_i16(i16 zeroext %a, i16 zeroext %b) nounwind {
1400; RV64IM-LABEL: zext_remuw_zext_zext_i16:
1401; RV64IM:       # %bb.0:
1402; RV64IM-NEXT:    remuw a0, a0, a1
1403; RV64IM-NEXT:    ret
1404  %1 = urem i16 %a, %b
1405  ret i16 %1
1406}
1407