1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i64 2>&1 < %s| FileCheck %s
2
3// ------------------------------------------------------------------------- //
4// Invalid tile
5
6addva za4.s, p0/m, p0/m, z0.s
7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8// CHECK-NEXT: addva za4.s, p0/m, p0/m, z0.s
9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10
11addva za8.d, p0/m, p0/m, z0.d
12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
13// CHECK-NEXT: addva za8.d, p0/m, p0/m, z0.d
14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15
16// ------------------------------------------------------------------------- //
17// Invalid predicate
18
19addva za0.s, p8/m, p0/m, z0.s
20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
21// CHECK-NEXT: addva za0.s, p8/m, p0/m, z0.s
22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24addva za0.s, p0/m, p8/m, z0.s
25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
26// CHECK-NEXT: addva za0.s, p0/m, p8/m, z0.s
27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28
29addva za0.d, p8/m, p0/m, z0.d
30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
31// CHECK-NEXT: addva za0.d, p8/m, p0/m, z0.d
32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33
34addva za0.d, p0/m, p8/m, z0.d
35// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
36// CHECK-NEXT: addva za0.d, p0/m, p8/m, z0.d
37// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38