1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s 2 3// ------------------------------------------------------------------------- // 4// Invalid tile (expected: za[0-3]h.s or za[0-3]v.s) 5 6st1w {za4h.s[w12, 0]}, p0, [x0] 7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unexpected token in argument list 8// CHECK-NEXT: st1w {za4h.s[w12, 0]}, p0, [x0] 9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11st1w {za[w12, 0]}, p0/z, [x0] 12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s 13// CHECK-NEXT: st1w {za[w12, 0]}, p0/z, [x0] 14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 15 16st1w {za1v.h[w12, 0]}, p0/z, [x0] 17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s 18// CHECK-NEXT: st1w {za1v.h[w12, 0]}, p0/z, [x0] 19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 20 21// ------------------------------------------------------------------------- // 22// Invalid vector select register (expected: w12-w15) 23 24st1w {za0h.s[w11, 0]}, p0, [x0] 25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] 26// CHECK-NEXT: st1w {za0h.s[w11, 0]}, p0, [x0] 27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 28 29st1w {za0h.s[w16, 0]}, p0, [x0] 30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15] 31// CHECK-NEXT: st1w {za0h.s[w16, 0]}, p0, [x0] 32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 33 34// ------------------------------------------------------------------------- // 35// Invalid vector select offset (expected: 0-3) 36 37st1w {za0h.s[w12]}, p0, [x0] 38// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3]. 39// CHECK-NEXT: st1w {za0h.s[w12]}, p0, [x0] 40// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 41 42st1w {za0h.s[w12, 4]}, p0, [x0] 43// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3]. 44// CHECK-NEXT: st1w {za0h.s[w12, 4]}, p0, [x0] 45// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 46 47// ------------------------------------------------------------------------- // 48// Invalid predicate (expected: p0-p7) 49 50st1w {za0h.s[w12, 0]}, p8, [x0] 51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 52// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p8, [x0] 53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 54 55// ------------------------------------------------------------------------- // 56// Unexpected predicate qualifier 57 58st1w {za0h.s[w12, 0]}, p0/z, [x0] 59// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 60// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0/z, [x0] 61// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 62 63st1w {za0h.s[w12, 0]}, p0/m, [x0] 64// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 65// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0/m, [x0] 66// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 67 68// ------------------------------------------------------------------------- // 69// Invalid memory operands 70 71st1w {za0h.s[w12, 0]}, p0, [w0] 72// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 73// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0, [w0] 74// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 75 76st1w {za0h.s[w12, 0]}, p0, [x0, w0] 77// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' 78// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0, [x0, w0] 79// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 80 81st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #3] 82// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' 83// CHECK-NEXT: st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #3] 84// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 85