1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
3; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s
4; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s
5
6; FUNC-LABEL: {{^}}ds_ordered_add:
7; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
8; GCN-DAG: s_mov_b32 m0,
9; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
10define amdgpu_kernel void @ds_ordered_add(i32 addrspace(2)* inreg %gds, i32 addrspace(1)* %out) {
11  %val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
12  store i32 %val, i32 addrspace(1)* %out
13  ret void
14}
15
16; Below are various modifications of input operands and shader types.
17
18; FUNC-LABEL: {{^}}ds_ordered_add_counter2:
19; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
20; GCN-DAG: s_mov_b32 m0,
21; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:776 gds
22define amdgpu_kernel void @ds_ordered_add_counter2(i32 addrspace(2)* inreg %gds, i32 addrspace(1)* %out) {
23  %val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 2, i1 true, i1 true)
24  store i32 %val, i32 addrspace(1)* %out
25  ret void
26}
27
28; FUNC-LABEL: {{^}}ds_ordered_add_nodone:
29; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
30; GCN-DAG: s_mov_b32 m0,
31; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:260 gds
32define amdgpu_kernel void @ds_ordered_add_nodone(i32 addrspace(2)* inreg %gds, i32 addrspace(1)* %out) {
33  %val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 false)
34  store i32 %val, i32 addrspace(1)* %out
35  ret void
36}
37
38; FUNC-LABEL: {{^}}ds_ordered_add_norelease:
39; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
40; GCN-DAG: s_mov_b32 m0,
41; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:4 gds
42define amdgpu_kernel void @ds_ordered_add_norelease(i32 addrspace(2)* inreg %gds, i32 addrspace(1)* %out) {
43  %val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 false, i1 false)
44  store i32 %val, i32 addrspace(1)* %out
45  ret void
46}
47
48; FUNC-LABEL: {{^}}ds_ordered_add_cs:
49; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
50; GCN: s_mov_b32 m0, s0
51; VIGFX9-NEXT: s_nop 0
52; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
53; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
54define amdgpu_cs float @ds_ordered_add_cs(i32 addrspace(2)* inreg %gds) {
55  %val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
56  %r = bitcast i32 %val to float
57  ret float %r
58}
59
60; FUNC-LABEL: {{^}}ds_ordered_add_ps:
61; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
62; GCN: s_mov_b32 m0, s0
63; VIGFX9-NEXT: s_nop 0
64; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:1796 gds
65; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
66define amdgpu_ps float @ds_ordered_add_ps(i32 addrspace(2)* inreg %gds) {
67  %val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
68  %r = bitcast i32 %val to float
69  ret float %r
70}
71
72; FUNC-LABEL: {{^}}ds_ordered_add_vs:
73; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
74; GCN: s_mov_b32 m0, s0
75; VIGFX9-NEXT: s_nop 0
76; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:2820 gds
77; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
78define amdgpu_vs float @ds_ordered_add_vs(i32 addrspace(2)* inreg %gds) {
79  %val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
80  %r = bitcast i32 %val to float
81  ret float %r
82}
83
84; FUNC-LABEL: {{^}}ds_ordered_add_gs:
85; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
86; GCN: s_mov_b32 m0, s0
87; VIGFX9-NEXT: s_nop 0
88; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:3844 gds
89; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
90define amdgpu_gs float @ds_ordered_add_gs(i32 addrspace(2)* inreg %gds) {
91  %val = call i32@llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
92  %r = bitcast i32 %val to float
93  ret float %r
94}
95
96declare i32 @llvm.amdgcn.ds.ordered.add(i32 addrspace(2)* nocapture, i32, i32, i32, i1, i32, i1, i1)
97