1; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ 2; RUN: < %s | FileCheck %s 3; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ 4; RUN: < %s | FileCheck %s 5 6@c = global i32 4, align 4 7@d = global i32 9, align 4 8@uc = global i32 4, align 4 9@ud = global i32 9, align 4 10@b1 = common global i32 0, align 4 11 12; Function Attrs: nounwind 13define void @eq() { 14entry: 15; CHECK-LABEL: .ent eq 16 17 %0 = load i32, i32* @c, align 4 18 %1 = load i32, i32* @d, align 4 19 %cmp = icmp eq i32 %0, %1 20 %conv = zext i1 %cmp to i32 21; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) 22; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) 23; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) 24; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) 25; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] 26; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1 27; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1. 28; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 29 30 store i32 %conv, i32* @b1, align 4 31 ret void 32} 33 34; Function Attrs: nounwind 35define void @ne() { 36entry: 37; CHECK-LABEL: .ent ne 38 %0 = load i32, i32* @c, align 4 39 %1 = load i32, i32* @d, align 4 40 %cmp = icmp ne i32 %0, %1 41 %conv = zext i1 %cmp to i32 42; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) 43; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) 44; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) 45; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) 46; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] 47; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]] 48; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. 49; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 50 51 store i32 %conv, i32* @b1, align 4 52 ret void 53} 54 55; Function Attrs: nounwind 56define void @ugt() { 57entry: 58; CHECK-LABEL: .ent ugt 59 %0 = load i32, i32* @uc, align 4 60 %1 = load i32, i32* @ud, align 4 61 %cmp = icmp ugt i32 %0, %1 62 %conv = zext i1 %cmp to i32 63; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) 64; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) 65; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) 66; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) 67; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]] 68; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. 69; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 70 71 store i32 %conv, i32* @b1, align 4 72 ret void 73} 74 75; Function Attrs: nounwind 76define void @ult() { 77entry: 78; CHECK-LABEL: .ent ult 79 %0 = load i32, i32* @uc, align 4 80 %1 = load i32, i32* @ud, align 4 81 %cmp = icmp ult i32 %0, %1 82 %conv = zext i1 %cmp to i32 83; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) 84; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) 85; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) 86; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) 87; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]] 88; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. 89; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 90 store i32 %conv, i32* @b1, align 4 91 ret void 92} 93 94; Function Attrs: nounwind 95define void @uge() { 96entry: 97; CHECK-LABEL: .ent uge 98 %0 = load i32, i32* @uc, align 4 99 %1 = load i32, i32* @ud, align 4 100 %cmp = icmp uge i32 %0, %1 101 %conv = zext i1 %cmp to i32 102; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) 103; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) 104; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) 105; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) 106; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]] 107; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 108; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. 109; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 110 store i32 %conv, i32* @b1, align 4 111 ret void 112} 113 114; Function Attrs: nounwind 115define void @ule() { 116entry: 117; CHECK-LABEL: .ent ule 118 %0 = load i32, i32* @uc, align 4 119 %1 = load i32, i32* @ud, align 4 120 %cmp = icmp ule i32 %0, %1 121 %conv = zext i1 %cmp to i32 122; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) 123; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) 124; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) 125; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) 126; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]] 127; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 128; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. 129; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 130 store i32 %conv, i32* @b1, align 4 131 ret void 132} 133 134; Function Attrs: nounwind 135define void @sgt() { 136entry: 137; CHECK-LABEL: .ent sgt 138 %0 = load i32, i32* @c, align 4 139 %1 = load i32, i32* @d, align 4 140 %cmp = icmp sgt i32 %0, %1 141 %conv = zext i1 %cmp to i32 142; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) 143; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) 144; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) 145; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) 146; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]] 147; FIXME: This instruction is redundant. The slt can only produce 0 and 1. 148; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 149 store i32 %conv, i32* @b1, align 4 150 ret void 151} 152 153; Function Attrs: nounwind 154define void @slt() { 155entry: 156; CHECK-LABEL: .ent slt 157 %0 = load i32, i32* @c, align 4 158 %1 = load i32, i32* @d, align 4 159 %cmp = icmp slt i32 %0, %1 160 %conv = zext i1 %cmp to i32 161; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) 162; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) 163; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) 164; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) 165; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] 166; FIXME: This instruction is redundant. The slt can only produce 0 and 1. 167; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 168 store i32 %conv, i32* @b1, align 4 169 ret void 170} 171 172; Function Attrs: nounwind 173define void @sge() { 174entry: 175; CHECK-LABEL: .ent sge 176 %0 = load i32, i32* @c, align 4 177 %1 = load i32, i32* @d, align 4 178 %cmp = icmp sge i32 %0, %1 179 %conv = zext i1 %cmp to i32 180 store i32 %conv, i32* @b1, align 4 181; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) 182; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) 183; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) 184; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) 185; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] 186; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 187; FIXME: This instruction is redundant. The slt can only produce 0 and 1. 188; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 189 ret void 190} 191 192; Function Attrs: nounwind 193define void @sle() { 194entry: 195; CHECK-LABEL: .ent sle 196 %0 = load i32, i32* @c, align 4 197 %1 = load i32, i32* @d, align 4 198 %cmp = icmp sle i32 %0, %1 199 %conv = zext i1 %cmp to i32 200; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) 201; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) 202; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) 203; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) 204; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]] 205; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 206; FIXME: This instruction is redundant. The slt can only produce 0 and 1. 207; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 208 store i32 %conv, i32* @b1, align 4 209 ret void 210} 211