1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-P7 %s 5define <8 x i16> @test_v8i16(<8 x i16> %m, <8 x i16> %n) { 6; CHECK-P9-LABEL: test_v8i16: 7; CHECK-P9: # %bb.0: # %entry 8; CHECK-P9-NEXT: vavguh 2, 3, 2 9; CHECK-P9-NEXT: blr 10; 11; CHECK-P8-LABEL: test_v8i16: 12; CHECK-P8: # %bb.0: # %entry 13; CHECK-P8-NEXT: vavguh 2, 3, 2 14; CHECK-P8-NEXT: blr 15; 16; CHECK-P7-LABEL: test_v8i16: 17; CHECK-P7: # %bb.0: # %entry 18; CHECK-P7-NEXT: vavguh 2, 3, 2 19; CHECK-P7-NEXT: blr 20entry: 21 %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 22 %add1 = add <8 x i16> %add, %n 23 %shr = lshr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 24 ret <8 x i16> %shr 25} 26 27define <8 x i16> @test_v8i16_sign(<8 x i16> %m, <8 x i16> %n) { 28; CHECK-P9-LABEL: test_v8i16_sign: 29; CHECK-P9: # %bb.0: # %entry 30; CHECK-P9-NEXT: vavgsh 2, 3, 2 31; CHECK-P9-NEXT: blr 32; 33; CHECK-P8-LABEL: test_v8i16_sign: 34; CHECK-P8: # %bb.0: # %entry 35; CHECK-P8-NEXT: vavgsh 2, 3, 2 36; CHECK-P8-NEXT: blr 37; 38; CHECK-P7-LABEL: test_v8i16_sign: 39; CHECK-P7: # %bb.0: # %entry 40; CHECK-P7-NEXT: vavgsh 2, 3, 2 41; CHECK-P7-NEXT: blr 42entry: 43 %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 44 %add1 = add <8 x i16> %add, %n 45 %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 46 ret <8 x i16> %shr 47} 48 49define <4 x i32> @test_v4i32(<4 x i32> %m, <4 x i32> %n) { 50; CHECK-P9-LABEL: test_v4i32: 51; CHECK-P9: # %bb.0: # %entry 52; CHECK-P9-NEXT: vavguw 2, 3, 2 53; CHECK-P9-NEXT: blr 54; 55; CHECK-P8-LABEL: test_v4i32: 56; CHECK-P8: # %bb.0: # %entry 57; CHECK-P8-NEXT: vavguw 2, 3, 2 58; CHECK-P8-NEXT: blr 59; 60; CHECK-P7-LABEL: test_v4i32: 61; CHECK-P7: # %bb.0: # %entry 62; CHECK-P7-NEXT: vavguw 2, 3, 2 63; CHECK-P7-NEXT: blr 64entry: 65 %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1> 66 %add1 = add <4 x i32> %add, %n 67 %shr = lshr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1> 68 ret <4 x i32> %shr 69} 70 71define <4 x i32> @test_v4i32_sign(<4 x i32> %m, <4 x i32> %n) { 72; CHECK-P9-LABEL: test_v4i32_sign: 73; CHECK-P9: # %bb.0: # %entry 74; CHECK-P9-NEXT: vavgsw 2, 3, 2 75; CHECK-P9-NEXT: blr 76; 77; CHECK-P8-LABEL: test_v4i32_sign: 78; CHECK-P8: # %bb.0: # %entry 79; CHECK-P8-NEXT: vavgsw 2, 3, 2 80; CHECK-P8-NEXT: blr 81; 82; CHECK-P7-LABEL: test_v4i32_sign: 83; CHECK-P7: # %bb.0: # %entry 84; CHECK-P7-NEXT: vavgsw 2, 3, 2 85; CHECK-P7-NEXT: blr 86entry: 87 %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1> 88 %add1 = add <4 x i32> %add, %n 89 %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1> 90 ret <4 x i32> %shr 91} 92 93define <16 x i8> @test_v16i8(<16 x i8> %m, <16 x i8> %n) { 94; CHECK-P9-LABEL: test_v16i8: 95; CHECK-P9: # %bb.0: # %entry 96; CHECK-P9-NEXT: vavgub 2, 3, 2 97; CHECK-P9-NEXT: blr 98; 99; CHECK-P8-LABEL: test_v16i8: 100; CHECK-P8: # %bb.0: # %entry 101; CHECK-P8-NEXT: vavgub 2, 3, 2 102; CHECK-P8-NEXT: blr 103; 104; CHECK-P7-LABEL: test_v16i8: 105; CHECK-P7: # %bb.0: # %entry 106; CHECK-P7-NEXT: vavgub 2, 3, 2 107; CHECK-P7-NEXT: blr 108entry: 109 %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 110 %add1 = add <16 x i8> %add, %n 111 %shr = lshr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 112 ret <16 x i8> %shr 113} 114 115define <16 x i8> @test_v16i8_sign(<16 x i8> %m, <16 x i8> %n) { 116; CHECK-P9-LABEL: test_v16i8_sign: 117; CHECK-P9: # %bb.0: # %entry 118; CHECK-P9-NEXT: vavgsb 2, 3, 2 119; CHECK-P9-NEXT: blr 120; 121; CHECK-P8-LABEL: test_v16i8_sign: 122; CHECK-P8: # %bb.0: # %entry 123; CHECK-P8-NEXT: vavgsb 2, 3, 2 124; CHECK-P8-NEXT: blr 125; 126; CHECK-P7-LABEL: test_v16i8_sign: 127; CHECK-P7: # %bb.0: # %entry 128; CHECK-P7-NEXT: vavgsb 2, 3, 2 129; CHECK-P7-NEXT: blr 130entry: 131 %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 132 %add1 = add <16 x i8> %add, %n 133 %shr = ashr <16 x i8> %add1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 134 ret <16 x i8> %shr 135} 136 137define <8 x i16> @test_v8i16_sign_negative(<8 x i16> %m, <8 x i16> %n) { 138; CHECK-P9-LABEL: test_v8i16_sign_negative: 139; CHECK-P9: # %bb.0: # %entry 140; CHECK-P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha 141; CHECK-P9-NEXT: addi 3, 3, .LCPI6_0@toc@l 142; CHECK-P9-NEXT: vadduhm 2, 2, 3 143; CHECK-P9-NEXT: lxvx 35, 0, 3 144; CHECK-P9-NEXT: vadduhm 2, 2, 3 145; CHECK-P9-NEXT: vspltish 3, 1 146; CHECK-P9-NEXT: vsrah 2, 2, 3 147; CHECK-P9-NEXT: blr 148; 149; CHECK-P8-LABEL: test_v8i16_sign_negative: 150; CHECK-P8: # %bb.0: # %entry 151; CHECK-P8-NEXT: addis 3, 2, .LCPI6_0@toc@ha 152; CHECK-P8-NEXT: vadduhm 2, 2, 3 153; CHECK-P8-NEXT: vspltish 4, 1 154; CHECK-P8-NEXT: addi 3, 3, .LCPI6_0@toc@l 155; CHECK-P8-NEXT: lvx 3, 0, 3 156; CHECK-P8-NEXT: vadduhm 2, 2, 3 157; CHECK-P8-NEXT: vsrah 2, 2, 4 158; CHECK-P8-NEXT: blr 159; 160; CHECK-P7-LABEL: test_v8i16_sign_negative: 161; CHECK-P7: # %bb.0: # %entry 162; CHECK-P7-NEXT: addis 3, 2, .LCPI6_0@toc@ha 163; CHECK-P7-NEXT: vadduhm 2, 2, 3 164; CHECK-P7-NEXT: vspltish 4, 1 165; CHECK-P7-NEXT: addi 3, 3, .LCPI6_0@toc@l 166; CHECK-P7-NEXT: lvx 3, 0, 3 167; CHECK-P7-NEXT: vadduhm 2, 2, 3 168; CHECK-P7-NEXT: vsrah 2, 2, 4 169; CHECK-P7-NEXT: blr 170entry: 171 %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 -1, i16 1, i16 1, i16 1, i16 1> 172 %add1 = add <8 x i16> %add, %n 173 %shr = ashr <8 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 174 ret <8 x i16> %shr 175} 176 177define <4 x i32> @test_v4i32_negative(<4 x i32> %m, <4 x i32> %n) { 178; CHECK-P9-LABEL: test_v4i32_negative: 179; CHECK-P9: # %bb.0: # %entry 180; CHECK-P9-NEXT: xxlnor 34, 34, 34 181; CHECK-P9-NEXT: vsubuwm 2, 3, 2 182; CHECK-P9-NEXT: vspltisw 3, 2 183; CHECK-P9-NEXT: vsrw 2, 2, 3 184; CHECK-P9-NEXT: blr 185; 186; CHECK-P8-LABEL: test_v4i32_negative: 187; CHECK-P8: # %bb.0: # %entry 188; CHECK-P8-NEXT: xxlnor 34, 34, 34 189; CHECK-P8-NEXT: vspltisw 4, 2 190; CHECK-P8-NEXT: vsubuwm 2, 3, 2 191; CHECK-P8-NEXT: vsrw 2, 2, 4 192; CHECK-P8-NEXT: blr 193; 194; CHECK-P7-LABEL: test_v4i32_negative: 195; CHECK-P7: # %bb.0: # %entry 196; CHECK-P7-NEXT: xxlnor 34, 34, 34 197; CHECK-P7-NEXT: vspltisw 4, 2 198; CHECK-P7-NEXT: vsubuwm 2, 3, 2 199; CHECK-P7-NEXT: vsrw 2, 2, 4 200; CHECK-P7-NEXT: blr 201entry: 202 %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1> 203 %add1 = add <4 x i32> %add, %n 204 %shr = lshr <4 x i32> %add1, <i32 2, i32 2, i32 2, i32 2> 205 ret <4 x i32> %shr 206} 207 208define <4 x i32> @test_v4i32_sign_negative(<4 x i32> %m, <4 x i32> %n) { 209; CHECK-P9-LABEL: test_v4i32_sign_negative: 210; CHECK-P9: # %bb.0: # %entry 211; CHECK-P9-NEXT: vadduwm 2, 2, 3 212; CHECK-P9-NEXT: xxleqv 35, 35, 35 213; CHECK-P9-NEXT: vadduwm 2, 2, 3 214; CHECK-P9-NEXT: vspltisw 3, 1 215; CHECK-P9-NEXT: vsraw 2, 2, 3 216; CHECK-P9-NEXT: blr 217; 218; CHECK-P8-LABEL: test_v4i32_sign_negative: 219; CHECK-P8: # %bb.0: # %entry 220; CHECK-P8-NEXT: xxleqv 36, 36, 36 221; CHECK-P8-NEXT: vadduwm 2, 2, 3 222; CHECK-P8-NEXT: vspltisw 3, 1 223; CHECK-P8-NEXT: vadduwm 2, 2, 4 224; CHECK-P8-NEXT: vsraw 2, 2, 3 225; CHECK-P8-NEXT: blr 226; 227; CHECK-P7-LABEL: test_v4i32_sign_negative: 228; CHECK-P7: # %bb.0: # %entry 229; CHECK-P7-NEXT: vspltisb 4, -1 230; CHECK-P7-NEXT: vadduwm 2, 2, 3 231; CHECK-P7-NEXT: vspltisw 3, 1 232; CHECK-P7-NEXT: vadduwm 2, 2, 4 233; CHECK-P7-NEXT: vsraw 2, 2, 3 234; CHECK-P7-NEXT: blr 235entry: 236 %add = add <4 x i32> %m, <i32 -1, i32 -1, i32 -1, i32 -1> 237 %add1 = add <4 x i32> %add, %n 238 %shr = ashr <4 x i32> %add1, <i32 1, i32 1, i32 1, i32 1> 239 ret <4 x i32> %shr 240} 241