1; RUN: opt < %s -loop-vectorize -enable-vplan-native-path -vplan-build-stress-test -vplan-verify-hcfg -debug-only=loop-vectorize -disable-output 2>&1 | FileCheck %s -check-prefix=VERIFIER 2; RUN: opt < %s -loop-vectorize -enable-vplan-native-path -vplan-build-stress-test -debug-only=loop-vectorize -disable-output 2>&1 | FileCheck %s -check-prefix=NO-VERIFIER -allow-empty 3; REQUIRES: asserts 4 5; Verify that the stress testing flag for the VPlan H-CFG builder works as 6; expected with and without enabling the VPlan H-CFG Verifier. 7 8; VERIFIER: Verifying VPlan H-CFG. 9; NO-VERIFIER-NOT: Verifying VPlan H-CFG. 10 11target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 12 13define void @foo(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) { 14entry: 15 %cmp32 = icmp sgt i32 %N, 0 16 br i1 %cmp32, label %outer.ph, label %for.end15 17 18outer.ph: 19 %cmp230 = icmp sgt i32 %M, 0 20 %0 = sext i32 %M to i64 21 %wide.trip.count = zext i32 %M to i64 22 %wide.trip.count38 = zext i32 %N to i64 23 br label %outer.body 24 25outer.body: 26 %indvars.iv35 = phi i64 [ 0, %outer.ph ], [ %indvars.iv.next36, %outer.inc ] 27 br i1 %cmp230, label %inner.ph, label %outer.inc 28 29inner.ph: 30 %1 = mul nsw i64 %indvars.iv35, %0 31 br label %inner.body 32 33inner.body: 34 %indvars.iv = phi i64 [ 0, %inner.ph ], [ %indvars.iv.next, %inner.body ] 35 %2 = add nsw i64 %indvars.iv, %1 36 %arrayidx = getelementptr inbounds i32, i32* %b, i64 %2 37 %3 = load i32, i32* %arrayidx, align 4 38 %arrayidx12 = getelementptr inbounds i32, i32* %a, i64 %2 39 store i32 %3, i32* %arrayidx12, align 4 40 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 41 %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count 42 br i1 %exitcond, label %outer.inc, label %inner.body 43 44outer.inc: 45 %indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1 46 %exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count38 47 br i1 %exitcond39, label %for.end15, label %outer.body 48 49for.end15: 50 ret void 51} 52