1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3; CHECK-LABEL: test0000: 4; CHECK: v0.h = vasl(v0.h,r0) 5define <32 x i16> @test0000(<32 x i16> %a0, i16 %a1) #0 { 6 %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0 7 %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer 8 9 %v0 = shl <32 x i16> %a0, %b1 10 ret <32 x i16> %v0 11} 12 13; CHECK-LABEL: test0001: 14; CHECK: v0.h = vasr(v0.h,r0) 15define <32 x i16> @test0001(<32 x i16> %a0, i16 %a1) #0 { 16 %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0 17 %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer 18 %v0 = ashr <32 x i16> %a0, %b1 19 ret <32 x i16> %v0 20} 21 22; CHECK-LABEL: test0002: 23; CHECK: v0.uh = vlsr(v0.uh,r0) 24define <32 x i16> @test0002(<32 x i16> %a0, i16 %a1) #0 { 25 %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0 26 %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer 27 %v0 = lshr <32 x i16> %a0, %b1 28 ret <32 x i16> %v0 29} 30 31; CHECK-LABEL: test0010: 32; CHECK: v0.w = vasl(v0.w,r0) 33define <16 x i32> @test0010(<16 x i32> %a0, i32 %a1) #0 { 34 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0 35 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer 36 %v0 = shl <16 x i32> %a0, %b1 37 ret <16 x i32> %v0 38} 39 40; CHECK-LABEL: test0011: 41; CHECK: v0.w = vasr(v0.w,r0) 42define <16 x i32> @test0011(<16 x i32> %a0, i32 %a1) #0 { 43 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0 44 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer 45 %v0 = ashr <16 x i32> %a0, %b1 46 ret <16 x i32> %v0 47} 48 49; CHECK-LABEL: test0012: 50; CHECK: v0.uw = vlsr(v0.uw,r0) 51define <16 x i32> @test0012(<16 x i32> %a0, i32 %a1) #0 { 52 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0 53 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer 54 %v0 = lshr <16 x i32> %a0, %b1 55 ret <16 x i32> %v0 56} 57 58; CHECK-LABEL: test0013: 59; CHECK: v0.w += vasl(v1.w,r0) 60define <16 x i32> @test0013(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 { 61 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a2, i32 0 62 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer 63 %v0 = shl <16 x i32> %a1, %b1 64 %v1 = add <16 x i32> %a0, %v0 65 ret <16 x i32> %v1 66} 67 68; CHECK-LABEL: test0014: 69; CHECK: v0.w += vasr(v1.w,r0) 70define <16 x i32> @test0014(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 { 71 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a2, i32 0 72 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer 73 %v0 = ashr <16 x i32> %a1, %b1 74 %v1 = add <16 x i32> %a0, %v0 75 ret <16 x i32> %v1 76} 77 78; CHECK-LABEL: test0020: 79; CHECK: v0.h = vasl(v0.h,v1.h) 80define <32 x i16> @test0020(<32 x i16> %a0, <32 x i16> %a1) #0 { 81 %v0 = shl <32 x i16> %a0, %a1 82 ret <32 x i16> %v0 83} 84 85; CHECK-LABEL: test0021: 86; CHECK: v0.h = vasr(v0.h,v1.h) 87define <32 x i16> @test0021(<32 x i16> %a0, <32 x i16> %a1) #0 { 88 %v0 = ashr <32 x i16> %a0, %a1 89 ret <32 x i16> %v0 90} 91 92; CHECK-LABEL: test0022: 93; CHECK: v0.h = vlsr(v0.h,v1.h) 94define <32 x i16> @test0022(<32 x i16> %a0, <32 x i16> %a1) #0 { 95 %v0 = lshr <32 x i16> %a0, %a1 96 ret <32 x i16> %v0 97} 98 99; CHECK-LABEL: test0030: 100; CHECK: v0.w = vasl(v0.w,v1.w) 101define <16 x i32> @test0030(<16 x i32> %a0, <16 x i32> %a1) #0 { 102 %v0 = shl <16 x i32> %a0, %a1 103 ret <16 x i32> %v0 104} 105 106; CHECK-LABEL: test0031: 107; CHECK: v0.w = vasr(v0.w,v1.w) 108define <16 x i32> @test0031(<16 x i32> %a0, <16 x i32> %a1) #0 { 109 %v0 = ashr <16 x i32> %a0, %a1 110 ret <16 x i32> %v0 111} 112 113; CHECK-LABEL: test0032: 114; CHECK: v0.w = vlsr(v0.w,v1.w) 115define <16 x i32> @test0032(<16 x i32> %a0, <16 x i32> %a1) #0 { 116 %v0 = lshr <16 x i32> %a0, %a1 117 ret <16 x i32> %v0 118} 119 120attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } 121 122