1; RUN: llc -march=hexagon < %s | FileCheck %s
2; Check that we generate load instructions with global + offset
3
4
5%s.0 = type { i8, i8, i16, i32 }
6
7@g0 = common global %s.0 zeroinitializer, align 4
8
9; CHECK-LABEL: f0:
10; CHECK: r{{[0-9]+}} = memw(##g0+4)
11define void @f0(i32 %a0, i32 %a1, i32* nocapture %a2) #0 {
12b0:
13  %v0 = icmp sgt i32 %a0, %a1
14  br i1 %v0, label %b1, label %b2
15
16b1:                                               ; preds = %b0
17  %v1 = load i32, i32* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 3), align 4
18  store i32 %v1, i32* %a2, align 4
19  br label %b2
20
21b2:                                               ; preds = %b1, %b0
22  ret void
23}
24
25; CHECK-LABEL: f1:
26; CHECK: r{{[0-9]+}} = memub(##g0+1)
27define void @f1(i32 %a0, i32 %a1, i8* nocapture %a2) #0 {
28b0:
29  %v0 = icmp sgt i32 %a0, %a1
30  br i1 %v0, label %b1, label %b2
31
32b1:                                               ; preds = %b0
33  %v1 = load i8, i8* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 1), align 1
34  store i8 %v1, i8* %a2, align 1
35  br label %b2
36
37b2:                                               ; preds = %b1, %b0
38  ret void
39}
40
41; CHECK-LABEL: f2:
42; CHECK: r{{[0-9]+}} = memuh(##g0+2)
43define void @f2(i32 %a0, i32 %a1, i16* %a2) #0 {
44b0:
45  %v0 = icmp sgt i32 %a0, %a1
46  br i1 %v0, label %b1, label %b2
47
48b1:                                               ; preds = %b0
49  %v1 = load i16, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 2
50  store i16 %v1, i16* %a2, align 2
51  br label %b2
52
53b2:                                               ; preds = %b1, %b0
54  ret void
55}
56
57attributes #0 = { nounwind "target-cpu"="hexagonv5" }
58