1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; Test that we compile the HVX dual output intrinsics.
4
5; CHECK-LABEL: f0:
6; CHECK: v{{[0-9]+}}.w = vadd(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry
7define inreg <16 x i32> @f0(<16 x i32> %a0, <16 x i32> %a1, i8* nocapture readonly %a2) #0 {
8b0:
9  %v0 = bitcast i8* %a2 to <16 x i32>*
10  %v1 = load <16 x i32>, <16 x i32>* %v0, align 64
11  %v2 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v1, i32 -1)
12  %v3 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v2)
13  %v4 = extractvalue { <16 x i32>, <64 x i1> } %v3, 0
14  ret <16 x i32> %v4
15}
16
17; CHECK-LABEL: f1:
18; CHECK: v{{[0-9]+}}.w = vsub(v{{[0-9]+}}.w,v{{[0-9]+}}.w,q{{[0-3]}}):carry
19define inreg <16 x i32> @f1(<16 x i32> %a0, <16 x i32> %a1, i8* nocapture readonly %a2) #0 {
20b0:
21  %v0 = bitcast i8* %a2 to <16 x i32>*
22  %v1 = load <16 x i32>, <16 x i32>* %v0, align 64
23  %v2 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v1, i32 -1)
24  %v3 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v2)
25  %v4 = extractvalue { <16 x i32>, <64 x i1> } %v3, 0
26  ret <16 x i32> %v4
27}
28
29; Function Attrs: nounwind readnone
30declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
31
32; Function Attrs: nounwind readnone
33declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
34
35; Function Attrs: nounwind readnone
36declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
37
38attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }
39attributes #1 = { nounwind readnone }
40