1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; OR of two rotates of %a0(r0).
4; CHECK-LABEL: f0:
5; CHECK: r[[R00:[0-9]+]] = rol(r0,#7)
6; CHECK: r[[R00]] |= rol(r0,#9)
7define i32 @f0(i32 %a0) #0 {
8b0:
9  %v0 = shl i32 %a0, 7
10  %v1 = lshr i32 %a0, 25
11  %v2 = or i32 %v0, %v1
12  %v3 = shl i32 %a0, 9
13  %v4 = lshr i32 %a0, 23
14  %v5 = or i32 %v3, %v4
15  %v6 = or i32 %v2, %v5
16  ret i32 %v6
17}
18
19; OR of two rotates of %a0(r0) with an extra input %a1(r1).
20; CHECK-LABEL: f1:
21; CHECK: r1 |= asl(r0,#7)
22; CHECK: r1 |= rol(r0,#9)
23define i32 @f1(i32 %a0, i32 %a1) #0 {
24b0:
25  %v0 = shl i32 %a0, 7
26  %v1 = lshr i32 %a0, 25
27  %v2 = or i32 %v0, %a1
28  %v3 = shl i32 %a0, 9
29  %v4 = lshr i32 %a0, 23
30  %v5 = or i32 %v3, %v4
31  %v6 = or i32 %v2, %v5
32  %v7 = or i32 %v6, %v1
33  ret i32 %v6
34}
35
36; OR of two rotates of two different inputs: %a0(r0) and %a1(r1).
37; CHECK-LABEL: f2:
38; CHECK: r[[R20:[0-9]+]] = asl(r0,#11)
39; CHECK: r[[R21:[0-9]+]] = lsr(r0,#21)
40; CHECK: r[[R22:[0-9]+]] = lsr(r1,#13)
41; CHECK: r[[R20]] |= asl(r1,#19)
42; CHECK: r[[R20]] |= or(r[[R21]],r[[R22]])
43define i32 @f2(i32 %a0, i32 %a1) #0 {
44  %v0 = shl i32 %a0, 11
45  %v1 = lshr i32 %a0, 21
46  %v2 = shl i32 %a1, 19
47  %v3 = lshr i32 %a1, 13
48  %v4 = or i32 %v0, %v2
49  %v5 = or i32 %v1, %v3
50  %v6 = or i32 %v4, %v5
51  ret i32 %v6
52}
53
54; ORs of multiple shifts of the same value with only one pair actually
55; matching a rotate.
56; CHECK-LABEL: f3:
57; CHECK: r[[R30:[0-9]+]] = asl(r0,#3)
58; CHECK: r[[R30]] |= asl(r0,#5)
59; CHECK: r[[R30]] |= asl(r0,#7)
60; CHECK: r[[R30]] |= asl(r0,#13)
61; CHECK: r[[R30]] |= asl(r0,#19)
62; CHECK: r[[R30]] |= lsr(r0,#2)
63; CHECK: r[[R30]] |= lsr(r0,#15)
64; CHECK: r[[R30]] |= lsr(r0,#23)
65; CHECK: r[[R30]] |= lsr(r0,#25)
66; CHECK: r[[R30]] |= lsr(r0,#30)
67define i32 @f3(i32 %a0) #0 {
68  %v0 = shl i32 %a0, 3
69  %v1 = shl i32 %a0, 5
70  %v2 = shl i32 %a0, 7      ; rotate
71  %v3 = shl i32 %a0, 13
72  %v4 = shl i32 %a0, 19
73  %v5 = lshr i32 %a0, 2
74  %v6 = lshr i32 %a0, 15
75  %v7 = lshr i32 %a0, 23
76  %v8 = lshr i32 %a0, 25    ; rotate
77  %v9 = lshr i32 %a0, 30
78  %v10 = or i32  %v0, %v1
79  %v11 = or i32 %v10, %v2
80  %v12 = or i32 %v11, %v3
81  %v13 = or i32 %v12, %v4
82  %v14 = or i32 %v13, %v5
83  %v15 = or i32 %v14, %v6
84  %v16 = or i32 %v15, %v7
85  %v17 = or i32 %v16, %v8
86  %v18 = or i32 %v17, %v9
87  ret i32 %v18
88}
89
90attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="-packets" }
91