1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; Test that the store widening optimization correctly transforms to a wider
4; instruction with a sub register. Recently, the store widening occurs in the
5; DAG combiner, so this test doesn't fail any more.
6
7; CHECK: memh({{r[0-9]+}}+#{{[0-9]+}}) =
8
9%s.0 = type { %s.1, %s.2, %s.3*, %s.0*, i32, i8, i8, i32, i8, i8, i32, i32, i8, i32, %s.4*, [2 x %s.4*], %s.13, i8*, %s.15*, %s.26, i32, i32, i32 }
10%s.1 = type { i64, [8 x i8] }
11%s.2 = type { i64*, i32, i8 }
12%s.3 = type { %s.1, %s.26, %s.26, i32, i32, i32, void (%s.1*)*, void (%s.1*)*, i32 (%s.1*)*, void (%s.1*)*, i32, i64* }
13%s.4 = type { %s.5, %s.12 }
14%s.5 = type { i32, i32, i32, i32, i32, i32, i32, i32, %s.6 }
15%s.6 = type { %s.7 }
16%s.7 = type { i32, i32, %s.8, %s.9, i32, [4 x %s.10], %s.11 }
17%s.8 = type { i32, i32, i32 }
18%s.9 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
19%s.10 = type { i32, i32 }
20%s.11 = type { i32, i32, i32, i32, i32, i32, i32, i32 }
21%s.12 = type { i32, i32, i32, i32, i32, i32, i32 }
22%s.13 = type { i32, i32, i32, %s.14*, %s.14*, %s.14*, %s.14*, i32 }
23%s.14 = type { %s.14*, i8, i32, %s.4*, i32, %s.4* }
24%s.15 = type { %s.16, %s.17, %s.19, %s.20, %s.21, %s.24 }
25%s.16 = type { i64, i64, i64, i32 }
26%s.17 = type { i16, i16, i8, [4 x %s.18], i8, i8 }
27%s.18 = type { i32, i32 }
28%s.19 = type { i32*, i32, i32* }
29%s.20 = type { i8, i8, i32, i32, i8, i32, i32, i32, i32, i32 }
30%s.21 = type { i32, %s.22 }
31%s.22 = type { %s.23 }
32%s.23 = type { i32, i32, i32, i32, i32, i32, i32 }
33%s.24 = type { %s.25 }
34%s.25 = type { i32, i32, i32, i32, i32, i32, i32 }
35%s.26 = type { %s.27 }
36%s.27 = type { i16, i16, i32, i32, i32 }
37
38; Function Attrs: nounwind
39define void @f0(i64* %a0, i1 %a1) #0 {
40b0:
41  %v0 = load i64, i64* %a0, align 8
42  br i1 %a1, label %b1, label %b2
43
44b1:                                               ; preds = %b0
45  %v1 = trunc i64 %v0 to i32
46  %v2 = inttoptr i32 %v1 to %s.0*
47  %v3 = getelementptr inbounds %s.0, %s.0* %v2, i32 0, i32 8
48  store i8 0, i8* %v3, align 8
49  %v4 = getelementptr inbounds %s.0, %s.0* %v2, i32 0, i32 9
50  store i8 1, i8* %v4, align 1
51  %v5 = getelementptr inbounds %s.0, %s.0* %v2, i32 0, i32 6
52  store i8 1, i8* %v5, align 1
53  ret void
54
55b2:                                               ; preds = %b0
56  ret void
57}
58
59attributes #0 = { nounwind }
60