1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4
5@src = global i32 0
6@dst = global i32 0
7
8; Tests that the common hi20 value (1) for the constants is used rather than
9; redundantly re-materialised.
10define void @imm32_cse() nounwind {
11; RV32I-LABEL: imm32_cse:
12; RV32I:       # %bb.0:
13; RV32I-NEXT:    lui a0, %hi(src)
14; RV32I-NEXT:    lw a1, %lo(src)(a0)
15; RV32I-NEXT:    lui a2, 1
16; RV32I-NEXT:    addi a2, a2, 1
17; RV32I-NEXT:    add a1, a1, a2
18; RV32I-NEXT:    lui a3, %hi(dst)
19; RV32I-NEXT:    sw a1, %lo(dst)(a3)
20; RV32I-NEXT:    lw a1, %lo(src)(a0)
21; RV32I-NEXT:    add a1, a1, a2
22; RV32I-NEXT:    addi a1, a1, 1
23; RV32I-NEXT:    sw a1, %lo(dst)(a3)
24; RV32I-NEXT:    lw a0, %lo(src)(a0)
25; RV32I-NEXT:    add a0, a0, a2
26; RV32I-NEXT:    addi a0, a0, 2
27; RV32I-NEXT:    sw a0, %lo(dst)(a3)
28; RV32I-NEXT:    ret
29  %1 = load volatile i32, i32* @src
30  %2 = add i32 %1, 4097
31  store volatile i32 %2, i32* @dst
32  %3 = load volatile i32, i32* @src
33  %4 = add i32 %3, 4098
34  store volatile i32 %4, i32* @dst
35  %5 = load volatile i32, i32* @src
36  %6 = add i32 %5, 4099
37  store volatile i32 %6, i32* @dst
38  ret void
39}
40