1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64I
4
5; The patterns for the 'W' suffixed RV64I instructions have the potential of
6; missing cases. This file checks all the variants of
7; sign-extended/zero-extended/any-extended inputs and outputs.
8
9; The 64-bit add instruction can safely be used when the result is anyext.
10
11define i32 @aext_addw_aext_aext(i32 %a, i32 %b) nounwind {
12; RV64I-LABEL: aext_addw_aext_aext:
13; RV64I:       # %bb.0:
14; RV64I-NEXT:    addw a0, a0, a1
15; RV64I-NEXT:    ret
16  %1 = add i32 %a, %b
17  ret i32 %1
18}
19
20define i32 @aext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
21; RV64I-LABEL: aext_addw_aext_sext:
22; RV64I:       # %bb.0:
23; RV64I-NEXT:    addw a0, a0, a1
24; RV64I-NEXT:    ret
25  %1 = add i32 %a, %b
26  ret i32 %1
27}
28
29define i32 @aext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
30; RV64I-LABEL: aext_addw_aext_zext:
31; RV64I:       # %bb.0:
32; RV64I-NEXT:    addw a0, a0, a1
33; RV64I-NEXT:    ret
34  %1 = add i32 %a, %b
35  ret i32 %1
36}
37
38define i32 @aext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
39; RV64I-LABEL: aext_addw_sext_aext:
40; RV64I:       # %bb.0:
41; RV64I-NEXT:    addw a0, a0, a1
42; RV64I-NEXT:    ret
43  %1 = add i32 %a, %b
44  ret i32 %1
45}
46
47define i32 @aext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
48; RV64I-LABEL: aext_addw_sext_sext:
49; RV64I:       # %bb.0:
50; RV64I-NEXT:    addw a0, a0, a1
51; RV64I-NEXT:    ret
52  %1 = add i32 %a, %b
53  ret i32 %1
54}
55
56define i32 @aext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
57; RV64I-LABEL: aext_addw_sext_zext:
58; RV64I:       # %bb.0:
59; RV64I-NEXT:    addw a0, a0, a1
60; RV64I-NEXT:    ret
61  %1 = add i32 %a, %b
62  ret i32 %1
63}
64
65define i32 @aext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
66; RV64I-LABEL: aext_addw_zext_aext:
67; RV64I:       # %bb.0:
68; RV64I-NEXT:    addw a0, a0, a1
69; RV64I-NEXT:    ret
70  %1 = add i32 %a, %b
71  ret i32 %1
72}
73
74define i32 @aext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
75; RV64I-LABEL: aext_addw_zext_sext:
76; RV64I:       # %bb.0:
77; RV64I-NEXT:    addw a0, a0, a1
78; RV64I-NEXT:    ret
79  %1 = add i32 %a, %b
80  ret i32 %1
81}
82
83define i32 @aext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
84; RV64I-LABEL: aext_addw_zext_zext:
85; RV64I:       # %bb.0:
86; RV64I-NEXT:    addw a0, a0, a1
87; RV64I-NEXT:    ret
88  %1 = add i32 %a, %b
89  ret i32 %1
90}
91
92; Always select addw when a signext result is required.
93
94define signext i32 @sext_addw_aext_aext(i32 %a, i32 %b) nounwind {
95; RV64I-LABEL: sext_addw_aext_aext:
96; RV64I:       # %bb.0:
97; RV64I-NEXT:    addw a0, a0, a1
98; RV64I-NEXT:    ret
99  %1 = add i32 %a, %b
100  ret i32 %1
101}
102
103define signext i32 @sext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
104; RV64I-LABEL: sext_addw_aext_sext:
105; RV64I:       # %bb.0:
106; RV64I-NEXT:    addw a0, a0, a1
107; RV64I-NEXT:    ret
108  %1 = add i32 %a, %b
109  ret i32 %1
110}
111
112define signext i32 @sext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
113; RV64I-LABEL: sext_addw_aext_zext:
114; RV64I:       # %bb.0:
115; RV64I-NEXT:    addw a0, a0, a1
116; RV64I-NEXT:    ret
117  %1 = add i32 %a, %b
118  ret i32 %1
119}
120
121define signext i32 @sext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
122; RV64I-LABEL: sext_addw_sext_aext:
123; RV64I:       # %bb.0:
124; RV64I-NEXT:    addw a0, a0, a1
125; RV64I-NEXT:    ret
126  %1 = add i32 %a, %b
127  ret i32 %1
128}
129
130define signext i32 @sext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
131; RV64I-LABEL: sext_addw_sext_sext:
132; RV64I:       # %bb.0:
133; RV64I-NEXT:    addw a0, a0, a1
134; RV64I-NEXT:    ret
135  %1 = add i32 %a, %b
136  ret i32 %1
137}
138
139define signext i32 @sext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
140; RV64I-LABEL: sext_addw_sext_zext:
141; RV64I:       # %bb.0:
142; RV64I-NEXT:    addw a0, a0, a1
143; RV64I-NEXT:    ret
144  %1 = add i32 %a, %b
145  ret i32 %1
146}
147
148define signext i32 @sext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
149; RV64I-LABEL: sext_addw_zext_aext:
150; RV64I:       # %bb.0:
151; RV64I-NEXT:    addw a0, a0, a1
152; RV64I-NEXT:    ret
153  %1 = add i32 %a, %b
154  ret i32 %1
155}
156
157define signext i32 @sext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
158; RV64I-LABEL: sext_addw_zext_sext:
159; RV64I:       # %bb.0:
160; RV64I-NEXT:    addw a0, a0, a1
161; RV64I-NEXT:    ret
162  %1 = add i32 %a, %b
163  ret i32 %1
164}
165
166define signext i32 @sext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
167; RV64I-LABEL: sext_addw_zext_zext:
168; RV64I:       # %bb.0:
169; RV64I-NEXT:    addw a0, a0, a1
170; RV64I-NEXT:    ret
171  %1 = add i32 %a, %b
172  ret i32 %1
173}
174
175; 64-bit add followed by zero-extension is a safe option when a zeroext result
176; is required.
177
178define zeroext i32 @zext_addw_aext_aext(i32 %a, i32 %b) nounwind {
179; RV64I-LABEL: zext_addw_aext_aext:
180; RV64I:       # %bb.0:
181; RV64I-NEXT:    add a0, a0, a1
182; RV64I-NEXT:    slli a0, a0, 32
183; RV64I-NEXT:    srli a0, a0, 32
184; RV64I-NEXT:    ret
185  %1 = add i32 %a, %b
186  ret i32 %1
187}
188
189define zeroext i32 @zext_addw_aext_sext(i32 %a, i32 signext %b) nounwind {
190; RV64I-LABEL: zext_addw_aext_sext:
191; RV64I:       # %bb.0:
192; RV64I-NEXT:    add a0, a0, a1
193; RV64I-NEXT:    slli a0, a0, 32
194; RV64I-NEXT:    srli a0, a0, 32
195; RV64I-NEXT:    ret
196  %1 = add i32 %a, %b
197  ret i32 %1
198}
199
200define zeroext i32 @zext_addw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
201; RV64I-LABEL: zext_addw_aext_zext:
202; RV64I:       # %bb.0:
203; RV64I-NEXT:    add a0, a0, a1
204; RV64I-NEXT:    slli a0, a0, 32
205; RV64I-NEXT:    srli a0, a0, 32
206; RV64I-NEXT:    ret
207  %1 = add i32 %a, %b
208  ret i32 %1
209}
210
211define zeroext i32 @zext_addw_sext_aext(i32 signext %a, i32 %b) nounwind {
212; RV64I-LABEL: zext_addw_sext_aext:
213; RV64I:       # %bb.0:
214; RV64I-NEXT:    add a0, a0, a1
215; RV64I-NEXT:    slli a0, a0, 32
216; RV64I-NEXT:    srli a0, a0, 32
217; RV64I-NEXT:    ret
218  %1 = add i32 %a, %b
219  ret i32 %1
220}
221
222define zeroext i32 @zext_addw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
223; RV64I-LABEL: zext_addw_sext_sext:
224; RV64I:       # %bb.0:
225; RV64I-NEXT:    add a0, a0, a1
226; RV64I-NEXT:    slli a0, a0, 32
227; RV64I-NEXT:    srli a0, a0, 32
228; RV64I-NEXT:    ret
229  %1 = add i32 %a, %b
230  ret i32 %1
231}
232
233define zeroext i32 @zext_addw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
234; RV64I-LABEL: zext_addw_sext_zext:
235; RV64I:       # %bb.0:
236; RV64I-NEXT:    add a0, a0, a1
237; RV64I-NEXT:    slli a0, a0, 32
238; RV64I-NEXT:    srli a0, a0, 32
239; RV64I-NEXT:    ret
240  %1 = add i32 %a, %b
241  ret i32 %1
242}
243
244define zeroext i32 @zext_addw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
245; RV64I-LABEL: zext_addw_zext_aext:
246; RV64I:       # %bb.0:
247; RV64I-NEXT:    add a0, a0, a1
248; RV64I-NEXT:    slli a0, a0, 32
249; RV64I-NEXT:    srli a0, a0, 32
250; RV64I-NEXT:    ret
251  %1 = add i32 %a, %b
252  ret i32 %1
253}
254
255define zeroext i32 @zext_addw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
256; RV64I-LABEL: zext_addw_zext_sext:
257; RV64I:       # %bb.0:
258; RV64I-NEXT:    add a0, a0, a1
259; RV64I-NEXT:    slli a0, a0, 32
260; RV64I-NEXT:    srli a0, a0, 32
261; RV64I-NEXT:    ret
262  %1 = add i32 %a, %b
263  ret i32 %1
264}
265
266define zeroext i32 @zext_addw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
267; RV64I-LABEL: zext_addw_zext_zext:
268; RV64I:       # %bb.0:
269; RV64I-NEXT:    add a0, a0, a1
270; RV64I-NEXT:    slli a0, a0, 32
271; RV64I-NEXT:    srli a0, a0, 32
272; RV64I-NEXT:    ret
273  %1 = add i32 %a, %b
274  ret i32 %1
275}
276
277; 64-bit sub is safe for an anyext result.
278
279define i32 @aext_subw_aext_aext(i32 %a, i32 %b) nounwind {
280; RV64I-LABEL: aext_subw_aext_aext:
281; RV64I:       # %bb.0:
282; RV64I-NEXT:    subw a0, a0, a1
283; RV64I-NEXT:    ret
284  %1 = sub i32 %a, %b
285  ret i32 %1
286}
287
288define i32 @aext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
289; RV64I-LABEL: aext_subw_aext_sext:
290; RV64I:       # %bb.0:
291; RV64I-NEXT:    subw a0, a0, a1
292; RV64I-NEXT:    ret
293  %1 = sub i32 %a, %b
294  ret i32 %1
295}
296
297define i32 @aext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
298; RV64I-LABEL: aext_subw_aext_zext:
299; RV64I:       # %bb.0:
300; RV64I-NEXT:    subw a0, a0, a1
301; RV64I-NEXT:    ret
302  %1 = sub i32 %a, %b
303  ret i32 %1
304}
305
306define i32 @aext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
307; RV64I-LABEL: aext_subw_sext_aext:
308; RV64I:       # %bb.0:
309; RV64I-NEXT:    subw a0, a0, a1
310; RV64I-NEXT:    ret
311  %1 = sub i32 %a, %b
312  ret i32 %1
313}
314
315define i32 @aext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
316; RV64I-LABEL: aext_subw_sext_sext:
317; RV64I:       # %bb.0:
318; RV64I-NEXT:    subw a0, a0, a1
319; RV64I-NEXT:    ret
320  %1 = sub i32 %a, %b
321  ret i32 %1
322}
323
324define i32 @aext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
325; RV64I-LABEL: aext_subw_sext_zext:
326; RV64I:       # %bb.0:
327; RV64I-NEXT:    subw a0, a0, a1
328; RV64I-NEXT:    ret
329  %1 = sub i32 %a, %b
330  ret i32 %1
331}
332
333define i32 @aext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
334; RV64I-LABEL: aext_subw_zext_aext:
335; RV64I:       # %bb.0:
336; RV64I-NEXT:    subw a0, a0, a1
337; RV64I-NEXT:    ret
338  %1 = sub i32 %a, %b
339  ret i32 %1
340}
341
342define i32 @aext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
343; RV64I-LABEL: aext_subw_zext_sext:
344; RV64I:       # %bb.0:
345; RV64I-NEXT:    subw a0, a0, a1
346; RV64I-NEXT:    ret
347  %1 = sub i32 %a, %b
348  ret i32 %1
349}
350
351define i32 @aext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
352; RV64I-LABEL: aext_subw_zext_zext:
353; RV64I:       # %bb.0:
354; RV64I-NEXT:    subw a0, a0, a1
355; RV64I-NEXT:    ret
356  %1 = sub i32 %a, %b
357  ret i32 %1
358}
359
360; Always select subw for a signext result.
361
362define signext i32 @sext_subw_aext_aext(i32 %a, i32 %b) nounwind {
363; RV64I-LABEL: sext_subw_aext_aext:
364; RV64I:       # %bb.0:
365; RV64I-NEXT:    subw a0, a0, a1
366; RV64I-NEXT:    ret
367  %1 = sub i32 %a, %b
368  ret i32 %1
369}
370
371define signext i32 @sext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
372; RV64I-LABEL: sext_subw_aext_sext:
373; RV64I:       # %bb.0:
374; RV64I-NEXT:    subw a0, a0, a1
375; RV64I-NEXT:    ret
376  %1 = sub i32 %a, %b
377  ret i32 %1
378}
379
380define signext i32 @sext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
381; RV64I-LABEL: sext_subw_aext_zext:
382; RV64I:       # %bb.0:
383; RV64I-NEXT:    subw a0, a0, a1
384; RV64I-NEXT:    ret
385  %1 = sub i32 %a, %b
386  ret i32 %1
387}
388
389define signext i32 @sext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
390; RV64I-LABEL: sext_subw_sext_aext:
391; RV64I:       # %bb.0:
392; RV64I-NEXT:    subw a0, a0, a1
393; RV64I-NEXT:    ret
394  %1 = sub i32 %a, %b
395  ret i32 %1
396}
397
398define signext i32 @sext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
399; RV64I-LABEL: sext_subw_sext_sext:
400; RV64I:       # %bb.0:
401; RV64I-NEXT:    subw a0, a0, a1
402; RV64I-NEXT:    ret
403  %1 = sub i32 %a, %b
404  ret i32 %1
405}
406
407define signext i32 @sext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
408; RV64I-LABEL: sext_subw_sext_zext:
409; RV64I:       # %bb.0:
410; RV64I-NEXT:    subw a0, a0, a1
411; RV64I-NEXT:    ret
412  %1 = sub i32 %a, %b
413  ret i32 %1
414}
415
416define signext i32 @sext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
417; RV64I-LABEL: sext_subw_zext_aext:
418; RV64I:       # %bb.0:
419; RV64I-NEXT:    subw a0, a0, a1
420; RV64I-NEXT:    ret
421  %1 = sub i32 %a, %b
422  ret i32 %1
423}
424
425define signext i32 @sext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
426; RV64I-LABEL: sext_subw_zext_sext:
427; RV64I:       # %bb.0:
428; RV64I-NEXT:    subw a0, a0, a1
429; RV64I-NEXT:    ret
430  %1 = sub i32 %a, %b
431  ret i32 %1
432}
433
434define signext i32 @sext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
435; RV64I-LABEL: sext_subw_zext_zext:
436; RV64I:       # %bb.0:
437; RV64I-NEXT:    subw a0, a0, a1
438; RV64I-NEXT:    ret
439  %1 = sub i32 %a, %b
440  ret i32 %1
441}
442
443; 64-bit sub followed by zero-extension is safe for a zeroext result.
444
445define zeroext i32 @zext_subw_aext_aext(i32 %a, i32 %b) nounwind {
446; RV64I-LABEL: zext_subw_aext_aext:
447; RV64I:       # %bb.0:
448; RV64I-NEXT:    sub a0, a0, a1
449; RV64I-NEXT:    slli a0, a0, 32
450; RV64I-NEXT:    srli a0, a0, 32
451; RV64I-NEXT:    ret
452  %1 = sub i32 %a, %b
453  ret i32 %1
454}
455
456define zeroext i32 @zext_subw_aext_sext(i32 %a, i32 signext %b) nounwind {
457; RV64I-LABEL: zext_subw_aext_sext:
458; RV64I:       # %bb.0:
459; RV64I-NEXT:    sub a0, a0, a1
460; RV64I-NEXT:    slli a0, a0, 32
461; RV64I-NEXT:    srli a0, a0, 32
462; RV64I-NEXT:    ret
463  %1 = sub i32 %a, %b
464  ret i32 %1
465}
466
467define zeroext i32 @zext_subw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
468; RV64I-LABEL: zext_subw_aext_zext:
469; RV64I:       # %bb.0:
470; RV64I-NEXT:    sub a0, a0, a1
471; RV64I-NEXT:    slli a0, a0, 32
472; RV64I-NEXT:    srli a0, a0, 32
473; RV64I-NEXT:    ret
474  %1 = sub i32 %a, %b
475  ret i32 %1
476}
477
478define zeroext i32 @zext_subw_sext_aext(i32 signext %a, i32 %b) nounwind {
479; RV64I-LABEL: zext_subw_sext_aext:
480; RV64I:       # %bb.0:
481; RV64I-NEXT:    sub a0, a0, a1
482; RV64I-NEXT:    slli a0, a0, 32
483; RV64I-NEXT:    srli a0, a0, 32
484; RV64I-NEXT:    ret
485  %1 = sub i32 %a, %b
486  ret i32 %1
487}
488
489define zeroext i32 @zext_subw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
490; RV64I-LABEL: zext_subw_sext_sext:
491; RV64I:       # %bb.0:
492; RV64I-NEXT:    sub a0, a0, a1
493; RV64I-NEXT:    slli a0, a0, 32
494; RV64I-NEXT:    srli a0, a0, 32
495; RV64I-NEXT:    ret
496  %1 = sub i32 %a, %b
497  ret i32 %1
498}
499
500define zeroext i32 @zext_subw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
501; RV64I-LABEL: zext_subw_sext_zext:
502; RV64I:       # %bb.0:
503; RV64I-NEXT:    sub a0, a0, a1
504; RV64I-NEXT:    slli a0, a0, 32
505; RV64I-NEXT:    srli a0, a0, 32
506; RV64I-NEXT:    ret
507  %1 = sub i32 %a, %b
508  ret i32 %1
509}
510
511define zeroext i32 @zext_subw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
512; RV64I-LABEL: zext_subw_zext_aext:
513; RV64I:       # %bb.0:
514; RV64I-NEXT:    sub a0, a0, a1
515; RV64I-NEXT:    slli a0, a0, 32
516; RV64I-NEXT:    srli a0, a0, 32
517; RV64I-NEXT:    ret
518  %1 = sub i32 %a, %b
519  ret i32 %1
520}
521
522define zeroext i32 @zext_subw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
523; RV64I-LABEL: zext_subw_zext_sext:
524; RV64I:       # %bb.0:
525; RV64I-NEXT:    sub a0, a0, a1
526; RV64I-NEXT:    slli a0, a0, 32
527; RV64I-NEXT:    srli a0, a0, 32
528; RV64I-NEXT:    ret
529  %1 = sub i32 %a, %b
530  ret i32 %1
531}
532
533define zeroext i32 @zext_subw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
534; RV64I-LABEL: zext_subw_zext_zext:
535; RV64I:       # %bb.0:
536; RV64I-NEXT:    sub a0, a0, a1
537; RV64I-NEXT:    slli a0, a0, 32
538; RV64I-NEXT:    srli a0, a0, 32
539; RV64I-NEXT:    ret
540  %1 = sub i32 %a, %b
541  ret i32 %1
542}
543
544; 64-bit sll is a safe choice for an anyext result.
545
546define i32 @aext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
547; RV64I-LABEL: aext_sllw_aext_aext:
548; RV64I:       # %bb.0:
549; RV64I-NEXT:    sllw a0, a0, a1
550; RV64I-NEXT:    ret
551  %1 = shl i32 %a, %b
552  ret i32 %1
553}
554
555define i32 @aext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
556; RV64I-LABEL: aext_sllw_aext_sext:
557; RV64I:       # %bb.0:
558; RV64I-NEXT:    sllw a0, a0, a1
559; RV64I-NEXT:    ret
560  %1 = shl i32 %a, %b
561  ret i32 %1
562}
563
564define i32 @aext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
565; RV64I-LABEL: aext_sllw_aext_zext:
566; RV64I:       # %bb.0:
567; RV64I-NEXT:    sllw a0, a0, a1
568; RV64I-NEXT:    ret
569  %1 = shl i32 %a, %b
570  ret i32 %1
571}
572
573define i32 @aext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
574; RV64I-LABEL: aext_sllw_sext_aext:
575; RV64I:       # %bb.0:
576; RV64I-NEXT:    sllw a0, a0, a1
577; RV64I-NEXT:    ret
578  %1 = shl i32 %a, %b
579  ret i32 %1
580}
581
582define i32 @aext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
583; RV64I-LABEL: aext_sllw_sext_sext:
584; RV64I:       # %bb.0:
585; RV64I-NEXT:    sllw a0, a0, a1
586; RV64I-NEXT:    ret
587  %1 = shl i32 %a, %b
588  ret i32 %1
589}
590
591define i32 @aext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
592; RV64I-LABEL: aext_sllw_sext_zext:
593; RV64I:       # %bb.0:
594; RV64I-NEXT:    sllw a0, a0, a1
595; RV64I-NEXT:    ret
596  %1 = shl i32 %a, %b
597  ret i32 %1
598}
599
600define i32 @aext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
601; RV64I-LABEL: aext_sllw_zext_aext:
602; RV64I:       # %bb.0:
603; RV64I-NEXT:    sllw a0, a0, a1
604; RV64I-NEXT:    ret
605  %1 = shl i32 %a, %b
606  ret i32 %1
607}
608
609define i32 @aext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
610; RV64I-LABEL: aext_sllw_zext_sext:
611; RV64I:       # %bb.0:
612; RV64I-NEXT:    sllw a0, a0, a1
613; RV64I-NEXT:    ret
614  %1 = shl i32 %a, %b
615  ret i32 %1
616}
617
618define i32 @aext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
619; RV64I-LABEL: aext_sllw_zext_zext:
620; RV64I:       # %bb.0:
621; RV64I-NEXT:    sllw a0, a0, a1
622; RV64I-NEXT:    ret
623  %1 = shl i32 %a, %b
624  ret i32 %1
625}
626
627define signext i32 @sext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
628; RV64I-LABEL: sext_sllw_aext_aext:
629; RV64I:       # %bb.0:
630; RV64I-NEXT:    sllw a0, a0, a1
631; RV64I-NEXT:    ret
632  %1 = shl i32 %a, %b
633  ret i32 %1
634}
635
636define signext i32 @sext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
637; RV64I-LABEL: sext_sllw_aext_sext:
638; RV64I:       # %bb.0:
639; RV64I-NEXT:    sllw a0, a0, a1
640; RV64I-NEXT:    ret
641  %1 = shl i32 %a, %b
642  ret i32 %1
643}
644
645define signext i32 @sext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
646; RV64I-LABEL: sext_sllw_aext_zext:
647; RV64I:       # %bb.0:
648; RV64I-NEXT:    sllw a0, a0, a1
649; RV64I-NEXT:    ret
650  %1 = shl i32 %a, %b
651  ret i32 %1
652}
653
654define signext i32 @sext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
655; RV64I-LABEL: sext_sllw_sext_aext:
656; RV64I:       # %bb.0:
657; RV64I-NEXT:    sllw a0, a0, a1
658; RV64I-NEXT:    ret
659  %1 = shl i32 %a, %b
660  ret i32 %1
661}
662
663define signext i32 @sext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
664; RV64I-LABEL: sext_sllw_sext_sext:
665; RV64I:       # %bb.0:
666; RV64I-NEXT:    sllw a0, a0, a1
667; RV64I-NEXT:    ret
668  %1 = shl i32 %a, %b
669  ret i32 %1
670}
671
672define signext i32 @sext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
673; RV64I-LABEL: sext_sllw_sext_zext:
674; RV64I:       # %bb.0:
675; RV64I-NEXT:    sllw a0, a0, a1
676; RV64I-NEXT:    ret
677  %1 = shl i32 %a, %b
678  ret i32 %1
679}
680
681define signext i32 @sext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
682; RV64I-LABEL: sext_sllw_zext_aext:
683; RV64I:       # %bb.0:
684; RV64I-NEXT:    sllw a0, a0, a1
685; RV64I-NEXT:    ret
686  %1 = shl i32 %a, %b
687  ret i32 %1
688}
689
690define signext i32 @sext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
691; RV64I-LABEL: sext_sllw_zext_sext:
692; RV64I:       # %bb.0:
693; RV64I-NEXT:    sllw a0, a0, a1
694; RV64I-NEXT:    ret
695  %1 = shl i32 %a, %b
696  ret i32 %1
697}
698
699define signext i32 @sext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
700; RV64I-LABEL: sext_sllw_zext_zext:
701; RV64I:       # %bb.0:
702; RV64I-NEXT:    sllw a0, a0, a1
703; RV64I-NEXT:    ret
704  %1 = shl i32 %a, %b
705  ret i32 %1
706}
707
708; 64-bit sll followed by zero-extension for a zeroext result.
709
710define zeroext i32 @zext_sllw_aext_aext(i32 %a, i32 %b) nounwind {
711; RV64I-LABEL: zext_sllw_aext_aext:
712; RV64I:       # %bb.0:
713; RV64I-NEXT:    sllw a0, a0, a1
714; RV64I-NEXT:    slli a0, a0, 32
715; RV64I-NEXT:    srli a0, a0, 32
716; RV64I-NEXT:    ret
717  %1 = shl i32 %a, %b
718  ret i32 %1
719}
720
721define zeroext i32 @zext_sllw_aext_sext(i32 %a, i32 signext %b) nounwind {
722; RV64I-LABEL: zext_sllw_aext_sext:
723; RV64I:       # %bb.0:
724; RV64I-NEXT:    sllw a0, a0, a1
725; RV64I-NEXT:    slli a0, a0, 32
726; RV64I-NEXT:    srli a0, a0, 32
727; RV64I-NEXT:    ret
728  %1 = shl i32 %a, %b
729  ret i32 %1
730}
731
732define zeroext i32 @zext_sllw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
733; RV64I-LABEL: zext_sllw_aext_zext:
734; RV64I:       # %bb.0:
735; RV64I-NEXT:    sllw a0, a0, a1
736; RV64I-NEXT:    slli a0, a0, 32
737; RV64I-NEXT:    srli a0, a0, 32
738; RV64I-NEXT:    ret
739  %1 = shl i32 %a, %b
740  ret i32 %1
741}
742
743define zeroext i32 @zext_sllw_sext_aext(i32 signext %a, i32 %b) nounwind {
744; RV64I-LABEL: zext_sllw_sext_aext:
745; RV64I:       # %bb.0:
746; RV64I-NEXT:    sllw a0, a0, a1
747; RV64I-NEXT:    slli a0, a0, 32
748; RV64I-NEXT:    srli a0, a0, 32
749; RV64I-NEXT:    ret
750  %1 = shl i32 %a, %b
751  ret i32 %1
752}
753
754define zeroext i32 @zext_sllw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
755; RV64I-LABEL: zext_sllw_sext_sext:
756; RV64I:       # %bb.0:
757; RV64I-NEXT:    sllw a0, a0, a1
758; RV64I-NEXT:    slli a0, a0, 32
759; RV64I-NEXT:    srli a0, a0, 32
760; RV64I-NEXT:    ret
761  %1 = shl i32 %a, %b
762  ret i32 %1
763}
764
765define zeroext i32 @zext_sllw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
766; RV64I-LABEL: zext_sllw_sext_zext:
767; RV64I:       # %bb.0:
768; RV64I-NEXT:    sllw a0, a0, a1
769; RV64I-NEXT:    slli a0, a0, 32
770; RV64I-NEXT:    srli a0, a0, 32
771; RV64I-NEXT:    ret
772  %1 = shl i32 %a, %b
773  ret i32 %1
774}
775
776define zeroext i32 @zext_sllw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
777; RV64I-LABEL: zext_sllw_zext_aext:
778; RV64I:       # %bb.0:
779; RV64I-NEXT:    sllw a0, a0, a1
780; RV64I-NEXT:    slli a0, a0, 32
781; RV64I-NEXT:    srli a0, a0, 32
782; RV64I-NEXT:    ret
783  %1 = shl i32 %a, %b
784  ret i32 %1
785}
786
787define zeroext i32 @zext_sllw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
788; RV64I-LABEL: zext_sllw_zext_sext:
789; RV64I:       # %bb.0:
790; RV64I-NEXT:    sllw a0, a0, a1
791; RV64I-NEXT:    slli a0, a0, 32
792; RV64I-NEXT:    srli a0, a0, 32
793; RV64I-NEXT:    ret
794  %1 = shl i32 %a, %b
795  ret i32 %1
796}
797
798define zeroext i32 @zext_sllw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
799; RV64I-LABEL: zext_sllw_zext_zext:
800; RV64I:       # %bb.0:
801; RV64I-NEXT:    sllw a0, a0, a1
802; RV64I-NEXT:    slli a0, a0, 32
803; RV64I-NEXT:    srli a0, a0, 32
804; RV64I-NEXT:    ret
805  %1 = shl i32 %a, %b
806  ret i32 %1
807}
808
809define i32 @aext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
810; RV64I-LABEL: aext_srlw_aext_aext:
811; RV64I:       # %bb.0:
812; RV64I-NEXT:    srlw a0, a0, a1
813; RV64I-NEXT:    ret
814  %1 = lshr i32 %a, %b
815  ret i32 %1
816}
817
818define i32 @aext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
819; RV64I-LABEL: aext_srlw_aext_sext:
820; RV64I:       # %bb.0:
821; RV64I-NEXT:    srlw a0, a0, a1
822; RV64I-NEXT:    ret
823  %1 = lshr i32 %a, %b
824  ret i32 %1
825}
826
827define i32 @aext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
828; RV64I-LABEL: aext_srlw_aext_zext:
829; RV64I:       # %bb.0:
830; RV64I-NEXT:    srlw a0, a0, a1
831; RV64I-NEXT:    ret
832  %1 = lshr i32 %a, %b
833  ret i32 %1
834}
835
836define i32 @aext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
837; RV64I-LABEL: aext_srlw_sext_aext:
838; RV64I:       # %bb.0:
839; RV64I-NEXT:    srlw a0, a0, a1
840; RV64I-NEXT:    ret
841  %1 = lshr i32 %a, %b
842  ret i32 %1
843}
844
845define i32 @aext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
846; RV64I-LABEL: aext_srlw_sext_sext:
847; RV64I:       # %bb.0:
848; RV64I-NEXT:    srlw a0, a0, a1
849; RV64I-NEXT:    ret
850  %1 = lshr i32 %a, %b
851  ret i32 %1
852}
853
854define i32 @aext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
855; RV64I-LABEL: aext_srlw_sext_zext:
856; RV64I:       # %bb.0:
857; RV64I-NEXT:    srlw a0, a0, a1
858; RV64I-NEXT:    ret
859  %1 = lshr i32 %a, %b
860  ret i32 %1
861}
862
863define i32 @aext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
864; RV64I-LABEL: aext_srlw_zext_aext:
865; RV64I:       # %bb.0:
866; RV64I-NEXT:    srlw a0, a0, a1
867; RV64I-NEXT:    ret
868  %1 = lshr i32 %a, %b
869  ret i32 %1
870}
871
872define i32 @aext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
873; RV64I-LABEL: aext_srlw_zext_sext:
874; RV64I:       # %bb.0:
875; RV64I-NEXT:    srlw a0, a0, a1
876; RV64I-NEXT:    ret
877  %1 = lshr i32 %a, %b
878  ret i32 %1
879}
880
881define i32 @aext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
882; RV64I-LABEL: aext_srlw_zext_zext:
883; RV64I:       # %bb.0:
884; RV64I-NEXT:    srlw a0, a0, a1
885; RV64I-NEXT:    ret
886  %1 = lshr i32 %a, %b
887  ret i32 %1
888}
889
890define signext i32 @sext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
891; RV64I-LABEL: sext_srlw_aext_aext:
892; RV64I:       # %bb.0:
893; RV64I-NEXT:    srlw a0, a0, a1
894; RV64I-NEXT:    ret
895  %1 = lshr i32 %a, %b
896  ret i32 %1
897}
898
899define signext i32 @sext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
900; RV64I-LABEL: sext_srlw_aext_sext:
901; RV64I:       # %bb.0:
902; RV64I-NEXT:    srlw a0, a0, a1
903; RV64I-NEXT:    ret
904  %1 = lshr i32 %a, %b
905  ret i32 %1
906}
907
908define signext i32 @sext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
909; RV64I-LABEL: sext_srlw_aext_zext:
910; RV64I:       # %bb.0:
911; RV64I-NEXT:    srlw a0, a0, a1
912; RV64I-NEXT:    ret
913  %1 = lshr i32 %a, %b
914  ret i32 %1
915}
916
917define signext i32 @sext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
918; RV64I-LABEL: sext_srlw_sext_aext:
919; RV64I:       # %bb.0:
920; RV64I-NEXT:    srlw a0, a0, a1
921; RV64I-NEXT:    ret
922  %1 = lshr i32 %a, %b
923  ret i32 %1
924}
925
926define signext i32 @sext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
927; RV64I-LABEL: sext_srlw_sext_sext:
928; RV64I:       # %bb.0:
929; RV64I-NEXT:    srlw a0, a0, a1
930; RV64I-NEXT:    ret
931  %1 = lshr i32 %a, %b
932  ret i32 %1
933}
934
935define signext i32 @sext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
936; RV64I-LABEL: sext_srlw_sext_zext:
937; RV64I:       # %bb.0:
938; RV64I-NEXT:    srlw a0, a0, a1
939; RV64I-NEXT:    ret
940  %1 = lshr i32 %a, %b
941  ret i32 %1
942}
943
944define signext i32 @sext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
945; RV64I-LABEL: sext_srlw_zext_aext:
946; RV64I:       # %bb.0:
947; RV64I-NEXT:    srlw a0, a0, a1
948; RV64I-NEXT:    ret
949  %1 = lshr i32 %a, %b
950  ret i32 %1
951}
952
953define signext i32 @sext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
954; RV64I-LABEL: sext_srlw_zext_sext:
955; RV64I:       # %bb.0:
956; RV64I-NEXT:    srlw a0, a0, a1
957; RV64I-NEXT:    ret
958  %1 = lshr i32 %a, %b
959  ret i32 %1
960}
961
962define signext i32 @sext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
963; RV64I-LABEL: sext_srlw_zext_zext:
964; RV64I:       # %bb.0:
965; RV64I-NEXT:    srlw a0, a0, a1
966; RV64I-NEXT:    ret
967  %1 = lshr i32 %a, %b
968  ret i32 %1
969}
970
971define zeroext i32 @zext_srlw_aext_aext(i32 %a, i32 %b) nounwind {
972; RV64I-LABEL: zext_srlw_aext_aext:
973; RV64I:       # %bb.0:
974; RV64I-NEXT:    srlw a0, a0, a1
975; RV64I-NEXT:    slli a0, a0, 32
976; RV64I-NEXT:    srli a0, a0, 32
977; RV64I-NEXT:    ret
978  %1 = lshr i32 %a, %b
979  ret i32 %1
980}
981
982define zeroext i32 @zext_srlw_aext_sext(i32 %a, i32 signext %b) nounwind {
983; RV64I-LABEL: zext_srlw_aext_sext:
984; RV64I:       # %bb.0:
985; RV64I-NEXT:    srlw a0, a0, a1
986; RV64I-NEXT:    slli a0, a0, 32
987; RV64I-NEXT:    srli a0, a0, 32
988; RV64I-NEXT:    ret
989  %1 = lshr i32 %a, %b
990  ret i32 %1
991}
992
993define zeroext i32 @zext_srlw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
994; RV64I-LABEL: zext_srlw_aext_zext:
995; RV64I:       # %bb.0:
996; RV64I-NEXT:    srlw a0, a0, a1
997; RV64I-NEXT:    slli a0, a0, 32
998; RV64I-NEXT:    srli a0, a0, 32
999; RV64I-NEXT:    ret
1000  %1 = lshr i32 %a, %b
1001  ret i32 %1
1002}
1003
1004define zeroext i32 @zext_srlw_sext_aext(i32 signext %a, i32 %b) nounwind {
1005; RV64I-LABEL: zext_srlw_sext_aext:
1006; RV64I:       # %bb.0:
1007; RV64I-NEXT:    srlw a0, a0, a1
1008; RV64I-NEXT:    slli a0, a0, 32
1009; RV64I-NEXT:    srli a0, a0, 32
1010; RV64I-NEXT:    ret
1011  %1 = lshr i32 %a, %b
1012  ret i32 %1
1013}
1014
1015define zeroext i32 @zext_srlw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1016; RV64I-LABEL: zext_srlw_sext_sext:
1017; RV64I:       # %bb.0:
1018; RV64I-NEXT:    srlw a0, a0, a1
1019; RV64I-NEXT:    slli a0, a0, 32
1020; RV64I-NEXT:    srli a0, a0, 32
1021; RV64I-NEXT:    ret
1022  %1 = lshr i32 %a, %b
1023  ret i32 %1
1024}
1025
1026define zeroext i32 @zext_srlw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1027; RV64I-LABEL: zext_srlw_sext_zext:
1028; RV64I:       # %bb.0:
1029; RV64I-NEXT:    srlw a0, a0, a1
1030; RV64I-NEXT:    slli a0, a0, 32
1031; RV64I-NEXT:    srli a0, a0, 32
1032; RV64I-NEXT:    ret
1033  %1 = lshr i32 %a, %b
1034  ret i32 %1
1035}
1036
1037define zeroext i32 @zext_srlw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1038; RV64I-LABEL: zext_srlw_zext_aext:
1039; RV64I:       # %bb.0:
1040; RV64I-NEXT:    srlw a0, a0, a1
1041; RV64I-NEXT:    slli a0, a0, 32
1042; RV64I-NEXT:    srli a0, a0, 32
1043; RV64I-NEXT:    ret
1044  %1 = lshr i32 %a, %b
1045  ret i32 %1
1046}
1047
1048define zeroext i32 @zext_srlw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1049; RV64I-LABEL: zext_srlw_zext_sext:
1050; RV64I:       # %bb.0:
1051; RV64I-NEXT:    srlw a0, a0, a1
1052; RV64I-NEXT:    slli a0, a0, 32
1053; RV64I-NEXT:    srli a0, a0, 32
1054; RV64I-NEXT:    ret
1055  %1 = lshr i32 %a, %b
1056  ret i32 %1
1057}
1058
1059define zeroext i32 @zext_srlw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1060; RV64I-LABEL: zext_srlw_zext_zext:
1061; RV64I:       # %bb.0:
1062; RV64I-NEXT:    srlw a0, a0, a1
1063; RV64I-NEXT:    slli a0, a0, 32
1064; RV64I-NEXT:    srli a0, a0, 32
1065; RV64I-NEXT:    ret
1066  %1 = lshr i32 %a, %b
1067  ret i32 %1
1068}
1069
1070define i32 @aext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
1071; RV64I-LABEL: aext_sraw_aext_aext:
1072; RV64I:       # %bb.0:
1073; RV64I-NEXT:    sraw a0, a0, a1
1074; RV64I-NEXT:    ret
1075  %1 = ashr i32 %a, %b
1076  ret i32 %1
1077}
1078
1079define i32 @aext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
1080; RV64I-LABEL: aext_sraw_aext_sext:
1081; RV64I:       # %bb.0:
1082; RV64I-NEXT:    sraw a0, a0, a1
1083; RV64I-NEXT:    ret
1084  %1 = ashr i32 %a, %b
1085  ret i32 %1
1086}
1087
1088define i32 @aext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1089; RV64I-LABEL: aext_sraw_aext_zext:
1090; RV64I:       # %bb.0:
1091; RV64I-NEXT:    sraw a0, a0, a1
1092; RV64I-NEXT:    ret
1093  %1 = ashr i32 %a, %b
1094  ret i32 %1
1095}
1096
1097define i32 @aext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
1098; RV64I-LABEL: aext_sraw_sext_aext:
1099; RV64I:       # %bb.0:
1100; RV64I-NEXT:    sraw a0, a0, a1
1101; RV64I-NEXT:    ret
1102  %1 = ashr i32 %a, %b
1103  ret i32 %1
1104}
1105
1106define i32 @aext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1107; RV64I-LABEL: aext_sraw_sext_sext:
1108; RV64I:       # %bb.0:
1109; RV64I-NEXT:    sraw a0, a0, a1
1110; RV64I-NEXT:    ret
1111  %1 = ashr i32 %a, %b
1112  ret i32 %1
1113}
1114
1115define i32 @aext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1116; RV64I-LABEL: aext_sraw_sext_zext:
1117; RV64I:       # %bb.0:
1118; RV64I-NEXT:    sraw a0, a0, a1
1119; RV64I-NEXT:    ret
1120  %1 = ashr i32 %a, %b
1121  ret i32 %1
1122}
1123
1124define i32 @aext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1125; RV64I-LABEL: aext_sraw_zext_aext:
1126; RV64I:       # %bb.0:
1127; RV64I-NEXT:    sraw a0, a0, a1
1128; RV64I-NEXT:    ret
1129  %1 = ashr i32 %a, %b
1130  ret i32 %1
1131}
1132
1133define i32 @aext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1134; RV64I-LABEL: aext_sraw_zext_sext:
1135; RV64I:       # %bb.0:
1136; RV64I-NEXT:    sraw a0, a0, a1
1137; RV64I-NEXT:    ret
1138  %1 = ashr i32 %a, %b
1139  ret i32 %1
1140}
1141
1142define i32 @aext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1143; RV64I-LABEL: aext_sraw_zext_zext:
1144; RV64I:       # %bb.0:
1145; RV64I-NEXT:    sraw a0, a0, a1
1146; RV64I-NEXT:    ret
1147  %1 = ashr i32 %a, %b
1148  ret i32 %1
1149}
1150
1151define signext i32 @sext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
1152; RV64I-LABEL: sext_sraw_aext_aext:
1153; RV64I:       # %bb.0:
1154; RV64I-NEXT:    sraw a0, a0, a1
1155; RV64I-NEXT:    ret
1156  %1 = ashr i32 %a, %b
1157  ret i32 %1
1158}
1159
1160define signext i32 @sext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
1161; RV64I-LABEL: sext_sraw_aext_sext:
1162; RV64I:       # %bb.0:
1163; RV64I-NEXT:    sraw a0, a0, a1
1164; RV64I-NEXT:    ret
1165  %1 = ashr i32 %a, %b
1166  ret i32 %1
1167}
1168
1169define signext i32 @sext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1170; RV64I-LABEL: sext_sraw_aext_zext:
1171; RV64I:       # %bb.0:
1172; RV64I-NEXT:    sraw a0, a0, a1
1173; RV64I-NEXT:    ret
1174  %1 = ashr i32 %a, %b
1175  ret i32 %1
1176}
1177
1178define signext i32 @sext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
1179; RV64I-LABEL: sext_sraw_sext_aext:
1180; RV64I:       # %bb.0:
1181; RV64I-NEXT:    sraw a0, a0, a1
1182; RV64I-NEXT:    ret
1183  %1 = ashr i32 %a, %b
1184  ret i32 %1
1185}
1186
1187define signext i32 @sext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1188; RV64I-LABEL: sext_sraw_sext_sext:
1189; RV64I:       # %bb.0:
1190; RV64I-NEXT:    sraw a0, a0, a1
1191; RV64I-NEXT:    ret
1192  %1 = ashr i32 %a, %b
1193  ret i32 %1
1194}
1195
1196define signext i32 @sext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1197; RV64I-LABEL: sext_sraw_sext_zext:
1198; RV64I:       # %bb.0:
1199; RV64I-NEXT:    sraw a0, a0, a1
1200; RV64I-NEXT:    ret
1201  %1 = ashr i32 %a, %b
1202  ret i32 %1
1203}
1204
1205define signext i32 @sext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1206; RV64I-LABEL: sext_sraw_zext_aext:
1207; RV64I:       # %bb.0:
1208; RV64I-NEXT:    sraw a0, a0, a1
1209; RV64I-NEXT:    ret
1210  %1 = ashr i32 %a, %b
1211  ret i32 %1
1212}
1213
1214define signext i32 @sext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1215; RV64I-LABEL: sext_sraw_zext_sext:
1216; RV64I:       # %bb.0:
1217; RV64I-NEXT:    sraw a0, a0, a1
1218; RV64I-NEXT:    ret
1219  %1 = ashr i32 %a, %b
1220  ret i32 %1
1221}
1222
1223define signext i32 @sext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1224; RV64I-LABEL: sext_sraw_zext_zext:
1225; RV64I:       # %bb.0:
1226; RV64I-NEXT:    sraw a0, a0, a1
1227; RV64I-NEXT:    ret
1228  %1 = ashr i32 %a, %b
1229  ret i32 %1
1230}
1231
1232define zeroext i32 @zext_sraw_aext_aext(i32 %a, i32 %b) nounwind {
1233; RV64I-LABEL: zext_sraw_aext_aext:
1234; RV64I:       # %bb.0:
1235; RV64I-NEXT:    sraw a0, a0, a1
1236; RV64I-NEXT:    slli a0, a0, 32
1237; RV64I-NEXT:    srli a0, a0, 32
1238; RV64I-NEXT:    ret
1239  %1 = ashr i32 %a, %b
1240  ret i32 %1
1241}
1242
1243define zeroext i32 @zext_sraw_aext_sext(i32 %a, i32 signext %b) nounwind {
1244; RV64I-LABEL: zext_sraw_aext_sext:
1245; RV64I:       # %bb.0:
1246; RV64I-NEXT:    sraw a0, a0, a1
1247; RV64I-NEXT:    slli a0, a0, 32
1248; RV64I-NEXT:    srli a0, a0, 32
1249; RV64I-NEXT:    ret
1250  %1 = ashr i32 %a, %b
1251  ret i32 %1
1252}
1253
1254define zeroext i32 @zext_sraw_aext_zext(i32 %a, i32 zeroext %b) nounwind {
1255; RV64I-LABEL: zext_sraw_aext_zext:
1256; RV64I:       # %bb.0:
1257; RV64I-NEXT:    sraw a0, a0, a1
1258; RV64I-NEXT:    slli a0, a0, 32
1259; RV64I-NEXT:    srli a0, a0, 32
1260; RV64I-NEXT:    ret
1261  %1 = ashr i32 %a, %b
1262  ret i32 %1
1263}
1264
1265define zeroext i32 @zext_sraw_sext_aext(i32 signext %a, i32 %b) nounwind {
1266; RV64I-LABEL: zext_sraw_sext_aext:
1267; RV64I:       # %bb.0:
1268; RV64I-NEXT:    sraw a0, a0, a1
1269; RV64I-NEXT:    slli a0, a0, 32
1270; RV64I-NEXT:    srli a0, a0, 32
1271; RV64I-NEXT:    ret
1272  %1 = ashr i32 %a, %b
1273  ret i32 %1
1274}
1275
1276define zeroext i32 @zext_sraw_sext_sext(i32 signext %a, i32 signext %b) nounwind {
1277; RV64I-LABEL: zext_sraw_sext_sext:
1278; RV64I:       # %bb.0:
1279; RV64I-NEXT:    sraw a0, a0, a1
1280; RV64I-NEXT:    slli a0, a0, 32
1281; RV64I-NEXT:    srli a0, a0, 32
1282; RV64I-NEXT:    ret
1283  %1 = ashr i32 %a, %b
1284  ret i32 %1
1285}
1286
1287define zeroext i32 @zext_sraw_sext_zext(i32 signext %a, i32 zeroext %b) nounwind {
1288; RV64I-LABEL: zext_sraw_sext_zext:
1289; RV64I:       # %bb.0:
1290; RV64I-NEXT:    sraw a0, a0, a1
1291; RV64I-NEXT:    slli a0, a0, 32
1292; RV64I-NEXT:    srli a0, a0, 32
1293; RV64I-NEXT:    ret
1294  %1 = ashr i32 %a, %b
1295  ret i32 %1
1296}
1297
1298define zeroext i32 @zext_sraw_zext_aext(i32 zeroext %a, i32 %b) nounwind {
1299; RV64I-LABEL: zext_sraw_zext_aext:
1300; RV64I:       # %bb.0:
1301; RV64I-NEXT:    sraw a0, a0, a1
1302; RV64I-NEXT:    slli a0, a0, 32
1303; RV64I-NEXT:    srli a0, a0, 32
1304; RV64I-NEXT:    ret
1305  %1 = ashr i32 %a, %b
1306  ret i32 %1
1307}
1308
1309define zeroext i32 @zext_sraw_zext_sext(i32 zeroext %a, i32 signext %b) nounwind {
1310; RV64I-LABEL: zext_sraw_zext_sext:
1311; RV64I:       # %bb.0:
1312; RV64I-NEXT:    sraw a0, a0, a1
1313; RV64I-NEXT:    slli a0, a0, 32
1314; RV64I-NEXT:    srli a0, a0, 32
1315; RV64I-NEXT:    ret
1316  %1 = ashr i32 %a, %b
1317  ret i32 %1
1318}
1319
1320define zeroext i32 @zext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
1321; RV64I-LABEL: zext_sraw_zext_zext:
1322; RV64I:       # %bb.0:
1323; RV64I-NEXT:    sraw a0, a0, a1
1324; RV64I-NEXT:    slli a0, a0, 32
1325; RV64I-NEXT:    srli a0, a0, 32
1326; RV64I-NEXT:    ret
1327  %1 = ashr i32 %a, %b
1328  ret i32 %1
1329}
1330
1331; addiw should be selected when there is a signext result.
1332
1333define i32 @aext_addiw_aext(i32 %a) nounwind {
1334; RV64I-LABEL: aext_addiw_aext:
1335; RV64I:       # %bb.0:
1336; RV64I-NEXT:    addi a0, a0, 1
1337; RV64I-NEXT:    ret
1338  %1 = add i32 %a, 1
1339  ret i32 %1
1340}
1341
1342define i32 @aext_addiw_sext(i32 signext %a) nounwind {
1343; RV64I-LABEL: aext_addiw_sext:
1344; RV64I:       # %bb.0:
1345; RV64I-NEXT:    addi a0, a0, 2
1346; RV64I-NEXT:    ret
1347  %1 = add i32 %a, 2
1348  ret i32 %1
1349}
1350
1351define i32 @aext_addiw_zext(i32 zeroext %a) nounwind {
1352; RV64I-LABEL: aext_addiw_zext:
1353; RV64I:       # %bb.0:
1354; RV64I-NEXT:    addi a0, a0, 3
1355; RV64I-NEXT:    ret
1356  %1 = add i32 %a, 3
1357  ret i32 %1
1358}
1359
1360define signext i32 @sext_addiw_aext(i32 %a) nounwind {
1361; RV64I-LABEL: sext_addiw_aext:
1362; RV64I:       # %bb.0:
1363; RV64I-NEXT:    addiw a0, a0, 4
1364; RV64I-NEXT:    ret
1365  %1 = add i32 %a, 4
1366  ret i32 %1
1367}
1368
1369define signext i32 @sext_addiw_sext(i32 signext %a) nounwind {
1370; RV64I-LABEL: sext_addiw_sext:
1371; RV64I:       # %bb.0:
1372; RV64I-NEXT:    addiw a0, a0, 5
1373; RV64I-NEXT:    ret
1374  %1 = add i32 %a, 5
1375  ret i32 %1
1376}
1377
1378define signext i32 @sext_addiw_zext(i32 zeroext %a) nounwind {
1379; RV64I-LABEL: sext_addiw_zext:
1380; RV64I:       # %bb.0:
1381; RV64I-NEXT:    addiw a0, a0, 6
1382; RV64I-NEXT:    ret
1383  %1 = add i32 %a, 6
1384  ret i32 %1
1385}
1386
1387define zeroext i32 @zext_addiw_aext(i32 %a) nounwind {
1388; RV64I-LABEL: zext_addiw_aext:
1389; RV64I:       # %bb.0:
1390; RV64I-NEXT:    addi a0, a0, 7
1391; RV64I-NEXT:    slli a0, a0, 32
1392; RV64I-NEXT:    srli a0, a0, 32
1393; RV64I-NEXT:    ret
1394  %1 = add i32 %a, 7
1395  ret i32 %1
1396}
1397
1398define zeroext i32 @zext_addiw_sext(i32 signext %a) nounwind {
1399; RV64I-LABEL: zext_addiw_sext:
1400; RV64I:       # %bb.0:
1401; RV64I-NEXT:    addi a0, a0, 8
1402; RV64I-NEXT:    slli a0, a0, 32
1403; RV64I-NEXT:    srli a0, a0, 32
1404; RV64I-NEXT:    ret
1405  %1 = add i32 %a, 8
1406  ret i32 %1
1407}
1408
1409define zeroext i32 @zext_addiw_zext(i32 zeroext %a) nounwind {
1410; RV64I-LABEL: zext_addiw_zext:
1411; RV64I:       # %bb.0:
1412; RV64I-NEXT:    addi a0, a0, 9
1413; RV64I-NEXT:    slli a0, a0, 32
1414; RV64I-NEXT:    srli a0, a0, 32
1415; RV64I-NEXT:    ret
1416  %1 = add i32 %a, 9
1417  ret i32 %1
1418}
1419
1420; slliw should be selected whenever the return is signext.
1421
1422define i32 @aext_slliw_aext(i32 %a) nounwind {
1423; RV64I-LABEL: aext_slliw_aext:
1424; RV64I:       # %bb.0:
1425; RV64I-NEXT:    slli a0, a0, 1
1426; RV64I-NEXT:    ret
1427  %1 = shl i32 %a, 1
1428  ret i32 %1
1429}
1430
1431define i32 @aext_slliw_sext(i32 signext %a) nounwind {
1432; RV64I-LABEL: aext_slliw_sext:
1433; RV64I:       # %bb.0:
1434; RV64I-NEXT:    slli a0, a0, 2
1435; RV64I-NEXT:    ret
1436  %1 = shl i32 %a, 2
1437  ret i32 %1
1438}
1439
1440define i32 @aext_slliw_zext(i32 zeroext %a) nounwind {
1441; RV64I-LABEL: aext_slliw_zext:
1442; RV64I:       # %bb.0:
1443; RV64I-NEXT:    slli a0, a0, 3
1444; RV64I-NEXT:    ret
1445  %1 = shl i32 %a, 3
1446  ret i32 %1
1447}
1448
1449define signext i32 @sext_slliw_aext(i32 %a) nounwind {
1450; RV64I-LABEL: sext_slliw_aext:
1451; RV64I:       # %bb.0:
1452; RV64I-NEXT:    slliw a0, a0, 4
1453; RV64I-NEXT:    ret
1454  %1 = shl i32 %a, 4
1455  ret i32 %1
1456}
1457
1458define signext i32 @sext_slliw_sext(i32 signext %a) nounwind {
1459; RV64I-LABEL: sext_slliw_sext:
1460; RV64I:       # %bb.0:
1461; RV64I-NEXT:    slliw a0, a0, 5
1462; RV64I-NEXT:    ret
1463  %1 = shl i32 %a, 5
1464  ret i32 %1
1465}
1466
1467define signext i32 @sext_slliw_zext(i32 zeroext %a) nounwind {
1468; RV64I-LABEL: sext_slliw_zext:
1469; RV64I:       # %bb.0:
1470; RV64I-NEXT:    slliw a0, a0, 6
1471; RV64I-NEXT:    ret
1472  %1 = shl i32 %a, 6
1473  ret i32 %1
1474}
1475
1476; TODO: the constant shifts could be combined.
1477
1478define zeroext i32 @zext_slliw_aext(i32 %a) nounwind {
1479; RV64I-LABEL: zext_slliw_aext:
1480; RV64I:       # %bb.0:
1481; RV64I-NEXT:    slli a0, a0, 7
1482; RV64I-NEXT:    slli a0, a0, 32
1483; RV64I-NEXT:    srli a0, a0, 32
1484; RV64I-NEXT:    ret
1485  %1 = shl i32 %a, 7
1486  ret i32 %1
1487}
1488
1489define zeroext i32 @zext_slliw_sext(i32 signext %a) nounwind {
1490; RV64I-LABEL: zext_slliw_sext:
1491; RV64I:       # %bb.0:
1492; RV64I-NEXT:    slli a0, a0, 8
1493; RV64I-NEXT:    slli a0, a0, 32
1494; RV64I-NEXT:    srli a0, a0, 32
1495; RV64I-NEXT:    ret
1496  %1 = shl i32 %a, 8
1497  ret i32 %1
1498}
1499
1500define zeroext i32 @zext_slliw_zext(i32 zeroext %a) nounwind {
1501; RV64I-LABEL: zext_slliw_zext:
1502; RV64I:       # %bb.0:
1503; RV64I-NEXT:    slli a0, a0, 9
1504; RV64I-NEXT:    slli a0, a0, 32
1505; RV64I-NEXT:    srli a0, a0, 32
1506; RV64I-NEXT:    ret
1507  %1 = shl i32 %a, 9
1508  ret i32 %1
1509}
1510
1511; srliw should be selected unless the first operand is zeroext, when srli is
1512; equivalent.
1513
1514define i32 @aext_srliw_aext(i32 %a) nounwind {
1515; RV64I-LABEL: aext_srliw_aext:
1516; RV64I:       # %bb.0:
1517; RV64I-NEXT:    srliw a0, a0, 1
1518; RV64I-NEXT:    ret
1519  %1 = lshr i32 %a, 1
1520  ret i32 %1
1521}
1522
1523define i32 @aext_srliw_sext(i32 signext %a) nounwind {
1524; RV64I-LABEL: aext_srliw_sext:
1525; RV64I:       # %bb.0:
1526; RV64I-NEXT:    srliw a0, a0, 2
1527; RV64I-NEXT:    ret
1528  %1 = lshr i32 %a, 2
1529  ret i32 %1
1530}
1531
1532define i32 @aext_srliw_zext(i32 zeroext %a) nounwind {
1533; RV64I-LABEL: aext_srliw_zext:
1534; RV64I:       # %bb.0:
1535; RV64I-NEXT:    srli a0, a0, 3
1536; RV64I-NEXT:    ret
1537  %1 = lshr i32 %a, 3
1538  ret i32 %1
1539}
1540
1541define signext i32 @sext_srliw_aext(i32 %a) nounwind {
1542; RV64I-LABEL: sext_srliw_aext:
1543; RV64I:       # %bb.0:
1544; RV64I-NEXT:    srliw a0, a0, 4
1545; RV64I-NEXT:    ret
1546  %1 = lshr i32 %a, 4
1547  ret i32 %1
1548}
1549
1550define signext i32 @sext_srliw_sext(i32 signext %a) nounwind {
1551; RV64I-LABEL: sext_srliw_sext:
1552; RV64I:       # %bb.0:
1553; RV64I-NEXT:    srliw a0, a0, 5
1554; RV64I-NEXT:    ret
1555  %1 = lshr i32 %a, 5
1556  ret i32 %1
1557}
1558
1559define signext i32 @sext_srliw_zext(i32 zeroext %a) nounwind {
1560; RV64I-LABEL: sext_srliw_zext:
1561; RV64I:       # %bb.0:
1562; RV64I-NEXT:    srli a0, a0, 6
1563; RV64I-NEXT:    ret
1564  %1 = lshr i32 %a, 6
1565  ret i32 %1
1566}
1567
1568define zeroext i32 @zext_srliw_aext(i32 %a) nounwind {
1569; RV64I-LABEL: zext_srliw_aext:
1570; RV64I:       # %bb.0:
1571; RV64I-NEXT:    srliw a0, a0, 7
1572; RV64I-NEXT:    ret
1573  %1 = lshr i32 %a, 7
1574  ret i32 %1
1575}
1576
1577define zeroext i32 @zext_srliw_sext(i32 signext %a) nounwind {
1578; RV64I-LABEL: zext_srliw_sext:
1579; RV64I:       # %bb.0:
1580; RV64I-NEXT:    srliw a0, a0, 8
1581; RV64I-NEXT:    ret
1582  %1 = lshr i32 %a, 8
1583  ret i32 %1
1584}
1585
1586define zeroext i32 @zext_srliw_zext(i32 zeroext %a) nounwind {
1587; RV64I-LABEL: zext_srliw_zext:
1588; RV64I:       # %bb.0:
1589; RV64I-NEXT:    srli a0, a0, 9
1590; RV64I-NEXT:    ret
1591  %1 = lshr i32 %a, 9
1592  ret i32 %1
1593}
1594
1595; srai is equivalent to sraiw if the first operand is sign-extended.
1596
1597define i32 @aext_sraiw_aext(i32 %a) nounwind {
1598; RV64I-LABEL: aext_sraiw_aext:
1599; RV64I:       # %bb.0:
1600; RV64I-NEXT:    sraiw a0, a0, 1
1601; RV64I-NEXT:    ret
1602  %1 = ashr i32 %a, 1
1603  ret i32 %1
1604}
1605
1606define i32 @aext_sraiw_sext(i32 signext %a) nounwind {
1607; RV64I-LABEL: aext_sraiw_sext:
1608; RV64I:       # %bb.0:
1609; RV64I-NEXT:    srai a0, a0, 2
1610; RV64I-NEXT:    ret
1611  %1 = ashr i32 %a, 2
1612  ret i32 %1
1613}
1614
1615define i32 @aext_sraiw_zext(i32 zeroext %a) nounwind {
1616; RV64I-LABEL: aext_sraiw_zext:
1617; RV64I:       # %bb.0:
1618; RV64I-NEXT:    sraiw a0, a0, 3
1619; RV64I-NEXT:    ret
1620  %1 = ashr i32 %a, 3
1621  ret i32 %1
1622}
1623
1624define signext i32 @sext_sraiw_aext(i32 %a) nounwind {
1625; RV64I-LABEL: sext_sraiw_aext:
1626; RV64I:       # %bb.0:
1627; RV64I-NEXT:    sraiw a0, a0, 4
1628; RV64I-NEXT:    ret
1629  %1 = ashr i32 %a, 4
1630  ret i32 %1
1631}
1632
1633define signext i32 @sext_sraiw_sext(i32 signext %a) nounwind {
1634; RV64I-LABEL: sext_sraiw_sext:
1635; RV64I:       # %bb.0:
1636; RV64I-NEXT:    srai a0, a0, 5
1637; RV64I-NEXT:    ret
1638  %1 = ashr i32 %a, 5
1639  ret i32 %1
1640}
1641
1642define signext i32 @sext_sraiw_zext(i32 zeroext %a) nounwind {
1643; RV64I-LABEL: sext_sraiw_zext:
1644; RV64I:       # %bb.0:
1645; RV64I-NEXT:    sraiw a0, a0, 6
1646; RV64I-NEXT:    ret
1647  %1 = ashr i32 %a, 6
1648  ret i32 %1
1649}
1650
1651; TODO: sraiw could be selected rather than sext.w and srli. Alternatively,
1652; the srli could be merged in to the shifts used for zero-extension.
1653
1654define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
1655; RV64I-LABEL: zext_sraiw_aext:
1656; RV64I:       # %bb.0:
1657; RV64I-NEXT:    sext.w a0, a0
1658; RV64I-NEXT:    srli a0, a0, 7
1659; RV64I-NEXT:    slli a0, a0, 32
1660; RV64I-NEXT:    srli a0, a0, 32
1661; RV64I-NEXT:    ret
1662  %1 = ashr i32 %a, 7
1663  ret i32 %1
1664}
1665
1666define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {
1667; RV64I-LABEL: zext_sraiw_sext:
1668; RV64I:       # %bb.0:
1669; RV64I-NEXT:    srli a0, a0, 8
1670; RV64I-NEXT:    slli a0, a0, 32
1671; RV64I-NEXT:    srli a0, a0, 32
1672; RV64I-NEXT:    ret
1673  %1 = ashr i32 %a, 8
1674  ret i32 %1
1675}
1676
1677; TODO: sraiw could be selected rather than sext.w and srli. Alternatively,
1678; the srli could be merged in to the shifts used for zero-extension.
1679
1680define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
1681; RV64I-LABEL: zext_sraiw_zext:
1682; RV64I:       # %bb.0:
1683; RV64I-NEXT:    sext.w a0, a0
1684; RV64I-NEXT:    srli a0, a0, 9
1685; RV64I-NEXT:    slli a0, a0, 32
1686; RV64I-NEXT:    srli a0, a0, 32
1687; RV64I-NEXT:    ret
1688  %1 = ashr i32 %a, 9
1689  ret i32 %1
1690}
1691