1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The LiveRangeEdit class represents changes done to a virtual register when it
10 // is spilled or split.
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/CodeGen/LiveRangeEdit.h"
14 #include "llvm/ADT/Statistic.h"
15 #include "llvm/CodeGen/CalcSpillWeights.h"
16 #include "llvm/CodeGen/LiveIntervals.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/TargetInstrInfo.h"
19 #include "llvm/CodeGen/VirtRegMap.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22
23 using namespace llvm;
24
25 #define DEBUG_TYPE "regalloc"
26
27 STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
28 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
29 STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
30
anchor()31 void LiveRangeEdit::Delegate::anchor() { }
32
createEmptyIntervalFrom(Register OldReg,bool createSubRanges)33 LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(Register OldReg,
34 bool createSubRanges) {
35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
36 if (VRM)
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
38
39 LiveInterval &LI = LIS.createEmptyInterval(VReg);
40 if (Parent && !Parent->isSpillable())
41 LI.markNotSpillable();
42 if (createSubRanges) {
43 // Create empty subranges if the OldReg's interval has them. Do not create
44 // the main range here---it will be constructed later after the subranges
45 // have been finalized.
46 LiveInterval &OldLI = LIS.getInterval(OldReg);
47 VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
48 for (LiveInterval::SubRange &S : OldLI.subranges())
49 LI.createSubRange(Alloc, S.LaneMask);
50 }
51 return LI;
52 }
53
createFrom(Register OldReg)54 Register LiveRangeEdit::createFrom(Register OldReg) {
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
56 if (VRM) {
57 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
58 }
59 // FIXME: Getting the interval here actually computes it.
60 // In theory, this may not be what we want, but in practice
61 // the createEmptyIntervalFrom API is used when this is not
62 // the case. Generally speaking we just want to annotate the
63 // LiveInterval when it gets created but we cannot do that at
64 // the moment.
65 if (Parent && !Parent->isSpillable())
66 LIS.getInterval(VReg).markNotSpillable();
67 return VReg;
68 }
69
checkRematerializable(VNInfo * VNI,const MachineInstr * DefMI,AAResults * aa)70 bool LiveRangeEdit::checkRematerializable(VNInfo *VNI,
71 const MachineInstr *DefMI,
72 AAResults *aa) {
73 assert(DefMI && "Missing instruction");
74 ScannedRemattable = true;
75 if (!TII.isTriviallyReMaterializable(*DefMI, aa))
76 return false;
77 Remattable.insert(VNI);
78 return true;
79 }
80
scanRemattable(AAResults * aa)81 void LiveRangeEdit::scanRemattable(AAResults *aa) {
82 for (VNInfo *VNI : getParent().valnos) {
83 if (VNI->isUnused())
84 continue;
85 unsigned Original = VRM->getOriginal(getReg());
86 LiveInterval &OrigLI = LIS.getInterval(Original);
87 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
88 if (!OrigVNI)
89 continue;
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
91 if (!DefMI)
92 continue;
93 checkRematerializable(OrigVNI, DefMI, aa);
94 }
95 ScannedRemattable = true;
96 }
97
anyRematerializable(AAResults * aa)98 bool LiveRangeEdit::anyRematerializable(AAResults *aa) {
99 if (!ScannedRemattable)
100 scanRemattable(aa);
101 return !Remattable.empty();
102 }
103
104 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
105 /// OrigIdx are also available with the same value at UseIdx.
allUsesAvailableAt(const MachineInstr * OrigMI,SlotIndex OrigIdx,SlotIndex UseIdx) const106 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
107 SlotIndex OrigIdx,
108 SlotIndex UseIdx) const {
109 OrigIdx = OrigIdx.getRegSlot(true);
110 UseIdx = UseIdx.getRegSlot(true);
111 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
112 const MachineOperand &MO = OrigMI->getOperand(i);
113 if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
114 continue;
115
116 // We can't remat physreg uses, unless it is a constant.
117 if (Register::isPhysicalRegister(MO.getReg())) {
118 if (MRI.isConstantPhysReg(MO.getReg()))
119 continue;
120 return false;
121 }
122
123 LiveInterval &li = LIS.getInterval(MO.getReg());
124 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
125 if (!OVNI)
126 continue;
127
128 // Don't allow rematerialization immediately after the original def.
129 // It would be incorrect if OrigMI redefines the register.
130 // See PR14098.
131 if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
132 return false;
133
134 if (OVNI != li.getVNInfoAt(UseIdx))
135 return false;
136 }
137 return true;
138 }
139
canRematerializeAt(Remat & RM,VNInfo * OrigVNI,SlotIndex UseIdx,bool cheapAsAMove)140 bool LiveRangeEdit::canRematerializeAt(Remat &RM, VNInfo *OrigVNI,
141 SlotIndex UseIdx, bool cheapAsAMove) {
142 assert(ScannedRemattable && "Call anyRematerializable first");
143
144 // Use scanRemattable info.
145 if (!Remattable.count(OrigVNI))
146 return false;
147
148 // No defining instruction provided.
149 SlotIndex DefIdx;
150 assert(RM.OrigMI && "No defining instruction for remattable value");
151 DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
152
153 // If only cheap remats were requested, bail out early.
154 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
155 return false;
156
157 // Verify that all used registers are available with the same values.
158 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
159 return false;
160
161 return true;
162 }
163
rematerializeAt(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,const Remat & RM,const TargetRegisterInfo & tri,bool Late)164 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
165 MachineBasicBlock::iterator MI,
166 unsigned DestReg,
167 const Remat &RM,
168 const TargetRegisterInfo &tri,
169 bool Late) {
170 assert(RM.OrigMI && "Invalid remat");
171 TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
172 // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
173 // to false anyway in case the isDead flag of RM.OrigMI's dest register
174 // is true.
175 (*--MI).getOperand(0).setIsDead(false);
176 Rematted.insert(RM.ParentVNI);
177 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
178 }
179
eraseVirtReg(Register Reg)180 void LiveRangeEdit::eraseVirtReg(Register Reg) {
181 if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
182 LIS.removeInterval(Reg);
183 }
184
foldAsLoad(LiveInterval * LI,SmallVectorImpl<MachineInstr * > & Dead)185 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
186 SmallVectorImpl<MachineInstr*> &Dead) {
187 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
188
189 // Check that there is a single def and a single use.
190 for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg())) {
191 MachineInstr *MI = MO.getParent();
192 if (MO.isDef()) {
193 if (DefMI && DefMI != MI)
194 return false;
195 if (!MI->canFoldAsLoad())
196 return false;
197 DefMI = MI;
198 } else if (!MO.isUndef()) {
199 if (UseMI && UseMI != MI)
200 return false;
201 // FIXME: Targets don't know how to fold subreg uses.
202 if (MO.getSubReg())
203 return false;
204 UseMI = MI;
205 }
206 }
207 if (!DefMI || !UseMI)
208 return false;
209
210 // Since we're moving the DefMI load, make sure we're not extending any live
211 // ranges.
212 if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
213 LIS.getInstructionIndex(*UseMI)))
214 return false;
215
216 // We also need to make sure it is safe to move the load.
217 // Assume there are stores between DefMI and UseMI.
218 bool SawStore = true;
219 if (!DefMI->isSafeToMove(nullptr, SawStore))
220 return false;
221
222 LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
223 << " into single use: " << *UseMI);
224
225 SmallVector<unsigned, 8> Ops;
226 if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second)
227 return false;
228
229 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
230 if (!FoldMI)
231 return false;
232 LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
233 LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
234 // Update the call site info.
235 if (UseMI->shouldUpdateCallSiteInfo())
236 UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI);
237 UseMI->eraseFromParent();
238 DefMI->addRegisterDead(LI->reg(), nullptr);
239 Dead.push_back(DefMI);
240 ++NumDCEFoldedLoads;
241 return true;
242 }
243
useIsKill(const LiveInterval & LI,const MachineOperand & MO) const244 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
245 const MachineOperand &MO) const {
246 const MachineInstr &MI = *MO.getParent();
247 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
248 if (LI.Query(Idx).isKill())
249 return true;
250 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
251 unsigned SubReg = MO.getSubReg();
252 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
253 for (const LiveInterval::SubRange &S : LI.subranges()) {
254 if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
255 return true;
256 }
257 return false;
258 }
259
260 /// Find all live intervals that need to shrink, then remove the instruction.
eliminateDeadDef(MachineInstr * MI,ToShrinkSet & ToShrink,AAResults * AA)261 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
262 AAResults *AA) {
263 assert(MI->allDefsAreDead() && "Def isn't really dead");
264 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
265
266 // Never delete a bundled instruction.
267 if (MI->isBundled()) {
268 return;
269 }
270 // Never delete inline asm.
271 if (MI->isInlineAsm()) {
272 LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
273 return;
274 }
275
276 // Use the same criteria as DeadMachineInstructionElim.
277 bool SawStore = false;
278 if (!MI->isSafeToMove(nullptr, SawStore)) {
279 LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
280 return;
281 }
282
283 LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
284
285 // Collect virtual registers to be erased after MI is gone.
286 SmallVector<unsigned, 8> RegsToErase;
287 bool ReadsPhysRegs = false;
288 bool isOrigDef = false;
289 unsigned Dest;
290 // Only optimize rematerialize case when the instruction has one def, since
291 // otherwise we could leave some dead defs in the code. This case is
292 // extremely rare.
293 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
294 MI->getDesc().getNumDefs() == 1) {
295 Dest = MI->getOperand(0).getReg();
296 unsigned Original = VRM->getOriginal(Dest);
297 LiveInterval &OrigLI = LIS.getInterval(Original);
298 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
299 // The original live-range may have been shrunk to
300 // an empty live-range. It happens when it is dead, but
301 // we still keep it around to be able to rematerialize
302 // other values that depend on it.
303 if (OrigVNI)
304 isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
305 }
306
307 // Check for live intervals that may shrink
308 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
309 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
310 if (!MOI->isReg())
311 continue;
312 Register Reg = MOI->getReg();
313 if (!Register::isVirtualRegister(Reg)) {
314 // Check if MI reads any unreserved physregs.
315 if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
316 ReadsPhysRegs = true;
317 else if (MOI->isDef())
318 LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
319 continue;
320 }
321 LiveInterval &LI = LIS.getInterval(Reg);
322
323 // Shrink read registers, unless it is likely to be expensive and
324 // unlikely to change anything. We typically don't want to shrink the
325 // PIC base register that has lots of uses everywhere.
326 // Always shrink COPY uses that probably come from live range splitting.
327 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
328 (MOI->readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
329 ToShrink.insert(&LI);
330
331 // Remove defined value.
332 if (MOI->isDef()) {
333 if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
334 TheDelegate->LRE_WillShrinkVirtReg(LI.reg());
335 LIS.removeVRegDefAt(LI, Idx);
336 if (LI.empty())
337 RegsToErase.push_back(Reg);
338 }
339 }
340
341 // Currently, we don't support DCE of physreg live ranges. If MI reads
342 // any unreserved physregs, don't erase the instruction, but turn it into
343 // a KILL instead. This way, the physreg live ranges don't end up
344 // dangling.
345 // FIXME: It would be better to have something like shrinkToUses() for
346 // physregs. That could potentially enable more DCE and it would free up
347 // the physreg. It would not happen often, though.
348 if (ReadsPhysRegs) {
349 MI->setDesc(TII.get(TargetOpcode::KILL));
350 // Remove all operands that aren't physregs.
351 for (unsigned i = MI->getNumOperands(); i; --i) {
352 const MachineOperand &MO = MI->getOperand(i-1);
353 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
354 continue;
355 MI->RemoveOperand(i-1);
356 }
357 LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
358 } else {
359 // If the dest of MI is an original reg and MI is reMaterializable,
360 // don't delete the inst. Replace the dest with a new reg, and keep
361 // the inst for remat of other siblings. The inst is saved in
362 // LiveRangeEdit::DeadRemats and will be deleted after all the
363 // allocations of the func are done.
364 if (isOrigDef && DeadRemats && TII.isTriviallyReMaterializable(*MI, AA)) {
365 LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
366 VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
367 NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
368 pop_back();
369 DeadRemats->insert(MI);
370 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
371 MI->substituteRegister(Dest, NewLI.reg(), 0, TRI);
372 MI->getOperand(0).setIsDead(true);
373 } else {
374 if (TheDelegate)
375 TheDelegate->LRE_WillEraseInstruction(MI);
376 LIS.RemoveMachineInstrFromMaps(*MI);
377 MI->eraseFromParent();
378 ++NumDCEDeleted;
379 }
380 }
381
382 // Erase any virtregs that are now empty and unused. There may be <undef>
383 // uses around. Keep the empty live range in that case.
384 for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
385 Register Reg = RegsToErase[i];
386 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
387 ToShrink.remove(&LIS.getInterval(Reg));
388 eraseVirtReg(Reg);
389 }
390 }
391 }
392
eliminateDeadDefs(SmallVectorImpl<MachineInstr * > & Dead,ArrayRef<Register> RegsBeingSpilled,AAResults * AA)393 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,
394 ArrayRef<Register> RegsBeingSpilled,
395 AAResults *AA) {
396 ToShrinkSet ToShrink;
397
398 for (;;) {
399 // Erase all dead defs.
400 while (!Dead.empty())
401 eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA);
402
403 if (ToShrink.empty())
404 break;
405
406 // Shrink just one live interval. Then delete new dead defs.
407 LiveInterval *LI = ToShrink.back();
408 ToShrink.pop_back();
409 if (foldAsLoad(LI, Dead))
410 continue;
411 unsigned VReg = LI->reg();
412 if (TheDelegate)
413 TheDelegate->LRE_WillShrinkVirtReg(VReg);
414 if (!LIS.shrinkToUses(LI, &Dead))
415 continue;
416
417 // Don't create new intervals for a register being spilled.
418 // The new intervals would have to be spilled anyway so its not worth it.
419 // Also they currently aren't spilled so creating them and not spilling
420 // them results in incorrect code.
421 bool BeingSpilled = false;
422 for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
423 if (VReg == RegsBeingSpilled[i]) {
424 BeingSpilled = true;
425 break;
426 }
427 }
428
429 if (BeingSpilled) continue;
430
431 // LI may have been separated, create new intervals.
432 LI->RenumberValues();
433 SmallVector<LiveInterval*, 8> SplitLIs;
434 LIS.splitSeparateComponents(*LI, SplitLIs);
435 if (!SplitLIs.empty())
436 ++NumFracRanges;
437
438 Register Original = VRM ? VRM->getOriginal(VReg) : Register();
439 for (const LiveInterval *SplitLI : SplitLIs) {
440 // If LI is an original interval that hasn't been split yet, make the new
441 // intervals their own originals instead of referring to LI. The original
442 // interval must contain all the split products, and LI doesn't.
443 if (Original != VReg && Original != 0)
444 VRM->setIsSplitFromReg(SplitLI->reg(), Original);
445 if (TheDelegate)
446 TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg(), VReg);
447 }
448 }
449 }
450
451 // Keep track of new virtual registers created via
452 // MachineRegisterInfo::createVirtualRegister.
453 void
MRI_NoteNewVirtualRegister(Register VReg)454 LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) {
455 if (VRM)
456 VRM->grow();
457
458 NewRegs.push_back(VReg);
459 }
460
461 void
calculateRegClassAndHint(MachineFunction & MF,const MachineLoopInfo & Loops,const MachineBlockFrequencyInfo & MBFI)462 LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
463 const MachineLoopInfo &Loops,
464 const MachineBlockFrequencyInfo &MBFI) {
465 VirtRegAuxInfo VRAI(MF, LIS, *VRM, Loops, MBFI);
466 for (unsigned I = 0, Size = size(); I < Size; ++I) {
467 LiveInterval &LI = LIS.getInterval(get(I));
468 if (MRI.recomputeRegClass(LI.reg()))
469 LLVM_DEBUG({
470 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
471 dbgs() << "Inflated " << printReg(LI.reg()) << " to "
472 << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n';
473 });
474 VRAI.calculateSpillWeightAndHint(LI);
475 }
476 }
477