1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetRegisterInfo interface.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/CodeGen/TargetRegisterInfo.h"
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/LiveInterval.h"
23 #include "llvm/CodeGen/TargetFrameLowering.h"
24 #include "llvm/CodeGen/TargetInstrInfo.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/CodeGen/VirtRegMap.h"
27 #include "llvm/Config/llvm-config.h"
28 #include "llvm/IR/Attributes.h"
29 #include "llvm/IR/DebugInfoMetadata.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/MC/MCRegisterInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MachineValueType.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Printable.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include <cassert>
40 #include <utility>
41
42 #define DEBUG_TYPE "target-reg-info"
43
44 using namespace llvm;
45
46 static cl::opt<unsigned>
47 HugeSizeForSplit("huge-size-for-split", cl::Hidden,
48 cl::desc("A threshold of live range size which may cause "
49 "high compile time cost in global splitting."),
50 cl::init(5000));
51
TargetRegisterInfo(const TargetRegisterInfoDesc * ID,regclass_iterator RCB,regclass_iterator RCE,const char * const * SRINames,const LaneBitmask * SRILaneMasks,LaneBitmask SRICoveringLanes,const RegClassInfo * const RCIs,unsigned Mode)52 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
53 regclass_iterator RCB, regclass_iterator RCE,
54 const char *const *SRINames,
55 const LaneBitmask *SRILaneMasks,
56 LaneBitmask SRICoveringLanes,
57 const RegClassInfo *const RCIs,
58 unsigned Mode)
59 : InfoDesc(ID), SubRegIndexNames(SRINames),
60 SubRegIndexLaneMasks(SRILaneMasks),
61 RegClassBegin(RCB), RegClassEnd(RCE),
62 CoveringLanes(SRICoveringLanes),
63 RCInfos(RCIs), HwMode(Mode) {
64 }
65
66 TargetRegisterInfo::~TargetRegisterInfo() = default;
67
shouldRegionSplitForVirtReg(const MachineFunction & MF,const LiveInterval & VirtReg) const68 bool TargetRegisterInfo::shouldRegionSplitForVirtReg(
69 const MachineFunction &MF, const LiveInterval &VirtReg) const {
70 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
71 const MachineRegisterInfo &MRI = MF.getRegInfo();
72 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
73 if (MI && TII->isTriviallyReMaterializable(*MI) &&
74 VirtReg.size() > HugeSizeForSplit)
75 return false;
76 return true;
77 }
78
markSuperRegs(BitVector & RegisterSet,MCRegister Reg) const79 void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,
80 MCRegister Reg) const {
81 for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
82 RegisterSet.set(*AI);
83 }
84
checkAllSuperRegsMarked(const BitVector & RegisterSet,ArrayRef<MCPhysReg> Exceptions) const85 bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
86 ArrayRef<MCPhysReg> Exceptions) const {
87 // Check that all super registers of reserved regs are reserved as well.
88 BitVector Checked(getNumRegs());
89 for (unsigned Reg : RegisterSet.set_bits()) {
90 if (Checked[Reg])
91 continue;
92 for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
93 if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
94 dbgs() << "Error: Super register " << printReg(*SR, this)
95 << " of reserved register " << printReg(Reg, this)
96 << " is not reserved.\n";
97 return false;
98 }
99
100 // We transitively check superregs. So we can remember this for later
101 // to avoid compiletime explosion in deep register hierarchies.
102 Checked.set(*SR);
103 }
104 }
105 return true;
106 }
107
108 namespace llvm {
109
printReg(Register Reg,const TargetRegisterInfo * TRI,unsigned SubIdx,const MachineRegisterInfo * MRI)110 Printable printReg(Register Reg, const TargetRegisterInfo *TRI,
111 unsigned SubIdx, const MachineRegisterInfo *MRI) {
112 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
113 if (!Reg)
114 OS << "$noreg";
115 else if (Register::isStackSlot(Reg))
116 OS << "SS#" << Register::stackSlot2Index(Reg);
117 else if (Register::isVirtualRegister(Reg)) {
118 StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
119 if (Name != "") {
120 OS << '%' << Name;
121 } else {
122 OS << '%' << Register::virtReg2Index(Reg);
123 }
124 } else if (!TRI)
125 OS << '$' << "physreg" << Reg;
126 else if (Reg < TRI->getNumRegs()) {
127 OS << '$';
128 printLowerCase(TRI->getName(Reg), OS);
129 } else
130 llvm_unreachable("Register kind is unsupported.");
131
132 if (SubIdx) {
133 if (TRI)
134 OS << ':' << TRI->getSubRegIndexName(SubIdx);
135 else
136 OS << ":sub(" << SubIdx << ')';
137 }
138 });
139 }
140
printRegUnit(unsigned Unit,const TargetRegisterInfo * TRI)141 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
142 return Printable([Unit, TRI](raw_ostream &OS) {
143 // Generic printout when TRI is missing.
144 if (!TRI) {
145 OS << "Unit~" << Unit;
146 return;
147 }
148
149 // Check for invalid register units.
150 if (Unit >= TRI->getNumRegUnits()) {
151 OS << "BadUnit~" << Unit;
152 return;
153 }
154
155 // Normal units have at least one root.
156 MCRegUnitRootIterator Roots(Unit, TRI);
157 assert(Roots.isValid() && "Unit has no roots.");
158 OS << TRI->getName(*Roots);
159 for (++Roots; Roots.isValid(); ++Roots)
160 OS << '~' << TRI->getName(*Roots);
161 });
162 }
163
printVRegOrUnit(unsigned Unit,const TargetRegisterInfo * TRI)164 Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
165 return Printable([Unit, TRI](raw_ostream &OS) {
166 if (Register::isVirtualRegister(Unit)) {
167 OS << '%' << Register::virtReg2Index(Unit);
168 } else {
169 OS << printRegUnit(Unit, TRI);
170 }
171 });
172 }
173
printRegClassOrBank(Register Reg,const MachineRegisterInfo & RegInfo,const TargetRegisterInfo * TRI)174 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
175 const TargetRegisterInfo *TRI) {
176 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
177 if (RegInfo.getRegClassOrNull(Reg))
178 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
179 else if (RegInfo.getRegBankOrNull(Reg))
180 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
181 else {
182 OS << "_";
183 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
184 "Generic registers must have a valid type");
185 }
186 });
187 }
188
189 } // end namespace llvm
190
191 /// getAllocatableClass - Return the maximal subclass of the given register
192 /// class that is alloctable, or NULL.
193 const TargetRegisterClass *
getAllocatableClass(const TargetRegisterClass * RC) const194 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
195 if (!RC || RC->isAllocatable())
196 return RC;
197
198 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
199 ++It) {
200 const TargetRegisterClass *SubRC = getRegClass(It.getID());
201 if (SubRC->isAllocatable())
202 return SubRC;
203 }
204 return nullptr;
205 }
206
207 /// getMinimalPhysRegClass - Returns the Register Class of a physical
208 /// register of the given type, picking the most sub register class of
209 /// the right type that contains this physreg.
210 const TargetRegisterClass *
getMinimalPhysRegClass(MCRegister reg,MVT VT) const211 TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const {
212 assert(Register::isPhysicalRegister(reg) &&
213 "reg must be a physical register");
214
215 // Pick the most sub register class of the right type that contains
216 // this physreg.
217 const TargetRegisterClass* BestRC = nullptr;
218 for (const TargetRegisterClass* RC : regclasses()) {
219 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
220 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
221 BestRC = RC;
222 }
223
224 assert(BestRC && "Couldn't find the register class");
225 return BestRC;
226 }
227
228 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
229 /// registers for the specific register class.
getAllocatableSetForRC(const MachineFunction & MF,const TargetRegisterClass * RC,BitVector & R)230 static void getAllocatableSetForRC(const MachineFunction &MF,
231 const TargetRegisterClass *RC, BitVector &R){
232 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
233 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
234 for (unsigned i = 0; i != Order.size(); ++i)
235 R.set(Order[i]);
236 }
237
getAllocatableSet(const MachineFunction & MF,const TargetRegisterClass * RC) const238 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
239 const TargetRegisterClass *RC) const {
240 BitVector Allocatable(getNumRegs());
241 if (RC) {
242 // A register class with no allocatable subclass returns an empty set.
243 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
244 if (SubClass)
245 getAllocatableSetForRC(MF, SubClass, Allocatable);
246 } else {
247 for (const TargetRegisterClass *C : regclasses())
248 if (C->isAllocatable())
249 getAllocatableSetForRC(MF, C, Allocatable);
250 }
251
252 // Mask out the reserved registers
253 BitVector Reserved = getReservedRegs(MF);
254 Allocatable &= Reserved.flip();
255
256 return Allocatable;
257 }
258
259 static inline
firstCommonClass(const uint32_t * A,const uint32_t * B,const TargetRegisterInfo * TRI)260 const TargetRegisterClass *firstCommonClass(const uint32_t *A,
261 const uint32_t *B,
262 const TargetRegisterInfo *TRI) {
263 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
264 if (unsigned Common = *A++ & *B++)
265 return TRI->getRegClass(I + countTrailingZeros(Common));
266 return nullptr;
267 }
268
269 const TargetRegisterClass *
getCommonSubClass(const TargetRegisterClass * A,const TargetRegisterClass * B) const270 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
271 const TargetRegisterClass *B) const {
272 // First take care of the trivial cases.
273 if (A == B)
274 return A;
275 if (!A || !B)
276 return nullptr;
277
278 // Register classes are ordered topologically, so the largest common
279 // sub-class it the common sub-class with the smallest ID.
280 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
281 }
282
283 const TargetRegisterClass *
getMatchingSuperRegClass(const TargetRegisterClass * A,const TargetRegisterClass * B,unsigned Idx) const284 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
285 const TargetRegisterClass *B,
286 unsigned Idx) const {
287 assert(A && B && "Missing register class");
288 assert(Idx && "Bad sub-register index");
289
290 // Find Idx in the list of super-register indices.
291 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
292 if (RCI.getSubReg() == Idx)
293 // The bit mask contains all register classes that are projected into B
294 // by Idx. Find a class that is also a sub-class of A.
295 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
296 return nullptr;
297 }
298
299 const TargetRegisterClass *TargetRegisterInfo::
getCommonSuperRegClass(const TargetRegisterClass * RCA,unsigned SubA,const TargetRegisterClass * RCB,unsigned SubB,unsigned & PreA,unsigned & PreB) const300 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
301 const TargetRegisterClass *RCB, unsigned SubB,
302 unsigned &PreA, unsigned &PreB) const {
303 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
304
305 // Search all pairs of sub-register indices that project into RCA and RCB
306 // respectively. This is quadratic, but usually the sets are very small. On
307 // most targets like X86, there will only be a single sub-register index
308 // (e.g., sub_16bit projecting into GR16).
309 //
310 // The worst case is a register class like DPR on ARM.
311 // We have indices dsub_0..dsub_7 projecting into that class.
312 //
313 // It is very common that one register class is a sub-register of the other.
314 // Arrange for RCA to be the larger register so the answer will be found in
315 // the first iteration. This makes the search linear for the most common
316 // case.
317 const TargetRegisterClass *BestRC = nullptr;
318 unsigned *BestPreA = &PreA;
319 unsigned *BestPreB = &PreB;
320 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
321 std::swap(RCA, RCB);
322 std::swap(SubA, SubB);
323 std::swap(BestPreA, BestPreB);
324 }
325
326 // Also terminate the search one we have found a register class as small as
327 // RCA.
328 unsigned MinSize = getRegSizeInBits(*RCA);
329
330 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
331 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
332 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
333 // Check if a common super-register class exists for this index pair.
334 const TargetRegisterClass *RC =
335 firstCommonClass(IA.getMask(), IB.getMask(), this);
336 if (!RC || getRegSizeInBits(*RC) < MinSize)
337 continue;
338
339 // The indexes must compose identically: PreA+SubA == PreB+SubB.
340 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
341 if (FinalA != FinalB)
342 continue;
343
344 // Is RC a better candidate than BestRC?
345 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
346 continue;
347
348 // Yes, RC is the smallest super-register seen so far.
349 BestRC = RC;
350 *BestPreA = IA.getSubReg();
351 *BestPreB = IB.getSubReg();
352
353 // Bail early if we reached MinSize. We won't find a better candidate.
354 if (getRegSizeInBits(*BestRC) == MinSize)
355 return BestRC;
356 }
357 }
358 return BestRC;
359 }
360
361 /// Check if the registers defined by the pair (RegisterClass, SubReg)
362 /// share the same register file.
shareSameRegisterFile(const TargetRegisterInfo & TRI,const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg)363 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
364 const TargetRegisterClass *DefRC,
365 unsigned DefSubReg,
366 const TargetRegisterClass *SrcRC,
367 unsigned SrcSubReg) {
368 // Same register class.
369 if (DefRC == SrcRC)
370 return true;
371
372 // Both operands are sub registers. Check if they share a register class.
373 unsigned SrcIdx, DefIdx;
374 if (SrcSubReg && DefSubReg) {
375 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
376 SrcIdx, DefIdx) != nullptr;
377 }
378
379 // At most one of the register is a sub register, make it Src to avoid
380 // duplicating the test.
381 if (!SrcSubReg) {
382 std::swap(DefSubReg, SrcSubReg);
383 std::swap(DefRC, SrcRC);
384 }
385
386 // One of the register is a sub register, check if we can get a superclass.
387 if (SrcSubReg)
388 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
389
390 // Plain copy.
391 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
392 }
393
shouldRewriteCopySrc(const TargetRegisterClass * DefRC,unsigned DefSubReg,const TargetRegisterClass * SrcRC,unsigned SrcSubReg) const394 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
395 unsigned DefSubReg,
396 const TargetRegisterClass *SrcRC,
397 unsigned SrcSubReg) const {
398 // If this source does not incur a cross register bank copy, use it.
399 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
400 }
401
402 // Compute target-independent register allocator hints to help eliminate copies.
getRegAllocationHints(Register VirtReg,ArrayRef<MCPhysReg> Order,SmallVectorImpl<MCPhysReg> & Hints,const MachineFunction & MF,const VirtRegMap * VRM,const LiveRegMatrix * Matrix) const403 bool TargetRegisterInfo::getRegAllocationHints(
404 Register VirtReg, ArrayRef<MCPhysReg> Order,
405 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
406 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
407 const MachineRegisterInfo &MRI = MF.getRegInfo();
408 const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI =
409 MRI.getRegAllocationHints(VirtReg);
410
411 SmallSet<Register, 32> HintedRegs;
412 // First hint may be a target hint.
413 bool Skip = (Hints_MRI.first != 0);
414 for (auto Reg : Hints_MRI.second) {
415 if (Skip) {
416 Skip = false;
417 continue;
418 }
419
420 // Target-independent hints are either a physical or a virtual register.
421 Register Phys = Reg;
422 if (VRM && Phys.isVirtual())
423 Phys = VRM->getPhys(Phys);
424
425 // Don't add the same reg twice (Hints_MRI may contain multiple virtual
426 // registers allocated to the same physreg).
427 if (!HintedRegs.insert(Phys).second)
428 continue;
429 // Check that Phys is a valid hint in VirtReg's register class.
430 if (!Phys.isPhysical())
431 continue;
432 if (MRI.isReserved(Phys))
433 continue;
434 // Check that Phys is in the allocation order. We shouldn't heed hints
435 // from VirtReg's register class if they aren't in the allocation order. The
436 // target probably has a reason for removing the register.
437 if (!is_contained(Order, Phys))
438 continue;
439
440 // All clear, tell the register allocator to prefer this register.
441 Hints.push_back(Phys);
442 }
443 return false;
444 }
445
isCalleeSavedPhysReg(MCRegister PhysReg,const MachineFunction & MF) const446 bool TargetRegisterInfo::isCalleeSavedPhysReg(
447 MCRegister PhysReg, const MachineFunction &MF) const {
448 if (PhysReg == 0)
449 return false;
450 const uint32_t *callerPreservedRegs =
451 getCallPreservedMask(MF, MF.getFunction().getCallingConv());
452 if (callerPreservedRegs) {
453 assert(Register::isPhysicalRegister(PhysReg) &&
454 "Expected physical register");
455 return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
456 }
457 return false;
458 }
459
canRealignStack(const MachineFunction & MF) const460 bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
461 return !MF.getFunction().hasFnAttribute("no-realign-stack");
462 }
463
needsStackRealignment(const MachineFunction & MF) const464 bool TargetRegisterInfo::needsStackRealignment(
465 const MachineFunction &MF) const {
466 const MachineFrameInfo &MFI = MF.getFrameInfo();
467 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
468 const Function &F = MF.getFunction();
469 Align StackAlign = TFI->getStackAlign();
470 bool requiresRealignment = ((MFI.getMaxAlign() > StackAlign) ||
471 F.hasFnAttribute(Attribute::StackAlignment));
472 if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
473 if (canRealignStack(MF))
474 return true;
475 LLVM_DEBUG(dbgs() << "Can't realign function's stack: " << F.getName()
476 << "\n");
477 }
478 return false;
479 }
480
regmaskSubsetEqual(const uint32_t * mask0,const uint32_t * mask1) const481 bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
482 const uint32_t *mask1) const {
483 unsigned N = (getNumRegs()+31) / 32;
484 for (unsigned I = 0; I < N; ++I)
485 if ((mask0[I] & mask1[I]) != mask0[I])
486 return false;
487 return true;
488 }
489
490 unsigned
getRegSizeInBits(Register Reg,const MachineRegisterInfo & MRI) const491 TargetRegisterInfo::getRegSizeInBits(Register Reg,
492 const MachineRegisterInfo &MRI) const {
493 const TargetRegisterClass *RC{};
494 if (Reg.isPhysical()) {
495 // The size is not directly available for physical registers.
496 // Instead, we need to access a register class that contains Reg and
497 // get the size of that register class.
498 RC = getMinimalPhysRegClass(Reg);
499 } else {
500 LLT Ty = MRI.getType(Reg);
501 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
502 // If Reg is not a generic register, query the register class to
503 // get its size.
504 if (RegSize)
505 return RegSize;
506 // Since Reg is not a generic register, it must have a register class.
507 RC = MRI.getRegClass(Reg);
508 }
509 assert(RC && "Unable to deduce the register class");
510 return getRegSizeInBits(*RC);
511 }
512
513 Register
lookThruCopyLike(Register SrcReg,const MachineRegisterInfo * MRI) const514 TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
515 const MachineRegisterInfo *MRI) const {
516 while (true) {
517 const MachineInstr *MI = MRI->getVRegDef(SrcReg);
518 if (!MI->isCopyLike())
519 return SrcReg;
520
521 Register CopySrcReg;
522 if (MI->isCopy())
523 CopySrcReg = MI->getOperand(1).getReg();
524 else {
525 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
526 CopySrcReg = MI->getOperand(2).getReg();
527 }
528
529 if (!CopySrcReg.isVirtual())
530 return CopySrcReg;
531
532 SrcReg = CopySrcReg;
533 }
534 }
535
lookThruSingleUseCopyChain(Register SrcReg,const MachineRegisterInfo * MRI) const536 Register TargetRegisterInfo::lookThruSingleUseCopyChain(
537 Register SrcReg, const MachineRegisterInfo *MRI) const {
538 while (true) {
539 const MachineInstr *MI = MRI->getVRegDef(SrcReg);
540 // Found the real definition, return it if it has a single use.
541 if (!MI->isCopyLike())
542 return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();
543
544 Register CopySrcReg;
545 if (MI->isCopy())
546 CopySrcReg = MI->getOperand(1).getReg();
547 else {
548 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
549 CopySrcReg = MI->getOperand(2).getReg();
550 }
551
552 // Continue only if the next definition in the chain is for a virtual
553 // register that has a single use.
554 if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(CopySrcReg))
555 return Register();
556
557 SrcReg = CopySrcReg;
558 }
559 }
560
getOffsetOpcodes(const StackOffset & Offset,SmallVectorImpl<uint64_t> & Ops) const561 void TargetRegisterInfo::getOffsetOpcodes(
562 const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
563 assert(!Offset.getScalable() && "Scalable offsets are not handled");
564 DIExpression::appendOffset(Ops, Offset.getFixed());
565 }
566
567 DIExpression *
prependOffsetExpression(const DIExpression * Expr,unsigned PrependFlags,const StackOffset & Offset) const568 TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,
569 unsigned PrependFlags,
570 const StackOffset &Offset) const {
571 assert((PrependFlags &
572 ~(DIExpression::DerefBefore | DIExpression::DerefAfter |
573 DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&
574 "Unsupported prepend flag");
575 SmallVector<uint64_t, 16> OffsetExpr;
576 if (PrependFlags & DIExpression::DerefBefore)
577 OffsetExpr.push_back(dwarf::DW_OP_deref);
578 getOffsetOpcodes(Offset, OffsetExpr);
579 if (PrependFlags & DIExpression::DerefAfter)
580 OffsetExpr.push_back(dwarf::DW_OP_deref);
581 return DIExpression::prependOpcodes(Expr, OffsetExpr,
582 PrependFlags & DIExpression::StackValue,
583 PrependFlags & DIExpression::EntryValue);
584 }
585
586 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
587 LLVM_DUMP_METHOD
dumpReg(Register Reg,unsigned SubRegIndex,const TargetRegisterInfo * TRI)588 void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
589 const TargetRegisterInfo *TRI) {
590 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
591 }
592 #endif
593