1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 // Index into the OpcodesForSpill array. 114 enum SpillOpcodeKey { 115 SOK_Int4Spill, 116 SOK_Int8Spill, 117 SOK_Float8Spill, 118 SOK_Float4Spill, 119 SOK_CRSpill, 120 SOK_CRBitSpill, 121 SOK_VRVectorSpill, 122 SOK_VSXVectorSpill, 123 SOK_VectorFloat8Spill, 124 SOK_VectorFloat4Spill, 125 SOK_SpillToVSR, 126 SOK_PairedVecSpill, 127 SOK_AccumulatorSpill, 128 SOK_UAccumulatorSpill, 129 SOK_SPESpill, 130 SOK_LastOpcodeSpill // This must be last on the enum. 131 }; 132 133 // Define list of load and store spill opcodes. 134 #define NoInstr PPC::INSTRUCTION_LIST_END 135 #define Pwr8LoadOpcodes \ 136 { \ 137 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 138 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 139 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, PPC::EVLDD \ 140 } 141 142 #define Pwr9LoadOpcodes \ 143 { \ 144 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 145 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 146 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, NoInstr \ 147 } 148 149 #define Pwr10LoadOpcodes \ 150 { \ 151 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 152 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 153 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \ 154 PPC::RESTORE_UACC, NoInstr \ 155 } 156 157 #define Pwr8StoreOpcodes \ 158 { \ 159 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 160 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \ 161 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, PPC::EVSTDD \ 162 } 163 164 #define Pwr9StoreOpcodes \ 165 { \ 166 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 167 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 168 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr \ 169 } 170 171 #define Pwr10StoreOpcodes \ 172 { \ 173 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 174 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 175 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \ 176 NoInstr \ 177 } 178 179 // Initialize arrays for load and store spill opcodes on supported subtargets. 180 #define StoreOpcodesForSpill \ 181 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes } 182 #define LoadOpcodesForSpill \ 183 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes } 184 185 class PPCSubtarget; 186 class PPCInstrInfo : public PPCGenInstrInfo { 187 PPCSubtarget &Subtarget; 188 const PPCRegisterInfo RI; 189 const unsigned StoreSpillOpcodesArray[3][SOK_LastOpcodeSpill] = 190 StoreOpcodesForSpill; 191 const unsigned LoadSpillOpcodesArray[3][SOK_LastOpcodeSpill] = 192 LoadOpcodesForSpill; 193 194 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 195 int FrameIdx, const TargetRegisterClass *RC, 196 SmallVectorImpl<MachineInstr *> &NewMIs) const; 197 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 198 unsigned DestReg, int FrameIdx, 199 const TargetRegisterClass *RC, 200 SmallVectorImpl<MachineInstr *> &NewMIs) const; 201 202 // Replace the instruction with single LI if possible. \p DefMI must be LI or 203 // LI8. 204 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 205 unsigned OpNoForForwarding, MachineInstr **KilledDef) const; 206 // If the inst is imm-form and its register operand is produced by a ADDI, put 207 // the imm into the inst directly and remove the ADDI if possible. 208 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI, 209 unsigned OpNoForForwarding) const; 210 // If the inst is x-form and has imm-form and one of its operand is produced 211 // by a LI, put the imm into the inst directly and remove the LI if possible. 212 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 213 unsigned ConstantOpNo, 214 MachineInstr &DefMI) const; 215 // If the inst is x-form and has imm-form and one of its operand is produced 216 // by an add-immediate, try to transform it when possible. 217 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 218 unsigned ConstantOpNo, MachineInstr &DefMI, 219 bool KillDefMI) const; 220 // Try to find that, if the instruction 'MI' contains any operand that 221 // could be forwarded from some inst that feeds it. If yes, return the 222 // Def of that operand. And OpNoForForwarding is the operand index in 223 // the 'MI' for that 'Def'. If we see another use of this Def between 224 // the Def and the MI, SeenIntermediateUse becomes 'true'. 225 MachineInstr *getForwardingDefMI(MachineInstr &MI, 226 unsigned &OpNoForForwarding, 227 bool &SeenIntermediateUse) const; 228 229 // Can the user MI have it's source at index \p OpNoForForwarding 230 // forwarded from an add-immediate that feeds it? 231 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 232 unsigned OpNoForForwarding) const; 233 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 234 const ImmInstrInfo &III, 235 MachineOperand *&ImmMO, 236 MachineOperand *&RegMO) const; 237 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 238 const MachineInstr &DefMI, 239 const ImmInstrInfo &III, 240 int64_t &Imm, 241 int64_t BaseImm = 0) const; 242 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 243 const MachineInstr &DefMI, 244 const MachineInstr &MI, bool KillDefMI, 245 bool &IsFwdFeederRegKilled) const; 246 unsigned getSpillTarget() const; 247 const unsigned *getStoreOpcodesForSpillArray() const; 248 const unsigned *getLoadOpcodesForSpillArray() const; 249 unsigned getSpillIndex(const TargetRegisterClass *RC) const; 250 int16_t getFMAOpIdxInfo(unsigned Opcode) const; 251 void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern, 252 SmallVectorImpl<MachineInstr *> &InsInstrs, 253 SmallVectorImpl<MachineInstr *> &DelInstrs, 254 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 255 bool isLoadFromConstantPool(MachineInstr *I) const; 256 Register 257 generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty, 258 SmallVectorImpl<MachineInstr *> &InsInstrs) const; 259 const Constant *getConstantFromConstantPool(MachineInstr *I) const; 260 virtual void anchor(); 261 262 protected: 263 /// Commutes the operands in the given instruction. 264 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 265 /// 266 /// Do not call this method for a non-commutable instruction or for 267 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 268 /// Even though the instruction is commutable, the method may still 269 /// fail to commute the operands, null pointer is returned in such cases. 270 /// 271 /// For example, we can commute rlwimi instructions, but only if the 272 /// rotate amt is zero. We also have to munge the immediates a bit. 273 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 274 unsigned OpIdx1, 275 unsigned OpIdx2) const override; 276 277 public: 278 explicit PPCInstrInfo(PPCSubtarget &STI); 279 280 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 281 /// such, whenever a client has an instance of instruction info, it should 282 /// always be able to get register info as well (through this method). 283 /// getRegisterInfo()284 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 285 isXFormMemOp(unsigned Opcode)286 bool isXFormMemOp(unsigned Opcode) const { 287 return get(Opcode).TSFlags & PPCII::XFormMemOp; 288 } isPrefixed(unsigned Opcode)289 bool isPrefixed(unsigned Opcode) const { 290 return get(Opcode).TSFlags & PPCII::Prefixed; 291 } 292 isSameClassPhysRegCopy(unsigned Opcode)293 static bool isSameClassPhysRegCopy(unsigned Opcode) { 294 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR, 295 PPC::VOR, PPC::XXLOR, PPC::XXLORf, 296 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR, 297 PPC::EVOR, -1U}; 298 for (int i = 0; CopyOpcodes[i] != -1U; i++) 299 if (Opcode == CopyOpcodes[i]) 300 return true; 301 return false; 302 } 303 304 ScheduleHazardRecognizer * 305 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 306 const ScheduleDAG *DAG) const override; 307 ScheduleHazardRecognizer * 308 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 309 const ScheduleDAG *DAG) const override; 310 311 unsigned getInstrLatency(const InstrItineraryData *ItinData, 312 const MachineInstr &MI, 313 unsigned *PredCost = nullptr) const override; 314 315 int getOperandLatency(const InstrItineraryData *ItinData, 316 const MachineInstr &DefMI, unsigned DefIdx, 317 const MachineInstr &UseMI, 318 unsigned UseIdx) const override; getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx)319 int getOperandLatency(const InstrItineraryData *ItinData, 320 SDNode *DefNode, unsigned DefIdx, 321 SDNode *UseNode, unsigned UseIdx) const override { 322 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 323 UseNode, UseIdx); 324 } 325 hasLowDefLatency(const TargetSchedModel & SchedModel,const MachineInstr & DefMI,unsigned DefIdx)326 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 327 const MachineInstr &DefMI, 328 unsigned DefIdx) const override { 329 // Machine LICM should hoist all instructions in low-register-pressure 330 // situations; none are sufficiently free to justify leaving in a loop 331 // body. 332 return false; 333 } 334 useMachineCombiner()335 bool useMachineCombiner() const override { 336 return true; 337 } 338 339 /// When getMachineCombinerPatterns() finds patterns, this function generates 340 /// the instructions that could replace the original code sequence 341 void genAlternativeCodeSequence( 342 MachineInstr &Root, MachineCombinerPattern Pattern, 343 SmallVectorImpl<MachineInstr *> &InsInstrs, 344 SmallVectorImpl<MachineInstr *> &DelInstrs, 345 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 346 347 /// Return true when there is potentially a faster code sequence for a fma 348 /// chain ending in \p Root. All potential patterns are output in the \p 349 /// P array. 350 bool getFMAPatterns(MachineInstr &Root, 351 SmallVectorImpl<MachineCombinerPattern> &P, 352 bool DoRegPressureReduce) const; 353 354 /// Return true when there is potentially a faster code sequence 355 /// for an instruction chain ending in <Root>. All potential patterns are 356 /// output in the <Pattern> array. 357 bool getMachineCombinerPatterns(MachineInstr &Root, 358 SmallVectorImpl<MachineCombinerPattern> &P, 359 bool DoRegPressureReduce) const override; 360 361 /// On PowerPC, we leverage machine combiner pass to reduce register pressure 362 /// when the register pressure is high for one BB. 363 /// Return true if register pressure for \p MBB is high and ABI is supported 364 /// to reduce register pressure. Otherwise return false. 365 bool 366 shouldReduceRegisterPressure(MachineBasicBlock *MBB, 367 RegisterClassInfo *RegClassInfo) const override; 368 369 /// Fixup the placeholders we put in genAlternativeCodeSequence() for 370 /// MachineCombiner. 371 void 372 finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, 373 SmallVectorImpl<MachineInstr *> &InsInstrs) const override; 374 375 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 376 377 /// On PowerPC, we try to reassociate FMA chain which will increase 378 /// instruction size. Set extension resource length limit to 1 for edge case. 379 /// Resource Length is calculated by scaled resource usage in getCycles(). 380 /// Because of the division in getCycles(), it returns different cycles due to 381 /// legacy scaled resource usage. So new resource length may be same with 382 /// legacy or 1 bigger than legacy. 383 /// We need to execlude the 1 bigger case even the resource length is not 384 /// perserved for more FMA chain reassociations on PowerPC. getExtendResourceLenLimit()385 int getExtendResourceLenLimit() const override { return 1; } 386 387 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 388 MachineInstr &NewMI1, 389 MachineInstr &NewMI2) const override; 390 391 void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override; 392 393 bool isCoalescableExtInstr(const MachineInstr &MI, 394 Register &SrcReg, Register &DstReg, 395 unsigned &SubIdx) const override; 396 unsigned isLoadFromStackSlot(const MachineInstr &MI, 397 int &FrameIndex) const override; 398 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 399 AAResults *AA) const override; 400 unsigned isStoreToStackSlot(const MachineInstr &MI, 401 int &FrameIndex) const override; 402 403 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 404 unsigned &SrcOpIdx2) const override; 405 406 void insertNoop(MachineBasicBlock &MBB, 407 MachineBasicBlock::iterator MI) const override; 408 409 410 // Branch analysis. 411 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 412 MachineBasicBlock *&FBB, 413 SmallVectorImpl<MachineOperand> &Cond, 414 bool AllowModify) const override; 415 unsigned removeBranch(MachineBasicBlock &MBB, 416 int *BytesRemoved = nullptr) const override; 417 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 418 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 419 const DebugLoc &DL, 420 int *BytesAdded = nullptr) const override; 421 422 // Select analysis. 423 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 424 Register, Register, Register, int &, int &, 425 int &) const override; 426 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 427 const DebugLoc &DL, Register DstReg, 428 ArrayRef<MachineOperand> Cond, Register TrueReg, 429 Register FalseReg) const override; 430 431 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 432 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 433 bool KillSrc) const override; 434 435 void storeRegToStackSlot(MachineBasicBlock &MBB, 436 MachineBasicBlock::iterator MBBI, 437 Register SrcReg, bool isKill, int FrameIndex, 438 const TargetRegisterClass *RC, 439 const TargetRegisterInfo *TRI) const override; 440 441 // Emits a register spill without updating the register class for vector 442 // registers. This ensures that when we spill a vector register the 443 // element order in the register is the same as it was in memory. 444 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 445 MachineBasicBlock::iterator MBBI, 446 unsigned SrcReg, bool isKill, int FrameIndex, 447 const TargetRegisterClass *RC, 448 const TargetRegisterInfo *TRI) const; 449 450 void loadRegFromStackSlot(MachineBasicBlock &MBB, 451 MachineBasicBlock::iterator MBBI, 452 Register DestReg, int FrameIndex, 453 const TargetRegisterClass *RC, 454 const TargetRegisterInfo *TRI) const override; 455 456 // Emits a register reload without updating the register class for vector 457 // registers. This ensures that when we reload a vector register the 458 // element order in the register is the same as it was in memory. 459 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 460 MachineBasicBlock::iterator MBBI, 461 unsigned DestReg, int FrameIndex, 462 const TargetRegisterClass *RC, 463 const TargetRegisterInfo *TRI) const; 464 465 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 466 467 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 468 469 bool 470 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 471 472 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 473 MachineRegisterInfo *MRI) const override; 474 475 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 476 Register Reg) const; 477 478 // If conversion by predication (only supported by some branch instructions). 479 // All of the profitability checks always return true; it is always 480 // profitable to use the predicated branches. isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,BranchProbability Probability)481 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 482 unsigned NumCycles, unsigned ExtraPredCycles, 483 BranchProbability Probability) const override { 484 return true; 485 } 486 487 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 488 unsigned NumT, unsigned ExtraT, 489 MachineBasicBlock &FMBB, 490 unsigned NumF, unsigned ExtraF, 491 BranchProbability Probability) const override; 492 isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,BranchProbability Probability)493 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 494 BranchProbability Probability) const override { 495 return true; 496 } 497 isProfitableToUnpredicate(MachineBasicBlock & TMBB,MachineBasicBlock & FMBB)498 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 499 MachineBasicBlock &FMBB) const override { 500 return false; 501 } 502 503 // Predication support. 504 bool isPredicated(const MachineInstr &MI) const override; 505 506 bool isSchedulingBoundary(const MachineInstr &MI, 507 const MachineBasicBlock *MBB, 508 const MachineFunction &MF) const override; 509 510 bool PredicateInstruction(MachineInstr &MI, 511 ArrayRef<MachineOperand> Pred) const override; 512 513 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 514 ArrayRef<MachineOperand> Pred2) const override; 515 516 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred, 517 bool SkipDead) const override; 518 519 // Comparison optimization. 520 521 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 522 Register &SrcReg2, int &Mask, int &Value) const override; 523 524 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 525 Register SrcReg2, int Mask, int Value, 526 const MachineRegisterInfo *MRI) const override; 527 528 529 /// Return true if get the base operand, byte offset of an instruction and 530 /// the memory width. Width is the size of memory that is being 531 /// loaded/stored (e.g. 1, 2, 4, 8). 532 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 533 const MachineOperand *&BaseOp, 534 int64_t &Offset, unsigned &Width, 535 const TargetRegisterInfo *TRI) const; 536 537 /// Get the base operand and byte offset of an instruction that reads/writes 538 /// memory. 539 bool getMemOperandsWithOffsetWidth( 540 const MachineInstr &LdSt, 541 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 542 bool &OffsetIsScalable, unsigned &Width, 543 const TargetRegisterInfo *TRI) const override; 544 545 /// Returns true if the two given memory operations should be scheduled 546 /// adjacent. 547 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, 548 ArrayRef<const MachineOperand *> BaseOps2, 549 unsigned NumLoads, unsigned NumBytes) const override; 550 551 /// Return true if two MIs access different memory addresses and false 552 /// otherwise 553 bool 554 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 555 const MachineInstr &MIb) const override; 556 557 /// GetInstSize - Return the number of bytes of code the specified 558 /// instruction may be. This returns the maximum number of bytes. 559 /// 560 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 561 562 void getNoop(MCInst &NopInst) const override; 563 564 std::pair<unsigned, unsigned> 565 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 566 567 ArrayRef<std::pair<unsigned, const char *>> 568 getSerializableDirectMachineOperandTargetFlags() const override; 569 570 ArrayRef<std::pair<unsigned, const char *>> 571 getSerializableBitmaskMachineOperandTargetFlags() const override; 572 573 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 574 bool expandVSXMemPseudo(MachineInstr &MI) const; 575 576 // Lower pseudo instructions after register allocation. 577 bool expandPostRAPseudo(MachineInstr &MI) const override; 578 isVFRegister(unsigned Reg)579 static bool isVFRegister(unsigned Reg) { 580 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 581 } isVRRegister(unsigned Reg)582 static bool isVRRegister(unsigned Reg) { 583 return Reg >= PPC::V0 && Reg <= PPC::V31; 584 } 585 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 586 static int getRecordFormOpcode(unsigned Opcode); 587 588 bool isTOCSaveMI(const MachineInstr &MI) const; 589 590 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 591 const unsigned PhiDepth) const; 592 593 /// Return true if the output of the instruction is always a sign-extended, 594 /// i.e. 0 to 31-th bits are same as 32-th bit. 595 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 596 return isSignOrZeroExtended(MI, true, depth); 597 } 598 599 /// Return true if the output of the instruction is always zero-extended, 600 /// i.e. 0 to 31-th bits are all zeros 601 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 602 return isSignOrZeroExtended(MI, false, depth); 603 } 604 605 bool convertToImmediateForm(MachineInstr &MI, 606 MachineInstr **KilledDef = nullptr) const; 607 bool foldFrameOffset(MachineInstr &MI) const; 608 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const; 609 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 610 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 611 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 612 unsigned &XFormOpcode, 613 int64_t &OffsetOfImmInstr, 614 ImmInstrInfo &III) const; 615 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 616 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 617 int64_t OffsetImm) const; 618 619 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 620 /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate 621 /// register killed/dead flags semantics, this function can be called to fix 622 /// up. Before calling this function, 623 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 624 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 625 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For 626 /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI 627 /// will be adjust to true definition. 628 /// 3. We can do accurate fixup for the case when all instructions between 629 /// [\p StartMI, \p EndMI] are in same basic block. 630 /// 4. For the case when \p StartMI and \p EndMI are not in same basic block, 631 /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA 632 /// and for post-RA, we give an assertion as without reaching definition 633 /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right. 634 void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, 635 unsigned RegNo) const; 636 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 637 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 638 int64_t Imm) const; 639 640 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 641 bool PostRA) const; 642 643 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 644 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 645 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 646 bool &SeenIntermediateUse) const; 647 648 /// getRegNumForOperand - some operands use different numbering schemes 649 /// for the same registers. For example, a VSX instruction may have any of 650 /// vs0-vs63 allocated whereas an Altivec instruction could only have 651 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 652 /// register number needed for the opcode/operand number combination. 653 /// The operand number argument will be useful when we need to extend this 654 /// to instructions that use both Altivec and VSX numbering (for different 655 /// operands). getRegNumForOperand(const MCInstrDesc & Desc,unsigned Reg,unsigned OpNo)656 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 657 unsigned OpNo) { 658 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 659 switch (regClass) { 660 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 661 // VSX32-VSX63 during encoding/disassembling 662 case PPC::VSSRCRegClassID: 663 case PPC::VSFRCRegClassID: 664 if (isVFRegister(Reg)) 665 return PPC::VSX32 + (Reg - PPC::VF0); 666 break; 667 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 668 // VSX32-VSX63 during encoding/disassembling 669 case PPC::VSRCRegClassID: 670 if (isVRRegister(Reg)) 671 return PPC::VSX32 + (Reg - PPC::V0); 672 break; 673 // Other RegClass doesn't need mapping 674 default: 675 break; 676 } 677 return Reg; 678 } 679 680 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 681 bool isBDNZ(unsigned Opcode) const; 682 683 /// Find the hardware loop instruction used to set-up the specified loop. 684 /// On PPC, we have two instructions used to set-up the hardware loop 685 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 686 /// instructions to indicate the end of a loop. 687 MachineInstr * 688 findLoopInstr(MachineBasicBlock &PreHeader, 689 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 690 691 /// Analyze loop L, which must be a single-basic-block loop, and if the 692 /// conditions can be understood enough produce a PipelinerLoopInfo object. 693 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 694 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 695 }; 696 697 } 698 699 #endif 700