1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \ 3; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ 4; RUN: < %s | FileCheck %s 5 6; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \ 7; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu \ 8; RUN: < %s | FileCheck %s --check-prefix=P9BE 9 10; Function Attrs: norecurse nounwind readonly 11define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) { 12; CHECK-LABEL: test_pre_inc_disable_1: 13; CHECK: # %bb.0: # %entry 14; CHECK-NEXT: lxsd v5, 0(r5) 15; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha 16; CHECK-NEXT: xxlxor v3, v3, v3 17; CHECK-NEXT: li r6, 0 18; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l 19; CHECK-NEXT: lxvx v2, 0, r5 20; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha 21; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l 22; CHECK-NEXT: lxvx v4, 0, r5 23; CHECK-NEXT: li r5, 4 24; CHECK-NEXT: vperm v0, v3, v5, v2 25; CHECK-NEXT: mtctr r5 26; CHECK-NEXT: li r5, 0 27; CHECK-NEXT: vperm v1, v3, v5, v4 28; CHECK-NEXT: xvnegsp v5, v0 29; CHECK-NEXT: xvnegsp v0, v1 30; CHECK-NEXT: .p2align 4 31; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader 32; CHECK-NEXT: # 33; CHECK-NEXT: lxsd v1, 0(r3) 34; CHECK-NEXT: add r7, r3, r4 35; CHECK-NEXT: vperm v6, v3, v1, v4 36; CHECK-NEXT: vperm v1, v3, v1, v2 37; CHECK-NEXT: xvnegsp v1, v1 38; CHECK-NEXT: xvnegsp v6, v6 39; CHECK-NEXT: vabsduw v1, v1, v5 40; CHECK-NEXT: vabsduw v6, v6, v0 41; CHECK-NEXT: vadduwm v1, v6, v1 42; CHECK-NEXT: xxswapd v6, v1 43; CHECK-NEXT: vadduwm v1, v1, v6 44; CHECK-NEXT: xxspltw v6, v1, 2 45; CHECK-NEXT: vadduwm v1, v1, v6 46; CHECK-NEXT: lxsdx v6, r3, r4 47; CHECK-NEXT: vextuwrx r3, r5, v1 48; CHECK-NEXT: vperm v7, v3, v6, v4 49; CHECK-NEXT: vperm v6, v3, v6, v2 50; CHECK-NEXT: add r6, r3, r6 51; CHECK-NEXT: add r3, r7, r4 52; CHECK-NEXT: xvnegsp v6, v6 53; CHECK-NEXT: xvnegsp v1, v7 54; CHECK-NEXT: vabsduw v6, v6, v5 55; CHECK-NEXT: vabsduw v1, v1, v0 56; CHECK-NEXT: vadduwm v1, v1, v6 57; CHECK-NEXT: xxswapd v6, v1 58; CHECK-NEXT: vadduwm v1, v1, v6 59; CHECK-NEXT: xxspltw v6, v1, 2 60; CHECK-NEXT: vadduwm v1, v1, v6 61; CHECK-NEXT: vextuwrx r8, r5, v1 62; CHECK-NEXT: add r6, r8, r6 63; CHECK-NEXT: bdnz .LBB0_1 64; CHECK-NEXT: # %bb.2: # %for.cond.cleanup 65; CHECK-NEXT: extsw r3, r6 66; CHECK-NEXT: blr 67; 68; P9BE-LABEL: test_pre_inc_disable_1: 69; P9BE: # %bb.0: # %entry 70; P9BE-NEXT: lfd f0, 0(r5) 71; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha 72; P9BE-NEXT: xxlxor v3, v3, v3 73; P9BE-NEXT: li r6, 0 74; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l 75; P9BE-NEXT: lxvx v2, 0, r5 76; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha 77; P9BE-NEXT: xxlor v5, vs0, vs0 78; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l 79; P9BE-NEXT: lxvx v4, 0, r5 80; P9BE-NEXT: li r5, 4 81; P9BE-NEXT: vperm v0, v3, v5, v2 82; P9BE-NEXT: mtctr r5 83; P9BE-NEXT: li r5, 0 84; P9BE-NEXT: vperm v1, v3, v5, v4 85; P9BE-NEXT: xvnegsp v5, v0 86; P9BE-NEXT: xvnegsp v0, v1 87; P9BE-NEXT: .p2align 4 88; P9BE-NEXT: .LBB0_1: # %for.cond1.preheader 89; P9BE-NEXT: # 90; P9BE-NEXT: lfd f0, 0(r3) 91; P9BE-NEXT: add r7, r3, r4 92; P9BE-NEXT: xxlor v1, vs0, vs0 93; P9BE-NEXT: lfdx f0, r3, r4 94; P9BE-NEXT: vperm v6, v3, v1, v4 95; P9BE-NEXT: vperm v1, v3, v1, v2 96; P9BE-NEXT: xvnegsp v1, v1 97; P9BE-NEXT: xvnegsp v6, v6 98; P9BE-NEXT: vabsduw v1, v1, v5 99; P9BE-NEXT: vabsduw v6, v6, v0 100; P9BE-NEXT: vadduwm v1, v6, v1 101; P9BE-NEXT: xxswapd v6, v1 102; P9BE-NEXT: vadduwm v1, v1, v6 103; P9BE-NEXT: xxspltw v6, v1, 1 104; P9BE-NEXT: vadduwm v1, v1, v6 105; P9BE-NEXT: xxlor v6, vs0, vs0 106; P9BE-NEXT: vperm v7, v3, v6, v4 107; P9BE-NEXT: vperm v6, v3, v6, v2 108; P9BE-NEXT: vextuwlx r3, r5, v1 109; P9BE-NEXT: xvnegsp v6, v6 110; P9BE-NEXT: add r6, r3, r6 111; P9BE-NEXT: xvnegsp v1, v7 112; P9BE-NEXT: add r3, r7, r4 113; P9BE-NEXT: vabsduw v6, v6, v5 114; P9BE-NEXT: vabsduw v1, v1, v0 115; P9BE-NEXT: vadduwm v1, v1, v6 116; P9BE-NEXT: xxswapd v6, v1 117; P9BE-NEXT: vadduwm v1, v1, v6 118; P9BE-NEXT: xxspltw v6, v1, 1 119; P9BE-NEXT: vadduwm v1, v1, v6 120; P9BE-NEXT: vextuwlx r8, r5, v1 121; P9BE-NEXT: add r6, r8, r6 122; P9BE-NEXT: bdnz .LBB0_1 123; P9BE-NEXT: # %bb.2: # %for.cond.cleanup 124; P9BE-NEXT: extsw r3, r6 125; P9BE-NEXT: blr 126entry: 127 %idx.ext = sext i32 %i_stride_pix1 to i64 128 %0 = bitcast i8* %pix2 to <8 x i8>* 129 %1 = load <8 x i8>, <8 x i8>* %0, align 1 130 %2 = zext <8 x i8> %1 to <8 x i32> 131 br label %for.cond1.preheader 132 133for.cond1.preheader: ; preds = %for.cond1.preheader, %entry 134 %y.024 = phi i32 [ 0, %entry ], [ %inc9.1, %for.cond1.preheader ] 135 %i_sum.023 = phi i32 [ 0, %entry ], [ %op.extra.1, %for.cond1.preheader ] 136 %pix1.addr.022 = phi i8* [ %pix1, %entry ], [ %add.ptr.1, %for.cond1.preheader ] 137 %3 = bitcast i8* %pix1.addr.022 to <8 x i8>* 138 %4 = load <8 x i8>, <8 x i8>* %3, align 1 139 %5 = zext <8 x i8> %4 to <8 x i32> 140 %6 = sub nsw <8 x i32> %5, %2 141 %7 = icmp slt <8 x i32> %6, zeroinitializer 142 %8 = sub nsw <8 x i32> zeroinitializer, %6 143 %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6 144 %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> 145 %bin.rdx = add nsw <8 x i32> %9, %rdx.shuf 146 %rdx.shuf32 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 147 %bin.rdx33 = add nsw <8 x i32> %bin.rdx, %rdx.shuf32 148 %rdx.shuf34 = shufflevector <8 x i32> %bin.rdx33, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 149 %bin.rdx35 = add nsw <8 x i32> %bin.rdx33, %rdx.shuf34 150 %10 = extractelement <8 x i32> %bin.rdx35, i32 0 151 %op.extra = add nsw i32 %10, %i_sum.023 152 %add.ptr = getelementptr inbounds i8, i8* %pix1.addr.022, i64 %idx.ext 153 %11 = bitcast i8* %add.ptr to <8 x i8>* 154 %12 = load <8 x i8>, <8 x i8>* %11, align 1 155 %13 = zext <8 x i8> %12 to <8 x i32> 156 %14 = sub nsw <8 x i32> %13, %2 157 %15 = icmp slt <8 x i32> %14, zeroinitializer 158 %16 = sub nsw <8 x i32> zeroinitializer, %14 159 %17 = select <8 x i1> %15, <8 x i32> %16, <8 x i32> %14 160 %rdx.shuf.1 = shufflevector <8 x i32> %17, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> 161 %bin.rdx.1 = add nsw <8 x i32> %17, %rdx.shuf.1 162 %rdx.shuf32.1 = shufflevector <8 x i32> %bin.rdx.1, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 163 %bin.rdx33.1 = add nsw <8 x i32> %bin.rdx.1, %rdx.shuf32.1 164 %rdx.shuf34.1 = shufflevector <8 x i32> %bin.rdx33.1, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 165 %bin.rdx35.1 = add nsw <8 x i32> %bin.rdx33.1, %rdx.shuf34.1 166 %18 = extractelement <8 x i32> %bin.rdx35.1, i32 0 167 %op.extra.1 = add nsw i32 %18, %op.extra 168 %add.ptr.1 = getelementptr inbounds i8, i8* %add.ptr, i64 %idx.ext 169 %inc9.1 = add nuw nsw i32 %y.024, 2 170 %exitcond.1 = icmp eq i32 %inc9.1, 8 171 br i1 %exitcond.1, label %for.cond.cleanup, label %for.cond1.preheader 172 173for.cond.cleanup: ; preds = %for.cond1.preheader 174 ret i32 %op.extra.1 175} 176 177; Function Attrs: norecurse nounwind readonly 178define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) { 179; CHECK-LABEL: test_pre_inc_disable_2: 180; CHECK: # %bb.0: # %entry 181; CHECK-NEXT: lxsd v2, 0(r3) 182; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha 183; CHECK-NEXT: lxsd v1, 0(r4) 184; CHECK-NEXT: xxlxor v3, v3, v3 185; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l 186; CHECK-NEXT: lxvx v4, 0, r3 187; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha 188; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l 189; CHECK-NEXT: lxvx v0, 0, r3 190; CHECK-NEXT: li r3, 0 191; CHECK-NEXT: vperm v5, v3, v2, v4 192; CHECK-NEXT: vperm v2, v3, v2, v0 193; CHECK-NEXT: vperm v0, v3, v1, v0 194; CHECK-NEXT: vperm v3, v3, v1, v4 195; CHECK-NEXT: vabsduw v2, v2, v0 196; CHECK-NEXT: vabsduw v3, v5, v3 197; CHECK-NEXT: vadduwm v2, v3, v2 198; CHECK-NEXT: xxswapd v3, v2 199; CHECK-NEXT: vadduwm v2, v2, v3 200; CHECK-NEXT: xxspltw v3, v2, 2 201; CHECK-NEXT: vadduwm v2, v2, v3 202; CHECK-NEXT: vextuwrx r3, r3, v2 203; CHECK-NEXT: extsw r3, r3 204; CHECK-NEXT: blr 205; 206; P9BE-LABEL: test_pre_inc_disable_2: 207; P9BE: # %bb.0: # %entry 208; P9BE-NEXT: lfd f0, 0(r3) 209; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha 210; P9BE-NEXT: xxlxor v3, v3, v3 211; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l 212; P9BE-NEXT: lxvx v4, 0, r3 213; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha 214; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l 215; P9BE-NEXT: xxlor v2, vs0, vs0 216; P9BE-NEXT: lfd f0, 0(r4) 217; P9BE-NEXT: lxvx v0, 0, r3 218; P9BE-NEXT: xxlor v1, vs0, vs0 219; P9BE-NEXT: li r3, 0 220; P9BE-NEXT: vperm v5, v3, v2, v4 221; P9BE-NEXT: vperm v2, v3, v2, v0 222; P9BE-NEXT: vperm v0, v3, v1, v0 223; P9BE-NEXT: vperm v3, v3, v1, v4 224; P9BE-NEXT: vabsduw v2, v2, v0 225; P9BE-NEXT: vabsduw v3, v5, v3 226; P9BE-NEXT: vadduwm v2, v3, v2 227; P9BE-NEXT: xxswapd v3, v2 228; P9BE-NEXT: vadduwm v2, v2, v3 229; P9BE-NEXT: xxspltw v3, v2, 1 230; P9BE-NEXT: vadduwm v2, v2, v3 231; P9BE-NEXT: vextuwlx r3, r3, v2 232; P9BE-NEXT: extsw r3, r3 233; P9BE-NEXT: blr 234entry: 235 %0 = bitcast i8* %pix1 to <8 x i8>* 236 %1 = load <8 x i8>, <8 x i8>* %0, align 1 237 %2 = zext <8 x i8> %1 to <8 x i32> 238 %3 = bitcast i8* %pix2 to <8 x i8>* 239 %4 = load <8 x i8>, <8 x i8>* %3, align 1 240 %5 = zext <8 x i8> %4 to <8 x i32> 241 %6 = sub nsw <8 x i32> %2, %5 242 %7 = icmp slt <8 x i32> %6, zeroinitializer 243 %8 = sub nsw <8 x i32> zeroinitializer, %6 244 %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6 245 %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> 246 %bin.rdx = add nsw <8 x i32> %9, %rdx.shuf 247 %rdx.shuf12 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 248 %bin.rdx13 = add nsw <8 x i32> %bin.rdx, %rdx.shuf12 249 %rdx.shuf14 = shufflevector <8 x i32> %bin.rdx13, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 250 %bin.rdx15 = add nsw <8 x i32> %bin.rdx13, %rdx.shuf14 251 %10 = extractelement <8 x i32> %bin.rdx15, i32 0 252 ret i32 %10 253} 254 255 256; Generated from C source: 257; 258;#include <stdint.h> 259;#include <stdlib.h> 260;int test_pre_inc_disable_1( uint8_t *pix1, int i_stride_pix1, uint8_t *pix2 ) { 261; int i_sum = 0; 262; for( int y = 0; y < 8; y++ ) { 263; for( int x = 0; x < 8; x++) { 264; i_sum += abs( pix1[x] - pix2[x] ) 265; } 266; pix1 += i_stride_pix1; 267; } 268; return i_sum; 269;} 270 271;int test_pre_inc_disable_2( uint8_t *pix1, uint8_t *pix2 ) { 272; int i_sum = 0; 273; for( int x = 0; x < 8; x++ ) { 274; i_sum += abs( pix1[x] - pix2[x] ); 275; } 276; 277; return i_sum; 278;} 279 280define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) { 281; CHECK-LABEL: test32: 282; CHECK: # %bb.0: # %entry 283; CHECK-NEXT: add r5, r3, r4 284; CHECK-NEXT: lxsiwzx v2, r3, r4 285; CHECK-NEXT: addis r3, r2, .LCPI2_0@toc@ha 286; CHECK-NEXT: xxlxor v3, v3, v3 287; CHECK-NEXT: addi r3, r3, .LCPI2_0@toc@l 288; CHECK-NEXT: lxvx v4, 0, r3 289; CHECK-NEXT: li r3, 4 290; CHECK-NEXT: lxsiwzx v5, r5, r3 291; CHECK-NEXT: vperm v2, v2, v3, v4 292; CHECK-NEXT: vperm v3, v5, v3, v4 293; CHECK-NEXT: vspltisw v4, 8 294; CHECK-NEXT: vnegw v3, v3 295; CHECK-NEXT: vadduwm v4, v4, v4 296; CHECK-NEXT: vslw v3, v3, v4 297; CHECK-NEXT: vsubuwm v2, v3, v2 298; CHECK-NEXT: xxswapd vs0, v2 299; CHECK-NEXT: stxvx vs0, 0, r3 300; CHECK-NEXT: blr 301; 302; P9BE-LABEL: test32: 303; P9BE: # %bb.0: # %entry 304; P9BE-NEXT: add r5, r3, r4 305; P9BE-NEXT: lfiwzx f0, r3, r4 306; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha 307; P9BE-NEXT: xxlxor v3, v3, v3 308; P9BE-NEXT: xxsldwi v2, f0, f0, 1 309; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l 310; P9BE-NEXT: lxvx v4, 0, r3 311; P9BE-NEXT: li r3, 4 312; P9BE-NEXT: lfiwzx f0, r5, r3 313; P9BE-NEXT: vperm v2, v3, v2, v4 314; P9BE-NEXT: xxsldwi v5, f0, f0, 1 315; P9BE-NEXT: vperm v3, v3, v5, v4 316; P9BE-NEXT: vspltisw v4, 8 317; P9BE-NEXT: vnegw v3, v3 318; P9BE-NEXT: vadduwm v4, v4, v4 319; P9BE-NEXT: vslw v3, v3, v4 320; P9BE-NEXT: vsubuwm v2, v3, v2 321; P9BE-NEXT: xxswapd vs0, v2 322; P9BE-NEXT: stxvx vs0, 0, r3 323; P9BE-NEXT: blr 324entry: 325 %idx.ext63 = sext i32 %i_pix2 to i64 326 %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63 327 %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4 328 %0 = bitcast i8* %add.ptr64 to <4 x i8>* 329 %1 = load <4 x i8>, <4 x i8>* %0, align 1 330 %reorder_shuffle117 = shufflevector <4 x i8> %1, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 331 %2 = zext <4 x i8> %reorder_shuffle117 to <4 x i32> 332 %3 = sub nsw <4 x i32> zeroinitializer, %2 333 %4 = bitcast i8* %arrayidx5.1 to <4 x i8>* 334 %5 = load <4 x i8>, <4 x i8>* %4, align 1 335 %reorder_shuffle115 = shufflevector <4 x i8> %5, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 336 %6 = zext <4 x i8> %reorder_shuffle115 to <4 x i32> 337 %7 = sub nsw <4 x i32> zeroinitializer, %6 338 %8 = shl nsw <4 x i32> %7, <i32 16, i32 16, i32 16, i32 16> 339 %9 = add nsw <4 x i32> %8, %3 340 %10 = sub nsw <4 x i32> %9, zeroinitializer 341 %11 = shufflevector <4 x i32> undef, <4 x i32> %10, <4 x i32> <i32 2, i32 7, i32 0, i32 5> 342 %12 = add nsw <4 x i32> zeroinitializer, %11 343 %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 7> 344 store <4 x i32> %13, <4 x i32>* undef, align 16 345 ret void 346} 347 348define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) { 349; CHECK-LABEL: test16: 350; CHECK: # %bb.0: # %entry 351; CHECK-NEXT: sldi r4, r4, 1 352; CHECK-NEXT: li r7, 16 353; CHECK-NEXT: add r6, r3, r4 354; CHECK-NEXT: lxsihzx v4, r3, r4 355; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha 356; CHECK-NEXT: lxsihzx v2, r6, r7 357; CHECK-NEXT: li r6, 0 358; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l 359; CHECK-NEXT: mtvsrd v3, r6 360; CHECK-NEXT: vsplth v4, v4, 3 361; CHECK-NEXT: vsplth v2, v2, 3 362; CHECK-NEXT: vmrghh v4, v3, v4 363; CHECK-NEXT: vmrghh v2, v3, v2 364; CHECK-NEXT: vsplth v3, v3, 3 365; CHECK-NEXT: vmrglw v3, v4, v3 366; CHECK-NEXT: lxvx v4, 0, r3 367; CHECK-NEXT: li r3, 0 368; CHECK-NEXT: vperm v2, v2, v3, v4 369; CHECK-NEXT: xxspltw v3, v2, 2 370; CHECK-NEXT: vadduwm v2, v2, v3 371; CHECK-NEXT: vextuwrx r3, r3, v2 372; CHECK-NEXT: cmpw r3, r5 373; CHECK-NEXT: bgelr+ cr0 374; CHECK-NEXT: # %bb.1: # %if.then 375; 376; P9BE-LABEL: test16: 377; P9BE: # %bb.0: # %entry 378; P9BE-NEXT: sldi r4, r4, 1 379; P9BE-NEXT: li r7, 16 380; P9BE-NEXT: add r6, r3, r4 381; P9BE-NEXT: lxsihzx v4, r3, r4 382; P9BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha 383; P9BE-NEXT: lxsihzx v2, r6, r7 384; P9BE-NEXT: li r6, 0 385; P9BE-NEXT: addi r3, r3, .LCPI3_0@toc@l 386; P9BE-NEXT: sldi r6, r6, 48 387; P9BE-NEXT: vsplth v4, v4, 3 388; P9BE-NEXT: mtvsrd v3, r6 389; P9BE-NEXT: vsplth v2, v2, 3 390; P9BE-NEXT: vmrghh v4, v3, v4 391; P9BE-NEXT: vmrghh v2, v3, v2 392; P9BE-NEXT: vsplth v3, v3, 0 393; P9BE-NEXT: vmrghw v3, v3, v4 394; P9BE-NEXT: lxvx v4, 0, r3 395; P9BE-NEXT: li r3, 0 396; P9BE-NEXT: vperm v2, v3, v2, v4 397; P9BE-NEXT: xxspltw v3, v2, 1 398; P9BE-NEXT: vadduwm v2, v2, v3 399; P9BE-NEXT: vextuwlx r3, r3, v2 400; P9BE-NEXT: cmpw r3, r5 401; P9BE-NEXT: bgelr+ cr0 402; P9BE-NEXT: # %bb.1: # %if.then 403entry: 404 %idxprom = sext i32 %delta to i64 405 %add14 = add nsw i32 %delta, 8 406 %idxprom15 = sext i32 %add14 to i64 407 br label %for.body 408 409for.body: ; preds = %entry 410 %arrayidx8 = getelementptr inbounds i16, i16* %sums, i64 %idxprom 411 %0 = load i16, i16* %arrayidx8, align 2 412 %arrayidx16 = getelementptr inbounds i16, i16* %sums, i64 %idxprom15 413 %1 = load i16, i16* %arrayidx16, align 2 414 %2 = insertelement <4 x i16> undef, i16 %0, i32 2 415 %3 = insertelement <4 x i16> %2, i16 %1, i32 3 416 %4 = zext <4 x i16> %3 to <4 x i32> 417 %5 = sub nsw <4 x i32> zeroinitializer, %4 418 %6 = sub nsw <4 x i32> zeroinitializer, %5 419 %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5 420 %bin.rdx = add <4 x i32> %7, zeroinitializer 421 %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 422 %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54 423 %8 = extractelement <4 x i32> %bin.rdx55, i32 0 424 %op.extra = add nuw i32 %8, 0 425 %cmp25 = icmp slt i32 %op.extra, %thresh 426 br i1 %cmp25, label %if.then, label %if.end 427 428if.then: ; preds = %for.body 429 unreachable 430 431if.end: ; preds = %for.body 432 ret void 433} 434 435define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) { 436; CHECK-LABEL: test8: 437; CHECK: # %bb.0: # %entry 438; CHECK-NEXT: add r6, r3, r4 439; CHECK-NEXT: lxsibzx v2, r3, r4 440; CHECK-NEXT: li r3, 0 441; CHECK-NEXT: mtvsrd v3, r3 442; CHECK-NEXT: li r3, 8 443; CHECK-NEXT: lxsibzx v5, r6, r3 444; CHECK-NEXT: vspltb v4, v3, 7 445; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha 446; CHECK-NEXT: vspltb v2, v2, 7 447; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l 448; CHECK-NEXT: vmrghb v2, v3, v2 449; CHECK-NEXT: vspltb v5, v5, 7 450; CHECK-NEXT: vmrglh v2, v2, v4 451; CHECK-NEXT: vmrghb v3, v3, v5 452; CHECK-NEXT: vmrglw v2, v2, v4 453; CHECK-NEXT: vmrglh v3, v3, v4 454; CHECK-NEXT: vmrglw v3, v4, v3 455; CHECK-NEXT: lxvx v4, 0, r3 456; CHECK-NEXT: li r3, 0 457; CHECK-NEXT: vperm v2, v3, v2, v4 458; CHECK-NEXT: xxspltw v3, v2, 2 459; CHECK-NEXT: vadduwm v2, v2, v3 460; CHECK-NEXT: vextuwrx r3, r3, v2 461; CHECK-NEXT: cmpw r3, r5 462; CHECK-NEXT: bgelr+ cr0 463; CHECK-NEXT: # %bb.1: # %if.then 464; 465; P9BE-LABEL: test8: 466; P9BE: # %bb.0: # %entry 467; P9BE-NEXT: add r6, r3, r4 468; P9BE-NEXT: li r7, 8 469; P9BE-NEXT: lxsibzx v4, r3, r4 470; P9BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha 471; P9BE-NEXT: lxsibzx v2, r6, r7 472; P9BE-NEXT: li r6, 0 473; P9BE-NEXT: addi r3, r3, .LCPI4_0@toc@l 474; P9BE-NEXT: sldi r6, r6, 56 475; P9BE-NEXT: vspltb v4, v4, 7 476; P9BE-NEXT: mtvsrd v3, r6 477; P9BE-NEXT: vspltb v2, v2, 7 478; P9BE-NEXT: vmrghb v4, v3, v4 479; P9BE-NEXT: vmrghb v2, v3, v2 480; P9BE-NEXT: vspltb v3, v3, 0 481; P9BE-NEXT: vmrghh v4, v4, v3 482; P9BE-NEXT: xxspltw v3, v3, 0 483; P9BE-NEXT: vmrghw v2, v4, v2 484; P9BE-NEXT: lxvx v4, 0, r3 485; P9BE-NEXT: li r3, 0 486; P9BE-NEXT: vperm v2, v3, v2, v4 487; P9BE-NEXT: xxspltw v3, v2, 1 488; P9BE-NEXT: vadduwm v2, v2, v3 489; P9BE-NEXT: vextuwlx r3, r3, v2 490; P9BE-NEXT: cmpw r3, r5 491; P9BE-NEXT: bgelr+ cr0 492; P9BE-NEXT: # %bb.1: # %if.then 493entry: 494 %idxprom = sext i32 %delta to i64 495 %add14 = add nsw i32 %delta, 8 496 %idxprom15 = sext i32 %add14 to i64 497 br label %for.body 498 499for.body: ; preds = %entry 500 %arrayidx8 = getelementptr inbounds i8, i8* %sums, i64 %idxprom 501 %0 = load i8, i8* %arrayidx8, align 2 502 %arrayidx16 = getelementptr inbounds i8, i8* %sums, i64 %idxprom15 503 %1 = load i8, i8* %arrayidx16, align 2 504 %2 = insertelement <4 x i8> undef, i8 %0, i32 2 505 %3 = insertelement <4 x i8> %2, i8 %1, i32 3 506 %4 = zext <4 x i8> %3 to <4 x i32> 507 %5 = sub nsw <4 x i32> zeroinitializer, %4 508 %6 = sub nsw <4 x i32> zeroinitializer, %5 509 %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5 510 %bin.rdx = add <4 x i32> %7, zeroinitializer 511 %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> 512 %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54 513 %8 = extractelement <4 x i32> %bin.rdx55, i32 0 514 %op.extra = add nuw i32 %8, 0 515 %cmp25 = icmp slt i32 %op.extra, %thresh 516 br i1 %cmp25, label %if.then, label %if.end 517 518if.then: ; preds = %for.body 519 unreachable 520 521if.end: ; preds = %for.body 522 ret void 523} 524