1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
4
5 #include <riscv_vector.h>
6
7 //
8 // CHECK-RV64-LABEL: @test_vmmv_m_b1(
9 // CHECK-RV64-NEXT: entry:
10 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]])
11 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
12 //
test_vmmv_m_b1(vbool1_t op1,size_t vl)13 vbool1_t test_vmmv_m_b1 (vbool1_t op1, size_t vl) {
14 return vmmv_m_b1(op1, vl);
15 }
16
17 //
18 // CHECK-RV64-LABEL: @test_vmmv_m_b2(
19 // CHECK-RV64-NEXT: entry:
20 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]])
21 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
22 //
test_vmmv_m_b2(vbool2_t op1,size_t vl)23 vbool2_t test_vmmv_m_b2 (vbool2_t op1, size_t vl) {
24 return vmmv_m_b2(op1, vl);
25 }
26
27 //
28 // CHECK-RV64-LABEL: @test_vmmv_m_b4(
29 // CHECK-RV64-NEXT: entry:
30 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]])
31 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
32 //
test_vmmv_m_b4(vbool4_t op1,size_t vl)33 vbool4_t test_vmmv_m_b4 (vbool4_t op1, size_t vl) {
34 return vmmv_m_b4(op1, vl);
35 }
36
37 //
38 // CHECK-RV64-LABEL: @test_vmmv_m_b8(
39 // CHECK-RV64-NEXT: entry:
40 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]])
41 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
42 //
test_vmmv_m_b8(vbool8_t op1,size_t vl)43 vbool8_t test_vmmv_m_b8 (vbool8_t op1, size_t vl) {
44 return vmmv_m_b8(op1, vl);
45 }
46
47 //
48 // CHECK-RV64-LABEL: @test_vmmv_m_b16(
49 // CHECK-RV64-NEXT: entry:
50 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]])
51 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
52 //
test_vmmv_m_b16(vbool16_t op1,size_t vl)53 vbool16_t test_vmmv_m_b16 (vbool16_t op1, size_t vl) {
54 return vmmv_m_b16(op1, vl);
55 }
56
57 //
58 // CHECK-RV64-LABEL: @test_vmmv_m_b32(
59 // CHECK-RV64-NEXT: entry:
60 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]])
61 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
62 //
test_vmmv_m_b32(vbool32_t op1,size_t vl)63 vbool32_t test_vmmv_m_b32 (vbool32_t op1, size_t vl) {
64 return vmmv_m_b32(op1, vl);
65 }
66
67 //
68 // CHECK-RV64-LABEL: @test_vmmv_m_b64(
69 // CHECK-RV64-NEXT: entry:
70 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]])
71 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
72 //
test_vmmv_m_b64(vbool64_t op1,size_t vl)73 vbool64_t test_vmmv_m_b64 (vbool64_t op1, size_t vl) {
74 return vmmv_m_b64(op1, vl);
75 }
76
77