1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86 87def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 88 SDTCisPtrTy<0>, SDTCisVT<1, i32> 89]>; 90 91def tocentry32 : Operand<iPTR> { 92 let MIOperandInfo = (ops i32imm:$imm); 93} 94 95def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 96 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 97]>; 98def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 99 SDTCisVec<0>, SDTCisInt<1> 100]>; 101def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 102 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 103]>; 104def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 106]>; 107 108def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 109 SDTCisVec<0>, SDTCisVec<1> 110]>; 111 112def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 113 SDTCisVec<0>, SDTCisPtrTy<1> 114]>; 115 116def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 118]>; 119 120def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 121 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 122]>; 123 124//===----------------------------------------------------------------------===// 125// PowerPC specific DAG Nodes. 126// 127 128def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 129def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 130def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 131def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 132 133def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 134def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 135def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 136def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 137def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 138def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 139def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 140def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 141 142def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 143 SDTFPUnaryOp, [SDNPHasChain]>; 144def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 145 SDTFPUnaryOp, [SDNPHasChain]>; 146def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 147 SDTFPRoundOp, [SDNPHasChain]>; 148def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 149 SDTFPRoundOp, [SDNPHasChain]>; 150 151def PPCany_fcfid : PatFrags<(ops node:$op), 152 [(PPCfcfid node:$op), 153 (PPCstrict_fcfid node:$op)]>; 154def PPCany_fcfidu : PatFrags<(ops node:$op), 155 [(PPCfcfidu node:$op), 156 (PPCstrict_fcfidu node:$op)]>; 157def PPCany_fcfids : PatFrags<(ops node:$op), 158 [(PPCfcfids node:$op), 159 (PPCstrict_fcfids node:$op)]>; 160def PPCany_fcfidus : PatFrags<(ops node:$op), 161 [(PPCfcfidus node:$op), 162 (PPCstrict_fcfidus node:$op)]>; 163 164def PPCcv_fp_to_uint_in_vsr: 165 SDNode<"PPCISD::FP_TO_UINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 166def PPCcv_fp_to_sint_in_vsr: 167 SDNode<"PPCISD::FP_TO_SINT_IN_VSR", SDT_PPCcv_fp_to_int, []>; 168def PPCstore_scal_int_from_vsr: 169 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 170 [SDNPHasChain, SDNPMayStore]>; 171def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 172 [SDNPHasChain, SDNPMayStore]>; 173def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 174 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 175def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 176 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 177def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 178 [SDNPHasChain, SDNPMayLoad]>; 179def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 180 [SDNPHasChain, SDNPMayStore]>; 181def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 182 183// Extract FPSCR (not modeled at the DAG level). 184def PPCmffs : SDNode<"PPCISD::MFFS", 185 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 186 [SDNPHasChain]>; 187 188// Perform FADD in round-to-zero mode. 189def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 190def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 191 [SDNPHasChain]>; 192 193def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 194 [(PPCfaddrtz node:$lhs, node:$rhs), 195 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 196 197def PPCfsel : SDNode<"PPCISD::FSEL", 198 // Type constraint for fsel. 199 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 200 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 201def PPCxsmaxc : SDNode<"PPCISD::XSMAXCDP", SDT_PPCFPMinMax, []>; 202def PPCxsminc : SDNode<"PPCISD::XSMINCDP", SDT_PPCFPMinMax, []>; 203def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 204def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 205def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 206 [SDNPMayLoad, SDNPMemOperand]>; 207 208def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 209 210def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 211def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 212 [SDNPMayLoad]>; 213def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 214def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 215def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 216def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 217def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 218 SDTypeProfile<1, 3, [ 219 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 220 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 221def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 222def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 223def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 224def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 225def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 226 SDTypeProfile<1, 3, [ 227 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 228 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 229def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 230def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 231def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 232 233def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 234def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 235def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 236def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 237def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 238def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 239 240def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 241 242// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 243// amounts. These nodes are generated by the multi-precision shift code. 244def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 245def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 246def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 247 248def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 249 250def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 251 252def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 253 SDTFPUnaryOp, [SDNPHasChain]>; 254def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 255 SDTFPUnaryOp, [SDNPHasChain]>; 256def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 257 SDTFPUnaryOp, [SDNPHasChain]>; 258def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 259 SDTFPUnaryOp, [SDNPHasChain]>; 260 261def PPCany_fctidz : PatFrags<(ops node:$op), 262 [(PPCstrict_fctidz node:$op), 263 (PPCfctidz node:$op)]>; 264def PPCany_fctiwz : PatFrags<(ops node:$op), 265 [(PPCstrict_fctiwz node:$op), 266 (PPCfctiwz node:$op)]>; 267def PPCany_fctiduz : PatFrags<(ops node:$op), 268 [(PPCstrict_fctiduz node:$op), 269 (PPCfctiduz node:$op)]>; 270def PPCany_fctiwuz : PatFrags<(ops node:$op), 271 [(PPCstrict_fctiwuz node:$op), 272 (PPCfctiwuz node:$op)]>; 273 274// Move 2 i64 values into a VSX register 275def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 276 SDTypeProfile<1, 2, 277 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 278 SDTCisSameAs<1,2>]>, 279 []>; 280 281def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 282 SDTypeProfile<1, 2, 283 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 284 SDTCisVT<1,i32>]>, 285 []>; 286 287def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 288 SDTypeProfile<1, 2, 289 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 290 SDTCisPtrTy<2>]>, 291 []>; 292 293// These are target-independent nodes, but have target-specific formats. 294def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 295 [SDNPHasChain, SDNPOutGlue]>; 296def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 297 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 298 299def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 300def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 301 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 302 SDNPVariadic]>; 303def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 304 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 305 SDNPVariadic]>; 306def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 307 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 308 SDNPVariadic]>; 309def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 310 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 311def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 312 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 313 SDNPVariadic]>; 314def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 315 SDTypeProfile<0, 1, []>, 316 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 317 SDNPVariadic]>; 318 319def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 320 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 321 322def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 323 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 324 325def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 326 SDTypeProfile<1, 1, [SDTCisInt<0>, 327 SDTCisPtrTy<1>]>, 328 [SDNPHasChain, SDNPSideEffect]>; 329def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 330 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 331 [SDNPHasChain, SDNPSideEffect]>; 332 333def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 334def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 335 [SDNPHasChain, SDNPSideEffect]>; 336 337def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 338 [SDNPHasChain, SDNPSideEffect]>; 339def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 340def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 341 [SDNPHasChain, SDNPSideEffect]>; 342 343def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 344def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 345 346def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 347 [SDNPHasChain, SDNPOptInGlue]>; 348 349// PPC-specific atomic operations. 350def PPCatomicCmpSwap_8 : 351 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 352 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 353def PPCatomicCmpSwap_16 : 354 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 355 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 356def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 357 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 358def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 359 [SDNPHasChain, SDNPMayStore]>; 360 361// Instructions to set/unset CR bit 6 for SVR4 vararg calls 362def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 363 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 364def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 365 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 366 367// Instructions to support dynamic alloca. 368def SDTDynOp : SDTypeProfile<1, 2, []>; 369def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 370def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 371def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 372def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 373 374// PC Relative Specific Nodes 375def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 376def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 377 SDTIntUnaryOp, []>; 378def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 379 SDTIntUnaryOp, []>; 380 381//===----------------------------------------------------------------------===// 382// PowerPC specific transformation functions and pattern fragments. 383// 384 385// A floating point immediate that is not a positive zero and can be converted 386// to a single precision floating point non-denormal immediate without loss of 387// information. 388def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 389 APFloat APFloatOfN = N->getValueAPF(); 390 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 391}]>; 392 393// Convert the floating point immediate into a 32 bit floating point immediate 394// and get a i32 with the resulting bits. 395def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 396 APFloat APFloatOfN = N->getValueAPF(); 397 convertToNonDenormSingle(APFloatOfN); 398 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 399 SDLoc(N), MVT::i32); 400}]>; 401 402// Check if the value can be converted to be single precision immediate, which 403// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 404// precision before exploiting with XXSPLTI32DX. 405def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 406 APFloat APFloatOfN = N->getValueAPF(); 407 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 408}]>; 409 410// Get the Hi bits of a 64 bit immediate. 411def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 412 APFloat APFloatOfN = N->getValueAPF(); 413 bool Unused; 414 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 415 &Unused); 416 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 417 0xFFFFFFFF00000000LL) >> 32); 418 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 419}]>; 420 421// Get the Lo bits of a 64 bit immediate. 422def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 423 APFloat APFloatOfN = N->getValueAPF(); 424 bool Unused; 425 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 426 &Unused); 427 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 428 0xFFFFFFFF); 429 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 430}]>; 431 432def imm34 : PatLeaf<(imm), [{ 433 return isInt<34>(N->getSExtValue()); 434}]>; 435 436def getImmAs64BitInt : SDNodeXForm<imm, [{ 437 return getI64Imm(N->getSExtValue(), SDLoc(N)); 438}]>; 439 440def SHL32 : SDNodeXForm<imm, [{ 441 // Transformation function: 31 - imm 442 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 443}]>; 444 445def SRL32 : SDNodeXForm<imm, [{ 446 // Transformation function: 32 - imm 447 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 448 : getI32Imm(0, SDLoc(N)); 449}]>; 450 451def LO16 : SDNodeXForm<imm, [{ 452 // Transformation function: get the low 16 bits. 453 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 454}]>; 455 456def HI16 : SDNodeXForm<imm, [{ 457 // Transformation function: shift the immediate value down into the low bits. 458 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 459}]>; 460 461def HA16 : SDNodeXForm<imm, [{ 462 // Transformation function: shift the immediate value down into the low bits. 463 long Val = N->getZExtValue(); 464 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 465}]>; 466def MB : SDNodeXForm<imm, [{ 467 // Transformation function: get the start bit of a mask 468 unsigned mb = 0, me; 469 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 470 return getI32Imm(mb, SDLoc(N)); 471}]>; 472 473def ME : SDNodeXForm<imm, [{ 474 // Transformation function: get the end bit of a mask 475 unsigned mb, me = 0; 476 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 477 return getI32Imm(me, SDLoc(N)); 478}]>; 479def maskimm32 : PatLeaf<(imm), [{ 480 // maskImm predicate - True if immediate is a run of ones. 481 unsigned mb, me; 482 if (N->getValueType(0) == MVT::i32) 483 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 484 else 485 return false; 486}]>; 487 488def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 489 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 490 // sign extended field. Used by instructions like 'addi'. 491 return (int32_t)Imm == (short)Imm; 492}]>; 493def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 494 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 495 // sign extended field. Used by instructions like 'addi'. 496 return (int64_t)Imm == (short)Imm; 497}]>; 498def immZExt16 : PatLeaf<(imm), [{ 499 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 500 // field. Used by instructions like 'ori'. 501 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 502}], LO16>; 503def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 504 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 505}]>; 506def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 507def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 508 509// imm16Shifted* - These match immediates where the low 16-bits are zero. There 510// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 511// identical in 32-bit mode, but in 64-bit mode, they return true if the 512// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 513// clear). 514def imm16ShiftedZExt : PatLeaf<(imm), [{ 515 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 516 // immediate are set. Used by instructions like 'xoris'. 517 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 518}], HI16>; 519 520def imm16ShiftedSExt : PatLeaf<(imm), [{ 521 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 522 // immediate are set. Used by instructions like 'addis'. Identical to 523 // imm16ShiftedZExt in 32-bit mode. 524 if (N->getZExtValue() & 0xFFFF) return false; 525 if (N->getValueType(0) == MVT::i32) 526 return true; 527 // For 64-bit, make sure it is sext right. 528 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 529}], HI16>; 530 531def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 532 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 533 // zero extended field. 534 return isUInt<32>(Imm); 535}]>; 536 537// This is a somewhat weaker condition than actually checking for 4-byte 538// alignment. It is simply checking that the displacement can be represented 539// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 540// instructions). 541// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 542// restricted memrix (4-aligned) constants are alignment sensitive. If these 543// offsets are hidden behind TOC entries than the values of the lower-order 544// bits cannot be checked directly. As a result, we need to also incorporate 545// an alignment check into the relevant patterns. 546 547def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 548 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; 549}]>; 550def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 551 (store node:$val, node:$ptr), [{ 552 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; 553}]>; 554def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 555 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlignment() >= 4; 556}]>; 557def DSFormPreStore : PatFrag< 558 (ops node:$val, node:$base, node:$offset), 559 (pre_store node:$val, node:$base, node:$offset), [{ 560 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlignment() >= 4; 561}]>; 562 563def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 564 return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 565}]>; 566def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 567 (store node:$val, node:$ptr), [{ 568 return cast<StoreSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 569}]>; 570def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 571 return cast<LoadSDNode>(N)->getAlignment() < 4 && !isOffsetMultipleOf(N, 4); 572}]>; 573 574// This is a somewhat weaker condition than actually checking for 16-byte 575// alignment. It is simply checking that the displacement can be represented 576// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 577// instructions). 578def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 579 return isOffsetMultipleOf(N, 16); 580}]>; 581def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 582 (store node:$val, node:$ptr), [{ 583 return isOffsetMultipleOf(N, 16); 584}]>; 585def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 586 return !isOffsetMultipleOf(N, 16); 587}]>; 588def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 589 (store node:$val, node:$ptr), [{ 590 return !isOffsetMultipleOf(N, 16); 591}]>; 592 593// PatFrag for binary operation whose operands are both non-constant 594class BinOpWithoutSImm16Operand<SDNode opcode> : 595 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 596 int16_t Imm; 597 return !isIntS16Immediate(N->getOperand(0), Imm) 598 && !isIntS16Immediate(N->getOperand(1), Imm); 599}]>; 600 601def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 602def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 603 604//===----------------------------------------------------------------------===// 605// PowerPC Flag Definitions. 606 607class isPPC64 { bit PPC64 = 1; } 608class isRecordForm { bit RC = 1; } 609 610class RegConstraint<string C> { 611 string Constraints = C; 612} 613class NoEncode<string E> { 614 string DisableEncoding = E; 615} 616 617 618//===----------------------------------------------------------------------===// 619// PowerPC Operand Definitions. 620 621// In the default PowerPC assembler syntax, registers are specified simply 622// by number, so they cannot be distinguished from immediate values (without 623// looking at the opcode). This means that the default operand matching logic 624// for the asm parser does not work, and we need to specify custom matchers. 625// Since those can only be specified with RegisterOperand classes and not 626// directly on the RegisterClass, all instructions patterns used by the asm 627// parser need to use a RegisterOperand (instead of a RegisterClass) for 628// all their register operands. 629// For this purpose, we define one RegisterOperand for each RegisterClass, 630// using the same name as the class, just in lower case. 631 632def PPCRegGPRCAsmOperand : AsmOperandClass { 633 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 634} 635def gprc : RegisterOperand<GPRC> { 636 let ParserMatchClass = PPCRegGPRCAsmOperand; 637} 638def PPCRegG8RCAsmOperand : AsmOperandClass { 639 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 640} 641def g8rc : RegisterOperand<G8RC> { 642 let ParserMatchClass = PPCRegG8RCAsmOperand; 643} 644def PPCRegG8pRCAsmOperand : AsmOperandClass { 645 let Name = "RegG8pRC"; let PredicateMethod = "isEvenRegNumber"; 646} 647def g8prc : RegisterOperand<G8pRC> { 648 let ParserMatchClass = PPCRegG8pRCAsmOperand; 649} 650def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 651 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 652} 653def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 654 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 655} 656def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 657 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 658} 659def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 660 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 661} 662def PPCRegF8RCAsmOperand : AsmOperandClass { 663 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 664} 665def f8rc : RegisterOperand<F8RC> { 666 let ParserMatchClass = PPCRegF8RCAsmOperand; 667} 668def PPCRegF4RCAsmOperand : AsmOperandClass { 669 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 670} 671def f4rc : RegisterOperand<F4RC> { 672 let ParserMatchClass = PPCRegF4RCAsmOperand; 673} 674def PPCRegVRRCAsmOperand : AsmOperandClass { 675 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 676} 677def vrrc : RegisterOperand<VRRC> { 678 let ParserMatchClass = PPCRegVRRCAsmOperand; 679} 680def PPCRegVFRCAsmOperand : AsmOperandClass { 681 let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; 682} 683def vfrc : RegisterOperand<VFRC> { 684 let ParserMatchClass = PPCRegVFRCAsmOperand; 685} 686def PPCRegCRBITRCAsmOperand : AsmOperandClass { 687 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 688} 689def crbitrc : RegisterOperand<CRBITRC> { 690 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 691} 692def PPCRegCRRCAsmOperand : AsmOperandClass { 693 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 694} 695def crrc : RegisterOperand<CRRC> { 696 let ParserMatchClass = PPCRegCRRCAsmOperand; 697} 698def PPCRegSPERCAsmOperand : AsmOperandClass { 699 let Name = "RegSPERC"; let PredicateMethod = "isRegNumber"; 700} 701def sperc : RegisterOperand<SPERC> { 702 let ParserMatchClass = PPCRegSPERCAsmOperand; 703} 704def PPCRegSPE4RCAsmOperand : AsmOperandClass { 705 let Name = "RegSPE4RC"; let PredicateMethod = "isRegNumber"; 706} 707def spe4rc : RegisterOperand<GPRC> { 708 let ParserMatchClass = PPCRegSPE4RCAsmOperand; 709} 710 711def PPCU1ImmAsmOperand : AsmOperandClass { 712 let Name = "U1Imm"; let PredicateMethod = "isU1Imm"; 713 let RenderMethod = "addImmOperands"; 714} 715def u1imm : Operand<i32> { 716 let PrintMethod = "printU1ImmOperand"; 717 let ParserMatchClass = PPCU1ImmAsmOperand; 718 let OperandType = "OPERAND_IMMEDIATE"; 719} 720 721def PPCU2ImmAsmOperand : AsmOperandClass { 722 let Name = "U2Imm"; let PredicateMethod = "isU2Imm"; 723 let RenderMethod = "addImmOperands"; 724} 725def u2imm : Operand<i32> { 726 let PrintMethod = "printU2ImmOperand"; 727 let ParserMatchClass = PPCU2ImmAsmOperand; 728 let OperandType = "OPERAND_IMMEDIATE"; 729} 730 731def PPCATBitsAsHintAsmOperand : AsmOperandClass { 732 let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; 733 let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. 734} 735def atimm : Operand<i32> { 736 let PrintMethod = "printATBitsAsHint"; 737 let ParserMatchClass = PPCATBitsAsHintAsmOperand; 738 let OperandType = "OPERAND_IMMEDIATE"; 739} 740 741def PPCU3ImmAsmOperand : AsmOperandClass { 742 let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; 743 let RenderMethod = "addImmOperands"; 744} 745def u3imm : Operand<i32> { 746 let PrintMethod = "printU3ImmOperand"; 747 let ParserMatchClass = PPCU3ImmAsmOperand; 748 let OperandType = "OPERAND_IMMEDIATE"; 749} 750 751def PPCU4ImmAsmOperand : AsmOperandClass { 752 let Name = "U4Imm"; let PredicateMethod = "isU4Imm"; 753 let RenderMethod = "addImmOperands"; 754} 755def u4imm : Operand<i32> { 756 let PrintMethod = "printU4ImmOperand"; 757 let ParserMatchClass = PPCU4ImmAsmOperand; 758 let OperandType = "OPERAND_IMMEDIATE"; 759} 760def PPCS5ImmAsmOperand : AsmOperandClass { 761 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 762 let RenderMethod = "addImmOperands"; 763} 764def s5imm : Operand<i32> { 765 let PrintMethod = "printS5ImmOperand"; 766 let ParserMatchClass = PPCS5ImmAsmOperand; 767 let DecoderMethod = "decodeSImmOperand<5>"; 768 let OperandType = "OPERAND_IMMEDIATE"; 769} 770def PPCU5ImmAsmOperand : AsmOperandClass { 771 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 772 let RenderMethod = "addImmOperands"; 773} 774def u5imm : Operand<i32> { 775 let PrintMethod = "printU5ImmOperand"; 776 let ParserMatchClass = PPCU5ImmAsmOperand; 777 let DecoderMethod = "decodeUImmOperand<5>"; 778 let OperandType = "OPERAND_IMMEDIATE"; 779} 780def PPCU6ImmAsmOperand : AsmOperandClass { 781 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 782 let RenderMethod = "addImmOperands"; 783} 784def u6imm : Operand<i32> { 785 let PrintMethod = "printU6ImmOperand"; 786 let ParserMatchClass = PPCU6ImmAsmOperand; 787 let DecoderMethod = "decodeUImmOperand<6>"; 788 let OperandType = "OPERAND_IMMEDIATE"; 789} 790def PPCU7ImmAsmOperand : AsmOperandClass { 791 let Name = "U7Imm"; let PredicateMethod = "isU7Imm"; 792 let RenderMethod = "addImmOperands"; 793} 794def u7imm : Operand<i32> { 795 let PrintMethod = "printU7ImmOperand"; 796 let ParserMatchClass = PPCU7ImmAsmOperand; 797 let DecoderMethod = "decodeUImmOperand<7>"; 798 let OperandType = "OPERAND_IMMEDIATE"; 799} 800def PPCU8ImmAsmOperand : AsmOperandClass { 801 let Name = "U8Imm"; let PredicateMethod = "isU8Imm"; 802 let RenderMethod = "addImmOperands"; 803} 804def u8imm : Operand<i32> { 805 let PrintMethod = "printU8ImmOperand"; 806 let ParserMatchClass = PPCU8ImmAsmOperand; 807 let DecoderMethod = "decodeUImmOperand<8>"; 808 let OperandType = "OPERAND_IMMEDIATE"; 809} 810def PPCU10ImmAsmOperand : AsmOperandClass { 811 let Name = "U10Imm"; let PredicateMethod = "isU10Imm"; 812 let RenderMethod = "addImmOperands"; 813} 814def u10imm : Operand<i32> { 815 let PrintMethod = "printU10ImmOperand"; 816 let ParserMatchClass = PPCU10ImmAsmOperand; 817 let DecoderMethod = "decodeUImmOperand<10>"; 818 let OperandType = "OPERAND_IMMEDIATE"; 819} 820def PPCU12ImmAsmOperand : AsmOperandClass { 821 let Name = "U12Imm"; let PredicateMethod = "isU12Imm"; 822 let RenderMethod = "addImmOperands"; 823} 824def u12imm : Operand<i32> { 825 let PrintMethod = "printU12ImmOperand"; 826 let ParserMatchClass = PPCU12ImmAsmOperand; 827 let DecoderMethod = "decodeUImmOperand<12>"; 828 let OperandType = "OPERAND_IMMEDIATE"; 829} 830def PPCS16ImmAsmOperand : AsmOperandClass { 831 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 832 let RenderMethod = "addS16ImmOperands"; 833} 834def s16imm : Operand<i32> { 835 let PrintMethod = "printS16ImmOperand"; 836 let EncoderMethod = "getImm16Encoding"; 837 let ParserMatchClass = PPCS16ImmAsmOperand; 838 let DecoderMethod = "decodeSImmOperand<16>"; 839 let OperandType = "OPERAND_IMMEDIATE"; 840} 841def PPCU16ImmAsmOperand : AsmOperandClass { 842 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 843 let RenderMethod = "addU16ImmOperands"; 844} 845def u16imm : Operand<i32> { 846 let PrintMethod = "printU16ImmOperand"; 847 let EncoderMethod = "getImm16Encoding"; 848 let ParserMatchClass = PPCU16ImmAsmOperand; 849 let DecoderMethod = "decodeUImmOperand<16>"; 850 let OperandType = "OPERAND_IMMEDIATE"; 851} 852def PPCS17ImmAsmOperand : AsmOperandClass { 853 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 854 let RenderMethod = "addS16ImmOperands"; 855} 856def s17imm : Operand<i32> { 857 // This operand type is used for addis/lis to allow the assembler parser 858 // to accept immediates in the range -65536..65535 for compatibility with 859 // the GNU assembler. The operand is treated as 16-bit otherwise. 860 let PrintMethod = "printS16ImmOperand"; 861 let EncoderMethod = "getImm16Encoding"; 862 let ParserMatchClass = PPCS17ImmAsmOperand; 863 let DecoderMethod = "decodeSImmOperand<16>"; 864 let OperandType = "OPERAND_IMMEDIATE"; 865} 866def PPCS34ImmAsmOperand : AsmOperandClass { 867 let Name = "S34Imm"; 868 let PredicateMethod = "isS34Imm"; 869 let RenderMethod = "addImmOperands"; 870} 871def s34imm : Operand<i64> { 872 let PrintMethod = "printS34ImmOperand"; 873 let EncoderMethod = "getImm34EncodingNoPCRel"; 874 let ParserMatchClass = PPCS34ImmAsmOperand; 875 let DecoderMethod = "decodeSImmOperand<34>"; 876 let OperandType = "OPERAND_IMMEDIATE"; 877} 878def s34imm_pcrel : Operand<i64> { 879 let PrintMethod = "printS34ImmOperand"; 880 let EncoderMethod = "getImm34EncodingPCRel"; 881 let ParserMatchClass = PPCS34ImmAsmOperand; 882 let DecoderMethod = "decodeSImmOperand<34>"; 883 let OperandType = "OPERAND_IMMEDIATE"; 884} 885def PPCImmZeroAsmOperand : AsmOperandClass { 886 let Name = "ImmZero"; 887 let PredicateMethod = "isImmZero"; 888 let RenderMethod = "addImmOperands"; 889} 890def immZero : Operand<i32> { 891 let PrintMethod = "printImmZeroOperand"; 892 let ParserMatchClass = PPCImmZeroAsmOperand; 893 let DecoderMethod = "decodeImmZeroOperand"; 894 let OperandType = "OPERAND_IMMEDIATE"; 895} 896 897def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 898 899def PPCDirectBrAsmOperand : AsmOperandClass { 900 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 901 let RenderMethod = "addBranchTargetOperands"; 902} 903def directbrtarget : Operand<OtherVT> { 904 let PrintMethod = "printBranchOperand"; 905 let EncoderMethod = "getDirectBrEncoding"; 906 let DecoderMethod = "decodeDirectBrTarget"; 907 let ParserMatchClass = PPCDirectBrAsmOperand; 908 let OperandType = "OPERAND_PCREL"; 909} 910def absdirectbrtarget : Operand<OtherVT> { 911 let PrintMethod = "printAbsBranchOperand"; 912 let EncoderMethod = "getAbsDirectBrEncoding"; 913 let ParserMatchClass = PPCDirectBrAsmOperand; 914} 915def PPCCondBrAsmOperand : AsmOperandClass { 916 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 917 let RenderMethod = "addBranchTargetOperands"; 918} 919def condbrtarget : Operand<OtherVT> { 920 let PrintMethod = "printBranchOperand"; 921 let EncoderMethod = "getCondBrEncoding"; 922 let DecoderMethod = "decodeCondBrTarget"; 923 let ParserMatchClass = PPCCondBrAsmOperand; 924 let OperandType = "OPERAND_PCREL"; 925} 926def abscondbrtarget : Operand<OtherVT> { 927 let PrintMethod = "printAbsBranchOperand"; 928 let EncoderMethod = "getAbsCondBrEncoding"; 929 let ParserMatchClass = PPCCondBrAsmOperand; 930} 931def calltarget : Operand<iPTR> { 932 let PrintMethod = "printBranchOperand"; 933 let EncoderMethod = "getDirectBrEncoding"; 934 let DecoderMethod = "decodeDirectBrTarget"; 935 let ParserMatchClass = PPCDirectBrAsmOperand; 936 let OperandType = "OPERAND_PCREL"; 937} 938def abscalltarget : Operand<iPTR> { 939 let PrintMethod = "printAbsBranchOperand"; 940 let EncoderMethod = "getAbsDirectBrEncoding"; 941 let ParserMatchClass = PPCDirectBrAsmOperand; 942} 943def PPCCRBitMaskOperand : AsmOperandClass { 944 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 945} 946def crbitm: Operand<i8> { 947 let PrintMethod = "printcrbitm"; 948 let EncoderMethod = "get_crbitm_encoding"; 949 let DecoderMethod = "decodeCRBitMOperand"; 950 let ParserMatchClass = PPCCRBitMaskOperand; 951} 952// Address operands 953// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 954def PPCRegGxRCNoR0Operand : AsmOperandClass { 955 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 956} 957def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 958 let ParserMatchClass = PPCRegGxRCNoR0Operand; 959} 960 961// New addressing modes with 34 bit immediates. 962def PPCDispRI34Operand : AsmOperandClass { 963 let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; 964 let RenderMethod = "addImmOperands"; 965} 966def dispRI34 : Operand<iPTR> { 967 let ParserMatchClass = PPCDispRI34Operand; 968} 969def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value. 970 let PrintMethod = "printMemRegImm34"; 971 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 972 let EncoderMethod = "getMemRI34Encoding"; 973 let DecoderMethod = "decodeMemRI34Operands"; 974} 975// memri, imm is a 34-bit value for pc-relative instructions where 976// base register is set to zero. 977def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value. 978 let PrintMethod = "printMemRegImm34PCRel"; 979 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 980 let EncoderMethod = "getMemRI34PCRelEncoding"; 981 let DecoderMethod = "decodeMemRI34PCRelOperands"; 982} 983 984// A version of ptr_rc usable with the asm parser. 985def PPCRegGxRCOperand : AsmOperandClass { 986 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 987} 988def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 989 let ParserMatchClass = PPCRegGxRCOperand; 990} 991 992def PPCDispRIOperand : AsmOperandClass { 993 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 994 let RenderMethod = "addS16ImmOperands"; 995} 996def dispRI : Operand<iPTR> { 997 let ParserMatchClass = PPCDispRIOperand; 998} 999def PPCDispRIXOperand : AsmOperandClass { 1000 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 1001 let RenderMethod = "addImmOperands"; 1002} 1003def dispRIX : Operand<iPTR> { 1004 let ParserMatchClass = PPCDispRIXOperand; 1005} 1006def PPCDispRIHashOperand : AsmOperandClass { 1007 let Name = "DispRIHash"; let PredicateMethod = "isHashImmX8"; 1008 let RenderMethod = "addImmOperands"; 1009} 1010def dispRIHash : Operand<iPTR> { 1011 let ParserMatchClass = PPCDispRIHashOperand; 1012} 1013def PPCDispRIX16Operand : AsmOperandClass { 1014 let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16"; 1015 let RenderMethod = "addImmOperands"; 1016} 1017def dispRIX16 : Operand<iPTR> { 1018 let ParserMatchClass = PPCDispRIX16Operand; 1019} 1020def PPCDispSPE8Operand : AsmOperandClass { 1021 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8"; 1022 let RenderMethod = "addImmOperands"; 1023} 1024def dispSPE8 : Operand<iPTR> { 1025 let ParserMatchClass = PPCDispSPE8Operand; 1026} 1027def PPCDispSPE4Operand : AsmOperandClass { 1028 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4"; 1029 let RenderMethod = "addImmOperands"; 1030} 1031def dispSPE4 : Operand<iPTR> { 1032 let ParserMatchClass = PPCDispSPE4Operand; 1033} 1034def PPCDispSPE2Operand : AsmOperandClass { 1035 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2"; 1036 let RenderMethod = "addImmOperands"; 1037} 1038def dispSPE2 : Operand<iPTR> { 1039 let ParserMatchClass = PPCDispSPE2Operand; 1040} 1041 1042def memri : Operand<iPTR> { 1043 let PrintMethod = "printMemRegImm"; 1044 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 1045 let EncoderMethod = "getMemRIEncoding"; 1046 let DecoderMethod = "decodeMemRIOperands"; 1047 let OperandType = "OPERAND_MEMORY"; 1048} 1049def memrr : Operand<iPTR> { 1050 let PrintMethod = "printMemRegReg"; 1051 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 1052 let OperandType = "OPERAND_MEMORY"; 1053} 1054def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 1055 let PrintMethod = "printMemRegImm"; 1056 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 1057 let EncoderMethod = "getMemRIXEncoding"; 1058 let DecoderMethod = "decodeMemRIXOperands"; 1059 let OperandType = "OPERAND_MEMORY"; 1060} 1061def memrihash : Operand<iPTR> { 1062 // memrihash 8-aligned for ROP Protection Instructions. 1063 let PrintMethod = "printMemRegImmHash"; 1064 let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg); 1065 let EncoderMethod = "getMemRIHashEncoding"; 1066 let DecoderMethod = "decodeMemRIHashOperands"; 1067 let OperandType = "OPERAND_MEMORY"; 1068} 1069def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27} 1070 let PrintMethod = "printMemRegImm"; 1071 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 1072 let EncoderMethod = "getMemRIX16Encoding"; 1073 let DecoderMethod = "decodeMemRIX16Operands"; 1074 let OperandType = "OPERAND_MEMORY"; 1075} 1076def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned. 1077 let PrintMethod = "printMemRegImm"; 1078 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 1079 let EncoderMethod = "getSPE8DisEncoding"; 1080 let DecoderMethod = "decodeSPE8Operands"; 1081 let OperandType = "OPERAND_MEMORY"; 1082} 1083def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned. 1084 let PrintMethod = "printMemRegImm"; 1085 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 1086 let EncoderMethod = "getSPE4DisEncoding"; 1087 let DecoderMethod = "decodeSPE4Operands"; 1088 let OperandType = "OPERAND_MEMORY"; 1089} 1090def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned. 1091 let PrintMethod = "printMemRegImm"; 1092 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 1093 let EncoderMethod = "getSPE2DisEncoding"; 1094 let DecoderMethod = "decodeSPE2Operands"; 1095 let OperandType = "OPERAND_MEMORY"; 1096} 1097 1098// A single-register address. This is used with the SjLj 1099// pseudo-instructions which translates to LD/LWZ. These instructions requires 1100// G8RC_NOX0 registers. 1101def memr : Operand<iPTR> { 1102 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); 1103 let OperandType = "OPERAND_MEMORY"; 1104} 1105def PPCTLSRegOperand : AsmOperandClass { 1106 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 1107 let RenderMethod = "addTLSRegOperands"; 1108} 1109def tlsreg32 : Operand<i32> { 1110 let EncoderMethod = "getTLSRegEncoding"; 1111 let ParserMatchClass = PPCTLSRegOperand; 1112} 1113def tlsgd32 : Operand<i32> {} 1114def tlscall32 : Operand<i32> { 1115 let PrintMethod = "printTLSCall"; 1116 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym); 1117 let EncoderMethod = "getTLSCallEncoding"; 1118} 1119 1120// PowerPC Predicate operand. 1121def pred : Operand<OtherVT> { 1122 let PrintMethod = "printPredicateOperand"; 1123 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 1124} 1125 1126// Define PowerPC specific addressing mode. 1127 1128// d-form 1129def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 1130// ds-form 1131def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 1132// dq-form 1133def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 1134// 8LS:d-form 1135def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 1136 1137// Below forms are all x-form addressing mode, use three different ones so we 1138// can make a accurate check for x-form instructions in ISEL. 1139// x-form addressing mode whose associated displacement form is D. 1140def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 1141// x-form addressing mode whose associated displacement form is DS. 1142def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 1143// x-form addressing mode whose associated displacement form is DQ. 1144def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 1145 1146def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 1147 1148// The address in a single register. This is used with the SjLj 1149// pseudo-instructions. 1150def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 1151 1152/// This is just the offset part of iaddr, used for preinc. 1153def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 1154 1155// PC Relative Address 1156def pcreladdr : ComplexPattern<iPTR, 1, "SelectAddrPCRel", [], []>; 1157 1158// Load and Store Instruction Selection addressing modes. 1159def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>; 1160def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>; 1161def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>; 1162def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>; 1163def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>; 1164 1165//===----------------------------------------------------------------------===// 1166// PowerPC Instruction Predicate Definitions. 1167def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 1168def In64BitMode : Predicate<"Subtarget->isPPC64()">; 1169def IsBookE : Predicate<"Subtarget->isBookE()">; 1170def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 1171def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 1172def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 1173def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 1174def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 1175def IsE500 : Predicate<"Subtarget->isE500()">; 1176def HasSPE : Predicate<"Subtarget->hasSPE()">; 1177def HasICBT : Predicate<"Subtarget->hasICBT()">; 1178def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 1179def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 1180def NoNaNsFPMath 1181 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 1182def NaNsFPMath 1183 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 1184def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 1185def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 1186def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 1187def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 1188def HasFPU : Predicate<"Subtarget->hasFPU()">; 1189def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 1190def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 1191 1192// AIX assembler may not be modern enough to support some extended mne. 1193def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 1194 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 1195def IsAIX : Predicate<"Subtarget->isAIXABI()">; 1196def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 1197 1198//===----------------------------------------------------------------------===// 1199// PowerPC Multiclass Definitions. 1200 1201multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1202 string asmbase, string asmstr, InstrItinClass itin, 1203 list<dag> pattern> { 1204 let BaseName = asmbase in { 1205 def NAME : XForm_6<opcode, xo, OOL, IOL, 1206 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1207 pattern>, RecFormRel; 1208 let Defs = [CR0] in 1209 def _rec : XForm_6<opcode, xo, OOL, IOL, 1210 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1211 []>, isRecordForm, RecFormRel; 1212 } 1213} 1214 1215multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1216 string asmbase, string asmstr, InstrItinClass itin, 1217 list<dag> pattern> { 1218 let BaseName = asmbase in { 1219 let Defs = [CARRY] in 1220 def NAME : XForm_6<opcode, xo, OOL, IOL, 1221 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1222 pattern>, RecFormRel; 1223 let Defs = [CARRY, CR0] in 1224 def _rec : XForm_6<opcode, xo, OOL, IOL, 1225 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1226 []>, isRecordForm, RecFormRel; 1227 } 1228} 1229 1230multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1231 string asmbase, string asmstr, InstrItinClass itin, 1232 list<dag> pattern> { 1233 let BaseName = asmbase in { 1234 let Defs = [CARRY] in 1235 def NAME : XForm_10<opcode, xo, OOL, IOL, 1236 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1237 pattern>, RecFormRel; 1238 let Defs = [CARRY, CR0] in 1239 def _rec : XForm_10<opcode, xo, OOL, IOL, 1240 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1241 []>, isRecordForm, RecFormRel; 1242 } 1243} 1244 1245multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1246 string asmbase, string asmstr, InstrItinClass itin, 1247 list<dag> pattern> { 1248 let BaseName = asmbase in { 1249 def NAME : XForm_11<opcode, xo, OOL, IOL, 1250 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1251 pattern>, RecFormRel; 1252 let Defs = [CR0] in 1253 def _rec : XForm_11<opcode, xo, OOL, IOL, 1254 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1255 []>, isRecordForm, RecFormRel; 1256 } 1257} 1258 1259multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1260 string asmbase, string asmstr, InstrItinClass itin, 1261 list<dag> pattern> { 1262 let BaseName = asmbase in { 1263 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1264 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1265 pattern>, RecFormRel; 1266 let Defs = [CR0] in 1267 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1268 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1269 []>, isRecordForm, RecFormRel; 1270 } 1271} 1272 1273// Multiclass for instructions which have a record overflow form as well 1274// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 1275multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1276 string asmbase, string asmstr, InstrItinClass itin, 1277 list<dag> pattern> { 1278 let BaseName = asmbase in { 1279 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 1280 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1281 pattern>, RecFormRel; 1282 let Defs = [CR0] in 1283 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 1284 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1285 []>, isRecordForm, RecFormRel; 1286 } 1287 let BaseName = !strconcat(asmbase, "O") in { 1288 let Defs = [XER] in 1289 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1290 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1291 []>, RecFormRel; 1292 let Defs = [XER, CR0] in 1293 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1294 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1295 []>, isRecordForm, RecFormRel; 1296 } 1297} 1298 1299// Multiclass for instructions for which the non record form is not cracked 1300// and the record form is cracked (i.e. divw, mullw, etc.) 1301multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1302 string asmbase, string asmstr, InstrItinClass itin, 1303 list<dag> pattern> { 1304 let BaseName = asmbase in { 1305 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1306 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1307 pattern>, RecFormRel; 1308 let Defs = [CR0] in 1309 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1310 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1311 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 1312 PPC970_DGroup_Cracked; 1313 } 1314 let BaseName = !strconcat(asmbase, "O") in { 1315 let Defs = [XER] in 1316 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1317 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1318 []>, RecFormRel; 1319 let Defs = [XER, CR0] in 1320 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1321 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1322 []>, isRecordForm, RecFormRel; 1323 } 1324} 1325 1326multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1327 string asmbase, string asmstr, InstrItinClass itin, 1328 list<dag> pattern> { 1329 let BaseName = asmbase in { 1330 let Defs = [CARRY] in 1331 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 1332 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1333 pattern>, RecFormRel; 1334 let Defs = [CARRY, CR0] in 1335 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 1336 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1337 []>, isRecordForm, RecFormRel; 1338 } 1339 let BaseName = !strconcat(asmbase, "O") in { 1340 let Defs = [CARRY, XER] in 1341 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 1342 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1343 []>, RecFormRel; 1344 let Defs = [CARRY, XER, CR0] in 1345 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 1346 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1347 []>, isRecordForm, RecFormRel; 1348 } 1349} 1350 1351multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1352 string asmbase, string asmstr, InstrItinClass itin, 1353 list<dag> pattern> { 1354 let BaseName = asmbase in { 1355 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1356 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1357 pattern>, RecFormRel; 1358 let Defs = [CR0] in 1359 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1360 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1361 []>, isRecordForm, RecFormRel; 1362 } 1363 let BaseName = !strconcat(asmbase, "O") in { 1364 let Defs = [XER] in 1365 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1366 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1367 []>, RecFormRel; 1368 let Defs = [XER, CR0] in 1369 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1370 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1371 []>, isRecordForm, RecFormRel; 1372 } 1373} 1374 1375multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 1376 string asmbase, string asmstr, InstrItinClass itin, 1377 list<dag> pattern> { 1378 let BaseName = asmbase in { 1379 let Defs = [CARRY] in 1380 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 1381 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1382 pattern>, RecFormRel; 1383 let Defs = [CARRY, CR0] in 1384 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 1385 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1386 []>, isRecordForm, RecFormRel; 1387 } 1388 let BaseName = !strconcat(asmbase, "O") in { 1389 let Defs = [CARRY, XER] in 1390 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 1391 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 1392 []>, RecFormRel; 1393 let Defs = [CARRY, XER, CR0] in 1394 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 1395 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 1396 []>, isRecordForm, RecFormRel; 1397 } 1398} 1399 1400multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 1401 string asmbase, string asmstr, InstrItinClass itin, 1402 list<dag> pattern> { 1403 let BaseName = asmbase in { 1404 def NAME : MForm_2<opcode, OOL, IOL, 1405 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1406 pattern>, RecFormRel; 1407 let Defs = [CR0] in 1408 def _rec : MForm_2<opcode, OOL, IOL, 1409 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1410 []>, isRecordForm, RecFormRel; 1411 } 1412} 1413 1414multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 1415 string asmbase, string asmstr, InstrItinClass itin, 1416 list<dag> pattern> { 1417 let BaseName = asmbase in { 1418 def NAME : MDForm_1<opcode, xo, OOL, IOL, 1419 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1420 pattern>, RecFormRel; 1421 let Defs = [CR0] in 1422 def _rec : MDForm_1<opcode, xo, OOL, IOL, 1423 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1424 []>, isRecordForm, RecFormRel; 1425 } 1426} 1427 1428multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 1429 string asmbase, string asmstr, InstrItinClass itin, 1430 list<dag> pattern> { 1431 let BaseName = asmbase in { 1432 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 1433 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1434 pattern>, RecFormRel; 1435 let Defs = [CR0] in 1436 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 1437 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1438 []>, isRecordForm, RecFormRel; 1439 } 1440} 1441 1442multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1443 string asmbase, string asmstr, InstrItinClass itin, 1444 list<dag> pattern> { 1445 let BaseName = asmbase in { 1446 let Defs = [CARRY] in 1447 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1448 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1449 pattern>, RecFormRel; 1450 let Defs = [CARRY, CR0] in 1451 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1452 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1453 []>, isRecordForm, RecFormRel; 1454 } 1455} 1456 1457multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1458 string asmbase, string asmstr, InstrItinClass itin, 1459 list<dag> pattern> { 1460 let BaseName = asmbase in { 1461 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1462 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1463 pattern>, RecFormRel; 1464 let Defs = [CR0] in 1465 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1466 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1467 []>, isRecordForm, RecFormRel; 1468 } 1469} 1470 1471multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1472 string asmbase, string asmstr, InstrItinClass itin, 1473 list<dag> pattern> { 1474 let BaseName = asmbase in { 1475 def NAME : XForm_26<opcode, xo, OOL, IOL, 1476 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1477 pattern>, RecFormRel; 1478 let Defs = [CR1] in 1479 def _rec : XForm_26<opcode, xo, OOL, IOL, 1480 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1481 []>, isRecordForm, RecFormRel; 1482 } 1483} 1484 1485multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1486 string asmbase, string asmstr, InstrItinClass itin, 1487 list<dag> pattern> { 1488 let BaseName = asmbase in { 1489 def NAME : XForm_28<opcode, xo, OOL, IOL, 1490 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1491 pattern>, RecFormRel; 1492 let Defs = [CR1] in 1493 def _rec : XForm_28<opcode, xo, OOL, IOL, 1494 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1495 []>, isRecordForm, RecFormRel; 1496 } 1497} 1498 1499multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1500 string asmbase, string asmstr, InstrItinClass itin, 1501 list<dag> pattern> { 1502 let BaseName = asmbase in { 1503 def NAME : AForm_1<opcode, xo, OOL, IOL, 1504 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1505 pattern>, RecFormRel; 1506 let Defs = [CR1] in 1507 def _rec : AForm_1<opcode, xo, OOL, IOL, 1508 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1509 []>, isRecordForm, RecFormRel; 1510 } 1511} 1512 1513multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1514 string asmbase, string asmstr, InstrItinClass itin, 1515 list<dag> pattern> { 1516 let BaseName = asmbase in { 1517 def NAME : AForm_2<opcode, xo, OOL, IOL, 1518 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1519 pattern>, RecFormRel; 1520 let Defs = [CR1] in 1521 def _rec : AForm_2<opcode, xo, OOL, IOL, 1522 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1523 []>, isRecordForm, RecFormRel; 1524 } 1525} 1526 1527multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1528 string asmbase, string asmstr, InstrItinClass itin, 1529 list<dag> pattern> { 1530 let BaseName = asmbase in { 1531 def NAME : AForm_3<opcode, xo, OOL, IOL, 1532 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1533 pattern>, RecFormRel; 1534 let Defs = [CR1] in 1535 def _rec : AForm_3<opcode, xo, OOL, IOL, 1536 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1537 []>, isRecordForm, RecFormRel; 1538 } 1539} 1540 1541//===----------------------------------------------------------------------===// 1542// PowerPC Instruction Definitions. 1543 1544// Pseudo instructions: 1545 1546let hasCtrlDep = 1 in { 1547let Defs = [R1], Uses = [R1] in { 1548def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1549 "#ADJCALLSTACKDOWN $amt1 $amt2", 1550 [(callseq_start timm:$amt1, timm:$amt2)]>; 1551def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1552 "#ADJCALLSTACKUP $amt1 $amt2", 1553 [(callseq_end timm:$amt1, timm:$amt2)]>; 1554} 1555} // hasCtrlDep 1556 1557let Defs = [R1], Uses = [R1] in 1558def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1559 [(set i32:$result, 1560 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1561def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1562 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1563// Probed alloca to support stack clash protection. 1564let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1565def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1566 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1567 [(set i32:$result, 1568 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1569def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1570 gprc:$fp, gprc:$actual_negsize), 1571 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1572def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1573 gprc:$fp, gprc:$actual_negsize), 1574 (ins gprc:$negsize, memri:$fpsi), 1575 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1576 RegConstraint<"$actual_negsize = $negsize">; 1577def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1578 (ins i64imm:$stacksize), 1579 "#PROBED_STACKALLOC_32", []>; 1580} 1581 1582// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1583// instruction selection into a branch sequence. 1584let PPC970_Single = 1 in { 1585 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1586 // because either operand might become the first operand in an isel, and 1587 // that operand cannot be r0. 1588 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1589 gprc_nor0:$T, gprc_nor0:$F, 1590 i32imm:$BROPC), "#SELECT_CC_I4", 1591 []>; 1592 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1593 g8rc_nox0:$T, g8rc_nox0:$F, 1594 i32imm:$BROPC), "#SELECT_CC_I8", 1595 []>; 1596 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1597 i32imm:$BROPC), "#SELECT_CC_F4", 1598 []>; 1599 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1600 i32imm:$BROPC), "#SELECT_CC_F8", 1601 []>; 1602 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1603 i32imm:$BROPC), "#SELECT_CC_F16", 1604 []>; 1605 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1606 i32imm:$BROPC), "#SELECT_CC_VRRC", 1607 []>; 1608 1609 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1610 // register bit directly. 1611 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1612 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1613 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1614 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1615 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1616 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1617let Predicates = [HasFPU] in { 1618 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1619 f4rc:$T, f4rc:$F), "#SELECT_F4", 1620 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1621 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1622 f8rc:$T, f8rc:$F), "#SELECT_F8", 1623 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1624 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1625 vrrc:$T, vrrc:$F), "#SELECT_F16", 1626 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1627} 1628 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1629 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1630 [(set v4i32:$dst, 1631 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1632} 1633 1634// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1635// scavenge a register for it. 1636let mayStore = 1 in { 1637def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1638 "#SPILL_CR", []>; 1639def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1640 "#SPILL_CRBIT", []>; 1641} 1642 1643// RESTORE_CR - Indicate that we're restoring the CR register (previously 1644// spilled), so we'll need to scavenge a register for it. 1645let mayLoad = 1 in { 1646def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1647 "#RESTORE_CR", []>; 1648def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1649 "#RESTORE_CRBIT", []>; 1650} 1651 1652let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 1653 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1654 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1655 [(retflag)]>, Requires<[In32BitMode]>; 1656 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1657 let isPredicable = 1 in 1658 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1659 []>; 1660 1661 let isCodeGenOnly = 1 in { 1662 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 1663 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1664 []>; 1665 1666 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), 1667 "bcctr 12, $bi, 0", IIC_BrB, []>; 1668 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), 1669 "bcctr 4, $bi, 0", IIC_BrB, []>; 1670 } 1671 } 1672} 1673 1674// Set the float rounding mode. 1675let Uses = [RM], Defs = [RM] in { 1676def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1677 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1678 1679def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1680 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1681 1682def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1683 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1684} 1685 1686let Defs = [LR] in 1687 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1688 PPC970_Unit_BRU; 1689let Defs = [LR] in 1690 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1691 PPC970_Unit_BRU; 1692 1693let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 1694 let isBarrier = 1 in { 1695 let isPredicable = 1 in 1696 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 1697 "b $dst", IIC_BrB, 1698 [(br bb:$dst)]>; 1699 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 1700 "ba $dst", IIC_BrB, []>; 1701 } 1702 1703 // BCC represents an arbitrary conditional branch on a predicate. 1704 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1705 // a two-value operand where a dag node expects two operands. :( 1706 let isCodeGenOnly = 1 in { 1707 class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 1708 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 1709 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 1710 def BCC : BCC_class; 1711 1712 // The same as BCC, except that it's not a terminator. Used for introducing 1713 // control flow dependency without creating new blocks. 1714 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1715 1716 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1717 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 1718 1719 let isReturn = 1, Uses = [LR, RM] in 1720 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 1721 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1722 } 1723 1724 let isCodeGenOnly = 1 in { 1725 let Pattern = [(brcond i1:$bi, bb:$dst)] in 1726 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1727 "bc 12, $bi, $dst">; 1728 1729 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in 1730 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), 1731 "bc 4, $bi, $dst">; 1732 1733 let isReturn = 1, Uses = [LR, RM] in { 1734 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), 1735 "bclr 12, $bi, 0", IIC_BrB, []>; 1736 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), 1737 "bclr 4, $bi, 0", IIC_BrB, []>; 1738 } 1739 } 1740 1741 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1742 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1743 "bdzlr", IIC_BrB, []>; 1744 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1745 "bdnzlr", IIC_BrB, []>; 1746 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1747 "bdzlr+", IIC_BrB, []>; 1748 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1749 "bdnzlr+", IIC_BrB, []>; 1750 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1751 "bdzlr-", IIC_BrB, []>; 1752 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1753 "bdnzlr-", IIC_BrB, []>; 1754 } 1755 1756 let Defs = [CTR], Uses = [CTR] in { 1757 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 1758 "bdz $dst">; 1759 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 1760 "bdnz $dst">; 1761 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 1762 "bdza $dst">; 1763 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 1764 "bdnza $dst">; 1765 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 1766 "bdz+ $dst">; 1767 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 1768 "bdnz+ $dst">; 1769 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 1770 "bdza+ $dst">; 1771 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 1772 "bdnza+ $dst">; 1773 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 1774 "bdz- $dst">; 1775 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 1776 "bdnz- $dst">; 1777 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 1778 "bdza- $dst">; 1779 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 1780 "bdnza- $dst">; 1781 } 1782} 1783 1784// The unconditional BCL used by the SjLj setjmp code. 1785let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 1786 let Defs = [LR], Uses = [RM] in { 1787 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 1788 "bcl 20, 31, $dst">; 1789 } 1790} 1791 1792let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1793 // Convenient aliases for call instructions 1794 let Uses = [RM] in { 1795 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 1796 "bl $func", IIC_BrB, []>; // See Pat patterns below. 1797 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 1798 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; 1799 1800 let isCodeGenOnly = 1 in { 1801 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), 1802 "bl $func", IIC_BrB, []>; 1803 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 1804 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 1805 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 1806 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 1807 1808 def BCL : BForm_4<16, 12, 0, 1, (outs), 1809 (ins crbitrc:$bi, condbrtarget:$dst), 1810 "bcl 12, $bi, $dst">; 1811 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1812 (ins crbitrc:$bi, condbrtarget:$dst), 1813 "bcl 4, $bi, $dst">; 1814 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1815 (outs), (ins calltarget:$func), 1816 "bl $func\n\tnop", IIC_BrB, []>; 1817 } 1818 } 1819 let Uses = [CTR, RM] in { 1820 let isPredicable = 1 in 1821 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1822 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1823 Requires<[In32BitMode]>; 1824 1825 let isCodeGenOnly = 1 in { 1826 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1827 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1828 []>; 1829 1830 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), 1831 "bcctrl 12, $bi, 0", IIC_BrB, []>; 1832 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), 1833 "bcctrl 4, $bi, 0", IIC_BrB, []>; 1834 } 1835 } 1836 let Uses = [LR, RM] in { 1837 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1838 "blrl", IIC_BrB, []>; 1839 1840 let isCodeGenOnly = 1 in { 1841 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1842 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1843 []>; 1844 1845 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), 1846 "bclrl 12, $bi, 0", IIC_BrB, []>; 1847 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), 1848 "bclrl 4, $bi, 0", IIC_BrB, []>; 1849 } 1850 } 1851 let Defs = [CTR], Uses = [CTR, RM] in { 1852 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1853 "bdzl $dst">; 1854 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1855 "bdnzl $dst">; 1856 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1857 "bdzla $dst">; 1858 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1859 "bdnzla $dst">; 1860 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1861 "bdzl+ $dst">; 1862 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1863 "bdnzl+ $dst">; 1864 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1865 "bdzla+ $dst">; 1866 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1867 "bdnzla+ $dst">; 1868 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1869 "bdzl- $dst">; 1870 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1871 "bdnzl- $dst">; 1872 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1873 "bdzla- $dst">; 1874 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1875 "bdnzla- $dst">; 1876 } 1877 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1878 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1879 "bdzlrl", IIC_BrB, []>; 1880 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1881 "bdnzlrl", IIC_BrB, []>; 1882 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1883 "bdzlrl+", IIC_BrB, []>; 1884 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1885 "bdnzlrl+", IIC_BrB, []>; 1886 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1887 "bdzlrl-", IIC_BrB, []>; 1888 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1889 "bdnzlrl-", IIC_BrB, []>; 1890 } 1891} 1892 1893let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1894def TCRETURNdi :PPCEmitTimePseudo< (outs), 1895 (ins calltarget:$dst, i32imm:$offset), 1896 "#TC_RETURNd $dst $offset", 1897 []>; 1898 1899 1900let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1901def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1902 "#TC_RETURNa $func $offset", 1903 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1904 1905let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1906def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1907 "#TC_RETURNr $dst $offset", 1908 []>; 1909 1910let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1911 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1912 def BCTRL_LWZinto_toc: 1913 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1914 (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, 1915 [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; 1916 1917} 1918 1919 1920let isCodeGenOnly = 1 in { 1921 1922let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1923 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1924def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1925 []>, Requires<[In32BitMode]>; 1926 1927let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1928 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1929def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1930 "b $dst", IIC_BrB, 1931 []>; 1932 1933let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1934 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1935def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1936 "ba $dst", IIC_BrB, 1937 []>; 1938 1939} 1940 1941// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1942// is not. 1943let hasSideEffects = 1 in { 1944 let Defs = [CTR] in 1945 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1946 "#EH_SJLJ_SETJMP32", 1947 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1948 Requires<[In32BitMode]>; 1949} 1950 1951let hasSideEffects = 1, isBarrier = 1 in { 1952 let isTerminator = 1 in 1953 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1954 "#EH_SJLJ_LONGJMP32", 1955 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1956 Requires<[In32BitMode]>; 1957} 1958 1959// This pseudo is never removed from the function, as it serves as 1960// a terminator. Size is set to 0 to prevent the builtin assembler 1961// from emitting it. 1962let isBranch = 1, isTerminator = 1, Size = 0 in { 1963 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1964 "#EH_SjLj_Setup\t$dst", []>; 1965} 1966 1967// System call. 1968let PPC970_Unit = 7 in { 1969 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1970 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; 1971} 1972 1973// Branch history rolling buffer. 1974def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1975 [(PPCclrbhrb)]>, 1976 PPC970_DGroup_Single; 1977// The $dmy argument used for MFBHRBE is not needed; however, including 1978// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1979// interferes with necessary special handling (see PPCFastISel.cpp). 1980def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), 1981 (ins u10imm:$imm, u10imm:$dmy), 1982 "mfbhrbe $rD, $imm", IIC_BrB, 1983 [(set i32:$rD, 1984 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1985 PPC970_DGroup_First; 1986 1987def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", 1988 IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, 1989 PPC970_DGroup_Single; 1990 1991def : InstAlias<"rfebb", (RFEBB 1)>; 1992 1993// DCB* instructions. 1994def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", 1995 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1996 PPC970_DGroup_Single; 1997def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", 1998 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1999 PPC970_DGroup_Single; 2000def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", 2001 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 2002 PPC970_DGroup_Single; 2003def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", 2004 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 2005 PPC970_DGroup_Single; 2006def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", 2007 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 2008 PPC970_DGroup_Single; 2009 2010def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst), 2011 "dcbf $dst, $TH", IIC_LdStDCBF, []>, 2012 PPC970_DGroup_Single; 2013 2014let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 2015def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), 2016 "dcbt $dst, $TH", IIC_LdStDCBF, []>, 2017 PPC970_DGroup_Single; 2018def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), 2019 "dcbtst $dst, $TH", IIC_LdStDCBF, []>, 2020 PPC970_DGroup_Single; 2021} // hasSideEffects = 0 2022 2023def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), 2024 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; 2025def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), 2026 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 2027def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), 2028 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 2029def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), 2030 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; 2031 2032def : Pat<(int_ppc_dcbt xoaddr:$dst), 2033 (DCBT 0, xoaddr:$dst)>; 2034def : Pat<(int_ppc_dcbtst xoaddr:$dst), 2035 (DCBTST 0, xoaddr:$dst)>; 2036def : Pat<(int_ppc_dcbf xoaddr:$dst), 2037 (DCBF 0, xoaddr:$dst)>; 2038def : Pat<(int_ppc_icbt xoaddr:$dst), 2039 (ICBT 0, xoaddr:$dst)>; 2040 2041def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 2042 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 2043def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)), 2044 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 2045def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)), 2046 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 2047 2048def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 2049 (DCBT i32:$TH, xoaddr:$dst)>; 2050def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 2051 (DCBTST i32:$TH, xoaddr:$dst)>; 2052 2053// Atomic operations 2054// FIXME: some of these might be used with constant operands. This will result 2055// in constant materialization instructions that may be redundant. We currently 2056// clean this up in PPCMIPeephole with calls to 2057// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 2058// in the first place. 2059let Defs = [CR0] in { 2060 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 2061 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 2062 [(set i32:$dst, (atomic_load_add_8 ForceXForm:$ptr, i32:$incr))]>; 2063 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 2064 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 2065 [(set i32:$dst, (atomic_load_sub_8 ForceXForm:$ptr, i32:$incr))]>; 2066 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 2067 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 2068 [(set i32:$dst, (atomic_load_and_8 ForceXForm:$ptr, i32:$incr))]>; 2069 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 2070 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 2071 [(set i32:$dst, (atomic_load_or_8 ForceXForm:$ptr, i32:$incr))]>; 2072 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 2073 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 2074 [(set i32:$dst, (atomic_load_xor_8 ForceXForm:$ptr, i32:$incr))]>; 2075 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 2076 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 2077 [(set i32:$dst, (atomic_load_nand_8 ForceXForm:$ptr, i32:$incr))]>; 2078 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 2079 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 2080 [(set i32:$dst, (atomic_load_min_8 ForceXForm:$ptr, i32:$incr))]>; 2081 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 2082 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 2083 [(set i32:$dst, (atomic_load_max_8 ForceXForm:$ptr, i32:$incr))]>; 2084 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 2085 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 2086 [(set i32:$dst, (atomic_load_umin_8 ForceXForm:$ptr, i32:$incr))]>; 2087 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 2088 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 2089 [(set i32:$dst, (atomic_load_umax_8 ForceXForm:$ptr, i32:$incr))]>; 2090 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 2091 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 2092 [(set i32:$dst, (atomic_load_add_16 ForceXForm:$ptr, i32:$incr))]>; 2093 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 2094 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 2095 [(set i32:$dst, (atomic_load_sub_16 ForceXForm:$ptr, i32:$incr))]>; 2096 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 2097 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 2098 [(set i32:$dst, (atomic_load_and_16 ForceXForm:$ptr, i32:$incr))]>; 2099 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 2100 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 2101 [(set i32:$dst, (atomic_load_or_16 ForceXForm:$ptr, i32:$incr))]>; 2102 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 2103 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 2104 [(set i32:$dst, (atomic_load_xor_16 ForceXForm:$ptr, i32:$incr))]>; 2105 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 2106 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 2107 [(set i32:$dst, (atomic_load_nand_16 ForceXForm:$ptr, i32:$incr))]>; 2108 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 2109 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 2110 [(set i32:$dst, (atomic_load_min_16 ForceXForm:$ptr, i32:$incr))]>; 2111 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 2112 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 2113 [(set i32:$dst, (atomic_load_max_16 ForceXForm:$ptr, i32:$incr))]>; 2114 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 2115 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 2116 [(set i32:$dst, (atomic_load_umin_16 ForceXForm:$ptr, i32:$incr))]>; 2117 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 2118 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 2119 [(set i32:$dst, (atomic_load_umax_16 ForceXForm:$ptr, i32:$incr))]>; 2120 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 2121 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 2122 [(set i32:$dst, (atomic_load_add_32 ForceXForm:$ptr, i32:$incr))]>; 2123 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 2124 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 2125 [(set i32:$dst, (atomic_load_sub_32 ForceXForm:$ptr, i32:$incr))]>; 2126 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 2127 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 2128 [(set i32:$dst, (atomic_load_and_32 ForceXForm:$ptr, i32:$incr))]>; 2129 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 2130 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 2131 [(set i32:$dst, (atomic_load_or_32 ForceXForm:$ptr, i32:$incr))]>; 2132 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 2133 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 2134 [(set i32:$dst, (atomic_load_xor_32 ForceXForm:$ptr, i32:$incr))]>; 2135 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 2136 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 2137 [(set i32:$dst, (atomic_load_nand_32 ForceXForm:$ptr, i32:$incr))]>; 2138 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 2139 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 2140 [(set i32:$dst, (atomic_load_min_32 ForceXForm:$ptr, i32:$incr))]>; 2141 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 2142 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 2143 [(set i32:$dst, (atomic_load_max_32 ForceXForm:$ptr, i32:$incr))]>; 2144 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 2145 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 2146 [(set i32:$dst, (atomic_load_umin_32 ForceXForm:$ptr, i32:$incr))]>; 2147 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 2148 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 2149 [(set i32:$dst, (atomic_load_umax_32 ForceXForm:$ptr, i32:$incr))]>; 2150 2151 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 2152 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 2153 [(set i32:$dst, (atomic_cmp_swap_8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 2154 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 2155 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 2156 [(set i32:$dst, (atomic_cmp_swap_16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 2157 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 2158 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 2159 [(set i32:$dst, (atomic_cmp_swap_32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 2160 2161 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 2162 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 2163 [(set i32:$dst, (atomic_swap_8 ForceXForm:$ptr, i32:$new))]>; 2164 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 2165 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 2166 [(set i32:$dst, (atomic_swap_16 ForceXForm:$ptr, i32:$new))]>; 2167 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 2168 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 2169 [(set i32:$dst, (atomic_swap_32 ForceXForm:$ptr, i32:$new))]>; 2170} 2171 2172def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 2173 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 2174def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 2175 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 2176 2177// Instructions to support atomic operations 2178let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2179def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 2180 "lbarx $rD, $src", IIC_LdStLWARX, []>, 2181 Requires<[HasPartwordAtomics]>; 2182 2183def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 2184 "lharx $rD, $src", IIC_LdStLWARX, []>, 2185 Requires<[HasPartwordAtomics]>; 2186 2187def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 2188 "lwarx $rD, $src", IIC_LdStLWARX, []>; 2189 2190// Instructions to support lock versions of atomics 2191// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 2192def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), 2193 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 2194 Requires<[HasPartwordAtomics]>; 2195 2196def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), 2197 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, 2198 Requires<[HasPartwordAtomics]>; 2199 2200def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), 2201 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; 2202 2203// The atomic instructions use the destination register as well as the next one 2204// or two registers in order (modulo 31). 2205let hasExtraSrcRegAllocReq = 1 in 2206def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), 2207 "lwat $rD, $rA, $FC", IIC_LdStLoad>, 2208 Requires<[IsISA3_0]>; 2209} 2210 2211let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 2212def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), 2213 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, 2214 isRecordForm, Requires<[HasPartwordAtomics]>; 2215 2216def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), 2217 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, 2218 isRecordForm, Requires<[HasPartwordAtomics]>; 2219 2220def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 2221 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; 2222} 2223 2224let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2225def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), 2226 "stwat $rS, $rA, $FC", IIC_LdStStore>, 2227 Requires<[IsISA3_0]>; 2228 2229let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 2230def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 2231 2232def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 2233 "twi $to, $rA, $imm", IIC_IntTrapW, []>; 2234def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 2235 "tw $to, $rA, $rB", IIC_IntTrapW, []>; 2236def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 2237 "tdi $to, $rA, $imm", IIC_IntTrapD, []>; 2238def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 2239 "td $to, $rA, $rB", IIC_IntTrapD, []>; 2240 2241def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), 2242 "popcntb $rA, $rS", IIC_IntGeneral, 2243 [(set i32:$rA, (int_ppc_popcntb i32:$rS))]>; 2244 2245//===----------------------------------------------------------------------===// 2246// PPC32 Load Instructions. 2247// 2248 2249// Unindexed (r+i) Loads. 2250let PPC970_Unit = 2 in { 2251def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 2252 "lbz $rD, $src", IIC_LdStLoad, 2253 [(set i32:$rD, (zextloadi8 DForm:$src))]>; 2254def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 2255 "lha $rD, $src", IIC_LdStLHA, 2256 [(set i32:$rD, (sextloadi16 DForm:$src))]>, 2257 PPC970_DGroup_Cracked; 2258def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 2259 "lhz $rD, $src", IIC_LdStLoad, 2260 [(set i32:$rD, (zextloadi16 DForm:$src))]>; 2261def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 2262 "lwz $rD, $src", IIC_LdStLoad, 2263 [(set i32:$rD, (load DForm:$src))]>; 2264 2265let Predicates = [HasFPU] in { 2266def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 2267 "lfs $rD, $src", IIC_LdStLFD, 2268 [(set f32:$rD, (load DForm:$src))]>; 2269def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 2270 "lfd $rD, $src", IIC_LdStLFD, 2271 [(set f64:$rD, (load DForm:$src))]>; 2272} 2273 2274 2275// Unindexed (r+i) Loads with Update (preinc). 2276let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2277def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2278 "lbzu $rD, $addr", IIC_LdStLoadUpd, 2279 []>, RegConstraint<"$addr.reg = $ea_result">, 2280 NoEncode<"$ea_result">; 2281 2282def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2283 "lhau $rD, $addr", IIC_LdStLHAU, 2284 []>, RegConstraint<"$addr.reg = $ea_result">, 2285 NoEncode<"$ea_result">; 2286 2287def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2288 "lhzu $rD, $addr", IIC_LdStLoadUpd, 2289 []>, RegConstraint<"$addr.reg = $ea_result">, 2290 NoEncode<"$ea_result">; 2291 2292def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2293 "lwzu $rD, $addr", IIC_LdStLoadUpd, 2294 []>, RegConstraint<"$addr.reg = $ea_result">, 2295 NoEncode<"$ea_result">; 2296 2297let Predicates = [HasFPU] in { 2298def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2299 "lfsu $rD, $addr", IIC_LdStLFDU, 2300 []>, RegConstraint<"$addr.reg = $ea_result">, 2301 NoEncode<"$ea_result">; 2302 2303def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 2304 "lfdu $rD, $addr", IIC_LdStLFDU, 2305 []>, RegConstraint<"$addr.reg = $ea_result">, 2306 NoEncode<"$ea_result">; 2307} 2308 2309 2310// Indexed (r+r) Loads with Update (preinc). 2311def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2312 (ins memrr:$addr), 2313 "lbzux $rD, $addr", IIC_LdStLoadUpdX, 2314 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2315 NoEncode<"$ea_result">; 2316 2317def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2318 (ins memrr:$addr), 2319 "lhaux $rD, $addr", IIC_LdStLHAUX, 2320 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2321 NoEncode<"$ea_result">; 2322 2323def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2324 (ins memrr:$addr), 2325 "lhzux $rD, $addr", IIC_LdStLoadUpdX, 2326 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2327 NoEncode<"$ea_result">; 2328 2329def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 2330 (ins memrr:$addr), 2331 "lwzux $rD, $addr", IIC_LdStLoadUpdX, 2332 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2333 NoEncode<"$ea_result">; 2334 2335let Predicates = [HasFPU] in { 2336def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 2337 (ins memrr:$addr), 2338 "lfsux $rD, $addr", IIC_LdStLFDUX, 2339 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2340 NoEncode<"$ea_result">; 2341 2342def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 2343 (ins memrr:$addr), 2344 "lfdux $rD, $addr", IIC_LdStLFDUX, 2345 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2346 NoEncode<"$ea_result">; 2347} 2348} 2349} 2350 2351// Indexed (r+r) Loads. 2352// 2353let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2354def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), 2355 "lbzx $rD, $src", IIC_LdStLoad, 2356 [(set i32:$rD, (zextloadi8 XForm:$src))]>; 2357def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), 2358 "lhax $rD, $src", IIC_LdStLHA, 2359 [(set i32:$rD, (sextloadi16 XForm:$src))]>, 2360 PPC970_DGroup_Cracked; 2361def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), 2362 "lhzx $rD, $src", IIC_LdStLoad, 2363 [(set i32:$rD, (zextloadi16 XForm:$src))]>; 2364def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), 2365 "lwzx $rD, $src", IIC_LdStLoad, 2366 [(set i32:$rD, (load XForm:$src))]>; 2367def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), 2368 "lhbrx $rD, $src", IIC_LdStLoad, 2369 [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>; 2370def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), 2371 "lwbrx $rD, $src", IIC_LdStLoad, 2372 [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>; 2373 2374let Predicates = [HasFPU] in { 2375def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), 2376 "lfsx $frD, $src", IIC_LdStLFD, 2377 [(set f32:$frD, (load XForm:$src))]>; 2378def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), 2379 "lfdx $frD, $src", IIC_LdStLFD, 2380 [(set f64:$frD, (load XForm:$src))]>; 2381 2382def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), 2383 "lfiwax $frD, $src", IIC_LdStLFD, 2384 [(set f64:$frD, (PPClfiwax ForceXForm:$src))]>; 2385def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), 2386 "lfiwzx $frD, $src", IIC_LdStLFD, 2387 [(set f64:$frD, (PPClfiwzx ForceXForm:$src))]>; 2388} 2389} 2390 2391// Load Multiple 2392let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2393def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 2394 "lmw $rD, $src", IIC_LdStLMW, []>; 2395 2396//===----------------------------------------------------------------------===// 2397// PPC32 Store Instructions. 2398// 2399 2400// Unindexed (r+i) Stores. 2401let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2402def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), 2403 "stb $rS, $dst", IIC_LdStStore, 2404 [(truncstorei8 i32:$rS, DForm:$dst)]>; 2405def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), 2406 "sth $rS, $dst", IIC_LdStStore, 2407 [(truncstorei16 i32:$rS, DForm:$dst)]>; 2408def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), 2409 "stw $rS, $dst", IIC_LdStStore, 2410 [(store i32:$rS, DForm:$dst)]>; 2411let Predicates = [HasFPU] in { 2412def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 2413 "stfs $rS, $dst", IIC_LdStSTFD, 2414 [(store f32:$rS, DForm:$dst)]>; 2415def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 2416 "stfd $rS, $dst", IIC_LdStSTFD, 2417 [(store f64:$rS, DForm:$dst)]>; 2418} 2419} 2420 2421// Unindexed (r+i) Stores with Update (preinc). 2422let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2423def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2424 "stbu $rS, $dst", IIC_LdStSTU, []>, 2425 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2426def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2427 "sthu $rS, $dst", IIC_LdStSTU, []>, 2428 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2429def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 2430 "stwu $rS, $dst", IIC_LdStSTU, []>, 2431 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2432let Predicates = [HasFPU] in { 2433def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 2434 "stfsu $rS, $dst", IIC_LdStSTFDU, []>, 2435 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2436def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 2437 "stfdu $rS, $dst", IIC_LdStSTFDU, []>, 2438 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2439} 2440} 2441 2442// Patterns to match the pre-inc stores. We can't put the patterns on 2443// the instruction definitions directly as ISel wants the address base 2444// and offset to be separate operands, not a single complex operand. 2445def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2446 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2447def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2448 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2449def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2450 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2451def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2452 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2453def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2454 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2455 2456// Indexed (r+r) Stores. 2457let PPC970_Unit = 2 in { 2458def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 2459 "stbx $rS, $dst", IIC_LdStStore, 2460 [(truncstorei8 i32:$rS, XForm:$dst)]>, 2461 PPC970_DGroup_Cracked; 2462def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 2463 "sthx $rS, $dst", IIC_LdStStore, 2464 [(truncstorei16 i32:$rS, XForm:$dst)]>, 2465 PPC970_DGroup_Cracked; 2466def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 2467 "stwx $rS, $dst", IIC_LdStStore, 2468 [(store i32:$rS, XForm:$dst)]>, 2469 PPC970_DGroup_Cracked; 2470 2471def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 2472 "sthbrx $rS, $dst", IIC_LdStStore, 2473 [(PPCstbrx i32:$rS, ForceXForm:$dst, i16)]>, 2474 PPC970_DGroup_Cracked; 2475def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 2476 "stwbrx $rS, $dst", IIC_LdStStore, 2477 [(PPCstbrx i32:$rS, ForceXForm:$dst, i32)]>, 2478 PPC970_DGroup_Cracked; 2479 2480let Predicates = [HasFPU] in { 2481def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 2482 "stfiwx $frS, $dst", IIC_LdStSTFD, 2483 [(PPCstfiwx f64:$frS, ForceXForm:$dst)]>; 2484 2485def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 2486 "stfsx $frS, $dst", IIC_LdStSTFD, 2487 [(store f32:$frS, XForm:$dst)]>; 2488def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 2489 "stfdx $frS, $dst", IIC_LdStSTFD, 2490 [(store f64:$frS, XForm:$dst)]>; 2491} 2492} 2493 2494// Indexed (r+r) Stores with Update (preinc). 2495let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2496def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2497 (ins gprc:$rS, memrr:$dst), 2498 "stbux $rS, $dst", IIC_LdStSTUX, []>, 2499 RegConstraint<"$dst.ptrreg = $ea_res">, 2500 NoEncode<"$ea_res">, 2501 PPC970_DGroup_Cracked; 2502def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2503 (ins gprc:$rS, memrr:$dst), 2504 "sthux $rS, $dst", IIC_LdStSTUX, []>, 2505 RegConstraint<"$dst.ptrreg = $ea_res">, 2506 NoEncode<"$ea_res">, 2507 PPC970_DGroup_Cracked; 2508def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2509 (ins gprc:$rS, memrr:$dst), 2510 "stwux $rS, $dst", IIC_LdStSTUX, []>, 2511 RegConstraint<"$dst.ptrreg = $ea_res">, 2512 NoEncode<"$ea_res">, 2513 PPC970_DGroup_Cracked; 2514let Predicates = [HasFPU] in { 2515def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2516 (ins f4rc:$rS, memrr:$dst), 2517 "stfsux $rS, $dst", IIC_LdStSTFDU, []>, 2518 RegConstraint<"$dst.ptrreg = $ea_res">, 2519 NoEncode<"$ea_res">, 2520 PPC970_DGroup_Cracked; 2521def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2522 (ins f8rc:$rS, memrr:$dst), 2523 "stfdux $rS, $dst", IIC_LdStSTFDU, []>, 2524 RegConstraint<"$dst.ptrreg = $ea_res">, 2525 NoEncode<"$ea_res">, 2526 PPC970_DGroup_Cracked; 2527} 2528} 2529 2530// Patterns to match the pre-inc stores. We can't put the patterns on 2531// the instruction definitions directly as ISel wants the address base 2532// and offset to be separate operands, not a single complex operand. 2533def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2534 (STBUX $rS, $ptrreg, $ptroff)>; 2535def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2536 (STHUX $rS, $ptrreg, $ptroff)>; 2537def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2538 (STWUX $rS, $ptrreg, $ptroff)>; 2539let Predicates = [HasFPU] in { 2540def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2541 (STFSUX $rS, $ptrreg, $ptroff)>; 2542def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2543 (STFDUX $rS, $ptrreg, $ptroff)>; 2544} 2545 2546// Store Multiple 2547let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2548def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 2549 "stmw $rS, $dst", IIC_LdStLMW, []>; 2550 2551def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2552 "sync $L", IIC_LdStSync, []>; 2553 2554let isCodeGenOnly = 1 in { 2555 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2556 "msync", IIC_LdStSync, []> { 2557 let L = 0; 2558 } 2559} 2560 2561// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2562def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2563 "eieio", IIC_LdStLoad, []>; 2564 2565def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2566 [(int_ppc_eieio)]>; 2567 2568def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2569def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2570def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2571def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2572def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2573def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2574def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2575def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2576def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2577def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2578 2579//===----------------------------------------------------------------------===// 2580// PPC32 Arithmetic Instructions. 2581// 2582 2583let PPC970_Unit = 1 in { // FXU Operations. 2584def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 2585 "addi $rD, $rA, $imm", IIC_IntSimple, 2586 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 2587let BaseName = "addic" in { 2588let Defs = [CARRY] in 2589def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2590 "addic $rD, $rA, $imm", IIC_IntGeneral, 2591 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 2592 RecFormRel, PPC970_DGroup_Cracked; 2593let Defs = [CARRY, CR0] in 2594def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2595 "addic. $rD, $rA, $imm", IIC_IntGeneral, 2596 []>, isRecordForm, RecFormRel; 2597} 2598def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 2599 "addis $rD, $rA, $imm", IIC_IntSimple, 2600 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 2601let isCodeGenOnly = 1 in 2602def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 2603 "la $rD, $sym($rA)", IIC_IntGeneral, 2604 [(set i32:$rD, (add i32:$rA, 2605 (PPClo tglobaladdr:$sym, 0)))]>; 2606def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2607 "mulli $rD, $rA, $imm", IIC_IntMulLI, 2608 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 2609let Defs = [CARRY] in 2610def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 2611 "subfic $rD, $rA, $imm", IIC_IntGeneral, 2612 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 2613 2614let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2615 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 2616 "li $rD, $imm", IIC_IntSimple, 2617 [(set i32:$rD, imm32SExt16:$imm)]>; 2618 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 2619 "lis $rD, $imm", IIC_IntSimple, 2620 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 2621} 2622} 2623 2624def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2625def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2626 2627let PPC970_Unit = 1 in { // FXU Operations. 2628let Defs = [CR0] in { 2629def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2630 "andi. $dst, $src1, $src2", IIC_IntGeneral, 2631 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 2632 isRecordForm; 2633def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2634 "andis. $dst, $src1, $src2", IIC_IntGeneral, 2635 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 2636 isRecordForm; 2637} 2638def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2639 "ori $dst, $src1, $src2", IIC_IntSimple, 2640 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 2641def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2642 "oris $dst, $src1, $src2", IIC_IntSimple, 2643 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 2644def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2645 "xori $dst, $src1, $src2", IIC_IntSimple, 2646 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 2647def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 2648 "xoris $dst, $src1, $src2", IIC_IntSimple, 2649 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 2650 2651def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2652 []>; 2653let isCodeGenOnly = 1 in { 2654// The POWER6 and POWER7 have special group-terminating nops. 2655def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2656 "ori 1, 1, 0", IIC_IntSimple, []>; 2657def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2658 "ori 2, 2, 0", IIC_IntSimple, []>; 2659} 2660 2661let isCompare = 1, hasSideEffects = 0 in { 2662 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 2663 "cmpwi $crD, $rA, $imm", IIC_IntCompare>; 2664 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 2665 "cmplwi $dst, $src1, $src2", IIC_IntCompare>; 2666 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2667 (ins u1imm:$L, gprc:$rA, gprc:$rB), 2668 "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, 2669 Requires<[IsISA3_0]>; 2670} 2671} 2672 2673let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2674let isCommutable = 1 in { 2675defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2676 "nand", "$rA, $rS, $rB", IIC_IntSimple, 2677 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 2678defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2679 "and", "$rA, $rS, $rB", IIC_IntSimple, 2680 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 2681} // isCommutable 2682defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2683 "andc", "$rA, $rS, $rB", IIC_IntSimple, 2684 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 2685let isCommutable = 1 in { 2686defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2687 "or", "$rA, $rS, $rB", IIC_IntSimple, 2688 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 2689defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2690 "nor", "$rA, $rS, $rB", IIC_IntSimple, 2691 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 2692} // isCommutable 2693defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2694 "orc", "$rA, $rS, $rB", IIC_IntSimple, 2695 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 2696let isCommutable = 1 in { 2697defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2698 "eqv", "$rA, $rS, $rB", IIC_IntSimple, 2699 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 2700defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2701 "xor", "$rA, $rS, $rB", IIC_IntSimple, 2702 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 2703} // isCommutable 2704defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2705 "slw", "$rA, $rS, $rB", IIC_IntGeneral, 2706 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 2707defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2708 "srw", "$rA, $rS, $rB", IIC_IntGeneral, 2709 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 2710defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2711 "sraw", "$rA, $rS, $rB", IIC_IntShift, 2712 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 2713} 2714 2715def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2716def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2717 2718def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2719def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2720 2721def : InstAlias<"nop", (ORI R0, R0, 0)>; 2722 2723let PPC970_Unit = 1 in { // FXU Operations. 2724let hasSideEffects = 0 in { 2725defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 2726 "srawi", "$rA, $rS, $SH", IIC_IntShift, 2727 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 2728defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 2729 "cntlzw", "$rA, $rS", IIC_IntGeneral, 2730 [(set i32:$rA, (ctlz i32:$rS))]>; 2731defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), 2732 "cnttzw", "$rA, $rS", IIC_IntGeneral, 2733 [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>; 2734defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 2735 "extsb", "$rA, $rS", IIC_IntSimple, 2736 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 2737defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 2738 "extsh", "$rA, $rS", IIC_IntSimple, 2739 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 2740 2741let isCommutable = 1 in 2742def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 2743 "cmpb $rA, $rS, $rB", IIC_IntGeneral, 2744 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; 2745} 2746let isCompare = 1, hasSideEffects = 0 in { 2747 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2748 "cmpw $crD, $rA, $rB", IIC_IntCompare>; 2749 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 2750 "cmplw $crD, $rA, $rB", IIC_IntCompare>; 2751} 2752} 2753let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2754let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2755 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2756 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2757 def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 2758 "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2759 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2760 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2761 "fcmpu $crD, $fA, $fB", IIC_FPCompare>; 2762 def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2763 "fcmpo $crD, $fA, $fB", IIC_FPCompare>; 2764 } 2765} 2766 2767def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 2768 "ftdiv $crD, $fA, $fB", IIC_FPCompare>; 2769def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), 2770 "ftsqrt $crD, $fB", IIC_FPCompare, 2771 [(set i32:$crD, (PPCftsqrt f64:$fB))]>; 2772 2773let mayRaiseFPException = 1, hasSideEffects = 0 in { 2774 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2775 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 2776 "frin", "$frD, $frB", IIC_FPGeneral, 2777 [(set f64:$frD, (any_fround f64:$frB))]>; 2778 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 2779 "frin", "$frD, $frB", IIC_FPGeneral, 2780 [(set f32:$frD, (any_fround f32:$frB))]>; 2781 2782 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2783 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 2784 "frip", "$frD, $frB", IIC_FPGeneral, 2785 [(set f64:$frD, (any_fceil f64:$frB))]>; 2786 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 2787 "frip", "$frD, $frB", IIC_FPGeneral, 2788 [(set f32:$frD, (any_fceil f32:$frB))]>; 2789 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2790 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 2791 "friz", "$frD, $frB", IIC_FPGeneral, 2792 [(set f64:$frD, (any_ftrunc f64:$frB))]>; 2793 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 2794 "friz", "$frD, $frB", IIC_FPGeneral, 2795 [(set f32:$frD, (any_ftrunc f32:$frB))]>; 2796 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2797 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 2798 "frim", "$frD, $frB", IIC_FPGeneral, 2799 [(set f64:$frD, (any_ffloor f64:$frB))]>; 2800 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 2801 "frim", "$frD, $frB", IIC_FPGeneral, 2802 [(set f32:$frD, (any_ffloor f32:$frB))]>; 2803} 2804 2805let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2806 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), 2807 "fctiw", "$frD, $frB", IIC_FPGeneral, 2808 []>; 2809 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), 2810 "fctiwu", "$frD, $frB", IIC_FPGeneral, 2811 []>; 2812 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 2813 "fctiwz", "$frD, $frB", IIC_FPGeneral, 2814 [(set f64:$frD, (PPCany_fctiwz f64:$frB))]>; 2815 2816 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 2817 "frsp", "$frD, $frB", IIC_FPGeneral, 2818 [(set f32:$frD, (any_fpround f64:$frB))]>; 2819 2820 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 2821 "fsqrt", "$frD, $frB", IIC_FPSqrtD, 2822 [(set f64:$frD, (any_fsqrt f64:$frB))]>; 2823 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 2824 "fsqrts", "$frD, $frB", IIC_FPSqrtS, 2825 [(set f32:$frD, (any_fsqrt f32:$frB))]>; 2826} 2827} 2828 2829def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2830 2831/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2832/// often coalesced away and we don't want the dispatch group builder to think 2833/// that they will fill slots (which could cause the load of a LSU reject to 2834/// sneak into a d-group with a store). 2835let hasSideEffects = 0, Predicates = [HasFPU] in 2836defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 2837 "fmr", "$frD, $frB", IIC_FPGeneral, 2838 []>, // (set f32:$frD, f32:$frB) 2839 PPC970_Unit_Pseudo; 2840 2841let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2842// These are artificially split into two different forms, for 4/8 byte FP. 2843defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 2844 "fabs", "$frD, $frB", IIC_FPGeneral, 2845 [(set f32:$frD, (fabs f32:$frB))]>; 2846let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2847defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 2848 "fabs", "$frD, $frB", IIC_FPGeneral, 2849 [(set f64:$frD, (fabs f64:$frB))]>; 2850defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 2851 "fnabs", "$frD, $frB", IIC_FPGeneral, 2852 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 2853let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2854defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 2855 "fnabs", "$frD, $frB", IIC_FPGeneral, 2856 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 2857defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 2858 "fneg", "$frD, $frB", IIC_FPGeneral, 2859 [(set f32:$frD, (fneg f32:$frB))]>; 2860let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2861defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 2862 "fneg", "$frD, $frB", IIC_FPGeneral, 2863 [(set f64:$frD, (fneg f64:$frB))]>; 2864 2865defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), 2866 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2867 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; 2868let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2869defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), 2870 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, 2871 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; 2872 2873// Reciprocal estimates. 2874let mayRaiseFPException = 1 in { 2875defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 2876 "fre", "$frD, $frB", IIC_FPGeneral, 2877 [(set f64:$frD, (PPCfre f64:$frB))]>; 2878defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 2879 "fres", "$frD, $frB", IIC_FPGeneral, 2880 [(set f32:$frD, (PPCfre f32:$frB))]>; 2881defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 2882 "frsqrte", "$frD, $frB", IIC_FPGeneral, 2883 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 2884defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 2885 "frsqrtes", "$frD, $frB", IIC_FPGeneral, 2886 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 2887} 2888} 2889 2890// XL-Form instructions. condition register logical ops. 2891// 2892let hasSideEffects = 0 in 2893def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2894 "mcrf $BF, $BFA", IIC_BrMCR>, 2895 PPC970_DGroup_First, PPC970_Unit_CRU; 2896 2897// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2898// condition-register logical instructions have preferred forms. Specifically, 2899// it is preferred that the bit specified by the BT field be in the same 2900// condition register as that specified by the bit BB. We might want to account 2901// for this via hinting the register allocator and anti-dep breakers, or we 2902// could constrain the register class to force this constraint and then loosen 2903// it during register allocation via convertToThreeAddress or some similar 2904// mechanism. 2905 2906let isCommutable = 1 in { 2907def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2908 (ins crbitrc:$CRA, crbitrc:$CRB), 2909 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2910 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2911 2912def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2913 (ins crbitrc:$CRA, crbitrc:$CRB), 2914 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2915 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2916 2917def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2918 (ins crbitrc:$CRA, crbitrc:$CRB), 2919 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2920 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2921 2922def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2923 (ins crbitrc:$CRA, crbitrc:$CRB), 2924 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2925 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2926 2927def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2928 (ins crbitrc:$CRA, crbitrc:$CRB), 2929 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2930 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2931 2932def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2933 (ins crbitrc:$CRA, crbitrc:$CRB), 2934 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2935 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2936} // isCommutable 2937 2938def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2939 (ins crbitrc:$CRA, crbitrc:$CRB), 2940 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2941 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2942 2943def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2944 (ins crbitrc:$CRA, crbitrc:$CRB), 2945 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2946 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2947 2948let isCodeGenOnly = 1 in { 2949let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2950def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 2951 "creqv $dst, $dst, $dst", IIC_BrCR, 2952 [(set i1:$dst, 1)]>; 2953 2954def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 2955 "crxor $dst, $dst, $dst", IIC_BrCR, 2956 [(set i1:$dst, 0)]>; 2957} 2958 2959let Defs = [CR1EQ], CRD = 6 in { 2960def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2961 "creqv 6, 6, 6", IIC_BrCR, 2962 [(PPCcr6set)]>; 2963 2964def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2965 "crxor 6, 6, 6", IIC_BrCR, 2966 [(PPCcr6unset)]>; 2967} 2968} 2969 2970// XFX-Form instructions. Instructions that deal with SPRs. 2971// 2972 2973def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 2974 "mfspr $RT, $SPR", IIC_SprMFSPR>; 2975def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 2976 "mtspr $SPR, $RT", IIC_SprMTSPR>; 2977 2978def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 2979 "mftb $RT, $SPR", IIC_SprMFTB>; 2980 2981def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), 2982 "mfpmr $RT, $SPR", IIC_SprMFPMR>; 2983 2984def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), 2985 "mtpmr $SPR, $RT", IIC_SprMTPMR>; 2986 2987 2988// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2989// on a 32-bit target. 2990let hasSideEffects = 1 in 2991def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2992 "#ReadTB", []>; 2993 2994let Uses = [CTR] in { 2995def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 2996 "mfctr $rT", IIC_SprMFSPR>, 2997 PPC970_DGroup_First, PPC970_Unit_FXU; 2998} 2999let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 3000def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 3001 "mtctr $rS", IIC_SprMTSPR>, 3002 PPC970_DGroup_First, PPC970_Unit_FXU; 3003} 3004let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 3005let Pattern = [(int_set_loop_iterations i32:$rS)] in 3006def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 3007 "mtctr $rS", IIC_SprMTSPR>, 3008 PPC970_DGroup_First, PPC970_Unit_FXU; 3009} 3010 3011let hasSideEffects = 0 in { 3012let Defs = [LR] in { 3013def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 3014 "mtlr $rS", IIC_SprMTSPR>, 3015 PPC970_DGroup_First, PPC970_Unit_FXU; 3016} 3017let Uses = [LR] in { 3018def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 3019 "mflr $rT", IIC_SprMFSPR>, 3020 PPC970_DGroup_First, PPC970_Unit_FXU; 3021} 3022} 3023 3024let isCodeGenOnly = 1 in { 3025 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 3026 // like a GPR on the PPC970. As such, copies in and out have the same 3027 // performance characteristics as an OR instruction. 3028 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 3029 "mtspr 256, $rS", IIC_IntGeneral>, 3030 PPC970_DGroup_Single, PPC970_Unit_FXU; 3031 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 3032 "mfspr $rT, 256", IIC_IntGeneral>, 3033 PPC970_DGroup_First, PPC970_Unit_FXU; 3034 3035 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 3036 (outs VRSAVERC:$reg), (ins gprc:$rS), 3037 "mtspr 256, $rS", IIC_IntGeneral>, 3038 PPC970_DGroup_Single, PPC970_Unit_FXU; 3039 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 3040 (ins VRSAVERC:$reg), 3041 "mfspr $rT, 256", IIC_IntGeneral>, 3042 PPC970_DGroup_First, PPC970_Unit_FXU; 3043} 3044 3045// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 3046def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 3047def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 3048 3049let hasSideEffects = 0 in { 3050// mtocrf's input needs to be prepared by shifting by an amount dependent 3051// on the cr register selected. Thus, post-ra anti-dep breaking must not 3052// later change that register assignment. 3053let hasExtraDefRegAllocReq = 1 in { 3054def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 3055 "mtocrf $FXM, $ST", IIC_BrMCRX>, 3056 PPC970_DGroup_First, PPC970_Unit_CRU; 3057 3058// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 3059// is dependent on the cr fields being set. 3060def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 3061 "mtcrf $FXM, $rS", IIC_BrMCRX>, 3062 PPC970_MicroCode, PPC970_Unit_CRU; 3063} // hasExtraDefRegAllocReq = 1 3064 3065// mfocrf's input needs to be prepared by shifting by an amount dependent 3066// on the cr register selected. Thus, post-ra anti-dep breaking must not 3067// later change that register assignment. 3068let hasExtraSrcRegAllocReq = 1 in { 3069def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 3070 "mfocrf $rT, $FXM", IIC_SprMFCRF>, 3071 PPC970_DGroup_First, PPC970_Unit_CRU; 3072 3073// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 3074// is dependent on the cr fields being copied. 3075def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 3076 "mfcr $rT", IIC_SprMFCR>, 3077 PPC970_MicroCode, PPC970_Unit_CRU; 3078} // hasExtraSrcRegAllocReq = 1 3079 3080def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 3081 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 3082} // hasSideEffects = 0 3083 3084def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 3085 3086let Predicates = [HasFPU] in { 3087// Custom inserter instruction to perform FADD in round-to-zero mode. 3088let Uses = [RM], mayRaiseFPException = 1 in { 3089 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 3090 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 3091} 3092 3093// The above pseudo gets expanded to make use of the following instructions 3094// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 3095 3096// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 3097// RM should be set. 3098let hasSideEffects = 1, Defs = [RM] in { 3099def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 3100 "mtfsb0 $FM", IIC_IntMTFSB0, 3101 [(int_ppc_mtfsb0 timm:$FM)]>, 3102 PPC970_DGroup_Single, PPC970_Unit_FPU; 3103def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 3104 "mtfsb1 $FM", IIC_IntMTFSB0, 3105 [(int_ppc_mtfsb1 timm:$FM)]>, 3106 PPC970_DGroup_Single, PPC970_Unit_FPU; 3107} 3108 3109let Defs = [RM] in { 3110 let isCodeGenOnly = 1 in 3111 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 3112 "mtfsf $FM, $rT", IIC_IntMTFSB0, 3113 [(int_ppc_mtfsf timm:$FM, f64:$rT)]>, 3114 PPC970_DGroup_Single, PPC970_Unit_FPU; 3115} 3116let Uses = [RM] in { 3117 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 3118 "mffs $rT", IIC_IntMFFS, 3119 [(set f64:$rT, (PPCmffs))]>, 3120 PPC970_DGroup_Single, PPC970_Unit_FPU; 3121 3122 let Defs = [CR1] in 3123 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), 3124 "mffs. $rT", IIC_IntMFFS, []>, isRecordForm; 3125 3126 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), 3127 "mffsce $rT", IIC_IntMFFS, []>, 3128 PPC970_DGroup_Single, PPC970_Unit_FPU; 3129 3130 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), 3131 (ins f8rc:$FRB), "mffscdrn $rT, $FRB", 3132 IIC_IntMFFS, []>, 3133 PPC970_DGroup_Single, PPC970_Unit_FPU; 3134 3135 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), 3136 (ins u3imm:$DRM), 3137 "mffscdrni $rT, $DRM", 3138 IIC_IntMFFS, []>, 3139 PPC970_DGroup_Single, PPC970_Unit_FPU; 3140 3141 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), 3142 (ins f8rc:$FRB), "mffscrn $rT, $FRB", 3143 IIC_IntMFFS, []>, 3144 PPC970_DGroup_Single, PPC970_Unit_FPU; 3145 3146 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), 3147 (ins u2imm:$RM), "mffscrni $rT, $RM", 3148 IIC_IntMFFS, []>, 3149 PPC970_DGroup_Single, PPC970_Unit_FPU; 3150 3151 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), 3152 "mffsl $rT", IIC_IntMFFS, []>, 3153 PPC970_DGroup_Single, PPC970_Unit_FPU; 3154} 3155} 3156 3157let Predicates = [IsISA3_0] in { 3158def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3159 "modsw $rT, $rA, $rB", IIC_IntDivW, 3160 [(set i32:$rT, (srem i32:$rA, i32:$rB))]>; 3161def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3162 "moduw $rT, $rA, $rB", IIC_IntDivW, 3163 [(set i32:$rT, (urem i32:$rA, i32:$rB))]>; 3164let hasSideEffects = 1 in 3165def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT), 3166 (ins gprc:$rA, gprc:$rB, u2imm:$CY), 3167 "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>; 3168} 3169 3170let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 3171// XO-Form instructions. Arithmetic instructions that can set overflow bit 3172let isCommutable = 1 in 3173defm ADD4 : XOForm_1rx<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3174 "add", "$rT, $rA, $rB", IIC_IntSimple, 3175 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 3176let isCodeGenOnly = 1 in 3177def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), 3178 "add $rT, $rA, $rB", IIC_IntSimple, 3179 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; 3180let isCommutable = 1 in 3181defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3182 "addc", "$rT, $rA, $rB", IIC_IntGeneral, 3183 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 3184 PPC970_DGroup_Cracked; 3185 3186defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3187 "divw", "$rT, $rA, $rB", IIC_IntDivW, 3188 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; 3189defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3190 "divwu", "$rT, $rA, $rB", IIC_IntDivW, 3191 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; 3192defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3193 "divwe", "$rT, $rA, $rB", IIC_IntDivW, 3194 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, 3195 Requires<[HasExtDiv]>; 3196defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3197 "divweu", "$rT, $rA, $rB", IIC_IntDivW, 3198 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, 3199 Requires<[HasExtDiv]>; 3200let isCommutable = 1 in { 3201defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3202 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, 3203 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 3204defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3205 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, 3206 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 3207defm MULLW : XOForm_1rx<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3208 "mullw", "$rT, $rA, $rB", IIC_IntMulHW, 3209 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 3210} // isCommutable 3211defm SUBF : XOForm_1rx<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3212 "subf", "$rT, $rA, $rB", IIC_IntGeneral, 3213 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 3214defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3215 "subfc", "$rT, $rA, $rB", IIC_IntGeneral, 3216 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 3217 PPC970_DGroup_Cracked; 3218defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 3219 "neg", "$rT, $rA", IIC_IntSimple, 3220 [(set i32:$rT, (ineg i32:$rA))]>; 3221let Uses = [CARRY] in { 3222let isCommutable = 1 in 3223defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3224 "adde", "$rT, $rA, $rB", IIC_IntGeneral, 3225 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 3226defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 3227 "addme", "$rT, $rA", IIC_IntGeneral, 3228 [(set i32:$rT, (adde i32:$rA, -1))]>; 3229defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 3230 "addze", "$rT, $rA", IIC_IntGeneral, 3231 [(set i32:$rT, (adde i32:$rA, 0))]>; 3232defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 3233 "subfe", "$rT, $rA, $rB", IIC_IntGeneral, 3234 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 3235defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 3236 "subfme", "$rT, $rA", IIC_IntGeneral, 3237 [(set i32:$rT, (sube -1, i32:$rA))]>; 3238defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 3239 "subfze", "$rT, $rA", IIC_IntGeneral, 3240 [(set i32:$rT, (sube 0, i32:$rA))]>; 3241} 3242} 3243 3244def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 3245def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 3246def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 3247def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 3248 3249// A-Form instructions. Most of the instructions executed in the FPU are of 3250// this type. 3251// 3252let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 3253let mayRaiseFPException = 1, Uses = [RM] in { 3254let isCommutable = 1 in { 3255 defm FMADD : AForm_1r<63, 29, 3256 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3257 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3258 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 3259 defm FMADDS : AForm_1r<59, 29, 3260 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3261 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3262 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 3263 defm FMSUB : AForm_1r<63, 28, 3264 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3265 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3266 [(set f64:$FRT, 3267 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 3268 defm FMSUBS : AForm_1r<59, 28, 3269 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3270 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3271 [(set f32:$FRT, 3272 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 3273 defm FNMADD : AForm_1r<63, 31, 3274 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3275 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3276 [(set f64:$FRT, 3277 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 3278 defm FNMADDS : AForm_1r<59, 31, 3279 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3280 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3281 [(set f32:$FRT, 3282 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3283 defm FNMSUB : AForm_1r<63, 30, 3284 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3285 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3286 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 3287 (fneg f64:$FRB))))]>; 3288 defm FNMSUBS : AForm_1r<59, 30, 3289 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3290 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3291 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 3292 (fneg f32:$FRB))))]>; 3293} // isCommutable 3294} 3295// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3296// having 4 of these, force the comparison to always be an 8-byte double (code 3297// should use an FMRSD if the input comparison value really wants to be a float) 3298// and 4/8 byte forms for the result and operand type.. 3299let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3300defm FSELD : AForm_1r<63, 23, 3301 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3302 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3303 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3304defm FSELS : AForm_1r<63, 23, 3305 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3306 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3307 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3308let Uses = [RM], mayRaiseFPException = 1 in { 3309 let isCommutable = 1 in { 3310 defm FADD : AForm_2r<63, 21, 3311 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3312 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3313 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3314 defm FADDS : AForm_2r<59, 21, 3315 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3316 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3317 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3318 } // isCommutable 3319 defm FDIV : AForm_2r<63, 18, 3320 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3321 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3322 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3323 defm FDIVS : AForm_2r<59, 18, 3324 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3325 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3326 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3327 let isCommutable = 1 in { 3328 defm FMUL : AForm_3r<63, 25, 3329 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3330 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3331 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3332 defm FMULS : AForm_3r<59, 25, 3333 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3334 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3335 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3336 } // isCommutable 3337 defm FSUB : AForm_2r<63, 20, 3338 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3339 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3340 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3341 defm FSUBS : AForm_2r<59, 20, 3342 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3343 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3344 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3345 } 3346} 3347 3348let hasSideEffects = 0 in { 3349let PPC970_Unit = 1 in { // FXU Operations. 3350 let isSelect = 1 in 3351 def ISEL : AForm_4<31, 15, 3352 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 3353 "isel $rT, $rA, $rB, $cond", IIC_IntISEL, 3354 []>; 3355} 3356 3357let PPC970_Unit = 1 in { // FXU Operations. 3358// M-Form instructions. rotate and mask instructions. 3359// 3360let isCommutable = 1 in { 3361// RLWIMI can be commuted if the rotate amount is zero. 3362defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 3363 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 3364 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", 3365 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3366 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; 3367} 3368let BaseName = "rlwinm" in { 3369def RLWINM : MForm_2<21, 3370 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3371 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3372 []>, RecFormRel; 3373let Defs = [CR0] in 3374def RLWINM_rec : MForm_2<21, 3375 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3376 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, 3377 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3378} 3379defm RLWNM : MForm_2r<23, (outs gprc:$rA), 3380 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 3381 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, 3382 []>; 3383} 3384} // hasSideEffects = 0 3385 3386//===----------------------------------------------------------------------===// 3387// PowerPC Instruction Patterns 3388// 3389 3390// Arbitrary immediate support. Implement in terms of LIS/ORI. 3391def : Pat<(i32 imm:$imm), 3392 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3393 3394// Implement the 'not' operation with the NOR instruction. 3395def i32not : OutPatFrag<(ops node:$in), 3396 (NOR $in, $in)>; 3397def : Pat<(not i32:$in), 3398 (i32not $in)>; 3399 3400// ADD an arbitrary immediate. 3401def : Pat<(add i32:$in, imm:$imm), 3402 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3403// OR an arbitrary immediate. 3404def : Pat<(or i32:$in, imm:$imm), 3405 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3406// XOR an arbitrary immediate. 3407def : Pat<(xor i32:$in, imm:$imm), 3408 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3409// SUBFIC 3410def : Pat<(sub imm32SExt16:$imm, i32:$in), 3411 (SUBFIC $in, imm:$imm)>; 3412 3413// SHL/SRL 3414def : Pat<(shl i32:$in, (i32 imm:$imm)), 3415 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3416def : Pat<(srl i32:$in, (i32 imm:$imm)), 3417 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3418 3419// ROTL 3420def : Pat<(rotl i32:$in, i32:$sh), 3421 (RLWNM $in, $sh, 0, 31)>; 3422def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3423 (RLWINM $in, imm:$imm, 0, 31)>; 3424 3425// RLWNM 3426def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3427 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3428 3429// Calls 3430def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3431 (BL tglobaladdr:$dst)>; 3432 3433def : Pat<(PPCcall (i32 texternalsym:$dst)), 3434 (BL texternalsym:$dst)>; 3435 3436// Calls for AIX only 3437def : Pat<(PPCcall (i32 mcsym:$dst)), 3438 (BL mcsym:$dst)>; 3439 3440def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3441 (BL_NOP mcsym:$dst)>; 3442 3443def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3444 (BL_NOP texternalsym:$dst)>; 3445 3446def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3447 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3448 3449def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3450 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3451 3452def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3453 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3454 3455def : Pat<(int_ppc_readflm), (MFFS)>; 3456 3457// Hi and Lo for Darwin Global Addresses. 3458def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3459def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3460def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3461def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3462def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3463def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3464def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3465def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3466def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3467 (ADDIS $in, tglobaltlsaddr:$g)>; 3468def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3469 (ADDI $in, tglobaltlsaddr:$g)>; 3470def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3471 (ADDIS $in, tglobaladdr:$g)>; 3472def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3473 (ADDIS $in, tconstpool:$g)>; 3474def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3475 (ADDIS $in, tjumptable:$g)>; 3476def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3477 (ADDIS $in, tblockaddress:$g)>; 3478 3479// Support for thread-local storage. 3480def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3481 [(set i32:$rD, (PPCppc32GOT))]>; 3482 3483// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3484// This uses two output registers, the first as the real output, the second as a 3485// temporary register, used internally in code generation. 3486def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3487 []>, NoEncode<"$rT">; 3488 3489def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3490 "#LDgotTprelL32", 3491 [(set i32:$rD, 3492 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3493def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3494 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3495 3496def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3497 "#ADDItlsgdL32", 3498 [(set i32:$rD, 3499 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3500// LR is a true define, while the rest of the Defs are clobbers. R3 is 3501// explicitly defined when this op is created, so not mentioned here. 3502let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3503 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3504def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3505 "GETtlsADDR32", 3506 [(set i32:$rD, 3507 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3508// R3 is explicitly defined when this op is created, so not mentioned here. 3509// The rest of the Defs are the exact set of registers that will be clobbered by 3510// the call. 3511let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3512 Defs = [R0,R4,R5,R11,LR,CR0] in 3513def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3514 "GETtlsADDR32AIX", 3515 [(set i32:$rD, 3516 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3517// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3518// are true defines while the rest of the Defs are clobbers. 3519let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3520 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3521def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3522 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3523 "#ADDItlsgdLADDR32", 3524 [(set i32:$rD, 3525 (PPCaddiTlsgdLAddr i32:$reg, 3526 tglobaltlsaddr:$disp, 3527 tglobaltlsaddr:$sym))]>; 3528def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3529 "#ADDItlsldL32", 3530 [(set i32:$rD, 3531 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3532// This pseudo is expanded to two copies to put the variable offset in R4 and 3533// the region handle in R3 and GETtlsADDR32AIX. 3534def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3535 "#TLSGDAIX", 3536 [(set i32:$rD, 3537 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3538// LR is a true define, while the rest of the Defs are clobbers. R3 is 3539// explicitly defined when this op is created, so not mentioned here. 3540let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3541 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3542def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3543 "GETtlsldADDR32", 3544 [(set i32:$rD, 3545 (PPCgetTlsldAddr i32:$reg, 3546 tglobaltlsaddr:$sym))]>; 3547// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3548// are true defines while the rest of the Defs are clobbers. 3549let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3550 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3551def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3552 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3553 "#ADDItlsldLADDR32", 3554 [(set i32:$rD, 3555 (PPCaddiTlsldLAddr i32:$reg, 3556 tglobaltlsaddr:$disp, 3557 tglobaltlsaddr:$sym))]>; 3558def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3559 "#ADDIdtprelL32", 3560 [(set i32:$rD, 3561 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3562def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3563 "#ADDISdtprelHA32", 3564 [(set i32:$rD, 3565 (PPCaddisDtprelHA i32:$reg, 3566 tglobaltlsaddr:$disp))]>; 3567 3568// Support for Position-independent code 3569def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3570 "#LWZtoc", 3571 [(set i32:$rD, 3572 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3573def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3574 "#LWZtocL", 3575 [(set i32:$rD, 3576 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3577def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3578 "#ADDIStocHA", 3579 [(set i32:$rD, 3580 (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>; 3581// Local Data Transform 3582def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3583 "#ADDItoc", 3584 [(set i32:$rD, 3585 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3586 3587// Get Global (GOT) Base Register offset, from the word immediately preceding 3588// the function label. 3589def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3590 3591// Pseudo-instruction marked for deletion. When deleting the instruction would 3592// cause iterator invalidation in MIR transformation passes, this pseudo can be 3593// used instead. It will be removed unconditionally at pre-emit time (prior to 3594// branch selection). 3595def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3596 3597// Standard shifts. These are represented separately from the real shifts above 3598// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3599// amounts. 3600def : Pat<(sra i32:$rS, i32:$rB), 3601 (SRAW $rS, $rB)>; 3602def : Pat<(srl i32:$rS, i32:$rB), 3603 (SRW $rS, $rB)>; 3604def : Pat<(shl i32:$rS, i32:$rB), 3605 (SLW $rS, $rB)>; 3606 3607def : Pat<(i32 (zextloadi1 DForm:$src)), 3608 (LBZ DForm:$src)>; 3609def : Pat<(i32 (zextloadi1 XForm:$src)), 3610 (LBZX XForm:$src)>; 3611def : Pat<(i32 (extloadi1 DForm:$src)), 3612 (LBZ DForm:$src)>; 3613def : Pat<(i32 (extloadi1 XForm:$src)), 3614 (LBZX XForm:$src)>; 3615def : Pat<(i32 (extloadi8 DForm:$src)), 3616 (LBZ DForm:$src)>; 3617def : Pat<(i32 (extloadi8 XForm:$src)), 3618 (LBZX XForm:$src)>; 3619def : Pat<(i32 (extloadi16 DForm:$src)), 3620 (LHZ DForm:$src)>; 3621def : Pat<(i32 (extloadi16 XForm:$src)), 3622 (LHZX XForm:$src)>; 3623let Predicates = [HasFPU] in { 3624def : Pat<(f64 (extloadf32 DForm:$src)), 3625 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3626def : Pat<(f64 (extloadf32 XForm:$src)), 3627 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3628 3629def : Pat<(f64 (any_fpextend f32:$src)), 3630 (COPY_TO_REGCLASS $src, F8RC)>; 3631} 3632 3633// Only seq_cst fences require the heavyweight sync (SYNC 0). 3634// All others can use the lightweight sync (SYNC 1). 3635// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3636// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3637// versions of Power. 3638def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3639def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3640def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3641def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3642 3643let Predicates = [HasFPU] in { 3644// Additional fnmsub patterns for custom node 3645def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3646 (FNMSUB $A, $B, $C)>; 3647def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3648 (FNMSUBS $A, $B, $C)>; 3649def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3650 (FMSUB $A, $B, $C)>; 3651def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3652 (FMSUBS $A, $B, $C)>; 3653def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3654 (FNMADD $A, $B, $C)>; 3655def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3656 (FNMADDS $A, $B, $C)>; 3657 3658// FCOPYSIGN's operand types need not agree. 3659def : Pat<(fcopysign f64:$frB, f32:$frA), 3660 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3661def : Pat<(fcopysign f32:$frB, f64:$frA), 3662 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3663} 3664 3665// XL Compat intrinsics. 3666def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3667def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3668def : Pat<(int_ppc_fnmsub f64:$A, f64:$B, f64:$C), (FNMSUB $A, $B, $C)>; 3669def : Pat<(int_ppc_fnmsubs f32:$A, f32:$B, f32:$C), (FNMSUBS $A, $B, $C)>; 3670def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3671def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3672def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3673def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3674 3675include "PPCInstrAltivec.td" 3676include "PPCInstrSPE.td" 3677include "PPCInstr64Bit.td" 3678include "PPCInstrVSX.td" 3679include "PPCInstrHTM.td" 3680 3681def crnot : OutPatFrag<(ops node:$in), 3682 (CRNOR $in, $in)>; 3683def : Pat<(not i1:$in), 3684 (crnot $in)>; 3685 3686// Prefixed instructions may require access to the above defs at a later 3687// time so we include this after the def. 3688include "PPCInstrPrefix.td" 3689 3690// Patterns for arithmetic i1 operations. 3691def : Pat<(add i1:$a, i1:$b), 3692 (CRXOR $a, $b)>; 3693def : Pat<(sub i1:$a, i1:$b), 3694 (CRXOR $a, $b)>; 3695def : Pat<(mul i1:$a, i1:$b), 3696 (CRAND $a, $b)>; 3697 3698// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3699// (-1 is used to mean all bits set). 3700def : Pat<(i1 -1), (CRSET)>; 3701 3702// i1 extensions, implemented in terms of isel. 3703def : Pat<(i32 (zext i1:$in)), 3704 (SELECT_I4 $in, (LI 1), (LI 0))>; 3705def : Pat<(i32 (sext i1:$in)), 3706 (SELECT_I4 $in, (LI -1), (LI 0))>; 3707 3708def : Pat<(i64 (zext i1:$in)), 3709 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3710def : Pat<(i64 (sext i1:$in)), 3711 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3712 3713// FIXME: We should choose either a zext or a sext based on other constants 3714// already around. 3715def : Pat<(i32 (anyext i1:$in)), 3716 (SELECT_I4 $in, (LI 1), (LI 0))>; 3717def : Pat<(i64 (anyext i1:$in)), 3718 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3719 3720// match setcc on i1 variables. 3721// CRANDC is: 3722// 1 1 : F 3723// 1 0 : T 3724// 0 1 : F 3725// 0 0 : F 3726// 3727// LT is: 3728// -1 -1 : F 3729// -1 0 : T 3730// 0 -1 : F 3731// 0 0 : F 3732// 3733// ULT is: 3734// 1 1 : F 3735// 1 0 : F 3736// 0 1 : T 3737// 0 0 : F 3738def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3739 (CRANDC $s1, $s2)>; 3740def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3741 (CRANDC $s2, $s1)>; 3742// CRORC is: 3743// 1 1 : T 3744// 1 0 : T 3745// 0 1 : F 3746// 0 0 : T 3747// 3748// LE is: 3749// -1 -1 : T 3750// -1 0 : T 3751// 0 -1 : F 3752// 0 0 : T 3753// 3754// ULE is: 3755// 1 1 : T 3756// 1 0 : F 3757// 0 1 : T 3758// 0 0 : T 3759def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3760 (CRORC $s1, $s2)>; 3761def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3762 (CRORC $s2, $s1)>; 3763 3764def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3765 (CREQV $s1, $s2)>; 3766 3767// GE is: 3768// -1 -1 : T 3769// -1 0 : F 3770// 0 -1 : T 3771// 0 0 : T 3772// 3773// UGE is: 3774// 1 1 : T 3775// 1 0 : T 3776// 0 1 : F 3777// 0 0 : T 3778def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3779 (CRORC $s2, $s1)>; 3780def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3781 (CRORC $s1, $s2)>; 3782 3783// GT is: 3784// -1 -1 : F 3785// -1 0 : F 3786// 0 -1 : T 3787// 0 0 : F 3788// 3789// UGT is: 3790// 1 1 : F 3791// 1 0 : T 3792// 0 1 : F 3793// 0 0 : F 3794def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3795 (CRANDC $s2, $s1)>; 3796def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3797 (CRANDC $s1, $s2)>; 3798 3799def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3800 (CRXOR $s1, $s2)>; 3801 3802// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3803// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3804// floating-point types. 3805 3806multiclass CRNotPat<dag pattern, dag result> { 3807 def : Pat<pattern, (crnot result)>; 3808 def : Pat<(not pattern), result>; 3809 3810 // We can also fold the crnot into an extension: 3811 def : Pat<(i32 (zext pattern)), 3812 (SELECT_I4 result, (LI 0), (LI 1))>; 3813 def : Pat<(i32 (sext pattern)), 3814 (SELECT_I4 result, (LI 0), (LI -1))>; 3815 3816 // We can also fold the crnot into an extension: 3817 def : Pat<(i64 (zext pattern)), 3818 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3819 def : Pat<(i64 (sext pattern)), 3820 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3821 3822 // FIXME: We should choose either a zext or a sext based on other constants 3823 // already around. 3824 def : Pat<(i32 (anyext pattern)), 3825 (SELECT_I4 result, (LI 0), (LI 1))>; 3826 3827 def : Pat<(i64 (anyext pattern)), 3828 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3829} 3830 3831// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3832// we need to write imm:$imm in the output patterns below, not just $imm, or 3833// else the resulting matcher will not correctly add the immediate operand 3834// (making it a register operand instead). 3835 3836// extended SETCC. 3837multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3838 OutPatFrag rfrag, OutPatFrag rfrag8> { 3839 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3840 (rfrag $s1)>; 3841 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3842 (rfrag8 $s1)>; 3843 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3844 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3845 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3846 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3847 3848 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3849 (rfrag $s1)>; 3850 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3851 (rfrag8 $s1)>; 3852 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3853 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3854 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3855 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3856} 3857 3858// Note that we do all inversions below with i(32|64)not, instead of using 3859// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3860// has 2-cycle latency. 3861 3862defm : ExtSetCCPat<SETEQ, 3863 PatFrag<(ops node:$in, node:$cc), 3864 (setcc $in, 0, $cc)>, 3865 OutPatFrag<(ops node:$in), 3866 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3867 OutPatFrag<(ops node:$in), 3868 (RLDICL (CNTLZD $in), 58, 63)> >; 3869 3870defm : ExtSetCCPat<SETNE, 3871 PatFrag<(ops node:$in, node:$cc), 3872 (setcc $in, 0, $cc)>, 3873 OutPatFrag<(ops node:$in), 3874 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3875 OutPatFrag<(ops node:$in), 3876 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3877 3878defm : ExtSetCCPat<SETLT, 3879 PatFrag<(ops node:$in, node:$cc), 3880 (setcc $in, 0, $cc)>, 3881 OutPatFrag<(ops node:$in), 3882 (RLWINM $in, 1, 31, 31)>, 3883 OutPatFrag<(ops node:$in), 3884 (RLDICL $in, 1, 63)> >; 3885 3886defm : ExtSetCCPat<SETGE, 3887 PatFrag<(ops node:$in, node:$cc), 3888 (setcc $in, 0, $cc)>, 3889 OutPatFrag<(ops node:$in), 3890 (RLWINM (i32not $in), 1, 31, 31)>, 3891 OutPatFrag<(ops node:$in), 3892 (RLDICL (i64not $in), 1, 63)> >; 3893 3894defm : ExtSetCCPat<SETGT, 3895 PatFrag<(ops node:$in, node:$cc), 3896 (setcc $in, 0, $cc)>, 3897 OutPatFrag<(ops node:$in), 3898 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3899 OutPatFrag<(ops node:$in), 3900 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3901 3902defm : ExtSetCCPat<SETLE, 3903 PatFrag<(ops node:$in, node:$cc), 3904 (setcc $in, 0, $cc)>, 3905 OutPatFrag<(ops node:$in), 3906 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3907 OutPatFrag<(ops node:$in), 3908 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3909 3910defm : ExtSetCCPat<SETLT, 3911 PatFrag<(ops node:$in, node:$cc), 3912 (setcc $in, -1, $cc)>, 3913 OutPatFrag<(ops node:$in), 3914 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3915 OutPatFrag<(ops node:$in), 3916 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3917 3918defm : ExtSetCCPat<SETGE, 3919 PatFrag<(ops node:$in, node:$cc), 3920 (setcc $in, -1, $cc)>, 3921 OutPatFrag<(ops node:$in), 3922 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3923 OutPatFrag<(ops node:$in), 3924 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3925 3926defm : ExtSetCCPat<SETGT, 3927 PatFrag<(ops node:$in, node:$cc), 3928 (setcc $in, -1, $cc)>, 3929 OutPatFrag<(ops node:$in), 3930 (RLWINM (i32not $in), 1, 31, 31)>, 3931 OutPatFrag<(ops node:$in), 3932 (RLDICL (i64not $in), 1, 63)> >; 3933 3934defm : ExtSetCCPat<SETLE, 3935 PatFrag<(ops node:$in, node:$cc), 3936 (setcc $in, -1, $cc)>, 3937 OutPatFrag<(ops node:$in), 3938 (RLWINM $in, 1, 31, 31)>, 3939 OutPatFrag<(ops node:$in), 3940 (RLDICL $in, 1, 63)> >; 3941 3942// An extended SETCC with shift amount. 3943multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3944 OutPatFrag rfrag, OutPatFrag rfrag8> { 3945 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3946 (rfrag $s1, $sa)>; 3947 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3948 (rfrag8 $s1, $sa)>; 3949 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3950 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3951 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3952 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3953 3954 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3955 (rfrag $s1, $sa)>; 3956 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3957 (rfrag8 $s1, $sa)>; 3958 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3959 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3960 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3961 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3962} 3963 3964defm : ExtSetCCShiftPat<SETNE, 3965 PatFrag<(ops node:$in, node:$sa, node:$cc), 3966 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3967 OutPatFrag<(ops node:$in, node:$sa), 3968 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3969 OutPatFrag<(ops node:$in, node:$sa), 3970 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3971 3972defm : ExtSetCCShiftPat<SETEQ, 3973 PatFrag<(ops node:$in, node:$sa, node:$cc), 3974 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3975 OutPatFrag<(ops node:$in, node:$sa), 3976 (RLWNM (i32not $in), 3977 (SUBFIC $sa, 32), 31, 31)>, 3978 OutPatFrag<(ops node:$in, node:$sa), 3979 (RLDCL (i64not $in), 3980 (SUBFIC $sa, 64), 63)> >; 3981 3982// SETCC for i32. 3983def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3984 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3985def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3986 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3987def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3988 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3989def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3990 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3991def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3992 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3993def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3994 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3995 3996// For non-equality comparisons, the default code would materialize the 3997// constant, then compare against it, like this: 3998// lis r2, 4660 3999// ori r2, r2, 22136 4000// cmpw cr0, r3, r2 4001// beq cr0,L6 4002// Since we are just comparing for equality, we can emit this instead: 4003// xoris r0,r3,0x1234 4004// cmplwi cr0,r0,0x5678 4005// beq cr0,L6 4006 4007def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 4008 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 4009 (LO16 imm:$imm)), sub_eq)>; 4010 4011def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 4012 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 4013def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 4014 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 4015def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 4016 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 4017def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 4018 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 4019def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 4020 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 4021 4022// SETCC for i64. 4023def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 4024 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 4025def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 4026 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 4027def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 4028 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 4029def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 4030 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 4031def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 4032 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 4033def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 4034 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 4035 4036// For non-equality comparisons, the default code would materialize the 4037// constant, then compare against it, like this: 4038// lis r2, 4660 4039// ori r2, r2, 22136 4040// cmpd cr0, r3, r2 4041// beq cr0,L6 4042// Since we are just comparing for equality, we can emit this instead: 4043// xoris r0,r3,0x1234 4044// cmpldi cr0,r0,0x5678 4045// beq cr0,L6 4046 4047def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 4048 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 4049 (LO16 imm:$imm)), sub_eq)>; 4050 4051def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 4052 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 4053def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 4054 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 4055def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 4056 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 4057def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 4058 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 4059def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 4060 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 4061 4062let Predicates = [IsNotISA3_1] in { 4063// Instantiations of CRNotPat for i32. 4064defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 4065 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 4066defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 4067 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 4068defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 4069 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 4070defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 4071 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 4072defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 4073 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 4074defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 4075 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 4076 4077defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 4078 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 4079 (LO16 imm:$imm)), sub_eq)>; 4080 4081defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 4082 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 4083defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 4084 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 4085defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 4086 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 4087defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 4088 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 4089defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 4090 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 4091 4092// Instantiations of CRNotPat for i64. 4093defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 4094 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 4095defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 4096 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 4097defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 4098 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 4099defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 4100 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 4101defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 4102 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 4103defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 4104 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 4105 4106defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 4107 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 4108 (LO16 imm:$imm)), sub_eq)>; 4109 4110defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 4111 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 4112defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 4113 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 4114defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 4115 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 4116defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 4117 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 4118defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 4119 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 4120} 4121 4122multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 4123 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 4124 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 4125 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 4126 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 4127 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 4128 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 4129 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 4130 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 4131 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 4132 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 4133 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 4134 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 4135 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 4136 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 4137 4138 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 4139 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 4140 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 4141 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 4142 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 4143 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 4144 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 4145 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 4146 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 4147 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 4148 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 4149 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 4150 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 4151 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 4152} 4153 4154let Predicates = [HasFPU] in { 4155// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 4156// SETCC for f32. 4157defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 4158 4159// SETCC for f64. 4160defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 4161 4162// SETCC for f128. 4163defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 4164 4165// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 4166// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 4167// then VXVC is set. 4168// SETCCS for f32. 4169defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 4170 4171// SETCCS for f64. 4172defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 4173 4174// SETCCS for f128. 4175defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 4176} 4177 4178// This must be in this file because it relies on patterns defined in this file 4179// after the inclusion of the instruction sets. 4180let Predicates = [HasSPE] in { 4181// SETCC for f32. 4182def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 4183 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4184def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 4185 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4186def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 4187 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4188def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 4189 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4190def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 4191 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4192def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 4193 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4194 4195defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 4196 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4197defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 4198 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4199defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 4200 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4201defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 4202 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4203defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 4204 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4205defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 4206 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4207 4208// SETCC for f64. 4209def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 4210 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4211def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 4212 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4213def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 4214 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4215def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 4216 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4217def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 4218 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4219def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 4220 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4221 4222defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 4223 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4224defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 4225 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4226defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 4227 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4228defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 4229 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4230defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 4231 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4232defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 4233 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4234} 4235// match select on i1 variables: 4236def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 4237 (CROR (CRAND $cond , $tval), 4238 (CRAND (crnot $cond), $fval))>; 4239 4240// match selectcc on i1 variables: 4241// select (lhs == rhs), tval, fval is: 4242// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 4243def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 4244 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4245 (CRAND (CRORC $rhs, $lhs), $fval))>; 4246def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 4247 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4248 (CRAND (CRORC $lhs, $rhs), $fval))>; 4249def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4250 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4251 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4252def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4253 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4254 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4255def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4256 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4257 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4258def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4259 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4260 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4261def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4262 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4263 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4264def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4265 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4266 (CRAND (CRORC $lhs, $rhs), $fval))>; 4267def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4268 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4269 (CRAND (CRORC $rhs, $lhs), $fval))>; 4270def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4271 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4272 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4273 4274// match selectcc on i1 variables with non-i1 output. 4275def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4276 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4277def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4278 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4279def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4280 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4281def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4282 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4283def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4284 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4285def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4286 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4287def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4288 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4289def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4290 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4291def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4292 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4293def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4294 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4295 4296def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4297 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4298def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4299 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4300def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4301 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4302def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4303 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4304def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4305 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4306def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4307 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4308def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4309 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4310def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4311 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4312def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4313 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4314def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4315 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4316 4317let Predicates = [HasFPU] in { 4318def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4319 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4320def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4321 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4322def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4323 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4324def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4325 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4326def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4327 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4328def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4329 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4330def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4331 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4332def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4333 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4334def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4335 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4336def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4337 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4338 4339def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4340 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4341def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4342 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4343def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4344 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4345def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4346 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4347def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4348 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4349def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4350 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4351def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4352 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4353def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4354 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4355def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4356 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4357def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4358 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4359} 4360 4361def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4362 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4363def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4364 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4365def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4366 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4367def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4368 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4369def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4370 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4371def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4372 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4373def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4374 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4375def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4376 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4377def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4378 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4379def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4380 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4381 4382def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4383 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4384def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4385 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4386def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4387 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4388def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4389 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4390def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4391 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4392def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4393 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4394def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4395 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4396def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4397 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4398def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4399 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4400def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4401 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4402 4403def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4404 "#ANDI_rec_1_EQ_BIT", 4405 [(set i1:$dst, (trunc (not i32:$in)))]>; 4406def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4407 "#ANDI_rec_1_GT_BIT", 4408 [(set i1:$dst, (trunc i32:$in))]>; 4409 4410def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4411 "#ANDI_rec_1_EQ_BIT8", 4412 [(set i1:$dst, (trunc (not i64:$in)))]>; 4413def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4414 "#ANDI_rec_1_GT_BIT8", 4415 [(set i1:$dst, (trunc i64:$in))]>; 4416 4417def : Pat<(i1 (not (trunc i32:$in))), 4418 (ANDI_rec_1_EQ_BIT $in)>; 4419def : Pat<(i1 (not (trunc i64:$in))), 4420 (ANDI_rec_1_EQ_BIT8 $in)>; 4421 4422def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 4423def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 4424def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 4425 4426//===----------------------------------------------------------------------===// 4427// PowerPC Instructions used for assembler/disassembler only 4428// 4429 4430// FIXME: For B=0 or B > 8, the registers following RT are used. 4431// WARNING: Do not add patterns for this instruction without fixing this. 4432def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), 4433 (ins gprc:$A, u5imm:$B), 4434 "lswi $RT, $A, $B", IIC_LdStLoad, []>; 4435 4436// FIXME: For B=0 or B > 8, the registers following RT are used. 4437// WARNING: Do not add patterns for this instruction without fixing this. 4438def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4439 (ins gprc:$RT, gprc:$A, u5imm:$B), 4440 "stswi $RT, $A, $B", IIC_LdStLoad, []>; 4441 4442def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4443 "isync", IIC_SprISYNC, []>; 4444 4445def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 4446 "icbi $src", IIC_LdStICBI, []>; 4447 4448def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4449 "wait $L", IIC_LdStLoad, []>; 4450 4451def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4452 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4453 4454def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4455 "mtsr $SR, $RS", IIC_SprMTSR>; 4456 4457def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4458 "mfsr $RS, $SR", IIC_SprMFSR>; 4459 4460def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4461 "mtsrin $RS, $RB", IIC_SprMTSR>; 4462 4463def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4464 "mfsrin $RS, $RB", IIC_SprMFSR>; 4465 4466def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4467 "mtmsr $RS, $L", IIC_SprMTMSR>; 4468 4469def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4470 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4471 let L = 0; 4472} 4473 4474def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4475 Requires<[IsBookE]> { 4476 bits<1> E; 4477 4478 let Inst{16} = E; 4479 let Inst{21-30} = 163; 4480} 4481 4482def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), 4483 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4484def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), 4485 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4486 4487def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4488def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4489def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4490def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4491 4492def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), 4493 "mfmsr $RT", IIC_SprMFMSR, []>; 4494 4495def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4496 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4497 4498def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4499 "mcrfs $BF, $BFA", IIC_BrMCR>; 4500 4501// All MTFSF variants may change the rounding mode so conservatively set it 4502// as an implicit def for all of them. 4503let Predicates = [HasFPU] in { 4504let Defs = [RM] in { 4505let isCodeGenOnly = 1, 4506 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4507def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4508 "mtfsfi $BF, $U", IIC_IntMFFS>; 4509def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4510 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4511let Defs = [CR1] in 4512def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4513 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4514 4515def MTFSF : XFLForm_1<63, 711, (outs), 4516 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4517 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4518let Defs = [CR1] in 4519def MTFSF_rec : XFLForm_1<63, 711, (outs), 4520 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4521 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4522} 4523 4524def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4525def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4526def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4527def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4528} 4529 4530def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4531 "slbie $RB", IIC_SprSLBIE, []>; 4532 4533def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), 4534 "slbmte $RS, $RB", IIC_SprSLBMTE, []>; 4535 4536def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), 4537 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; 4538 4539def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4540 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4541 4542def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4543 4544let Defs = [CR0] in 4545def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), 4546 "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4547 4548def TLBIA : XForm_0<31, 370, (outs), (ins), 4549 "tlbia", IIC_SprTLBIA, []>; 4550 4551def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4552 "tlbsync", IIC_SprTLBSYNC, []>; 4553 4554def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4555 "tlbiel $RB", IIC_SprTLBIEL, []>; 4556 4557def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4558 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4559def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4560 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4561 4562def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), 4563 "tlbie $RB,$RS", IIC_SprTLBIE, []>; 4564 4565def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", 4566 IIC_LdStLoad>, Requires<[IsBookE]>; 4567 4568def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", 4569 IIC_LdStLoad>, Requires<[IsBookE]>; 4570 4571def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4572 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4573 4574def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4575 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4576 4577def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), 4578 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4579 4580def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), 4581 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4582 4583def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), 4584 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, 4585 Requires<[IsPPC4xx]>; 4586def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4587 (ins gprc:$RST, gprc:$A, gprc:$B), 4588 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, 4589 Requires<[IsPPC4xx]>, isRecordForm; 4590 4591def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4592 4593def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4594 Requires<[IsBookE]>; 4595def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4596 Requires<[IsBookE]>; 4597 4598def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4599 Requires<[IsE500]>; 4600def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4601 Requires<[IsE500]>; 4602 4603def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), 4604 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4605def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), 4606 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4607 4608def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4609def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4610 4611def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4612 4613def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4614 (ins gprc:$A, gprc:$B), 4615 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; 4616def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4617 (ins gprc:$A, gprc:$B), 4618 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; 4619def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4620 (ins gprc:$A, gprc:$B), 4621 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; 4622def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4623 (ins gprc:$A, gprc:$B), 4624 "ldcix $RST, $A, $B", IIC_LdStLoad, []>; 4625 4626def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4627 (ins gprc:$RST, gprc:$A, gprc:$B), 4628 "stbcix $RST, $A, $B", IIC_LdStLoad, []>; 4629def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4630 (ins gprc:$RST, gprc:$A, gprc:$B), 4631 "sthcix $RST, $A, $B", IIC_LdStLoad, []>; 4632def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4633 (ins gprc:$RST, gprc:$A, gprc:$B), 4634 "stwcix $RST, $A, $B", IIC_LdStLoad, []>; 4635def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4636 (ins gprc:$RST, gprc:$A, gprc:$B), 4637 "stdcix $RST, $A, $B", IIC_LdStLoad, []>; 4638 4639// External PID Load Store Instructions 4640 4641def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), 4642 "lbepx $rD, $src", IIC_LdStLoad, []>, 4643 Requires<[IsE500]>; 4644 4645def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), 4646 "lfdepx $frD, $src", IIC_LdStLFD, []>, 4647 Requires<[IsE500]>; 4648 4649def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), 4650 "lhepx $rD, $src", IIC_LdStLoad, []>, 4651 Requires<[IsE500]>; 4652 4653def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), 4654 "lwepx $rD, $src", IIC_LdStLoad, []>, 4655 Requires<[IsE500]>; 4656 4657def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), 4658 "stbepx $rS, $dst", IIC_LdStStore, []>, 4659 Requires<[IsE500]>; 4660 4661def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), 4662 "stfdepx $frS, $dst", IIC_LdStSTFD, []>, 4663 Requires<[IsE500]>; 4664 4665def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), 4666 "sthepx $rS, $dst", IIC_LdStStore, []>, 4667 Requires<[IsE500]>; 4668 4669def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), 4670 "stwepx $rS, $dst", IIC_LdStStore, []>, 4671 Requires<[IsE500]>; 4672 4673def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", 4674 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4675 4676def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", 4677 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4678 4679def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), 4680 "dcbtep $TH, $dst", IIC_LdStDCBF, []>, 4681 Requires<[IsE500]>; 4682 4683def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), 4684 "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, 4685 Requires<[IsE500]>; 4686 4687def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", 4688 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4689 4690def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", 4691 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4692 4693def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", 4694 IIC_LdStICBI, []>, Requires<[IsE500]>; 4695 4696//===----------------------------------------------------------------------===// 4697// PowerPC Assembler Instruction Aliases 4698// 4699 4700// Pseudo-instructions for alternate assembly syntax (never used by codegen). 4701// These are aliases that require C++ handling to convert to the target 4702// instruction, while InstAliases can be handled directly by tblgen. 4703class PPCAsmPseudo<string asm, dag iops> 4704 : Instruction { 4705 let Namespace = "PPC"; 4706 bit PPC64 = 0; // Default value, override with isPPC64 4707 4708 let OutOperandList = (outs); 4709 let InOperandList = iops; 4710 let Pattern = []; 4711 let AsmString = asm; 4712 let isAsmParserOnly = 1; 4713 let isPseudo = 1; 4714 let hasNoSchedulingInfo = 1; 4715} 4716 4717def : InstAlias<"sc", (SC 0)>; 4718 4719def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4720def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4721def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4722def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4723 4724def : InstAlias<"wait", (WAIT 0)>; 4725def : InstAlias<"waitrsv", (WAIT 1)>; 4726def : InstAlias<"waitimpl", (WAIT 2)>; 4727 4728def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4729 4730def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4731def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4732 4733def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4734def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4735def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4736 4737def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4738def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4739def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4740 4741def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4742def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4743def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4744 4745def : Pat<(int_ppc_isync), (ISYNC)>; 4746def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4747 (DCBF 1, xoaddr:$dst)>; 4748def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4749 (DCBF 3, xoaddr:$dst)>; 4750 4751let Predicates = [IsISA3_1] in { 4752 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4753 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4754 4755 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4756 (DCBF 4, xoaddr:$dst)>; 4757 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4758 (DCBF 6, xoaddr:$dst)>; 4759} 4760 4761def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4762def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4763def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4764def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4765 4766def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4767def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4768def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4769 4770def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4771 4772def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4773def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4774 4775//Disable this alias on AIX for now because as does not support them. 4776let Predicates = [ModernAs] in { 4777 4778foreach BR = 0-7 in { 4779 def : InstAlias<"mfbr"#BR#" $Rx", 4780 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4781 Requires<[IsPPC4xx]>; 4782 def : InstAlias<"mtbr"#BR#" $Rx", 4783 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4784 Requires<[IsPPC4xx]>; 4785} 4786 4787def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4788def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4789def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4790def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4791 4792def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4793def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4794 4795def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4796def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4797 4798def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4799def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4800 4801def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4802def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4803 4804def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4805def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4806 4807def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4808def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4809 4810def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4811def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4812 4813def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4814def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4815 4816def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4817def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4818 4819def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4820def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4821 4822def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4823def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4824 4825def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4826def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4827 4828def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4829def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4830 4831def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4832def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4833 4834foreach SPRG = 4-7 in { 4835 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4836 Requires<[IsBookE]>; 4837 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4838 Requires<[IsBookE]>; 4839 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4840 Requires<[IsBookE]>; 4841 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4842 Requires<[IsBookE]>; 4843} 4844 4845foreach SPRG = 0-3 in { 4846 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4847 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4848 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4849 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4850} 4851 4852def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4853def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4854 4855def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4856def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4857 4858def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4859 4860def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4861def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4862 4863foreach BATR = 0-3 in { 4864 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4865 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4866 Requires<[IsPPC6xx]>; 4867 def : InstAlias<"mfdbatu $Rx, "#BATR, 4868 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4869 Requires<[IsPPC6xx]>; 4870 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4871 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4872 Requires<[IsPPC6xx]>; 4873 def : InstAlias<"mfdbatl $Rx, "#BATR, 4874 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4875 Requires<[IsPPC6xx]>; 4876 def : InstAlias<"mtibatu "#BATR#", $Rx", 4877 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4878 Requires<[IsPPC6xx]>; 4879 def : InstAlias<"mfibatu $Rx, "#BATR, 4880 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4881 Requires<[IsPPC6xx]>; 4882 def : InstAlias<"mtibatl "#BATR#", $Rx", 4883 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4884 Requires<[IsPPC6xx]>; 4885 def : InstAlias<"mfibatl $Rx, "#BATR, 4886 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4887 Requires<[IsPPC6xx]>; 4888} 4889 4890def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4891def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4892 4893def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4894def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4895 4896def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4897def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4898 4899def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4900def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4901 4902def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4903def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4904 4905def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4906def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4907 4908def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4909def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4910 4911def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4912def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4913 4914def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4915def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4916 4917def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4918def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4919 4920} 4921 4922def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4923 4924def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4925 Requires<[IsPPC4xx]>; 4926def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4927 Requires<[IsPPC4xx]>; 4928def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4929 Requires<[IsPPC4xx]>; 4930def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4931 Requires<[IsPPC4xx]>; 4932 4933def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 4934 4935def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4936 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4937def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4938 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4939def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4940 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4941def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4942 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4943 4944def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4945 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4946def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4947 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4948def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4949 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4950def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4951 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4952def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4953 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4954def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4955 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4956def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4957 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4958def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4959 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4960def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4961 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4962def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4963 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4964def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4965 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4966def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4967 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4968def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4969 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4970def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4971 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4972def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4973 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4974def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4975 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4976def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4977 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4978def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4979 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4980 4981def : InstAlias<"isellt $rT, $rA, $rB", 4982 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4983def : InstAlias<"iselgt $rT, $rA, $rB", 4984 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4985def : InstAlias<"iseleq $rT, $rA, $rB", 4986 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4987 4988def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4989def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4990def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4991def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4992def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4993def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4994 4995def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4996def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4997// The POWER variant 4998def : MnemonicAlias<"cntlz", "cntlzw">; 4999def : MnemonicAlias<"cntlz.", "cntlzw.">; 5000 5001def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 5002 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5003def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 5004 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5005def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 5006 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5007def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 5008 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5009def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 5010 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5011def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 5012 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 5013def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 5014 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5015def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 5016 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5017def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 5018 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5019def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 5020 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5021def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 5022 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5023def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 5024 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5025def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 5026 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5027def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 5028 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 5029def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 5030 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 5031def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 5032 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 5033def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 5034 5035def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 5036def : InstAlias<"rotldi $rA, $rS, $n", 5037 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 5038def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 5039def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 5040def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 5041def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 5042def : InstAlias<"clrldi $rA, $rS, $n", 5043 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 5044def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 5045def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 5046 5047def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 5048 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5049def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 5050 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5051def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 5052 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5053def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 5054 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5055def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 5056 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5057def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 5058 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 5059 5060// These generic branch instruction forms are used for the assembler parser only. 5061// Defs and Uses are conservative, since we don't know the BO value. 5062let PPC970_Unit = 7, isBranch = 1 in { 5063 let Defs = [CTR], Uses = [CTR, RM] in { 5064 def gBC : BForm_3<16, 0, 0, (outs), 5065 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 5066 "bc $bo, $bi, $dst">; 5067 def gBCA : BForm_3<16, 1, 0, (outs), 5068 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 5069 "bca $bo, $bi, $dst">; 5070 let isAsmParserOnly = 1 in { 5071 def gBCat : BForm_3_at<16, 0, 0, (outs), 5072 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 5073 condbrtarget:$dst), 5074 "bc$at $bo, $bi, $dst">; 5075 def gBCAat : BForm_3_at<16, 1, 0, (outs), 5076 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 5077 abscondbrtarget:$dst), 5078 "bca$at $bo, $bi, $dst">; 5079 } // isAsmParserOnly = 1 5080 } 5081 let Defs = [LR, CTR], Uses = [CTR, RM] in { 5082 def gBCL : BForm_3<16, 0, 1, (outs), 5083 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 5084 "bcl $bo, $bi, $dst">; 5085 def gBCLA : BForm_3<16, 1, 1, (outs), 5086 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 5087 "bcla $bo, $bi, $dst">; 5088 let isAsmParserOnly = 1 in { 5089 def gBCLat : BForm_3_at<16, 0, 1, (outs), 5090 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 5091 condbrtarget:$dst), 5092 "bcl$at $bo, $bi, $dst">; 5093 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 5094 (ins u5imm:$bo, atimm:$at, crbitrc:$bi, 5095 abscondbrtarget:$dst), 5096 "bcla$at $bo, $bi, $dst">; 5097 } // // isAsmParserOnly = 1 5098 } 5099 let Defs = [CTR], Uses = [CTR, LR, RM] in 5100 def gBCLR : XLForm_2<19, 16, 0, (outs), 5101 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 5102 "bclr $bo, $bi, $bh", IIC_BrB, []>; 5103 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 5104 def gBCLRL : XLForm_2<19, 16, 1, (outs), 5105 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 5106 "bclrl $bo, $bi, $bh", IIC_BrB, []>; 5107 let Defs = [CTR], Uses = [CTR, LR, RM] in 5108 def gBCCTR : XLForm_2<19, 528, 0, (outs), 5109 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 5110 "bcctr $bo, $bi, $bh", IIC_BrB, []>; 5111 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 5112 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 5113 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 5114 "bcctrl $bo, $bi, $bh", IIC_BrB, []>; 5115} 5116 5117multiclass BranchSimpleMnemonicAT<string pm, int at> { 5118 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 5119 condbrtarget:$dst)>; 5120 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 5121 condbrtarget:$dst)>; 5122 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 5123 condbrtarget:$dst)>; 5124 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 5125 condbrtarget:$dst)>; 5126} 5127defm : BranchSimpleMnemonicAT<"+", 3>; 5128defm : BranchSimpleMnemonicAT<"-", 2>; 5129 5130def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 5131def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 5132def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 5133def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 5134 5135multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 5136 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 5137 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 5138 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 5139 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 5140 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 5141 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 5142} 5143multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 5144 : BranchSimpleMnemonic1<name, pm, bo> { 5145 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 5146 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 5147} 5148defm : BranchSimpleMnemonic2<"t", "", 12>; 5149defm : BranchSimpleMnemonic2<"f", "", 4>; 5150defm : BranchSimpleMnemonic2<"t", "-", 14>; 5151defm : BranchSimpleMnemonic2<"f", "-", 6>; 5152defm : BranchSimpleMnemonic2<"t", "+", 15>; 5153defm : BranchSimpleMnemonic2<"f", "+", 7>; 5154defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 5155defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 5156defm : BranchSimpleMnemonic1<"dzt", "", 10>; 5157defm : BranchSimpleMnemonic1<"dzf", "", 2>; 5158 5159multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 5160 def : InstAlias<"b"#name#pm#" $cc, $dst", 5161 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 5162 def : InstAlias<"b"#name#pm#" $dst", 5163 (BCC bibo, CR0, condbrtarget:$dst)>; 5164 5165 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 5166 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 5167 def : InstAlias<"b"#name#"a"#pm#" $dst", 5168 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 5169 5170 def : InstAlias<"b"#name#"lr"#pm#" $cc", 5171 (BCCLR bibo, crrc:$cc)>; 5172 def : InstAlias<"b"#name#"lr"#pm, 5173 (BCCLR bibo, CR0)>; 5174 5175 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 5176 (BCCCTR bibo, crrc:$cc)>; 5177 def : InstAlias<"b"#name#"ctr"#pm, 5178 (BCCCTR bibo, CR0)>; 5179 5180 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 5181 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 5182 def : InstAlias<"b"#name#"l"#pm#" $dst", 5183 (BCCL bibo, CR0, condbrtarget:$dst)>; 5184 5185 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 5186 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 5187 def : InstAlias<"b"#name#"la"#pm#" $dst", 5188 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 5189 5190 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 5191 (BCCLRL bibo, crrc:$cc)>; 5192 def : InstAlias<"b"#name#"lrl"#pm, 5193 (BCCLRL bibo, CR0)>; 5194 5195 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 5196 (BCCCTRL bibo, crrc:$cc)>; 5197 def : InstAlias<"b"#name#"ctrl"#pm, 5198 (BCCCTRL bibo, CR0)>; 5199} 5200multiclass BranchExtendedMnemonic<string name, int bibo> { 5201 defm : BranchExtendedMnemonicPM<name, "", bibo>; 5202 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 5203 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 5204} 5205defm : BranchExtendedMnemonic<"lt", 12>; 5206defm : BranchExtendedMnemonic<"gt", 44>; 5207defm : BranchExtendedMnemonic<"eq", 76>; 5208defm : BranchExtendedMnemonic<"un", 108>; 5209defm : BranchExtendedMnemonic<"so", 108>; 5210defm : BranchExtendedMnemonic<"ge", 4>; 5211defm : BranchExtendedMnemonic<"nl", 4>; 5212defm : BranchExtendedMnemonic<"le", 36>; 5213defm : BranchExtendedMnemonic<"ng", 36>; 5214defm : BranchExtendedMnemonic<"ne", 68>; 5215defm : BranchExtendedMnemonic<"nu", 100>; 5216defm : BranchExtendedMnemonic<"ns", 100>; 5217 5218def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 5219def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 5220def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 5221def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 5222def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 5223def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 5224def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 5225def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 5226 5227def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 5228def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 5229def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 5230def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 5231def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 5232def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5233def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 5234def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5235 5236def : InstAlias<"trap", (TW 31, R0, R0)>; 5237 5238multiclass TrapExtendedMnemonic<string name, int to> { 5239 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 5240 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 5241 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 5242 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 5243} 5244defm : TrapExtendedMnemonic<"lt", 16>; 5245defm : TrapExtendedMnemonic<"le", 20>; 5246defm : TrapExtendedMnemonic<"eq", 4>; 5247defm : TrapExtendedMnemonic<"ge", 12>; 5248defm : TrapExtendedMnemonic<"gt", 8>; 5249defm : TrapExtendedMnemonic<"nl", 12>; 5250defm : TrapExtendedMnemonic<"ne", 24>; 5251defm : TrapExtendedMnemonic<"ng", 20>; 5252defm : TrapExtendedMnemonic<"llt", 2>; 5253defm : TrapExtendedMnemonic<"lle", 6>; 5254defm : TrapExtendedMnemonic<"lge", 5>; 5255defm : TrapExtendedMnemonic<"lgt", 1>; 5256defm : TrapExtendedMnemonic<"lnl", 5>; 5257defm : TrapExtendedMnemonic<"lng", 6>; 5258defm : TrapExtendedMnemonic<"u", 31>; 5259 5260// Atomic loads 5261def : Pat<(atomic_load_8 DForm:$src), (LBZ memri:$src)>; 5262def : Pat<(atomic_load_16 DForm:$src), (LHZ memri:$src)>; 5263def : Pat<(atomic_load_32 DForm:$src), (LWZ memri:$src)>; 5264def : Pat<(atomic_load_8 XForm:$src), (LBZX memrr:$src)>; 5265def : Pat<(atomic_load_16 XForm:$src), (LHZX memrr:$src)>; 5266def : Pat<(atomic_load_32 XForm:$src), (LWZX memrr:$src)>; 5267 5268// Atomic stores 5269def : Pat<(atomic_store_8 DForm:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>; 5270def : Pat<(atomic_store_16 DForm:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>; 5271def : Pat<(atomic_store_32 DForm:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>; 5272def : Pat<(atomic_store_8 XForm:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>; 5273def : Pat<(atomic_store_16 XForm:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>; 5274def : Pat<(atomic_store_32 XForm:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>; 5275 5276let Predicates = [IsISA3_0] in { 5277 5278// Copy-Paste Facility 5279// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 5280// PASTE for naming consistency. 5281let mayLoad = 1 in 5282def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 5283 5284let mayStore = 1, Defs = [CR0] in 5285def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 5286 5287def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 5288def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 5289 5290// Message Synchronize 5291def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5292 5293// Power-Saving Mode Instruction: 5294def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5295 5296def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 5297 "setb $RT, $BFA", IIC_IntGeneral>; 5298} // IsISA3_0 5299 5300let Predicates = [IsISA3_0] in { 5301def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 5302 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 5303} 5304def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 5305 (i32 (MULHW $a, $b))>; 5306def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 5307 (i32 (MULHWU $a, $b))>; 5308def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 5309 (i32 (CMPB $a, $b))>; 5310 5311def : Pat<(int_ppc_load2r ForceXForm:$ptr), 5312 (LHBRX ForceXForm:$ptr)>; 5313def : Pat<(int_ppc_load4r ForceXForm:$ptr), 5314 (LWBRX ForceXForm:$ptr)>; 5315def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 5316 (STHBRX gprc:$a, ForceXForm:$ptr)>; 5317def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 5318 (STWBRX gprc:$a, ForceXForm:$ptr)>; 5319 5320 5321// Fast 32-bit reverse bits algorithm: 5322// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5323// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5324// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5325// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5326// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5327// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5328// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5329// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5330// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5331// Step 4.2: Insert B3 to the right position: 5332// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5333// Step 4.3: Insert B1 to the right position: 5334// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5335def MaskValues { 5336 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5337 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5338 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5339 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5340 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5341 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5342} 5343 5344def Shift1 { 5345 dag Right = (RLWINM $A, 31, 1, 31); 5346 dag Left = (RLWINM $A, 1, 0, 30); 5347} 5348 5349def Swap1 { 5350 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5351 (AND Shift1.Left, MaskValues.Hi1)); 5352} 5353 5354def Shift2 { 5355 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5356 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5357} 5358 5359def Swap2 { 5360 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5361 (AND Shift2.Left, MaskValues.Hi2)); 5362} 5363 5364def Shift4 { 5365 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5366 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5367} 5368 5369def Swap4 { 5370 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5371 (AND Shift4.Left, MaskValues.Hi4)); 5372} 5373 5374def Rotate { 5375 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5376} 5377 5378def RotateInsertByte3 { 5379 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5380} 5381 5382def RotateInsertByte1 { 5383 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5384} 5385 5386// Clear the upper half of the register when in 64-bit mode 5387let Predicates = [In64BitMode] in 5388def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5389let Predicates = [In32BitMode] in 5390def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 5391 5392// Fast 64-bit reverse bits algorithm: 5393// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5394// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5395// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5396// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5397// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5398// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5399// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5400// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5401// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5402// then OR them together to get the final result. 5403def MaskValues64 { 5404 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5405 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5406 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5407 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5408 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5409 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5410} 5411 5412def DWMaskValues { 5413 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5414 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5415 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5416 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5417 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5418 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5419} 5420 5421def DWSwapInByte { 5422 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5423 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5424 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5425 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5426 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5427 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5428} 5429 5430// Intra-byte swap is done, now start inter-byte swap. 5431def DWBytes4567 { 5432 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5433} 5434 5435def DWBytes7456 { 5436 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5437} 5438 5439def DWBytes7656 { 5440 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5441} 5442 5443// B7 B6 B5 B4 in the right order 5444def DWBytes7654 { 5445 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5446 dag DWord = 5447 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5448} 5449 5450def DWBytes0123 { 5451 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5452} 5453 5454def DWBytes3012 { 5455 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5456} 5457 5458def DWBytes3212 { 5459 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5460} 5461 5462// B3 B2 B1 B0 in the right order 5463def DWBytes3210 { 5464 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5465 dag DWord = 5466 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5467} 5468 5469// Now both high word and low word are reversed, next 5470// swap the high word and low word. 5471def : Pat<(i64 (bitreverse i64:$A)), 5472 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5473 5474def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5475 (STWCX gprc:$A, ForceXForm:$dst)>; 5476def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5477 (STBCX gprc:$A, ForceXForm:$dst)>; 5478def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM), 5479 (TW $IMM, $A, $B)>; 5480def : Pat<(int_ppc_trap gprc:$A), 5481 (TWI 24, $A, 0)>; 5482 5483def : Pat<(int_ppc_fcfid f64:$A), 5484 (XSCVSXDDP $A)>; 5485def : Pat<(int_ppc_fcfud f64:$A), 5486 (XSCVUXDDP $A)>; 5487def : Pat<(int_ppc_fctid f64:$A), 5488 (FCTID $A)>; 5489def : Pat<(int_ppc_fctidz f64:$A), 5490 (XSCVDPSXDS $A)>; 5491def : Pat<(int_ppc_fctiw f64:$A), 5492 (FCTIW $A)>; 5493def : Pat<(int_ppc_fctiwz f64:$A), 5494 (XSCVDPSXWS $A)>; 5495def : Pat<(int_ppc_fctudz f64:$A), 5496 (XSCVDPUXDS $A)>; 5497def : Pat<(int_ppc_fctuwz f64:$A), 5498 (XSCVDPUXWS $A)>; 5499 5500def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5501def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5502def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5503 (MFSPR $SPR)>; 5504def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5505 (MTSPR $SPR, $RT)>; 5506def : Pat<(int_ppc_mtmsr gprc:$RS), 5507 (MTMSR $RS, 0)>; 5508 5509let Predicates = [IsISA2_07] in { 5510 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5511 (STHCX gprc:$A, ForceXForm:$dst)>; 5512} 5513def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5514 (DCBTST 16, ForceXForm:$dst)>; 5515def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5516 (DCBT 16, ForceXForm:$dst)>; 5517 5518def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5519 (STFIWX f64:$XT, ForceXForm:$dst)>; 5520