1; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs | FileCheck %s -check-prefix=A8 -check-prefix=CHECK -check-prefix=NORMAL 2; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK -check-prefix=NORMAL 3; rdar://6949835 4; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK -check-prefix=NORMAL 5; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK -check-prefix=NORMAL 6; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK -check-prefix=NORMAL 7 8; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-assume-misaligned-load-store | FileCheck %s -check-prefix=CHECK -check-prefix=CONSERVATIVE 9 10; Magic ARM pair hints works best with linearscan / fast. 11 12@b = external global i64* 13 14; We use the following two to force values into specific registers. 15declare i64* @get_ptr() 16declare void @use_i64(i64 %v) 17 18define void @test_ldrd(i64 %a) nounwind readonly "frame-pointer"="all" { 19; CHECK-LABEL: test_ldrd: 20; NORMAL: bl{{x?}} _get_ptr 21; A8: ldrd r0, r1, [r0] 22; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base 23; register when interrupted or faulted. 24; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]] 25; CONSERVATIVE-NOT: ldrd 26; NORMAL: bl{{x?}} _use_i64 27 %ptr = call i64* @get_ptr() 28 %v = load i64, i64* %ptr, align 8 29 call void @use_i64(i64 %v) 30 ret void 31} 32 33; rdar://10435045 mixed LDRi8/LDRi12 34; 35; In this case, LSR generate a sequence of LDRi8/LDRi12. We should be 36; able to generate an LDRD pair here, but this is highly sensitive to 37; regalloc hinting. So, this doubles as a register allocation 38; test. RABasic currently does a better job within the inner loop 39; because of its *lack* of hinting ability. Whereas RAGreedy keeps 40; R0/R1/R2 live as the three arguments, forcing the LDRD's odd 41; destination into R3. We then sensibly split LDRD again rather then 42; evict another live range or use callee saved regs. Sorry if the test 43; is sensitive to Regalloc changes, but it is an interesting case. 44; 45; CHECK-LABEL: f: 46; BASIC: %bb 47; BASIC: ldrd 48; BASIC: str 49; GREEDY: %bb 50; GREEDY: ldrd 51; GREEDY: str 52define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind "frame-pointer"="all" { 53entry: 54 %0 = add nsw i32 %n, -1 ; <i32> [#uses=2] 55 %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1] 56 br i1 %1, label %bb, label %return 57 58bb: ; preds = %bb, %entry 59 %i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3] 60 %scevgep = getelementptr i32, i32* %a, i32 %i.03 ; <i32*> [#uses=1] 61 %scevgep4 = getelementptr i32, i32* %b, i32 %i.03 ; <i32*> [#uses=1] 62 %tmp = add i32 %i.03, 1 ; <i32> [#uses=3] 63 %scevgep5 = getelementptr i32, i32* %a, i32 %tmp ; <i32*> [#uses=1] 64 %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1] 65 %3 = load i32, i32* %scevgep5, align 4 ; <i32> [#uses=1] 66 %4 = add nsw i32 %3, %2 ; <i32> [#uses=1] 67 store i32 %4, i32* %scevgep4, align 4 68 %exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1] 69 br i1 %exitcond, label %return, label %bb 70 71return: ; preds = %bb, %entry 72 ret void 73} 74 75; rdar://13978317 76; Pair of loads not formed when lifetime markers are set. 77%struct.Test = type { i32, i32, i32 } 78 79@TestVar = external global %struct.Test 80 81; CHECK-LABEL: Func1: 82define void @Func1() nounwind ssp "frame-pointer"="all" { 83entry: 84; A8: movw [[BASER:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}} 85; A8: movt [[BASER]], :upper16:{{.*}}TestVar{{.*}} 86; A8: ldr [[BASE:r[0-9]+]], {{\[}}[[BASER]]] 87; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4] 88; A8-NEXT: add [[FIELD2]], [[FIELD1]] 89; A8-NEXT: str [[FIELD2]], {{\[}}[[BASE]]{{\]}} 90; CONSERVATIVE-NOT: ldrd 91 %orig_blocks = alloca [256 x i16], align 2 92 %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start.p0i8(i64 512, i8* %0) nounwind 93 %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4 94 %tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4 95 %add = add nsw i32 %tmp2, %tmp1 96 store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4 97 call void @llvm.lifetime.end.p0i8(i64 512, i8* %0) nounwind 98 ret void 99} 100 101declare void @extfunc(i32, i32, i32, i32) 102 103; CHECK-LABEL: Func2: 104; CONSERVATIVE-NOT: ldrd 105; A8: ldrd 106; CHECK: bl{{x?}} _extfunc 107; A8: pop 108define void @Func2(i32* %p) "frame-pointer"="all" { 109entry: 110 %addr0 = getelementptr i32, i32* %p, i32 0 111 %addr1 = getelementptr i32, i32* %p, i32 1 112 %v0 = load i32, i32* %addr0 113 %v1 = load i32, i32* %addr1 114 ; try to force %v0/%v1 into non-adjacent registers 115 call void @extfunc(i32 %v0, i32 0, i32 0, i32 %v1) 116 ret void 117} 118 119; CHECK-LABEL: strd_spill_ldrd_reload: 120; A8: strd r1, r0, [sp, #-8]! 121; M3: strd r1, r0, [sp, #-8]! 122; BASIC: strd r1, r0, [sp, #-8]! 123; GREEDY: strd r0, r1, [sp, #-8]! 124; CONSERVATIVE: strd r0, r1, [sp, #-8]! 125; NORMAL: @ InlineAsm Start 126; NORMAL: @ InlineAsm End 127; A8: ldrd r2, r1, [sp] 128; M3: ldrd r2, r1, [sp] 129; BASIC: ldrd r2, r1, [sp] 130; GREEDY: ldrd r1, r2, [sp] 131; CONSERVATIVE: ldrd r1, r2, [sp] 132; CHECK: bl{{x?}} _extfunc 133define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) "frame-pointer"="all" { 134 ; force %v0 and %v1 to be spilled 135 call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{lr}"() 136 ; force the reloaded %v0, %v1 into different registers 137 call void @extfunc(i32 0, i32 %v0, i32 %v1, i32 7) 138 ret void 139} 140 141declare void @extfunc2(i32*, i32, i32) 142 143; CHECK-LABEL: ldrd_postupdate_dec: 144; NORMAL: ldrd r1, r2, [r0], #-8 145; CONSERVATIVE-NOT: ldrd 146; CHECK: bl{{x?}} _extfunc 147define void @ldrd_postupdate_dec(i32* %p0) "frame-pointer"="all" { 148 %p0.1 = getelementptr i32, i32* %p0, i32 1 149 %v0 = load i32, i32* %p0 150 %v1 = load i32, i32* %p0.1 151 %p1 = getelementptr i32, i32* %p0, i32 -2 152 call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) 153 ret void 154} 155 156; CHECK-LABEL: ldrd_postupdate_inc: 157; NORMAL: ldrd r1, r2, [r0], #8 158; CONSERVATIVE-NOT: ldrd 159; CHECK: bl{{x?}} _extfunc 160define void @ldrd_postupdate_inc(i32* %p0) "frame-pointer"="all" { 161 %p0.1 = getelementptr i32, i32* %p0, i32 1 162 %v0 = load i32, i32* %p0 163 %v1 = load i32, i32* %p0.1 164 %p1 = getelementptr i32, i32* %p0, i32 2 165 call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) 166 ret void 167} 168 169; CHECK-LABEL: strd_postupdate_dec: 170; NORMAL: strd r1, r2, [r0], #-8 171; CONSERVATIVE-NOT: strd 172; CHECK: bx lr 173define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) "frame-pointer"="all" { 174 %p0.1 = getelementptr i32, i32* %p0, i32 1 175 store i32 %v0, i32* %p0 176 store i32 %v1, i32* %p0.1 177 %p1 = getelementptr i32, i32* %p0, i32 -2 178 ret i32* %p1 179} 180 181; CHECK-LABEL: strd_postupdate_inc: 182; NORMAL: strd r1, r2, [r0], #8 183; CONSERVATIVE-NOT: strd 184; CHECK: bx lr 185define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) "frame-pointer"="all" { 186 %p0.1 = getelementptr i32, i32* %p0, i32 1 187 store i32 %v0, i32* %p0 188 store i32 %v1, i32* %p0.1 189 %p1 = getelementptr i32, i32* %p0, i32 2 190 ret i32* %p1 191} 192 193; CHECK-LABEL: ldrd_strd_aa: 194; NORMAL: ldrd [[TMP1:r[0-9]]], [[TMP2:r[0-9]]], 195; NORMAL: strd [[TMP1]], [[TMP2]], 196; CONSERVATIVE-NOT: ldrd 197; CONSERVATIVE-NOT: strd 198; CHECK: bx lr 199 200define void @ldrd_strd_aa(i32* noalias nocapture %x, i32* noalias nocapture readonly %y) { 201entry: 202 %0 = load i32, i32* %y, align 4 203 store i32 %0, i32* %x, align 4 204 %arrayidx2 = getelementptr inbounds i32, i32* %y, i32 1 205 %1 = load i32, i32* %arrayidx2, align 4 206 %arrayidx3 = getelementptr inbounds i32, i32* %x, i32 1 207 store i32 %1, i32* %arrayidx3, align 4 208 ret void 209} 210 211; CHECK-LABEL: bitcast_ptr_ldr 212; CHECK-NOT: ldrd 213define i32 @bitcast_ptr_ldr(i16* %In) { 214entry: 215 %0 = bitcast i16* %In to i32* 216 %in.addr.0 = getelementptr inbounds i32, i32* %0, i32 0 217 %in.addr.1 = getelementptr inbounds i32, i32* %0, i32 1 218 %1 = load i32, i32* %in.addr.0, align 2 219 %2 = load i32, i32* %in.addr.1, align 2 220 %mul = mul i32 %1, %2 221 ret i32 %mul 222} 223 224; CHECK-LABEL: bitcast_gep_ldr 225; CHECK-NOT: ldrd 226define i32 @bitcast_gep_ldr(i16* %In) { 227entry: 228 %in.addr.0 = getelementptr inbounds i16, i16* %In, i32 0 229 %in.addr.1 = getelementptr inbounds i16, i16* %In, i32 2 230 %cast.0 = bitcast i16* %in.addr.0 to i32* 231 %cast.1 = bitcast i16* %in.addr.1 to i32* 232 %0 = load i32, i32* %cast.0, align 2 233 %1 = load i32, i32* %cast.1, align 2 234 %mul = mul i32 %0, %1 235 ret i32 %mul 236} 237 238; CHECK-LABEL: bitcast_ptr_str 239; CHECK-NOT: strd 240define void @bitcast_ptr_str(i32 %arg0, i32 %arg1, i16* %out) { 241entry: 242 %0 = bitcast i16* %out to i32* 243 %out.addr.0 = getelementptr inbounds i32, i32* %0, i32 0 244 %out.addr.1 = getelementptr inbounds i32, i32* %0, i32 1 245 store i32 %arg0, i32* %out.addr.0, align 2 246 store i32 %arg1, i32* %out.addr.1, align 2 247 ret void 248} 249 250; CHECK-LABEL: bitcast_gep_str 251; CHECK-NOT: strd 252define void @bitcast_gep_str(i32 %arg0, i32 %arg1, i16* %out) { 253entry: 254 %out.addr.0 = getelementptr inbounds i16, i16* %out, i32 0 255 %out.addr.1 = getelementptr inbounds i16, i16* %out, i32 2 256 %cast.0 = bitcast i16* %out.addr.0 to i32* 257 %cast.1 = bitcast i16* %out.addr.1 to i32* 258 store i32 %arg0, i32* %cast.0, align 2 259 store i32 %arg1, i32* %cast.1, align 2 260 ret void 261} 262 263declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind 264declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind 265