1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
3---
4name:            cttz_i32
5alignment:       4
6tracksRegLiveness: true
7body:             |
8  bb.1.entry:
9    liveins: $a0
10
11    ; MIPS32-LABEL: name: cttz_i32
12    ; MIPS32: liveins: $a0
13    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
14    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
15    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
16    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
17    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
18    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
19    ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
20    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[CTLZ]]
21    ; MIPS32: $v0 = COPY [[SUB]](s32)
22    ; MIPS32: RetRA implicit $v0
23    %0:_(s32) = COPY $a0
24    %1:_(s32) = G_CTTZ %0(s32)
25    $v0 = COPY %1(s32)
26    RetRA implicit $v0
27
28...
29---
30name:            cttz_i64
31alignment:       4
32tracksRegLiveness: true
33body:             |
34  bb.1.entry:
35    liveins: $a0, $a1
36
37    ; MIPS32-LABEL: name: cttz_i64
38    ; MIPS32: liveins: $a0, $a1
39    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
40    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
41    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
42    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
43    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
44    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
45    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]
46    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
47    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
48    ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
49    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ]]
50    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C2]]
51    ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
52    ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
53    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
54    ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
55    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]]
56    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
57    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
58    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
59    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
60    ; MIPS32: $v0 = COPY [[SELECT]](s32)
61    ; MIPS32: $v1 = COPY [[C]](s32)
62    ; MIPS32: RetRA implicit $v0, implicit $v1
63    %1:_(s32) = COPY $a0
64    %2:_(s32) = COPY $a1
65    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
66    %3:_(s64) = G_CTTZ %0(s64)
67    %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
68    $v0 = COPY %4(s32)
69    $v1 = COPY %5(s32)
70    RetRA implicit $v0, implicit $v1
71
72...
73---
74name:            ffs_i32_expansion
75alignment:       4
76tracksRegLiveness: true
77body:             |
78  bb.1.entry:
79    liveins: $a0
80
81    ; MIPS32-LABEL: name: ffs_i32_expansion
82    ; MIPS32: liveins: $a0
83    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
84    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
85    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
86    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
87    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
88    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
89    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
90    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
91    ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
92    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
93    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[SUB]], [[C]]
94    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
95    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
96    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
97    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[C1]], [[ADD1]]
98    ; MIPS32: $v0 = COPY [[SELECT]](s32)
99    ; MIPS32: RetRA implicit $v0
100    %0:_(s32) = COPY $a0
101    %2:_(s32) = G_CONSTANT i32 1
102    %4:_(s32) = G_CONSTANT i32 0
103    %1:_(s32) = G_CTTZ_ZERO_UNDEF %0(s32)
104    %3:_(s32) = nuw nsw G_ADD %1, %2
105    %5:_(s1) = G_ICMP intpred(eq), %0(s32), %4
106    %6:_(s32) = G_SELECT %5(s1), %4, %3
107    $v0 = COPY %6(s32)
108    RetRA implicit $v0
109
110...
111---
112name:            ffs_i64_expansion
113alignment:       4
114tracksRegLiveness: true
115body:             |
116  bb.1.entry:
117    liveins: $a0, $a1
118
119    ; MIPS32-LABEL: name: ffs_i64_expansion
120    ; MIPS32: liveins: $a0, $a1
121    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
122    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
123    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
124    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
125    ; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[C1]](s32)
126    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
127    ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
128    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C2]]
129    ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C2]]
130    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]
131    ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
132    ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32)
133    ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
134    ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C3]]
135    ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
136    ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
137    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
138    ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
139    ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ1]]
140    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
141    ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
142    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
143    ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C]]
144    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]]
145    ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[C1]], [[C1]]
146    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
147    ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
148    ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND3]]
149    ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32)
150    ; MIPS32: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
151    ; MIPS32: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
152    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR2]], [[XOR3]]
153    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]]
154    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
155    ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
156    ; MIPS32: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV]], [[MV1]]
157    ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
158    ; MIPS32: $v0 = COPY [[UV]](s32)
159    ; MIPS32: $v1 = COPY [[UV1]](s32)
160    ; MIPS32: RetRA implicit $v0, implicit $v1
161    %1:_(s32) = COPY $a0
162    %2:_(s32) = COPY $a1
163    %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
164    %4:_(s64) = G_CONSTANT i64 1
165    %6:_(s64) = G_CONSTANT i64 0
166    %3:_(s64) = G_CTTZ_ZERO_UNDEF %0(s64)
167    %5:_(s64) = nuw nsw G_ADD %3, %4
168    %7:_(s1) = G_ICMP intpred(eq), %0(s64), %6
169    %8:_(s64) = G_SELECT %7(s1), %6, %5
170    %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64)
171    $v0 = COPY %9(s32)
172    $v1 = COPY %10(s32)
173    RetRA implicit $v0, implicit $v1
174
175...
176