1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
3--- |
4
5  define void @sdiv_i8() {entry: ret void}
6  define void @sdiv_i16() {entry: ret void}
7  define void @sdiv_i32() {entry: ret void}
8  define void @sdiv_i64() {entry: ret void}
9  define void @srem_i8() {entry: ret void}
10  define void @srem_i16() {entry: ret void}
11  define void @srem_i32() {entry: ret void}
12  define void @srem_i64() {entry: ret void}
13  define void @udiv_i8() {entry: ret void}
14  define void @udiv_i16() {entry: ret void}
15  define void @udiv_i32() {entry: ret void}
16  define void @udiv_i64() {entry: ret void}
17  define void @urem_i8() {entry: ret void}
18  define void @urem_i16() {entry: ret void}
19  define void @urem_i32() {entry: ret void}
20  define void @urem_i64() {entry: ret void}
21
22...
23---
24name:            sdiv_i8
25alignment:       4
26tracksRegLiveness: true
27body:             |
28  bb.1.entry:
29    liveins: $a0, $a1
30
31    ; MIPS32-LABEL: name: sdiv_i8
32    ; MIPS32: liveins: $a0, $a1
33    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
34    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
35    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
36    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
37    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
38    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
39    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
40    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
41    ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
42    ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
43    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
44    ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
45    ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
46    ; MIPS32: $v0 = COPY [[ASHR2]](s32)
47    ; MIPS32: RetRA implicit $v0
48    %2:_(s32) = COPY $a0
49    %0:_(s8) = G_TRUNC %2(s32)
50    %3:_(s32) = COPY $a1
51    %1:_(s8) = G_TRUNC %3(s32)
52    %4:_(s8) = G_SDIV %1, %0
53    %5:_(s32) = G_SEXT %4(s8)
54    $v0 = COPY %5(s32)
55    RetRA implicit $v0
56
57...
58---
59name:            sdiv_i16
60alignment:       4
61tracksRegLiveness: true
62body:             |
63  bb.1.entry:
64    liveins: $a0, $a1
65
66    ; MIPS32-LABEL: name: sdiv_i16
67    ; MIPS32: liveins: $a0, $a1
68    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
69    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
70    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
71    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
72    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
73    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
74    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
75    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
76    ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
77    ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
78    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
79    ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
80    ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
81    ; MIPS32: $v0 = COPY [[ASHR2]](s32)
82    ; MIPS32: RetRA implicit $v0
83    %2:_(s32) = COPY $a0
84    %0:_(s16) = G_TRUNC %2(s32)
85    %3:_(s32) = COPY $a1
86    %1:_(s16) = G_TRUNC %3(s32)
87    %4:_(s16) = G_SDIV %1, %0
88    %5:_(s32) = G_SEXT %4(s16)
89    $v0 = COPY %5(s32)
90    RetRA implicit $v0
91
92...
93---
94name:            sdiv_i32
95alignment:       4
96tracksRegLiveness: true
97body:             |
98  bb.1.entry:
99    liveins: $a0, $a1
100
101    ; MIPS32-LABEL: name: sdiv_i32
102    ; MIPS32: liveins: $a0, $a1
103    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
104    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
105    ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY1]], [[COPY]]
106    ; MIPS32: $v0 = COPY [[SDIV]](s32)
107    ; MIPS32: RetRA implicit $v0
108    %0:_(s32) = COPY $a0
109    %1:_(s32) = COPY $a1
110    %2:_(s32) = G_SDIV %1, %0
111    $v0 = COPY %2(s32)
112    RetRA implicit $v0
113
114...
115---
116name:            sdiv_i64
117alignment:       4
118tracksRegLiveness: true
119body:             |
120  bb.1.entry:
121    liveins: $a0, $a1, $a2, $a3
122
123    ; MIPS32-LABEL: name: sdiv_i64
124    ; MIPS32: liveins: $a0, $a1, $a2, $a3
125    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
126    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
127    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
128    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
129    ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
130    ; MIPS32: $a0 = COPY [[COPY2]](s32)
131    ; MIPS32: $a1 = COPY [[COPY3]](s32)
132    ; MIPS32: $a2 = COPY [[COPY]](s32)
133    ; MIPS32: $a3 = COPY [[COPY1]](s32)
134    ; MIPS32: JAL &__divdi3, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
135    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
136    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
137    ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
138    ; MIPS32: $v0 = COPY [[COPY4]](s32)
139    ; MIPS32: $v1 = COPY [[COPY5]](s32)
140    ; MIPS32: RetRA implicit $v0, implicit $v1
141    %2:_(s32) = COPY $a0
142    %3:_(s32) = COPY $a1
143    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
144    %4:_(s32) = COPY $a2
145    %5:_(s32) = COPY $a3
146    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
147    %6:_(s64) = G_SDIV %1, %0
148    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
149    $v0 = COPY %7(s32)
150    $v1 = COPY %8(s32)
151    RetRA implicit $v0, implicit $v1
152
153...
154---
155name:            srem_i8
156alignment:       4
157tracksRegLiveness: true
158body:             |
159  bb.1.entry:
160    liveins: $a0, $a1
161
162    ; MIPS32-LABEL: name: srem_i8
163    ; MIPS32: liveins: $a0, $a1
164    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
165    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
166    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
167    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
168    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
169    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
170    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
171    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
172    ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
173    ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
174    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
175    ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
176    ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
177    ; MIPS32: $v0 = COPY [[ASHR2]](s32)
178    ; MIPS32: RetRA implicit $v0
179    %2:_(s32) = COPY $a0
180    %0:_(s8) = G_TRUNC %2(s32)
181    %3:_(s32) = COPY $a1
182    %1:_(s8) = G_TRUNC %3(s32)
183    %4:_(s8) = G_SREM %1, %0
184    %5:_(s32) = G_SEXT %4(s8)
185    $v0 = COPY %5(s32)
186    RetRA implicit $v0
187
188...
189---
190name:            srem_i16
191alignment:       4
192tracksRegLiveness: true
193body:             |
194  bb.1.entry:
195    liveins: $a0, $a1
196
197    ; MIPS32-LABEL: name: srem_i16
198    ; MIPS32: liveins: $a0, $a1
199    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
200    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
201    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
202    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
203    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
204    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
205    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
206    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
207    ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
208    ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
209    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
210    ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
211    ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
212    ; MIPS32: $v0 = COPY [[ASHR2]](s32)
213    ; MIPS32: RetRA implicit $v0
214    %2:_(s32) = COPY $a0
215    %0:_(s16) = G_TRUNC %2(s32)
216    %3:_(s32) = COPY $a1
217    %1:_(s16) = G_TRUNC %3(s32)
218    %4:_(s16) = G_SREM %1, %0
219    %5:_(s32) = G_SEXT %4(s16)
220    $v0 = COPY %5(s32)
221    RetRA implicit $v0
222
223...
224---
225name:            srem_i32
226alignment:       4
227tracksRegLiveness: true
228body:             |
229  bb.1.entry:
230    liveins: $a0, $a1
231
232    ; MIPS32-LABEL: name: srem_i32
233    ; MIPS32: liveins: $a0, $a1
234    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
235    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
236    ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY1]], [[COPY]]
237    ; MIPS32: $v0 = COPY [[SREM]](s32)
238    ; MIPS32: RetRA implicit $v0
239    %0:_(s32) = COPY $a0
240    %1:_(s32) = COPY $a1
241    %2:_(s32) = G_SREM %1, %0
242    $v0 = COPY %2(s32)
243    RetRA implicit $v0
244
245...
246---
247name:            srem_i64
248alignment:       4
249tracksRegLiveness: true
250body:             |
251  bb.1.entry:
252    liveins: $a0, $a1, $a2, $a3
253
254    ; MIPS32-LABEL: name: srem_i64
255    ; MIPS32: liveins: $a0, $a1, $a2, $a3
256    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
257    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
258    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
259    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
260    ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
261    ; MIPS32: $a0 = COPY [[COPY2]](s32)
262    ; MIPS32: $a1 = COPY [[COPY3]](s32)
263    ; MIPS32: $a2 = COPY [[COPY]](s32)
264    ; MIPS32: $a3 = COPY [[COPY1]](s32)
265    ; MIPS32: JAL &__moddi3, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
266    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
267    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
268    ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
269    ; MIPS32: $v0 = COPY [[COPY4]](s32)
270    ; MIPS32: $v1 = COPY [[COPY5]](s32)
271    ; MIPS32: RetRA implicit $v0, implicit $v1
272    %2:_(s32) = COPY $a0
273    %3:_(s32) = COPY $a1
274    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
275    %4:_(s32) = COPY $a2
276    %5:_(s32) = COPY $a3
277    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
278    %6:_(s64) = G_SREM %1, %0
279    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
280    $v0 = COPY %7(s32)
281    $v1 = COPY %8(s32)
282    RetRA implicit $v0, implicit $v1
283
284...
285---
286name:            udiv_i8
287alignment:       4
288tracksRegLiveness: true
289body:             |
290  bb.1.entry:
291    liveins: $a0, $a1
292
293    ; MIPS32-LABEL: name: udiv_i8
294    ; MIPS32: liveins: $a0, $a1
295    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
296    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
297    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
298    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
299    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
300    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
301    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
302    ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
303    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
304    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
305    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
306    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
307    ; MIPS32: $v0 = COPY [[ASHR]](s32)
308    ; MIPS32: RetRA implicit $v0
309    %2:_(s32) = COPY $a0
310    %0:_(s8) = G_TRUNC %2(s32)
311    %3:_(s32) = COPY $a1
312    %1:_(s8) = G_TRUNC %3(s32)
313    %4:_(s8) = G_UDIV %1, %0
314    %5:_(s32) = G_SEXT %4(s8)
315    $v0 = COPY %5(s32)
316    RetRA implicit $v0
317
318...
319---
320name:            udiv_i16
321alignment:       4
322tracksRegLiveness: true
323body:             |
324  bb.1.entry:
325    liveins: $a0, $a1
326
327    ; MIPS32-LABEL: name: udiv_i16
328    ; MIPS32: liveins: $a0, $a1
329    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
330    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
331    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
332    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
333    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
334    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
335    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
336    ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
337    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
338    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
339    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
340    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
341    ; MIPS32: $v0 = COPY [[ASHR]](s32)
342    ; MIPS32: RetRA implicit $v0
343    %2:_(s32) = COPY $a0
344    %0:_(s16) = G_TRUNC %2(s32)
345    %3:_(s32) = COPY $a1
346    %1:_(s16) = G_TRUNC %3(s32)
347    %4:_(s16) = G_UDIV %1, %0
348    %5:_(s32) = G_SEXT %4(s16)
349    $v0 = COPY %5(s32)
350    RetRA implicit $v0
351
352...
353---
354name:            udiv_i32
355alignment:       4
356tracksRegLiveness: true
357body:             |
358  bb.1.entry:
359    liveins: $a0, $a1
360
361    ; MIPS32-LABEL: name: udiv_i32
362    ; MIPS32: liveins: $a0, $a1
363    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
364    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
365    ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY1]], [[COPY]]
366    ; MIPS32: $v0 = COPY [[UDIV]](s32)
367    ; MIPS32: RetRA implicit $v0
368    %0:_(s32) = COPY $a0
369    %1:_(s32) = COPY $a1
370    %2:_(s32) = G_UDIV %1, %0
371    $v0 = COPY %2(s32)
372    RetRA implicit $v0
373
374...
375---
376name:            udiv_i64
377alignment:       4
378tracksRegLiveness: true
379body:             |
380  bb.1.entry:
381    liveins: $a0, $a1, $a2, $a3
382
383    ; MIPS32-LABEL: name: udiv_i64
384    ; MIPS32: liveins: $a0, $a1, $a2, $a3
385    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
386    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
387    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
388    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
389    ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
390    ; MIPS32: $a0 = COPY [[COPY2]](s32)
391    ; MIPS32: $a1 = COPY [[COPY3]](s32)
392    ; MIPS32: $a2 = COPY [[COPY]](s32)
393    ; MIPS32: $a3 = COPY [[COPY1]](s32)
394    ; MIPS32: JAL &__udivdi3, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
395    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
396    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
397    ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
398    ; MIPS32: $v0 = COPY [[COPY4]](s32)
399    ; MIPS32: $v1 = COPY [[COPY5]](s32)
400    ; MIPS32: RetRA implicit $v0, implicit $v1
401    %2:_(s32) = COPY $a0
402    %3:_(s32) = COPY $a1
403    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
404    %4:_(s32) = COPY $a2
405    %5:_(s32) = COPY $a3
406    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
407    %6:_(s64) = G_UDIV %1, %0
408    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
409    $v0 = COPY %7(s32)
410    $v1 = COPY %8(s32)
411    RetRA implicit $v0, implicit $v1
412
413...
414---
415name:            urem_i8
416alignment:       4
417tracksRegLiveness: true
418body:             |
419  bb.1.entry:
420    liveins: $a0, $a1
421
422    ; MIPS32-LABEL: name: urem_i8
423    ; MIPS32: liveins: $a0, $a1
424    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
425    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
426    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
427    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
428    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
429    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
430    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
431    ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
432    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
433    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
434    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
435    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
436    ; MIPS32: $v0 = COPY [[ASHR]](s32)
437    ; MIPS32: RetRA implicit $v0
438    %2:_(s32) = COPY $a0
439    %0:_(s8) = G_TRUNC %2(s32)
440    %3:_(s32) = COPY $a1
441    %1:_(s8) = G_TRUNC %3(s32)
442    %4:_(s8) = G_UREM %1, %0
443    %5:_(s32) = G_SEXT %4(s8)
444    $v0 = COPY %5(s32)
445    RetRA implicit $v0
446
447...
448---
449name:            urem_i16
450alignment:       4
451tracksRegLiveness: true
452body:             |
453  bb.1.entry:
454    liveins: $a0, $a1
455
456    ; MIPS32-LABEL: name: urem_i16
457    ; MIPS32: liveins: $a0, $a1
458    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
459    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
460    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
461    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
462    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
463    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
464    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
465    ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
466    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
467    ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
468    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
469    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
470    ; MIPS32: $v0 = COPY [[ASHR]](s32)
471    ; MIPS32: RetRA implicit $v0
472    %2:_(s32) = COPY $a0
473    %0:_(s16) = G_TRUNC %2(s32)
474    %3:_(s32) = COPY $a1
475    %1:_(s16) = G_TRUNC %3(s32)
476    %4:_(s16) = G_UREM %1, %0
477    %5:_(s32) = G_SEXT %4(s16)
478    $v0 = COPY %5(s32)
479    RetRA implicit $v0
480
481...
482---
483name:            urem_i32
484alignment:       4
485tracksRegLiveness: true
486body:             |
487  bb.1.entry:
488    liveins: $a0, $a1
489
490    ; MIPS32-LABEL: name: urem_i32
491    ; MIPS32: liveins: $a0, $a1
492    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
493    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
494    ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY1]], [[COPY]]
495    ; MIPS32: $v0 = COPY [[UREM]](s32)
496    ; MIPS32: RetRA implicit $v0
497    %0:_(s32) = COPY $a0
498    %1:_(s32) = COPY $a1
499    %2:_(s32) = G_UREM %1, %0
500    $v0 = COPY %2(s32)
501    RetRA implicit $v0
502
503...
504---
505name:            urem_i64
506alignment:       4
507tracksRegLiveness: true
508body:             |
509  bb.1.entry:
510    liveins: $a0, $a1, $a2, $a3
511
512    ; MIPS32-LABEL: name: urem_i64
513    ; MIPS32: liveins: $a0, $a1, $a2, $a3
514    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
515    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
516    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
517    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
518    ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
519    ; MIPS32: $a0 = COPY [[COPY2]](s32)
520    ; MIPS32: $a1 = COPY [[COPY3]](s32)
521    ; MIPS32: $a2 = COPY [[COPY]](s32)
522    ; MIPS32: $a3 = COPY [[COPY1]](s32)
523    ; MIPS32: JAL &__umoddi3, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
524    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
525    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
526    ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
527    ; MIPS32: $v0 = COPY [[COPY4]](s32)
528    ; MIPS32: $v1 = COPY [[COPY5]](s32)
529    ; MIPS32: RetRA implicit $v0, implicit $v1
530    %2:_(s32) = COPY $a0
531    %3:_(s32) = COPY $a1
532    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
533    %4:_(s32) = COPY $a2
534    %5:_(s32) = COPY $a3
535    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
536    %6:_(s64) = G_UREM %1, %0
537    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
538    $v0 = COPY %7(s32)
539    $v1 = COPY %8(s32)
540    RetRA implicit $v0, implicit $v1
541
542...
543