1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN: FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN: FileCheck %s --check-prefix=CHECK-BE
8
9define void @test8i8(<8 x i8>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
10; CHECK-LABEL: test8i8:
11; CHECK:       # %bb.0: # %entry
12; CHECK-NEXT:    lvx v2, 0, r4
13; CHECK-NEXT:    vpkuhum v2, v2, v2
14; CHECK-NEXT:    xxswapd vs0, v2
15; CHECK-NEXT:    stfdx f0, 0, r3
16; CHECK-NEXT:    blr
17;
18; CHECK-BE-LABEL: test8i8:
19; CHECK-BE:       # %bb.0: # %entry
20; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
21; CHECK-BE-NEXT:    addi r5, r1, -16
22; CHECK-BE-NEXT:    vpkuhum v2, v2, v2
23; CHECK-BE-NEXT:    stxvd2x v2, 0, r5
24; CHECK-BE-NEXT:    ld r4, -16(r1)
25; CHECK-BE-NEXT:    std r4, 0(r3)
26; CHECK-BE-NEXT:    blr
27entry:
28  %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
29  %1 = trunc <8 x i16> %0 to <8 x i8>
30  store <8 x i8> %1, <8 x i8>* %Sink, align 16
31  ret void
32}
33
34define void @test4i8(<4 x i8>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
35; CHECK-LABEL: test4i8:
36; CHECK:       # %bb.0: # %entry
37; CHECK-NEXT:    lvx v2, 0, r4
38; CHECK-NEXT:    vpkuhum v2, v2, v2
39; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
40; CHECK-NEXT:    stfiwx f0, 0, r3
41; CHECK-NEXT:    blr
42;
43; CHECK-BE-LABEL: test4i8:
44; CHECK-BE:       # %bb.0: # %entry
45; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
46; CHECK-BE-NEXT:    addi r5, r1, -16
47; CHECK-BE-NEXT:    vpkuhum v2, v2, v2
48; CHECK-BE-NEXT:    stxvw4x v2, 0, r5
49; CHECK-BE-NEXT:    lwz r4, -16(r1)
50; CHECK-BE-NEXT:    stw r4, 0(r3)
51; CHECK-BE-NEXT:    blr
52entry:
53  %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
54  %1 = trunc <4 x i16> %0 to <4 x i8>
55  store <4 x i8> %1, <4 x i8>* %Sink, align 16
56  ret void
57}
58
59define void @test4i8w(<4 x i8>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
60; CHECK-LABEL: test4i8w:
61; CHECK:       # %bb.0: # %entry
62; CHECK-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
63; CHECK-NEXT:    lvx v3, 0, r4
64; CHECK-NEXT:    addi r5, r5, .LCPI2_0@toc@l
65; CHECK-NEXT:    lvx v2, 0, r5
66; CHECK-NEXT:    vperm v2, v3, v3, v2
67; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
68; CHECK-NEXT:    stfiwx f0, 0, r3
69; CHECK-NEXT:    blr
70;
71; CHECK-BE-LABEL: test4i8w:
72; CHECK-BE:       # %bb.0: # %entry
73; CHECK-BE-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
74; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
75; CHECK-BE-NEXT:    addi r4, r5, .LCPI2_0@toc@l
76; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
77; CHECK-BE-NEXT:    addi r4, r1, -16
78; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
79; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
80; CHECK-BE-NEXT:    lwz r4, -16(r1)
81; CHECK-BE-NEXT:    stw r4, 0(r3)
82; CHECK-BE-NEXT:    blr
83entry:
84  %0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16
85  %1 = trunc <4 x i32> %0 to <4 x i8>
86  store <4 x i8> %1, <4 x i8>* %Sink, align 16
87  ret void
88}
89
90define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
91; CHECK-LABEL: test2i8:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    lvx v2, 0, r4
94; CHECK-NEXT:    vpkuhum v2, v2, v2
95; CHECK-NEXT:    xxswapd vs0, v2
96; CHECK-NEXT:    mffprd r4, f0
97; CHECK-NEXT:    clrldi r4, r4, 48
98; CHECK-NEXT:    sth r4, 0(r3)
99; CHECK-NEXT:    blr
100;
101; CHECK-BE-LABEL: test2i8:
102; CHECK-BE:       # %bb.0: # %entry
103; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
104; CHECK-BE-NEXT:    addi r5, r1, -16
105; CHECK-BE-NEXT:    vpkuhum v2, v2, v2
106; CHECK-BE-NEXT:    stxvw4x v2, 0, r5
107; CHECK-BE-NEXT:    lhz r4, -16(r1)
108; CHECK-BE-NEXT:    sth r4, 0(r3)
109; CHECK-BE-NEXT:    blr
110entry:
111  %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
112  %1 = trunc <2 x i16> %0 to <2 x i8>
113  store <2 x i8> %1, <2 x i8>* %Sink, align 16
114  ret void
115}
116
117define void @test4i16(<4 x i16>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
118; CHECK-LABEL: test4i16:
119; CHECK:       # %bb.0: # %entry
120; CHECK-NEXT:    lvx v2, 0, r4
121; CHECK-NEXT:    vpkuwum v2, v2, v2
122; CHECK-NEXT:    xxswapd vs0, v2
123; CHECK-NEXT:    stfdx f0, 0, r3
124; CHECK-NEXT:    blr
125;
126; CHECK-BE-LABEL: test4i16:
127; CHECK-BE:       # %bb.0: # %entry
128; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
129; CHECK-BE-NEXT:    addi r5, r1, -16
130; CHECK-BE-NEXT:    vpkuwum v2, v2, v2
131; CHECK-BE-NEXT:    stxvd2x v2, 0, r5
132; CHECK-BE-NEXT:    ld r4, -16(r1)
133; CHECK-BE-NEXT:    std r4, 0(r3)
134; CHECK-BE-NEXT:    blr
135entry:
136  %0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16
137  %1 = trunc <4 x i32> %0 to <4 x i16>
138  store <4 x i16> %1, <4 x i16>* %Sink, align 16
139  ret void
140}
141
142define void @test2i16(<2 x i16>* nocapture %Sink, <2 x i32>* nocapture readonly %SrcPtr) {
143; CHECK-LABEL: test2i16:
144; CHECK:       # %bb.0: # %entry
145; CHECK-NEXT:    lvx v2, 0, r4
146; CHECK-NEXT:    vpkuwum v2, v2, v2
147; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
148; CHECK-NEXT:    stfiwx f0, 0, r3
149; CHECK-NEXT:    blr
150;
151; CHECK-BE-LABEL: test2i16:
152; CHECK-BE:       # %bb.0: # %entry
153; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
154; CHECK-BE-NEXT:    addi r5, r1, -16
155; CHECK-BE-NEXT:    vpkuwum v2, v2, v2
156; CHECK-BE-NEXT:    stxvw4x v2, 0, r5
157; CHECK-BE-NEXT:    lwz r4, -16(r1)
158; CHECK-BE-NEXT:    stw r4, 0(r3)
159; CHECK-BE-NEXT:    blr
160entry:
161  %0 = load <2 x i32>, <2 x i32>* %SrcPtr, align 16
162  %1 = trunc <2 x i32> %0 to <2 x i16>
163  store <2 x i16> %1, <2 x i16>* %Sink, align 16
164  ret void
165}
166
167define void @test2i16d(<2 x i16>* nocapture %Sink, <2 x i64>* nocapture readonly %SrcPtr) {
168; CHECK-LABEL: test2i16d:
169; CHECK:       # %bb.0: # %entry
170; CHECK-NEXT:    lxvd2x vs0, 0, r4
171; CHECK-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
172; CHECK-NEXT:    addi r4, r5, .LCPI6_0@toc@l
173; CHECK-NEXT:    lvx v3, 0, r4
174; CHECK-NEXT:    xxswapd v2, vs0
175; CHECK-NEXT:    vperm v2, v2, v2, v3
176; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
177; CHECK-NEXT:    stfiwx f0, 0, r3
178; CHECK-NEXT:    blr
179;
180; CHECK-BE-LABEL: test2i16d:
181; CHECK-BE:       # %bb.0: # %entry
182; CHECK-BE-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
183; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
184; CHECK-BE-NEXT:    addi r4, r5, .LCPI6_0@toc@l
185; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
186; CHECK-BE-NEXT:    addi r4, r1, -16
187; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
188; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
189; CHECK-BE-NEXT:    lwz r4, -16(r1)
190; CHECK-BE-NEXT:    stw r4, 0(r3)
191; CHECK-BE-NEXT:    blr
192entry:
193  %0 = load <2 x i64>, <2 x i64>* %SrcPtr, align 16
194  %1 = trunc <2 x i64> %0 to <2 x i16>
195  store <2 x i16> %1, <2 x i16>* %Sink, align 16
196  ret void
197}
198