1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s 4 5define <vscale x 4 x i5> @trunc_nxv4i32_to_nxv4i5(<vscale x 4 x i32> %a) { 6; CHECK-LABEL: trunc_nxv4i32_to_nxv4i5: 7; CHECK: # %bb.0: 8; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 9; CHECK-NEXT: vnsrl.wi v25, v8, 0 10; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu 11; CHECK-NEXT: vnsrl.wi v8, v25, 0 12; CHECK-NEXT: ret 13 %v = trunc <vscale x 4 x i32> %a to <vscale x 4 x i5> 14 ret <vscale x 4 x i5> %v 15} 16 17define <vscale x 1 x i5> @trunc_nxv1i32_to_nxv1i5(<vscale x 1 x i32> %a) { 18; CHECK-LABEL: trunc_nxv1i32_to_nxv1i5: 19; CHECK: # %bb.0: 20; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 21; CHECK-NEXT: vnsrl.wi v25, v8, 0 22; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu 23; CHECK-NEXT: vnsrl.wi v8, v25, 0 24; CHECK-NEXT: ret 25 %v = trunc <vscale x 1 x i32> %a to <vscale x 1 x i5> 26 ret <vscale x 1 x i5> %v 27} 28