1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s 3 4--- | 5 define dso_local arm_aapcs_vfpcc void @test1(i32* noalias nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr { 6 entry: 7 %cmp30 = icmp eq i32 %N, 0 8 %0 = add i32 %N, 3 9 %1 = lshr i32 %0, 2 10 %2 = shl nuw i32 %1, 2 11 %3 = add i32 %2, -4 12 %4 = lshr i32 %3, 2 13 %5 = add nuw nsw i32 %4, 1 14 br i1 %cmp30, label %for.cond.cleanup6, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %5) 18 br label %vector.body 19 20 vector.body: ; preds = %vector.body, %vector.ph 21 %lsr.iv68 = phi i32* [ %scevgep69, %vector.body ], [ %a, %vector.ph ] 22 %lsr.iv65 = phi i32* [ %scevgep66, %vector.body ], [ %c, %vector.ph ] 23 %lsr.iv62 = phi i32* [ %scevgep63, %vector.body ], [ %b, %vector.ph ] 24 %6 = phi i32 [ %start1, %vector.ph ], [ %11, %vector.body ] 25 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 26 %lsr.iv6870 = bitcast i32* %lsr.iv68 to <4 x i32>* 27 %lsr.iv6567 = bitcast i32* %lsr.iv65 to <4 x i32>* 28 %lsr.iv6264 = bitcast i32* %lsr.iv62 to <4 x i32>* 29 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 30 %9 = sub i32 %7, 4 31 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv6264, i32 4, <4 x i1> %8, <4 x i32> undef) 32 %wide.masked.load35 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv6567, i32 4, <4 x i1> %8, <4 x i32> undef) 33 %10 = mul nsw <4 x i32> %wide.masked.load35, %wide.masked.load 34 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %10, <4 x i32>* %lsr.iv6870, i32 4, <4 x i1> %8) 35 %scevgep63 = getelementptr i32, i32* %lsr.iv62, i32 4 36 %scevgep66 = getelementptr i32, i32* %lsr.iv65, i32 4 37 %scevgep69 = getelementptr i32, i32* %lsr.iv68, i32 4 38 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 39 %12 = icmp ne i32 %11, 0 40 br i1 %12, label %vector.body, label %for.cond4.preheader 41 42 for.cond4.preheader: ; preds = %vector.body 43 %13 = icmp eq i32 %N, 0 44 %14 = add i32 %N, 3 45 %15 = lshr i32 %14, 2 46 %16 = shl nuw i32 %15, 2 47 %17 = add i32 %16, -4 48 %18 = lshr i32 %17, 2 49 %19 = add nuw nsw i32 %18, 1 50 br i1 %13, label %for.cond.cleanup6, label %vector.ph39 51 52 vector.ph39: ; preds = %for.cond4.preheader 53 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %19) 54 br label %vector.body38 55 56 vector.body38: ; preds = %vector.body38, %vector.ph39 57 %lsr.iv59 = phi i32* [ %scevgep60, %vector.body38 ], [ %a, %vector.ph39 ] 58 %lsr.iv56 = phi i32* [ %scevgep57, %vector.body38 ], [ %c, %vector.ph39 ] 59 %lsr.iv = phi i32* [ %scevgep, %vector.body38 ], [ %b, %vector.ph39 ] 60 %20 = phi i32 [ %start2, %vector.ph39 ], [ %26, %vector.body38 ] 61 %21 = phi i32 [ %N, %vector.ph39 ], [ %23, %vector.body38 ] 62 %lsr.iv5961 = bitcast i32* %lsr.iv59 to <4 x i32>* 63 %lsr.iv5658 = bitcast i32* %lsr.iv56 to <4 x i32>* 64 %lsr.iv55 = bitcast i32* %lsr.iv to <4 x i32>* 65 %22 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %21) 66 %23 = sub i32 %21, 4 67 %wide.masked.load52 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv55, i32 4, <4 x i1> %22, <4 x i32> undef) 68 %wide.masked.load53 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv5658, i32 4, <4 x i1> %22, <4 x i32> undef) 69 %24 = xor <4 x i32> %wide.masked.load53, %wide.masked.load52 70 %wide.masked.load54 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv5961, i32 4, <4 x i1> %22, <4 x i32> undef) 71 %25 = add nsw <4 x i32> %wide.masked.load54, %24 72 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %25, <4 x i32>* %lsr.iv5961, i32 4, <4 x i1> %22) 73 %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 74 %scevgep57 = getelementptr i32, i32* %lsr.iv56, i32 4 75 %scevgep60 = getelementptr i32, i32* %lsr.iv59, i32 4 76 %26 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %20, i32 1) 77 %27 = icmp ne i32 %26, 0 78 br i1 %27, label %vector.body38, label %for.cond.cleanup6 79 80 for.cond.cleanup6: ; preds = %vector.body38, %entry, %for.cond4.preheader 81 ret void 82 } 83 ; Function Attrs: nofree norecurse nounwind 84 define dso_local arm_aapcs_vfpcc void @test2(i32* noalias nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr { 85 entry: 86 %div = lshr i32 %N, 1 87 %cmp30 = icmp eq i32 %div, 0 88 %0 = add nuw i32 %div, 3 89 %1 = lshr i32 %0, 2 90 %2 = shl nuw i32 %1, 2 91 %3 = add i32 %2, -4 92 %4 = lshr i32 %3, 2 93 %5 = add nuw nsw i32 %4, 1 94 br i1 %cmp30, label %for.cond4.preheader, label %vector.ph 95 96 vector.ph: ; preds = %entry 97 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %5) 98 br label %vector.body 99 100 vector.body: ; preds = %vector.body, %vector.ph 101 %lsr.iv68 = phi i32* [ %scevgep69, %vector.body ], [ %a, %vector.ph ] 102 %lsr.iv65 = phi i32* [ %scevgep66, %vector.body ], [ %c, %vector.ph ] 103 %lsr.iv62 = phi i32* [ %scevgep63, %vector.body ], [ %b, %vector.ph ] 104 %6 = phi i32 [ %start1, %vector.ph ], [ %11, %vector.body ] 105 %7 = phi i32 [ %div, %vector.ph ], [ %9, %vector.body ] 106 %lsr.iv6870 = bitcast i32* %lsr.iv68 to <4 x i32>* 107 %lsr.iv6567 = bitcast i32* %lsr.iv65 to <4 x i32>* 108 %lsr.iv6264 = bitcast i32* %lsr.iv62 to <4 x i32>* 109 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 110 %9 = sub i32 %7, 4 111 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv6264, i32 4, <4 x i1> %8, <4 x i32> undef) 112 %wide.masked.load35 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv6567, i32 4, <4 x i1> %8, <4 x i32> undef) 113 %10 = mul nsw <4 x i32> %wide.masked.load35, %wide.masked.load 114 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %10, <4 x i32>* %lsr.iv6870, i32 4, <4 x i1> %8) 115 %scevgep63 = getelementptr i32, i32* %lsr.iv62, i32 4 116 %scevgep66 = getelementptr i32, i32* %lsr.iv65, i32 4 117 %scevgep69 = getelementptr i32, i32* %lsr.iv68, i32 4 118 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 119 %12 = icmp ne i32 %11, 0 120 br i1 %12, label %vector.body, label %for.cond4.preheader 121 122 for.cond4.preheader: ; preds = %vector.body, %entry 123 %cmp528 = icmp eq i32 %N, 0 124 %13 = add i32 %N, 3 125 %14 = lshr i32 %13, 2 126 %15 = shl nuw i32 %14, 2 127 %16 = add i32 %15, -4 128 %17 = lshr i32 %16, 2 129 %18 = add nuw nsw i32 %17, 1 130 br i1 %cmp528, label %for.cond.cleanup6, label %vector.ph39 131 132 vector.ph39: ; preds = %for.cond4.preheader 133 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %18) 134 br label %vector.body38 135 136 vector.body38: ; preds = %vector.body38, %vector.ph39 137 %lsr.iv59 = phi i32* [ %scevgep60, %vector.body38 ], [ %a, %vector.ph39 ] 138 %lsr.iv56 = phi i32* [ %scevgep57, %vector.body38 ], [ %c, %vector.ph39 ] 139 %lsr.iv = phi i32* [ %scevgep, %vector.body38 ], [ %b, %vector.ph39 ] 140 %19 = phi i32 [ %start2, %vector.ph39 ], [ %25, %vector.body38 ] 141 %20 = phi i32 [ %N, %vector.ph39 ], [ %22, %vector.body38 ] 142 %lsr.iv5961 = bitcast i32* %lsr.iv59 to <4 x i32>* 143 %lsr.iv5658 = bitcast i32* %lsr.iv56 to <4 x i32>* 144 %lsr.iv55 = bitcast i32* %lsr.iv to <4 x i32>* 145 %21 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %20) 146 %22 = sub i32 %20, 4 147 %wide.masked.load52 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv55, i32 4, <4 x i1> %21, <4 x i32> undef) 148 %wide.masked.load53 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv5658, i32 4, <4 x i1> %21, <4 x i32> undef) 149 %23 = xor <4 x i32> %wide.masked.load53, %wide.masked.load52 150 %wide.masked.load54 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv5961, i32 4, <4 x i1> %21, <4 x i32> undef) 151 %24 = add nsw <4 x i32> %wide.masked.load54, %23 152 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %24, <4 x i32>* %lsr.iv5961, i32 4, <4 x i1> %21) 153 %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 154 %scevgep57 = getelementptr i32, i32* %lsr.iv56, i32 4 155 %scevgep60 = getelementptr i32, i32* %lsr.iv59, i32 4 156 %25 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %19, i32 1) 157 %26 = icmp ne i32 %25, 0 158 br i1 %26, label %vector.body38, label %for.cond.cleanup6 159 160 for.cond.cleanup6: ; preds = %vector.body38, %for.cond4.preheader 161 ret void 162 } 163 ; Function Attrs: nofree norecurse nounwind 164 define dso_local arm_aapcs_vfpcc void @test3(i32* noalias nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr { 165 entry: 166 %cmp54 = icmp eq i32 %N, 0 167 %0 = add i32 %N, 3 168 %1 = lshr i32 %0, 2 169 %2 = shl nuw i32 %1, 2 170 %3 = add i32 %2, -4 171 %4 = lshr i32 %3, 2 172 %5 = add nuw nsw i32 %4, 1 173 br i1 %cmp54, label %for.cond.cleanup17, label %vector.ph 174 175 vector.ph: ; preds = %entry 176 %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %5) 177 br label %vector.body 178 179 vector.body: ; preds = %vector.body, %vector.ph 180 %lsr.iv123 = phi i32* [ %scevgep124, %vector.body ], [ %a, %vector.ph ] 181 %lsr.iv120 = phi i32* [ %scevgep121, %vector.body ], [ %c, %vector.ph ] 182 %lsr.iv117 = phi i32* [ %scevgep118, %vector.body ], [ %b, %vector.ph ] 183 %6 = phi i32 [ %start1, %vector.ph ], [ %11, %vector.body ] 184 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 185 %lsr.iv123125 = bitcast i32* %lsr.iv123 to <4 x i32>* 186 %lsr.iv120122 = bitcast i32* %lsr.iv120 to <4 x i32>* 187 %lsr.iv117119 = bitcast i32* %lsr.iv117 to <4 x i32>* 188 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 189 %9 = sub i32 %7, 4 190 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv117119, i32 4, <4 x i1> %8, <4 x i32> undef) 191 %wide.masked.load62 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv120122, i32 4, <4 x i1> %8, <4 x i32> undef) 192 %10 = mul nsw <4 x i32> %wide.masked.load62, %wide.masked.load 193 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %10, <4 x i32>* %lsr.iv123125, i32 4, <4 x i1> %8) 194 %scevgep118 = getelementptr i32, i32* %lsr.iv117, i32 4 195 %scevgep121 = getelementptr i32, i32* %lsr.iv120, i32 4 196 %scevgep124 = getelementptr i32, i32* %lsr.iv123, i32 4 197 %11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 198 %12 = icmp ne i32 %11, 0 199 br i1 %12, label %vector.body, label %for.cond4.preheader 200 201 for.cond4.preheader: ; preds = %vector.body 202 %div = lshr i32 %N, 1 203 %cmp552 = icmp eq i32 %div, 0 204 %13 = add nuw i32 %div, 3 205 %14 = lshr i32 %13, 2 206 %15 = shl nuw i32 %14, 2 207 %16 = add i32 %15, -4 208 %17 = lshr i32 %16, 2 209 %18 = add nuw nsw i32 %17, 1 210 br i1 %cmp552, label %for.cond15.preheader, label %vector.ph66 211 212 vector.ph66: ; preds = %for.cond4.preheader 213 %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %18) 214 br label %vector.body65 215 216 vector.body65: ; preds = %vector.body65, %vector.ph66 217 %lsr.iv114 = phi i32* [ %scevgep115, %vector.body65 ], [ %a, %vector.ph66 ] 218 %lsr.iv111 = phi i32* [ %scevgep112, %vector.body65 ], [ %c, %vector.ph66 ] 219 %lsr.iv108 = phi i32* [ %scevgep109, %vector.body65 ], [ %b, %vector.ph66 ] 220 %19 = phi i32 [ %start2, %vector.ph66 ], [ %25, %vector.body65 ] 221 %20 = phi i32 [ %div, %vector.ph66 ], [ %22, %vector.body65 ] 222 %lsr.iv114116 = bitcast i32* %lsr.iv114 to <4 x i32>* 223 %lsr.iv111113 = bitcast i32* %lsr.iv111 to <4 x i32>* 224 %lsr.iv108110 = bitcast i32* %lsr.iv108 to <4 x i32>* 225 %21 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %20) 226 %22 = sub i32 %20, 4 227 %wide.masked.load79 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv108110, i32 4, <4 x i1> %21, <4 x i32> undef) 228 %wide.masked.load80 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv111113, i32 4, <4 x i1> %21, <4 x i32> undef) 229 %23 = xor <4 x i32> %wide.masked.load80, %wide.masked.load79 230 %wide.masked.load81 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv114116, i32 4, <4 x i1> %21, <4 x i32> undef) 231 %24 = add nsw <4 x i32> %wide.masked.load81, %23 232 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %24, <4 x i32>* %lsr.iv114116, i32 4, <4 x i1> %21) 233 %scevgep109 = getelementptr i32, i32* %lsr.iv108, i32 4 234 %scevgep112 = getelementptr i32, i32* %lsr.iv111, i32 4 235 %scevgep115 = getelementptr i32, i32* %lsr.iv114, i32 4 236 %25 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %19, i32 1) 237 %26 = icmp ne i32 %25, 0 238 br i1 %26, label %vector.body65, label %for.cond15.preheader 239 240 for.cond15.preheader: ; preds = %vector.body65, %for.cond4.preheader 241 %27 = icmp eq i32 %N, 0 242 %28 = add i32 %N, 3 243 %29 = lshr i32 %28, 2 244 %30 = shl nuw i32 %29, 2 245 %31 = add i32 %30, -4 246 %32 = lshr i32 %31, 2 247 %33 = add nuw nsw i32 %32, 1 248 br i1 %27, label %for.cond.cleanup17, label %vector.ph85 249 250 vector.ph85: ; preds = %for.cond15.preheader 251 %start3 = call i32 @llvm.start.loop.iterations.i32(i32 %33) 252 br label %vector.body84 253 254 vector.body84: ; preds = %vector.body84, %vector.ph85 255 %lsr.iv105 = phi i32* [ %scevgep106, %vector.body84 ], [ %a, %vector.ph85 ] 256 %lsr.iv102 = phi i32* [ %scevgep103, %vector.body84 ], [ %c, %vector.ph85 ] 257 %lsr.iv = phi i32* [ %scevgep, %vector.body84 ], [ %b, %vector.ph85 ] 258 %34 = phi i32 [ %start3, %vector.ph85 ], [ %40, %vector.body84 ] 259 %35 = phi i32 [ %N, %vector.ph85 ], [ %37, %vector.body84 ] 260 %lsr.iv105107 = bitcast i32* %lsr.iv105 to <4 x i32>* 261 %lsr.iv102104 = bitcast i32* %lsr.iv102 to <4 x i32>* 262 %lsr.iv101 = bitcast i32* %lsr.iv to <4 x i32>* 263 %36 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %35) 264 %37 = sub i32 %35, 4 265 %wide.masked.load98 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv101, i32 4, <4 x i1> %36, <4 x i32> undef) 266 %wide.masked.load99 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv102104, i32 4, <4 x i1> %36, <4 x i32> undef) 267 %wide.masked.load100 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv105107, i32 4, <4 x i1> %36, <4 x i32> undef) 268 %38 = add <4 x i32> %wide.masked.load99, %wide.masked.load98 269 %39 = sub <4 x i32> %wide.masked.load100, %38 270 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %39, <4 x i32>* %lsr.iv105107, i32 4, <4 x i1> %36) 271 %scevgep = getelementptr i32, i32* %lsr.iv, i32 4 272 %scevgep103 = getelementptr i32, i32* %lsr.iv102, i32 4 273 %scevgep106 = getelementptr i32, i32* %lsr.iv105, i32 4 274 %40 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %34, i32 1) 275 %41 = icmp ne i32 %40, 0 276 br i1 %41, label %vector.body84, label %for.cond.cleanup17 277 278 for.cond.cleanup17: ; preds = %vector.body84, %entry, %for.cond15.preheader 279 ret void 280 } 281 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) 282 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) 283 declare i32 @llvm.start.loop.iterations.i32(i32) 284 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 285 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 286 287... 288--- 289name: test1 290alignment: 2 291exposesReturnsTwice: false 292legalized: false 293regBankSelected: false 294selected: false 295failedISel: false 296tracksRegLiveness: true 297hasWinCFI: false 298registers: [] 299liveins: 300 - { reg: '$r0', virtual-reg: '' } 301 - { reg: '$r1', virtual-reg: '' } 302 - { reg: '$r2', virtual-reg: '' } 303 - { reg: '$r3', virtual-reg: '' } 304frameInfo: 305 isFrameAddressTaken: false 306 isReturnAddressTaken: false 307 hasStackMap: false 308 hasPatchPoint: false 309 stackSize: 24 310 offsetAdjustment: -16 311 maxAlignment: 4 312 adjustsStack: false 313 hasCalls: false 314 stackProtector: '' 315 maxCallFrameSize: 0 316 cvBytesOfCalleeSavedRegisters: 0 317 hasOpaqueSPAdjustment: false 318 hasVAStart: false 319 hasMustTailInVarArgFunc: false 320 localFrameSize: 0 321 savePoint: '' 322 restorePoint: '' 323fixedStack: [] 324stack: 325 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 326 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 327 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 328 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 329 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 330 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 331 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 332 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 333 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 334 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 335 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 336 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 337 - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 338 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 339 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 340 - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 341 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 342 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 343callSites: [] 344constants: [] 345machineFunctionInfo: {} 346body: | 347 ; CHECK-LABEL: name: test1 348 ; CHECK: bb.0.entry: 349 ; CHECK: successors: %bb.6(0x30000000), %bb.1(0x50000000) 350 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 351 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp 352 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 353 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 354 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 355 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 356 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 357 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 358 ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg 359 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 360 ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg 361 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24 362 ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 363 ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr 364 ; CHECK: bb.1.vector.ph: 365 ; CHECK: successors: %bb.2(0x80000000) 366 ; CHECK: liveins: $r0, $r1, $r2, $r3 367 ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg 368 ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg 369 ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg 370 ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg 371 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 372 ; CHECK: bb.2.vector.body: 373 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 374 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 375 ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4) 376 ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4) 377 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 378 ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv6870, align 4) 379 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 380 ; CHECK: bb.3.for.cond4.preheader: 381 ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) 382 ; CHECK: liveins: $r0, $r1, $r2, $r3 383 ; CHECK: tCBZ $r3, %bb.6 384 ; CHECK: bb.4.vector.ph39: 385 ; CHECK: successors: %bb.5(0x80000000) 386 ; CHECK: liveins: $r0, $r1, $r2, $r3 387 ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg 388 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 389 ; CHECK: bb.5.vector.body38: 390 ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) 391 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12 392 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv55, align 4) 393 ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4) 394 ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4) 395 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 396 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 397 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv5961, align 4) 398 ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg 399 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 400 ; CHECK: bb.6.for.cond.cleanup6: 401 ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg 402 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc 403 bb.0.entry: 404 successors: %bb.6(0x30000000), %bb.1(0x50000000) 405 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 406 407 frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp 408 frame-setup CFI_INSTRUCTION def_cfa_offset 20 409 frame-setup CFI_INSTRUCTION offset $lr, -4 410 frame-setup CFI_INSTRUCTION offset $r7, -8 411 frame-setup CFI_INSTRUCTION offset $r6, -12 412 frame-setup CFI_INSTRUCTION offset $r5, -16 413 frame-setup CFI_INSTRUCTION offset $r4, -20 414 $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg 415 frame-setup CFI_INSTRUCTION def_cfa $r7, 8 416 early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14, $noreg 417 frame-setup CFI_INSTRUCTION offset $r8, -24 418 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 419 tBcc %bb.6, 0, killed $cpsr 420 421 bb.1.vector.ph: 422 successors: %bb.2(0x80000000) 423 liveins: $r0, $r1, $r2, $r3 424 425 renamable $r6, dead $cpsr = tADDi3 renamable $r3, 3, 14, $noreg 426 $r8 = tMOVr $r0, 14, $noreg 427 renamable $r6 = t2BICri killed renamable $r6, 3, 14, $noreg, $noreg 428 $r5 = tMOVr $r2, 14, $noreg 429 renamable $r12 = t2SUBri killed renamable $r6, 4, 14, $noreg, $noreg 430 renamable $r6, dead $cpsr = tMOVi8 1, 14, $noreg 431 $r4 = tMOVr $r3, 14, $noreg 432 renamable $lr = nuw nsw t2ADDrs killed renamable $r6, renamable $r12, 19, 14, $noreg, $noreg 433 $r6 = tMOVr $r1, 14, $noreg 434 $lr = t2DoLoopStart renamable $lr 435 436 bb.2.vector.body: 437 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 438 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12 439 440 renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg 441 MVE_VPST 4, implicit $vpr 442 renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv6264, align 4) 443 renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv6567, align 4) 444 renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg 445 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 446 MVE_VPST 8, implicit $vpr 447 renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv6870, align 4) 448 renamable $lr = t2LoopDec killed renamable $lr, 1 449 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 450 tB %bb.3, 14, $noreg 451 452 bb.3.for.cond4.preheader: 453 successors: %bb.6(0x30000000), %bb.4(0x50000000) 454 liveins: $r0, $r1, $r2, $r3, $r12 455 456 tCBZ $r3, %bb.6 457 458 bb.4.vector.ph39: 459 successors: %bb.5(0x80000000) 460 liveins: $r0, $r1, $r2, $r3, $r12 461 462 renamable $r6, dead $cpsr = tMOVi8 1, 14, $noreg 463 renamable $lr = nuw nsw t2ADDrs killed renamable $r6, killed renamable $r12, 19, 14, $noreg, $noreg 464 $r12 = tMOVr $r0, 14, $noreg 465 $lr = t2DoLoopStart renamable $lr 466 467 bb.5.vector.body38: 468 successors: %bb.5(0x7c000000), %bb.6(0x04000000) 469 liveins: $lr, $r0, $r1, $r2, $r3, $r12 470 471 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg 472 MVE_VPST 2, implicit $vpr 473 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv55, align 4) 474 renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv5658, align 4) 475 renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv5961, align 4) 476 renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 477 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg 478 renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 479 MVE_VPST 8, implicit $vpr 480 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv5961, align 4) 481 renamable $lr = t2LoopDec killed renamable $lr, 1 482 $r0 = tMOVr $r12, 14, $noreg 483 t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr 484 tB %bb.6, 14, $noreg 485 486 bb.6.for.cond.cleanup6: 487 $r8, $sp = t2LDR_POST $sp, 4, 14, $noreg 488 tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc 489 490... 491--- 492name: test2 493alignment: 2 494exposesReturnsTwice: false 495legalized: false 496regBankSelected: false 497selected: false 498failedISel: false 499tracksRegLiveness: true 500hasWinCFI: false 501registers: [] 502liveins: 503 - { reg: '$r0', virtual-reg: '' } 504 - { reg: '$r1', virtual-reg: '' } 505 - { reg: '$r2', virtual-reg: '' } 506 - { reg: '$r3', virtual-reg: '' } 507frameInfo: 508 isFrameAddressTaken: false 509 isReturnAddressTaken: false 510 hasStackMap: false 511 hasPatchPoint: false 512 stackSize: 24 513 offsetAdjustment: -16 514 maxAlignment: 4 515 adjustsStack: false 516 hasCalls: false 517 stackProtector: '' 518 maxCallFrameSize: 0 519 cvBytesOfCalleeSavedRegisters: 0 520 hasOpaqueSPAdjustment: false 521 hasVAStart: false 522 hasMustTailInVarArgFunc: false 523 localFrameSize: 0 524 savePoint: '' 525 restorePoint: '' 526fixedStack: [] 527stack: 528 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 529 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 530 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 531 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 532 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 533 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 534 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 535 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 536 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 537 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 538 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 539 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 540 - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 541 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 542 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 543 - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 544 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 545 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 546callSites: [] 547constants: [] 548machineFunctionInfo: {} 549body: | 550 ; CHECK-LABEL: name: test2 551 ; CHECK: bb.0.entry: 552 ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) 553 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 554 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp 555 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 556 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 557 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 558 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 559 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 560 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 561 ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg 562 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 563 ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 /* CC::al */, $noreg 564 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24 565 ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 566 ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr 567 ; CHECK: tBcc %bb.3, 0 /* CC::eq */, killed $cpsr 568 ; CHECK: bb.1.vector.ph: 569 ; CHECK: successors: %bb.2(0x80000000) 570 ; CHECK: liveins: $r0, $r1, $r2, $r3 571 ; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg 572 ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg 573 ; CHECK: $r5 = tMOVr $r1, 14 /* CC::al */, $noreg 574 ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg 575 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 576 ; CHECK: bb.2.vector.body: 577 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 578 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 579 ; CHECK: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4) 580 ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4) 581 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 582 ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv6870, align 4) 583 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 584 ; CHECK: bb.3.for.cond4.preheader: 585 ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) 586 ; CHECK: liveins: $r0, $r1, $r2, $r3 587 ; CHECK: tCBZ $r3, %bb.6 588 ; CHECK: bb.4.vector.ph39: 589 ; CHECK: successors: %bb.5(0x80000000) 590 ; CHECK: liveins: $r0, $r1, $r2, $r3 591 ; CHECK: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg 592 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 593 ; CHECK: bb.5.vector.body38: 594 ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) 595 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 596 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv55, align 4) 597 ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4) 598 ; CHECK: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4) 599 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 600 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 601 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv5961, align 4) 602 ; CHECK: $r0 = tMOVr $r4, 14 /* CC::al */, $noreg 603 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 604 ; CHECK: bb.6.for.cond.cleanup6: 605 ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg 606 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc 607 bb.0.entry: 608 successors: %bb.3(0x30000000), %bb.1(0x50000000) 609 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 610 611 frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp 612 frame-setup CFI_INSTRUCTION def_cfa_offset 20 613 frame-setup CFI_INSTRUCTION offset $lr, -4 614 frame-setup CFI_INSTRUCTION offset $r7, -8 615 frame-setup CFI_INSTRUCTION offset $r6, -12 616 frame-setup CFI_INSTRUCTION offset $r5, -16 617 frame-setup CFI_INSTRUCTION offset $r4, -20 618 $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg 619 frame-setup CFI_INSTRUCTION def_cfa $r7, 8 620 early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14, $noreg 621 frame-setup CFI_INSTRUCTION offset $r8, -24 622 renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg 623 renamable $r12 = t2MOVi 1, 14, $noreg, $noreg 624 t2CMPrs killed renamable $r6, renamable $r3, 11, 14, $noreg, implicit-def $cpsr 625 tBcc %bb.3, 0, killed $cpsr 626 627 bb.1.vector.ph: 628 successors: %bb.2(0x80000000) 629 liveins: $r0, $r1, $r2, $r3, $r12 630 631 renamable $r6, dead $cpsr = tMOVi8 3, 14, $noreg 632 renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14, $noreg 633 renamable $r6 = nuw t2ADDrs killed renamable $r6, renamable $r3, 11, 14, $noreg, $noreg 634 $r8 = tMOVr $r0, 14, $noreg 635 renamable $r6 = t2BICri killed renamable $r6, 3, 14, $noreg, $noreg 636 $r5 = tMOVr $r1, 14, $noreg 637 renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14, $noreg 638 renamable $lr = nuw nsw t2ADDrs renamable $r12, killed renamable $r6, 19, 14, $noreg, $noreg 639 $r6 = tMOVr $r2, 14, $noreg 640 $lr = t2DoLoopStart renamable $lr 641 642 bb.2.vector.body: 643 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 644 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12 645 646 renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg 647 MVE_VPST 4, implicit $vpr 648 renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv6264, align 4) 649 renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv6567, align 4) 650 renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg 651 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 652 MVE_VPST 8, implicit $vpr 653 renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv6870, align 4) 654 renamable $lr = t2LoopDec killed renamable $lr, 1 655 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 656 tB %bb.3, 14, $noreg 657 658 bb.3.for.cond4.preheader: 659 successors: %bb.6(0x30000000), %bb.4(0x50000000) 660 liveins: $r0, $r1, $r2, $r3, $r12 661 662 tCBZ $r3, %bb.6 663 664 bb.4.vector.ph39: 665 successors: %bb.5(0x80000000) 666 liveins: $r0, $r1, $r2, $r3, $r12 667 668 renamable $r6, dead $cpsr = tADDi3 renamable $r3, 3, 14, $noreg 669 $r4 = tMOVr $r0, 14, $noreg 670 renamable $r6 = t2BICri killed renamable $r6, 3, 14, $noreg, $noreg 671 renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14, $noreg 672 renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r6, 19, 14, $noreg, $noreg 673 $lr = t2DoLoopStart renamable $lr 674 675 bb.5.vector.body38: 676 successors: %bb.5(0x7c000000), %bb.6(0x04000000) 677 liveins: $lr, $r0, $r1, $r2, $r3, $r4 678 679 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg 680 MVE_VPST 2, implicit $vpr 681 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv55, align 4) 682 renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv5658, align 4) 683 renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv5961, align 4) 684 renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 685 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg 686 renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 687 MVE_VPST 8, implicit $vpr 688 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv5961, align 4) 689 renamable $lr = t2LoopDec killed renamable $lr, 1 690 $r0 = tMOVr $r4, 14, $noreg 691 t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr 692 tB %bb.6, 14, $noreg 693 694 bb.6.for.cond.cleanup6: 695 $r8, $sp = t2LDR_POST $sp, 4, 14, $noreg 696 tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc 697 698... 699--- 700name: test3 701alignment: 2 702exposesReturnsTwice: false 703legalized: false 704regBankSelected: false 705selected: false 706failedISel: false 707tracksRegLiveness: true 708hasWinCFI: false 709registers: [] 710liveins: 711 - { reg: '$r0', virtual-reg: '' } 712 - { reg: '$r1', virtual-reg: '' } 713 - { reg: '$r2', virtual-reg: '' } 714 - { reg: '$r3', virtual-reg: '' } 715frameInfo: 716 isFrameAddressTaken: false 717 isReturnAddressTaken: false 718 hasStackMap: false 719 hasPatchPoint: false 720 stackSize: 32 721 offsetAdjustment: -24 722 maxAlignment: 4 723 adjustsStack: false 724 hasCalls: false 725 stackProtector: '' 726 maxCallFrameSize: 0 727 cvBytesOfCalleeSavedRegisters: 0 728 hasOpaqueSPAdjustment: false 729 hasVAStart: false 730 hasMustTailInVarArgFunc: false 731 localFrameSize: 0 732 savePoint: '' 733 restorePoint: '' 734fixedStack: [] 735stack: 736 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 737 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 738 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 739 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 740 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 741 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 742 - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 743 stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, 744 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 745 - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 746 stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, 747 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 748 - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, 749 stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, 750 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 751 - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, 752 stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, 753 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 754 - { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, 755 stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, 756 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 757 - { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, 758 stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, 759 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 760callSites: [] 761constants: [] 762machineFunctionInfo: {} 763body: | 764 ; CHECK-LABEL: name: test3 765 ; CHECK: bb.0.entry: 766 ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) 767 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10 768 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp 769 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 770 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 771 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 772 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 773 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 774 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 775 ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg 776 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 777 ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10 778 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 779 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 780 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 781 ; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 782 ; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr 783 ; CHECK: bb.1.vector.ph: 784 ; CHECK: successors: %bb.2(0x80000000) 785 ; CHECK: liveins: $r0, $r1, $r2, $r3 786 ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg 787 ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg 788 ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg 789 ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg 790 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 791 ; CHECK: bb.2.vector.body: 792 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 793 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 794 ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv117119, align 4) 795 ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv120122, align 4) 796 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 797 ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv123125, align 4) 798 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 799 ; CHECK: bb.3.for.cond4.preheader: 800 ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) 801 ; CHECK: liveins: $r0, $r1, $r2, $r3 802 ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 803 ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr 804 ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr 805 ; CHECK: bb.4.vector.ph66: 806 ; CHECK: successors: %bb.5(0x80000000) 807 ; CHECK: liveins: $r0, $r1, $r2, $r3 808 ; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg 809 ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg 810 ; CHECK: $r9 = tMOVr $r2, 14 /* CC::al */, $noreg 811 ; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg 812 ; CHECK: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg 813 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r5 814 ; CHECK: bb.5.vector.body65: 815 ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) 816 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10 817 ; CHECK: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv108110, align 4) 818 ; CHECK: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv111113, align 4) 819 ; CHECK: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv114116, align 4) 820 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 821 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 822 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv114116, align 4) 823 ; CHECK: $r10 = tMOVr $r6, 14 /* CC::al */, $noreg 824 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 825 ; CHECK: bb.6.for.cond15.preheader: 826 ; CHECK: successors: %bb.9(0x30000000), %bb.7(0x50000000) 827 ; CHECK: liveins: $r0, $r1, $r2, $r3 828 ; CHECK: tCBZ $r3, %bb.9 829 ; CHECK: bb.7.vector.ph85: 830 ; CHECK: successors: %bb.8(0x80000000) 831 ; CHECK: liveins: $r0, $r1, $r2, $r3 832 ; CHECK: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg 833 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 834 ; CHECK: bb.8.vector.body84: 835 ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) 836 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5 837 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv101, align 4) 838 ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv102104, align 4) 839 ; CHECK: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv105107, align 4) 840 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 841 ; CHECK: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 842 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv105107, align 4) 843 ; CHECK: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg 844 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.8 845 ; CHECK: bb.9.for.cond.cleanup17: 846 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 847 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc 848 bb.0.entry: 849 successors: %bb.9(0x30000000), %bb.1(0x50000000) 850 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 851 852 frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp 853 frame-setup CFI_INSTRUCTION def_cfa_offset 20 854 frame-setup CFI_INSTRUCTION offset $lr, -4 855 frame-setup CFI_INSTRUCTION offset $r7, -8 856 frame-setup CFI_INSTRUCTION offset $r6, -12 857 frame-setup CFI_INSTRUCTION offset $r5, -16 858 frame-setup CFI_INSTRUCTION offset $r4, -20 859 $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg 860 frame-setup CFI_INSTRUCTION def_cfa $r7, 8 861 $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10 862 frame-setup CFI_INSTRUCTION offset $r10, -24 863 frame-setup CFI_INSTRUCTION offset $r9, -28 864 frame-setup CFI_INSTRUCTION offset $r8, -32 865 tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr 866 tBcc %bb.9, 0, killed $cpsr 867 868 bb.1.vector.ph: 869 successors: %bb.2(0x80000000) 870 liveins: $r0, $r1, $r2, $r3 871 872 renamable $r6, dead $cpsr = tADDi3 renamable $r3, 3, 14, $noreg 873 $r8 = tMOVr $r0, 14, $noreg 874 renamable $r6 = t2BICri killed renamable $r6, 3, 14, $noreg, $noreg 875 $r5 = tMOVr $r2, 14, $noreg 876 renamable $r12 = t2SUBri killed renamable $r6, 4, 14, $noreg, $noreg 877 renamable $r6, dead $cpsr = tMOVi8 1, 14, $noreg 878 $r4 = tMOVr $r3, 14, $noreg 879 renamable $lr = nuw nsw t2ADDrs killed renamable $r6, renamable $r12, 19, 14, $noreg, $noreg 880 $r6 = tMOVr $r1, 14, $noreg 881 $lr = t2DoLoopStart renamable $lr 882 883 bb.2.vector.body: 884 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 885 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12 886 887 renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg 888 MVE_VPST 4, implicit $vpr 889 renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv117119, align 4) 890 renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv120122, align 4) 891 renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg 892 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 893 MVE_VPST 8, implicit $vpr 894 renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv123125, align 4) 895 renamable $lr = t2LoopDec killed renamable $lr, 1 896 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 897 tB %bb.3, 14, $noreg 898 899 bb.3.for.cond4.preheader: 900 successors: %bb.6(0x30000000), %bb.4(0x50000000) 901 liveins: $r0, $r1, $r2, $r3, $r12 902 903 renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg 904 renamable $r8 = t2MOVi 1, 14, $noreg, $noreg 905 t2CMPrs killed renamable $r6, renamable $r3, 11, 14, $noreg, implicit-def $cpsr 906 tBcc %bb.6, 0, killed $cpsr 907 908 bb.4.vector.ph66: 909 successors: %bb.5(0x80000000) 910 liveins: $r0, $r1, $r2, $r3, $r8, $r12 911 912 renamable $r6, dead $cpsr = tMOVi8 3, 14, $noreg 913 renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14, $noreg 914 renamable $r6 = nuw t2ADDrs killed renamable $r6, renamable $r3, 11, 14, $noreg, $noreg 915 $r10 = tMOVr $r0, 14, $noreg 916 renamable $r6 = t2BICri killed renamable $r6, 3, 14, $noreg, $noreg 917 $r9 = tMOVr $r2, 14, $noreg 918 renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14, $noreg 919 $r4 = tMOVr $r1, 14, $noreg 920 renamable $lr = nuw nsw t2ADDrs renamable $r8, killed renamable $r6, 19, 14, $noreg, $noreg 921 $r6 = tMOVr $r0, 14, $noreg 922 $lr = t2DoLoopStart renamable $lr 923 924 bb.5.vector.body65: 925 successors: %bb.5(0x7c000000), %bb.6(0x04000000) 926 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r12 927 928 renamable $vpr = MVE_VCTP32 renamable $r5, 0, $noreg 929 MVE_VPST 2, implicit $vpr 930 renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv108110, align 4) 931 renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv111113, align 4) 932 renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv114116, align 4) 933 renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 934 renamable $r5, dead $cpsr = tSUBi8 killed renamable $r5, 4, 14, $noreg 935 renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 936 MVE_VPST 8, implicit $vpr 937 MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv114116, align 4) 938 renamable $lr = t2LoopDec killed renamable $lr, 1 939 $r10 = tMOVr $r6, 14, $noreg 940 t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr 941 tB %bb.6, 14, $noreg 942 943 bb.6.for.cond15.preheader: 944 successors: %bb.9(0x30000000), %bb.7(0x50000000) 945 liveins: $r0, $r1, $r2, $r3, $r8, $r12 946 947 tCBZ $r3, %bb.9 948 949 bb.7.vector.ph85: 950 successors: %bb.8(0x80000000) 951 liveins: $r0, $r1, $r2, $r3, $r8, $r12 952 953 renamable $lr = nuw nsw t2ADDrs killed renamable $r8, killed renamable $r12, 19, 14, $noreg, $noreg 954 $r5 = tMOVr $r0, 14, $noreg 955 $lr = t2DoLoopStart renamable $lr 956 957 bb.8.vector.body84: 958 successors: %bb.8(0x7c000000), %bb.9(0x04000000) 959 liveins: $lr, $r0, $r1, $r2, $r3, $r5 960 961 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg 962 MVE_VPST 2, implicit $vpr 963 renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv101, align 4) 964 renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv102104, align 4) 965 renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv105107, align 4) 966 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 967 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg 968 renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 969 MVE_VPST 8, implicit $vpr 970 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv105107, align 4) 971 renamable $lr = t2LoopDec killed renamable $lr, 1 972 $r0 = tMOVr $r5, 14, $noreg 973 t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr 974 tB %bb.9, 14, $noreg 975 976 bb.9.for.cond.cleanup17: 977 $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10 978 tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc 979 980... 981