1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s --verify-machineinstrs -o - | FileCheck %s 3 4--- | 5 define i16 @predicated_livout(i8* %input_1_vect, i8* %input_2_vect, i32 %block_size) #0 { 6 entry: 7 %rnd.up = add i32 %block_size, 7 8 %div = lshr i32 %rnd.up, 3 9 %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %div) 10 br i1 %0, label %for.body.preheader, label %for.cond.cleanup 11 12 for.body.preheader: ; preds = %entry 13 br label %for.body 14 15 for.body: ; preds = %for.body.preheader, %for.body 16 %lsr.iv = phi i32 [ 0, %for.body.preheader ], [ %lsr.iv.next, %for.body ] 17 %input_1_vect.addr.052 = phi i8* [ %add.ptr, %for.body ], [ %input_1_vect, %for.body.preheader ] 18 %input_2_vect.addr.051 = phi i8* [ %add.ptr14, %for.body ], [ %input_2_vect, %for.body.preheader ] 19 %num_elements.049 = phi i32 [ %sub, %for.body ], [ %block_size, %for.body.preheader ] 20 %acc = phi <8 x i16> [ %acc.next, %for.body ], [ zeroinitializer, %for.body.preheader ] 21 %input_2_cast = bitcast i8* %input_2_vect.addr.051 to <8 x i8>* 22 %input_1_cast = bitcast i8* %input_1_vect.addr.052 to <8 x i8>* 23 %pred = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %num_elements.049) 24 %load.1 = tail call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %input_1_cast, i32 1, <8 x i1> %pred, <8 x i8> undef) 25 %zext.load.1 = zext <8 x i8> %load.1 to <8 x i16> 26 %load.2 = tail call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %input_2_cast, i32 1, <8 x i1> %pred, <8 x i8> undef) 27 %zext.load.2 = zext <8 x i8> %load.2 to <8 x i16> 28 %add = tail call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %zext.load.1, <8 x i16> %zext.load.2, <8 x i1> %pred, <8 x i16> undef) 29 %acc.next = tail call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %add, <8 x i16> %acc, <8 x i1> %pred, <8 x i16> undef) 30 %add.ptr = getelementptr inbounds i8, i8* %input_1_vect.addr.052, i32 8 31 %add.ptr14 = getelementptr inbounds i8, i8* %input_2_vect.addr.051, i32 8 32 %sub = add i32 %num_elements.049, -8 33 %iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1) 34 %cmp = icmp ne i32 %iv.next, 0 35 %lsr.iv.next = add i32 %lsr.iv, -1 36 br i1 %cmp, label %for.body, label %middle.block 37 38 middle.block: ; preds = %for.body 39 %reduce = tail call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %acc.next) 40 ret i16 %reduce 41 42 for.cond.cleanup: ; preds = %entry 43 ret i16 0 44 } 45 46 declare <8 x i1> @llvm.arm.mve.vctp16(i32) #1 47 declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>) #2 48 declare i1 @llvm.test.set.loop.iterations.i32(i32) #3 49 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3 50 declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) #4 51 declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1 52 53... 54--- 55name: predicated_livout 56alignment: 2 57tracksRegLiveness: true 58registers: [] 59liveins: 60 - { reg: '$r0', virtual-reg: '' } 61 - { reg: '$r1', virtual-reg: '' } 62 - { reg: '$r2', virtual-reg: '' } 63frameInfo: 64 stackSize: 8 65 offsetAdjustment: 0 66 maxAlignment: 4 67fixedStack: [] 68stack: 69 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 70 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 71 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 72 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 73 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 74 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 75callSites: [] 76constants: [] 77machineFunctionInfo: {} 78body: | 79 ; CHECK-LABEL: name: predicated_livout 80 ; CHECK: bb.0.entry: 81 ; CHECK: successors: %bb.1(0x40000000), %bb.4(0x40000000) 82 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 83 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 84 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 85 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 86 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 87 ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4 88 ; CHECK: bb.1.for.body.preheader: 89 ; CHECK: successors: %bb.2(0x80000000) 90 ; CHECK: liveins: $lr, $r0, $r1 91 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 92 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 93 ; CHECK: bb.2.for.body: 94 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 95 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r3 96 ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg 97 ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg :: (load (s64) from %ir.input_2_cast, align 1) 98 ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.input_1_cast, align 1) 99 ; CHECK: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 100 ; CHECK: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, undef renamable $q0 101 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 102 ; CHECK: bb.3.middle.block: 103 ; CHECK: liveins: $q0 104 ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg 105 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 106 ; CHECK: bb.4.for.cond.cleanup: 107 ; CHECK: liveins: $lr 108 ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 109 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 110 bb.0.entry: 111 successors: %bb.1(0x40000000), %bb.4(0x40000000) 112 liveins: $r0, $r1, $r2, $lr, $r7 113 114 frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 115 frame-setup CFI_INSTRUCTION def_cfa_offset 8 116 frame-setup CFI_INSTRUCTION offset $lr, -4 117 frame-setup CFI_INSTRUCTION offset $r7, -8 118 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg 119 renamable $lr = t2LSRri killed renamable $r3, 3, 14, $noreg, $noreg 120 $lr = t2WhileLoopStartLR renamable $lr, %bb.4, implicit-def dead $cpsr 121 tB %bb.1, 14, $noreg 122 123 bb.1.for.body.preheader: 124 successors: %bb.2(0x80000000) 125 liveins: $r0, $r1, $r2, $lr 126 127 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 128 renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg 129 130 bb.2.for.body: 131 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 132 liveins: $q0, $r0, $r1, $r2, $r3, $lr 133 134 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg 135 renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14, $noreg 136 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg 137 renamable $lr = t2LoopDec killed renamable $lr, 1 138 MVE_VPST 1, implicit $vpr 139 renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.input_2_cast, align 1) 140 renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.input_1_cast, align 1) 141 renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 1, renamable $vpr, undef renamable $q1 142 renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 1, killed renamable $vpr, undef renamable $q0 143 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 144 tB %bb.3, 14, $noreg 145 146 bb.3.middle.block: 147 liveins: $q0 148 149 renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg 150 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 151 152 bb.4.for.cond.cleanup: 153 liveins: $lr 154 155 $r0, dead $cpsr = tMOVi8 0, 14, $noreg 156 tBX_RET 14, $noreg, implicit killed $r0 157 158... 159