1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x i32> @cmpeqz_v4i1(<4 x i32> %a, <4 x i32> %b) {
5; CHECK-LABEL: cmpeqz_v4i1:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vcmp.i32 eq, q1, zr
8; CHECK-NEXT:    vmrs r0, p0
9; CHECK-NEXT:    vcmp.i32 eq, q0, zr
10; CHECK-NEXT:    vmrs r1, p0
11; CHECK-NEXT:    eors r0, r1
12; CHECK-NEXT:    vmsr p0, r0
13; CHECK-NEXT:    vpsel q0, q0, q1
14; CHECK-NEXT:    bx lr
15entry:
16  %c1 = icmp eq <4 x i32> %a, zeroinitializer
17  %c2 = icmp eq <4 x i32> %b, zeroinitializer
18  %o = xor <4 x i1> %c1, %c2
19  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
20  ret <4 x i32> %s
21}
22
23define arm_aapcs_vfpcc <4 x i32> @cmpnez_v4i1(<4 x i32> %a, <4 x i32> %b) {
24; CHECK-LABEL: cmpnez_v4i1:
25; CHECK:       @ %bb.0: @ %entry
26; CHECK-NEXT:    vcmp.i32 ne, q1, zr
27; CHECK-NEXT:    vmrs r0, p0
28; CHECK-NEXT:    vcmp.i32 eq, q0, zr
29; CHECK-NEXT:    vmrs r1, p0
30; CHECK-NEXT:    eors r0, r1
31; CHECK-NEXT:    vmsr p0, r0
32; CHECK-NEXT:    vpsel q0, q0, q1
33; CHECK-NEXT:    bx lr
34entry:
35  %c1 = icmp eq <4 x i32> %a, zeroinitializer
36  %c2 = icmp ne <4 x i32> %b, zeroinitializer
37  %o = xor <4 x i1> %c1, %c2
38  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
39  ret <4 x i32> %s
40}
41
42define arm_aapcs_vfpcc <4 x i32> @cmpsltz_v4i1(<4 x i32> %a, <4 x i32> %b) {
43; CHECK-LABEL: cmpsltz_v4i1:
44; CHECK:       @ %bb.0: @ %entry
45; CHECK-NEXT:    vcmp.s32 lt, q1, zr
46; CHECK-NEXT:    vmrs r0, p0
47; CHECK-NEXT:    vcmp.i32 eq, q0, zr
48; CHECK-NEXT:    vmrs r1, p0
49; CHECK-NEXT:    eors r0, r1
50; CHECK-NEXT:    vmsr p0, r0
51; CHECK-NEXT:    vpsel q0, q0, q1
52; CHECK-NEXT:    bx lr
53entry:
54  %c1 = icmp eq <4 x i32> %a, zeroinitializer
55  %c2 = icmp slt <4 x i32> %b, zeroinitializer
56  %o = xor <4 x i1> %c1, %c2
57  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
58  ret <4 x i32> %s
59}
60
61define arm_aapcs_vfpcc <4 x i32> @cmpsgtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
62; CHECK-LABEL: cmpsgtz_v4i1:
63; CHECK:       @ %bb.0: @ %entry
64; CHECK-NEXT:    vcmp.s32 gt, q1, zr
65; CHECK-NEXT:    vmrs r0, p0
66; CHECK-NEXT:    vcmp.i32 eq, q0, zr
67; CHECK-NEXT:    vmrs r1, p0
68; CHECK-NEXT:    eors r0, r1
69; CHECK-NEXT:    vmsr p0, r0
70; CHECK-NEXT:    vpsel q0, q0, q1
71; CHECK-NEXT:    bx lr
72entry:
73  %c1 = icmp eq <4 x i32> %a, zeroinitializer
74  %c2 = icmp sgt <4 x i32> %b, zeroinitializer
75  %o = xor <4 x i1> %c1, %c2
76  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
77  ret <4 x i32> %s
78}
79
80define arm_aapcs_vfpcc <4 x i32> @cmpslez_v4i1(<4 x i32> %a, <4 x i32> %b) {
81; CHECK-LABEL: cmpslez_v4i1:
82; CHECK:       @ %bb.0: @ %entry
83; CHECK-NEXT:    vcmp.s32 le, q1, zr
84; CHECK-NEXT:    vmrs r0, p0
85; CHECK-NEXT:    vcmp.i32 eq, q0, zr
86; CHECK-NEXT:    vmrs r1, p0
87; CHECK-NEXT:    eors r0, r1
88; CHECK-NEXT:    vmsr p0, r0
89; CHECK-NEXT:    vpsel q0, q0, q1
90; CHECK-NEXT:    bx lr
91entry:
92  %c1 = icmp eq <4 x i32> %a, zeroinitializer
93  %c2 = icmp sle <4 x i32> %b, zeroinitializer
94  %o = xor <4 x i1> %c1, %c2
95  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
96  ret <4 x i32> %s
97}
98
99define arm_aapcs_vfpcc <4 x i32> @cmpsgez_v4i1(<4 x i32> %a, <4 x i32> %b) {
100; CHECK-LABEL: cmpsgez_v4i1:
101; CHECK:       @ %bb.0: @ %entry
102; CHECK-NEXT:    vcmp.s32 ge, q1, zr
103; CHECK-NEXT:    vmrs r0, p0
104; CHECK-NEXT:    vcmp.i32 eq, q0, zr
105; CHECK-NEXT:    vmrs r1, p0
106; CHECK-NEXT:    eors r0, r1
107; CHECK-NEXT:    vmsr p0, r0
108; CHECK-NEXT:    vpsel q0, q0, q1
109; CHECK-NEXT:    bx lr
110entry:
111  %c1 = icmp eq <4 x i32> %a, zeroinitializer
112  %c2 = icmp sge <4 x i32> %b, zeroinitializer
113  %o = xor <4 x i1> %c1, %c2
114  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
115  ret <4 x i32> %s
116}
117
118define arm_aapcs_vfpcc <4 x i32> @cmpultz_v4i1(<4 x i32> %a, <4 x i32> %b) {
119; CHECK-LABEL: cmpultz_v4i1:
120; CHECK:       @ %bb.0: @ %entry
121; CHECK-NEXT:    vcmp.i32 eq, q0, zr
122; CHECK-NEXT:    vpsel q0, q0, q1
123; CHECK-NEXT:    bx lr
124entry:
125  %c1 = icmp eq <4 x i32> %a, zeroinitializer
126  %c2 = icmp ult <4 x i32> %b, zeroinitializer
127  %o = xor <4 x i1> %c1, %c2
128  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
129  ret <4 x i32> %s
130}
131
132define arm_aapcs_vfpcc <4 x i32> @cmpugtz_v4i1(<4 x i32> %a, <4 x i32> %b) {
133; CHECK-LABEL: cmpugtz_v4i1:
134; CHECK:       @ %bb.0: @ %entry
135; CHECK-NEXT:    vcmp.i32 ne, q1, zr
136; CHECK-NEXT:    vmrs r0, p0
137; CHECK-NEXT:    vcmp.i32 eq, q0, zr
138; CHECK-NEXT:    vmrs r1, p0
139; CHECK-NEXT:    eors r0, r1
140; CHECK-NEXT:    vmsr p0, r0
141; CHECK-NEXT:    vpsel q0, q0, q1
142; CHECK-NEXT:    bx lr
143entry:
144  %c1 = icmp eq <4 x i32> %a, zeroinitializer
145  %c2 = icmp ugt <4 x i32> %b, zeroinitializer
146  %o = xor <4 x i1> %c1, %c2
147  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
148  ret <4 x i32> %s
149}
150
151define arm_aapcs_vfpcc <4 x i32> @cmpulez_v4i1(<4 x i32> %a, <4 x i32> %b) {
152; CHECK-LABEL: cmpulez_v4i1:
153; CHECK:       @ %bb.0: @ %entry
154; CHECK-NEXT:    vcmp.u32 cs, q1, zr
155; CHECK-NEXT:    vmrs r0, p0
156; CHECK-NEXT:    vcmp.i32 eq, q0, zr
157; CHECK-NEXT:    vmrs r1, p0
158; CHECK-NEXT:    eors r0, r1
159; CHECK-NEXT:    vmsr p0, r0
160; CHECK-NEXT:    vpsel q0, q0, q1
161; CHECK-NEXT:    bx lr
162entry:
163  %c1 = icmp eq <4 x i32> %a, zeroinitializer
164  %c2 = icmp ule <4 x i32> %b, zeroinitializer
165  %o = xor <4 x i1> %c1, %c2
166  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
167  ret <4 x i32> %s
168}
169
170define arm_aapcs_vfpcc <4 x i32> @cmpugez_v4i1(<4 x i32> %a, <4 x i32> %b) {
171; CHECK-LABEL: cmpugez_v4i1:
172; CHECK:       @ %bb.0: @ %entry
173; CHECK-NEXT:    vcmp.i32 eq, q0, zr
174; CHECK-NEXT:    vpsel q0, q1, q0
175; CHECK-NEXT:    bx lr
176entry:
177  %c1 = icmp eq <4 x i32> %a, zeroinitializer
178  %c2 = icmp uge <4 x i32> %b, zeroinitializer
179  %o = xor <4 x i1> %c1, %c2
180  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
181  ret <4 x i32> %s
182}
183
184
185
186define arm_aapcs_vfpcc <4 x i32> @cmpeq_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
187; CHECK-LABEL: cmpeq_v4i1:
188; CHECK:       @ %bb.0: @ %entry
189; CHECK-NEXT:    vcmp.i32 eq, q1, q2
190; CHECK-NEXT:    vmrs r0, p0
191; CHECK-NEXT:    vcmp.i32 eq, q0, zr
192; CHECK-NEXT:    vmrs r1, p0
193; CHECK-NEXT:    eors r0, r1
194; CHECK-NEXT:    vmsr p0, r0
195; CHECK-NEXT:    vpsel q0, q0, q1
196; CHECK-NEXT:    bx lr
197entry:
198  %c1 = icmp eq <4 x i32> %a, zeroinitializer
199  %c2 = icmp eq <4 x i32> %b, %c
200  %o = xor <4 x i1> %c1, %c2
201  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
202  ret <4 x i32> %s
203}
204
205define arm_aapcs_vfpcc <4 x i32> @cmpne_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
206; CHECK-LABEL: cmpne_v4i1:
207; CHECK:       @ %bb.0: @ %entry
208; CHECK-NEXT:    vcmp.i32 ne, q1, q2
209; CHECK-NEXT:    vmrs r0, p0
210; CHECK-NEXT:    vcmp.i32 eq, q0, zr
211; CHECK-NEXT:    vmrs r1, p0
212; CHECK-NEXT:    eors r0, r1
213; CHECK-NEXT:    vmsr p0, r0
214; CHECK-NEXT:    vpsel q0, q0, q1
215; CHECK-NEXT:    bx lr
216entry:
217  %c1 = icmp eq <4 x i32> %a, zeroinitializer
218  %c2 = icmp ne <4 x i32> %b, %c
219  %o = xor <4 x i1> %c1, %c2
220  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
221  ret <4 x i32> %s
222}
223
224define arm_aapcs_vfpcc <4 x i32> @cmpslt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
225; CHECK-LABEL: cmpslt_v4i1:
226; CHECK:       @ %bb.0: @ %entry
227; CHECK-NEXT:    vcmp.s32 gt, q2, q1
228; CHECK-NEXT:    vmrs r0, p0
229; CHECK-NEXT:    vcmp.i32 eq, q0, zr
230; CHECK-NEXT:    vmrs r1, p0
231; CHECK-NEXT:    eors r0, r1
232; CHECK-NEXT:    vmsr p0, r0
233; CHECK-NEXT:    vpsel q0, q0, q1
234; CHECK-NEXT:    bx lr
235entry:
236  %c1 = icmp eq <4 x i32> %a, zeroinitializer
237  %c2 = icmp slt <4 x i32> %b, %c
238  %o = xor <4 x i1> %c1, %c2
239  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
240  ret <4 x i32> %s
241}
242
243define arm_aapcs_vfpcc <4 x i32> @cmpsgt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
244; CHECK-LABEL: cmpsgt_v4i1:
245; CHECK:       @ %bb.0: @ %entry
246; CHECK-NEXT:    vcmp.s32 gt, q1, q2
247; CHECK-NEXT:    vmrs r0, p0
248; CHECK-NEXT:    vcmp.i32 eq, q0, zr
249; CHECK-NEXT:    vmrs r1, p0
250; CHECK-NEXT:    eors r0, r1
251; CHECK-NEXT:    vmsr p0, r0
252; CHECK-NEXT:    vpsel q0, q0, q1
253; CHECK-NEXT:    bx lr
254entry:
255  %c1 = icmp eq <4 x i32> %a, zeroinitializer
256  %c2 = icmp sgt <4 x i32> %b, %c
257  %o = xor <4 x i1> %c1, %c2
258  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
259  ret <4 x i32> %s
260}
261
262define arm_aapcs_vfpcc <4 x i32> @cmpsle_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
263; CHECK-LABEL: cmpsle_v4i1:
264; CHECK:       @ %bb.0: @ %entry
265; CHECK-NEXT:    vcmp.s32 ge, q2, q1
266; CHECK-NEXT:    vmrs r0, p0
267; CHECK-NEXT:    vcmp.i32 eq, q0, zr
268; CHECK-NEXT:    vmrs r1, p0
269; CHECK-NEXT:    eors r0, r1
270; CHECK-NEXT:    vmsr p0, r0
271; CHECK-NEXT:    vpsel q0, q0, q1
272; CHECK-NEXT:    bx lr
273entry:
274  %c1 = icmp eq <4 x i32> %a, zeroinitializer
275  %c2 = icmp sle <4 x i32> %b, %c
276  %o = xor <4 x i1> %c1, %c2
277  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
278  ret <4 x i32> %s
279}
280
281define arm_aapcs_vfpcc <4 x i32> @cmpsge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
282; CHECK-LABEL: cmpsge_v4i1:
283; CHECK:       @ %bb.0: @ %entry
284; CHECK-NEXT:    vcmp.s32 ge, q1, q2
285; CHECK-NEXT:    vmrs r0, p0
286; CHECK-NEXT:    vcmp.i32 eq, q0, zr
287; CHECK-NEXT:    vmrs r1, p0
288; CHECK-NEXT:    eors r0, r1
289; CHECK-NEXT:    vmsr p0, r0
290; CHECK-NEXT:    vpsel q0, q0, q1
291; CHECK-NEXT:    bx lr
292entry:
293  %c1 = icmp eq <4 x i32> %a, zeroinitializer
294  %c2 = icmp sge <4 x i32> %b, %c
295  %o = xor <4 x i1> %c1, %c2
296  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
297  ret <4 x i32> %s
298}
299
300define arm_aapcs_vfpcc <4 x i32> @cmpult_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
301; CHECK-LABEL: cmpult_v4i1:
302; CHECK:       @ %bb.0: @ %entry
303; CHECK-NEXT:    vcmp.u32 hi, q2, q1
304; CHECK-NEXT:    vmrs r0, p0
305; CHECK-NEXT:    vcmp.i32 eq, q0, zr
306; CHECK-NEXT:    vmrs r1, p0
307; CHECK-NEXT:    eors r0, r1
308; CHECK-NEXT:    vmsr p0, r0
309; CHECK-NEXT:    vpsel q0, q0, q1
310; CHECK-NEXT:    bx lr
311entry:
312  %c1 = icmp eq <4 x i32> %a, zeroinitializer
313  %c2 = icmp ult <4 x i32> %b, %c
314  %o = xor <4 x i1> %c1, %c2
315  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
316  ret <4 x i32> %s
317}
318
319define arm_aapcs_vfpcc <4 x i32> @cmpugt_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
320; CHECK-LABEL: cmpugt_v4i1:
321; CHECK:       @ %bb.0: @ %entry
322; CHECK-NEXT:    vcmp.u32 hi, q1, q2
323; CHECK-NEXT:    vmrs r0, p0
324; CHECK-NEXT:    vcmp.i32 eq, q0, zr
325; CHECK-NEXT:    vmrs r1, p0
326; CHECK-NEXT:    eors r0, r1
327; CHECK-NEXT:    vmsr p0, r0
328; CHECK-NEXT:    vpsel q0, q0, q1
329; CHECK-NEXT:    bx lr
330entry:
331  %c1 = icmp eq <4 x i32> %a, zeroinitializer
332  %c2 = icmp ugt <4 x i32> %b, %c
333  %o = xor <4 x i1> %c1, %c2
334  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
335  ret <4 x i32> %s
336}
337
338define arm_aapcs_vfpcc <4 x i32> @cmpule_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
339; CHECK-LABEL: cmpule_v4i1:
340; CHECK:       @ %bb.0: @ %entry
341; CHECK-NEXT:    vcmp.u32 cs, q2, q1
342; CHECK-NEXT:    vmrs r0, p0
343; CHECK-NEXT:    vcmp.i32 eq, q0, zr
344; CHECK-NEXT:    vmrs r1, p0
345; CHECK-NEXT:    eors r0, r1
346; CHECK-NEXT:    vmsr p0, r0
347; CHECK-NEXT:    vpsel q0, q0, q1
348; CHECK-NEXT:    bx lr
349entry:
350  %c1 = icmp eq <4 x i32> %a, zeroinitializer
351  %c2 = icmp ule <4 x i32> %b, %c
352  %o = xor <4 x i1> %c1, %c2
353  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
354  ret <4 x i32> %s
355}
356
357define arm_aapcs_vfpcc <4 x i32> @cmpuge_v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
358; CHECK-LABEL: cmpuge_v4i1:
359; CHECK:       @ %bb.0: @ %entry
360; CHECK-NEXT:    vcmp.u32 cs, q1, q2
361; CHECK-NEXT:    vmrs r0, p0
362; CHECK-NEXT:    vcmp.i32 eq, q0, zr
363; CHECK-NEXT:    vmrs r1, p0
364; CHECK-NEXT:    eors r0, r1
365; CHECK-NEXT:    vmsr p0, r0
366; CHECK-NEXT:    vpsel q0, q0, q1
367; CHECK-NEXT:    bx lr
368entry:
369  %c1 = icmp eq <4 x i32> %a, zeroinitializer
370  %c2 = icmp uge <4 x i32> %b, %c
371  %o = xor <4 x i1> %c1, %c2
372  %s = select <4 x i1> %o, <4 x i32> %a, <4 x i32> %b
373  ret <4 x i32> %s
374}
375
376
377
378
379define arm_aapcs_vfpcc <8 x i16> @cmpeqz_v8i1(<8 x i16> %a, <8 x i16> %b) {
380; CHECK-LABEL: cmpeqz_v8i1:
381; CHECK:       @ %bb.0: @ %entry
382; CHECK-NEXT:    vcmp.i16 eq, q1, zr
383; CHECK-NEXT:    vmrs r0, p0
384; CHECK-NEXT:    vcmp.i16 eq, q0, zr
385; CHECK-NEXT:    vmrs r1, p0
386; CHECK-NEXT:    eors r0, r1
387; CHECK-NEXT:    vmsr p0, r0
388; CHECK-NEXT:    vpsel q0, q0, q1
389; CHECK-NEXT:    bx lr
390entry:
391  %c1 = icmp eq <8 x i16> %a, zeroinitializer
392  %c2 = icmp eq <8 x i16> %b, zeroinitializer
393  %o = xor <8 x i1> %c1, %c2
394  %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
395  ret <8 x i16> %s
396}
397
398define arm_aapcs_vfpcc <8 x i16> @cmpeq_v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
399; CHECK-LABEL: cmpeq_v8i1:
400; CHECK:       @ %bb.0: @ %entry
401; CHECK-NEXT:    vcmp.i16 eq, q1, q2
402; CHECK-NEXT:    vmrs r0, p0
403; CHECK-NEXT:    vcmp.i16 eq, q0, zr
404; CHECK-NEXT:    vmrs r1, p0
405; CHECK-NEXT:    eors r0, r1
406; CHECK-NEXT:    vmsr p0, r0
407; CHECK-NEXT:    vpsel q0, q0, q1
408; CHECK-NEXT:    bx lr
409entry:
410  %c1 = icmp eq <8 x i16> %a, zeroinitializer
411  %c2 = icmp eq <8 x i16> %b, %c
412  %o = xor <8 x i1> %c1, %c2
413  %s = select <8 x i1> %o, <8 x i16> %a, <8 x i16> %b
414  ret <8 x i16> %s
415}
416
417
418define arm_aapcs_vfpcc <16 x i8> @cmpeqz_v16i1(<16 x i8> %a, <16 x i8> %b) {
419; CHECK-LABEL: cmpeqz_v16i1:
420; CHECK:       @ %bb.0: @ %entry
421; CHECK-NEXT:    vcmp.i8 eq, q1, zr
422; CHECK-NEXT:    vmrs r0, p0
423; CHECK-NEXT:    vcmp.i8 eq, q0, zr
424; CHECK-NEXT:    vmrs r1, p0
425; CHECK-NEXT:    eors r0, r1
426; CHECK-NEXT:    vmsr p0, r0
427; CHECK-NEXT:    vpsel q0, q0, q1
428; CHECK-NEXT:    bx lr
429entry:
430  %c1 = icmp eq <16 x i8> %a, zeroinitializer
431  %c2 = icmp eq <16 x i8> %b, zeroinitializer
432  %o = xor <16 x i1> %c1, %c2
433  %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
434  ret <16 x i8> %s
435}
436
437define arm_aapcs_vfpcc <16 x i8> @cmpeq_v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
438; CHECK-LABEL: cmpeq_v16i1:
439; CHECK:       @ %bb.0: @ %entry
440; CHECK-NEXT:    vcmp.i8 eq, q1, q2
441; CHECK-NEXT:    vmrs r0, p0
442; CHECK-NEXT:    vcmp.i8 eq, q0, zr
443; CHECK-NEXT:    vmrs r1, p0
444; CHECK-NEXT:    eors r0, r1
445; CHECK-NEXT:    vmsr p0, r0
446; CHECK-NEXT:    vpsel q0, q0, q1
447; CHECK-NEXT:    bx lr
448entry:
449  %c1 = icmp eq <16 x i8> %a, zeroinitializer
450  %c2 = icmp eq <16 x i8> %b, %c
451  %o = xor <16 x i1> %c1, %c2
452  %s = select <16 x i1> %o, <16 x i8> %a, <16 x i8> %b
453  ret <16 x i8> %s
454}
455
456
457define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
458; CHECK-LABEL: cmpeqz_v2i1:
459; CHECK:       @ %bb.0: @ %entry
460; CHECK-NEXT:    vmov r0, r1, d3
461; CHECK-NEXT:    orrs r0, r1
462; CHECK-NEXT:    vmov r1, r2, d2
463; CHECK-NEXT:    cset r0, eq
464; CHECK-NEXT:    cmp r0, #0
465; CHECK-NEXT:    csetm r0, ne
466; CHECK-NEXT:    orrs r1, r2
467; CHECK-NEXT:    cset r1, eq
468; CHECK-NEXT:    cmp r1, #0
469; CHECK-NEXT:    csetm r1, ne
470; CHECK-NEXT:    vmov q2[2], q2[0], r1, r0
471; CHECK-NEXT:    vmov q2[3], q2[1], r1, r0
472; CHECK-NEXT:    vmov r0, r1, d1
473; CHECK-NEXT:    orrs r0, r1
474; CHECK-NEXT:    vmov r1, r2, d0
475; CHECK-NEXT:    cset r0, eq
476; CHECK-NEXT:    cmp r0, #0
477; CHECK-NEXT:    csetm r0, ne
478; CHECK-NEXT:    orrs r1, r2
479; CHECK-NEXT:    cset r1, eq
480; CHECK-NEXT:    cmp r1, #0
481; CHECK-NEXT:    csetm r1, ne
482; CHECK-NEXT:    vmov q3[2], q3[0], r1, r0
483; CHECK-NEXT:    vmov q3[3], q3[1], r1, r0
484; CHECK-NEXT:    veor q2, q3, q2
485; CHECK-NEXT:    vbic q1, q1, q2
486; CHECK-NEXT:    vand q0, q0, q2
487; CHECK-NEXT:    vorr q0, q0, q1
488; CHECK-NEXT:    bx lr
489entry:
490  %c1 = icmp eq <2 x i64> %a, zeroinitializer
491  %c2 = icmp eq <2 x i64> %b, zeroinitializer
492  %o = xor <2 x i1> %c1, %c2
493  %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
494  ret <2 x i64> %s
495}
496
497define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
498; CHECK-LABEL: cmpeq_v2i1:
499; CHECK:       @ %bb.0: @ %entry
500; CHECK-NEXT:    vmov r0, r1, d5
501; CHECK-NEXT:    vmov r2, r3, d3
502; CHECK-NEXT:    eors r0, r2
503; CHECK-NEXT:    eors r1, r3
504; CHECK-NEXT:    orrs r0, r1
505; CHECK-NEXT:    vmov r12, r2, d4
506; CHECK-NEXT:    vmov r3, r1, d2
507; CHECK-NEXT:    cset r0, eq
508; CHECK-NEXT:    cmp r0, #0
509; CHECK-NEXT:    csetm r0, ne
510; CHECK-NEXT:    eors r1, r2
511; CHECK-NEXT:    eor.w r2, r3, r12
512; CHECK-NEXT:    orrs r1, r2
513; CHECK-NEXT:    cset r1, eq
514; CHECK-NEXT:    cmp r1, #0
515; CHECK-NEXT:    csetm r1, ne
516; CHECK-NEXT:    vmov q2[2], q2[0], r1, r0
517; CHECK-NEXT:    vmov q2[3], q2[1], r1, r0
518; CHECK-NEXT:    vmov r0, r1, d1
519; CHECK-NEXT:    orrs r0, r1
520; CHECK-NEXT:    vmov r1, r2, d0
521; CHECK-NEXT:    cset r0, eq
522; CHECK-NEXT:    cmp r0, #0
523; CHECK-NEXT:    csetm r0, ne
524; CHECK-NEXT:    orrs r1, r2
525; CHECK-NEXT:    cset r1, eq
526; CHECK-NEXT:    cmp r1, #0
527; CHECK-NEXT:    csetm r1, ne
528; CHECK-NEXT:    vmov q3[2], q3[0], r1, r0
529; CHECK-NEXT:    vmov q3[3], q3[1], r1, r0
530; CHECK-NEXT:    veor q2, q3, q2
531; CHECK-NEXT:    vbic q1, q1, q2
532; CHECK-NEXT:    vand q0, q0, q2
533; CHECK-NEXT:    vorr q0, q0, q1
534; CHECK-NEXT:    bx lr
535entry:
536  %c1 = icmp eq <2 x i64> %a, zeroinitializer
537  %c2 = icmp eq <2 x i64> %b, %c
538  %o = xor <2 x i1> %c1, %c2
539  %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
540  ret <2 x i64> %s
541}
542
543
544