1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s 2 3 4// ------------------------------------------------------------------------- // 5// Invalid element widths. 6 7ext z0.h, { z1.h, z2.h }, #0 8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 9// CHECK-NEXT: ext z0.h, { z1.h, z2.h }, #0 10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 11 12ext z0.s, { z1.s, z2.s }, #0 13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 14// CHECK-NEXT: ext z0.s, { z1.s, z2.s }, #0 15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 16 17ext z0.d, { z1.d, z2.d }, #0 18// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 19// CHECK-NEXT: ext z0.d, { z1.d, z2.d }, #0 20// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 21 22 23// ------------------------------------------------------------------------- // 24// Invalid immediate range. 25 26ext z0.b, { z1.b, z2.b }, #-1 27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. 28// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #-1 29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 30 31ext z0.b, { z1.b, z2.b }, #256 32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. 33// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #256 34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 35 36 37// --------------------------------------------------------------------------// 38// Invalid vector list. 39 40ext z0.b, { }, #0 41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 42// CHECK-NEXT: ext z0.b, { }, #0 43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 44 45ext z0.b, { z1.b }, #0 46// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 47// CHECK-NEXT: ext z0.b, { z1.b }, #0 48// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 49 50ext z0.b, { z1.b, z2.b, z3.b }, #0 51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 52// CHECK-NEXT: ext z0.b, { z1.b, z2.b, z3.b }, #0 53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 54 55ext z0.b, { z1.b, z2.h }, #0 56// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix 57// CHECK-NEXT: ext z0.b, { z1.b, z2.h }, #0 58// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 59 60ext z0.b, { z1.b, z31.b }, #0 61// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential 62// CHECK-NEXT: ext z0.b, { z1.b, z31.b }, #0 63// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 64 65ext z0.b, { v0.4b, v1.4b }, #0 66// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 67// CHECK-NEXT: ext z0.b, { v0.4b, v1.4b }, #0 68// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 69 70 71// --------------------------------------------------------------------------// 72// Negative tests for instructions that are incompatible with movprfx 73 74movprfx z31, z6 75ext z31.b, { z30.b, z31.b }, #255 76// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 77// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255 78// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 79 80movprfx z31.b, p0/z, z6.b 81ext z31.b, { z30.b, z31.b }, #255 82// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 83// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255 84// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 85