1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32 3; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3 4; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6 5; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6 6; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS4 7; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6 8 9; Test subword and word stores. 10 11@a = common global i8 0, align 4 12@b = common global i16 0, align 4 13@c = common global i32 0, align 4 14@d = common global i64 0, align 8 15 16define void @f1(i8 %a) { 17; MIPS32-LABEL: f1: 18; MIPS32: # %bb.0: 19; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 20; MIPS32-NEXT: # <MCOperand Reg:1> 21; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>> 22; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR 23; MIPS32-NEXT: # <MCOperand Reg:19>> 24; MIPS32-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB 25; MIPS32-NEXT: # <MCOperand Reg:22> 26; MIPS32-NEXT: # <MCOperand Reg:1> 27; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>> 28; 29; MMR3-LABEL: f1: 30; MMR3: # %bb.0: 31; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 32; MMR3-NEXT: # <MCOperand Reg:1> 33; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>> 34; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM 35; MMR3-NEXT: # <MCOperand Reg:19>> 36; MMR3-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM 37; MMR3-NEXT: # <MCOperand Reg:22> 38; MMR3-NEXT: # <MCOperand Reg:1> 39; MMR3-NEXT: # <MCOperand Expr:(%lo(a))>> 40; 41; MIPS32R6-LABEL: f1: 42; MIPS32R6: # %bb.0: 43; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 44; MIPS32R6-NEXT: # <MCOperand Reg:1> 45; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(a))>> 46; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR 47; MIPS32R6-NEXT: # <MCOperand Reg:21> 48; MIPS32R6-NEXT: # <MCOperand Reg:19>> 49; MIPS32R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB 50; MIPS32R6-NEXT: # <MCOperand Reg:22> 51; MIPS32R6-NEXT: # <MCOperand Reg:1> 52; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(a))>> 53; 54; MMR6-LABEL: f1: 55; MMR6: # %bb.0: 56; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 57; MMR6-NEXT: # <MCOperand Reg:1> 58; MMR6-NEXT: # <MCOperand Expr:(%hi(a))>> 59; MMR6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM 60; MMR6-NEXT: # <MCOperand Reg:22> 61; MMR6-NEXT: # <MCOperand Reg:1> 62; MMR6-NEXT: # <MCOperand Expr:(%lo(a))>> 63; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM 64; MMR6-NEXT: # <MCOperand Reg:19>> 65; 66; MIPS4-LABEL: f1: 67; MIPS4: # %bb.0: 68; MIPS4-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64 69; MIPS4-NEXT: # <MCOperand Reg:30> 70; MIPS4-NEXT: # <MCOperand Expr:(%highest(a))>> 71; MIPS4-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu 72; MIPS4-NEXT: # <MCOperand Reg:30> 73; MIPS4-NEXT: # <MCOperand Reg:30> 74; MIPS4-NEXT: # <MCOperand Expr:(%higher(a))>> 75; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 76; MIPS4-NEXT: # <MCOperand Reg:30> 77; MIPS4-NEXT: # <MCOperand Reg:30> 78; MIPS4-NEXT: # <MCOperand Imm:16>> 79; MIPS4-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu 80; MIPS4-NEXT: # <MCOperand Reg:30> 81; MIPS4-NEXT: # <MCOperand Reg:30> 82; MIPS4-NEXT: # <MCOperand Expr:(%hi(a))>> 83; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 84; MIPS4-NEXT: # <MCOperand Reg:30> 85; MIPS4-NEXT: # <MCOperand Reg:30> 86; MIPS4-NEXT: # <MCOperand Imm:16>> 87; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR 88; MIPS4-NEXT: # <MCOperand Reg:301>> 89; MIPS4-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64 90; MIPS4-NEXT: # <MCOperand Reg:356> 91; MIPS4-NEXT: # <MCOperand Reg:30> 92; MIPS4-NEXT: # <MCOperand Expr:(%lo(a))>> 93; 94; MIPS64R6-LABEL: f1: 95; MIPS64R6: # %bb.0: 96; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64 97; MIPS64R6-NEXT: # <MCOperand Reg:30> 98; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(a))>> 99; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu 100; MIPS64R6-NEXT: # <MCOperand Reg:30> 101; MIPS64R6-NEXT: # <MCOperand Reg:30> 102; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(a))>> 103; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 104; MIPS64R6-NEXT: # <MCOperand Reg:30> 105; MIPS64R6-NEXT: # <MCOperand Reg:30> 106; MIPS64R6-NEXT: # <MCOperand Imm:16>> 107; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu 108; MIPS64R6-NEXT: # <MCOperand Reg:30> 109; MIPS64R6-NEXT: # <MCOperand Reg:30> 110; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(a))>> 111; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 112; MIPS64R6-NEXT: # <MCOperand Reg:30> 113; MIPS64R6-NEXT: # <MCOperand Reg:30> 114; MIPS64R6-NEXT: # <MCOperand Imm:16>> 115; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64 116; MIPS64R6-NEXT: # <MCOperand Reg:355> 117; MIPS64R6-NEXT: # <MCOperand Reg:301>> 118; MIPS64R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64 119; MIPS64R6-NEXT: # <MCOperand Reg:356> 120; MIPS64R6-NEXT: # <MCOperand Reg:30> 121; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(a))>> 122 store i8 %a, i8 * @a 123 ret void 124} 125 126define void @f2(i16 %a) { 127; MIPS32-LABEL: f2: 128; MIPS32: # %bb.0: 129; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 130; MIPS32-NEXT: # <MCOperand Reg:1> 131; MIPS32-NEXT: # <MCOperand Expr:(%hi(b))>> 132; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR 133; MIPS32-NEXT: # <MCOperand Reg:19>> 134; MIPS32-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH 135; MIPS32-NEXT: # <MCOperand Reg:22> 136; MIPS32-NEXT: # <MCOperand Reg:1> 137; MIPS32-NEXT: # <MCOperand Expr:(%lo(b))>> 138; 139; MMR3-LABEL: f2: 140; MMR3: # %bb.0: 141; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 142; MMR3-NEXT: # <MCOperand Reg:1> 143; MMR3-NEXT: # <MCOperand Expr:(%hi(b))>> 144; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM 145; MMR3-NEXT: # <MCOperand Reg:19>> 146; MMR3-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM 147; MMR3-NEXT: # <MCOperand Reg:22> 148; MMR3-NEXT: # <MCOperand Reg:1> 149; MMR3-NEXT: # <MCOperand Expr:(%lo(b))>> 150; 151; MIPS32R6-LABEL: f2: 152; MIPS32R6: # %bb.0: 153; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 154; MIPS32R6-NEXT: # <MCOperand Reg:1> 155; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(b))>> 156; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR 157; MIPS32R6-NEXT: # <MCOperand Reg:21> 158; MIPS32R6-NEXT: # <MCOperand Reg:19>> 159; MIPS32R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH 160; MIPS32R6-NEXT: # <MCOperand Reg:22> 161; MIPS32R6-NEXT: # <MCOperand Reg:1> 162; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(b))>> 163; 164; MMR6-LABEL: f2: 165; MMR6: # %bb.0: 166; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 167; MMR6-NEXT: # <MCOperand Reg:1> 168; MMR6-NEXT: # <MCOperand Expr:(%hi(b))>> 169; MMR6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM 170; MMR6-NEXT: # <MCOperand Reg:22> 171; MMR6-NEXT: # <MCOperand Reg:1> 172; MMR6-NEXT: # <MCOperand Expr:(%lo(b))>> 173; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM 174; MMR6-NEXT: # <MCOperand Reg:19>> 175; 176; MIPS4-LABEL: f2: 177; MIPS4: # %bb.0: 178; MIPS4-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64 179; MIPS4-NEXT: # <MCOperand Reg:30> 180; MIPS4-NEXT: # <MCOperand Expr:(%highest(b))>> 181; MIPS4-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu 182; MIPS4-NEXT: # <MCOperand Reg:30> 183; MIPS4-NEXT: # <MCOperand Reg:30> 184; MIPS4-NEXT: # <MCOperand Expr:(%higher(b))>> 185; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 186; MIPS4-NEXT: # <MCOperand Reg:30> 187; MIPS4-NEXT: # <MCOperand Reg:30> 188; MIPS4-NEXT: # <MCOperand Imm:16>> 189; MIPS4-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu 190; MIPS4-NEXT: # <MCOperand Reg:30> 191; MIPS4-NEXT: # <MCOperand Reg:30> 192; MIPS4-NEXT: # <MCOperand Expr:(%hi(b))>> 193; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 194; MIPS4-NEXT: # <MCOperand Reg:30> 195; MIPS4-NEXT: # <MCOperand Reg:30> 196; MIPS4-NEXT: # <MCOperand Imm:16>> 197; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR 198; MIPS4-NEXT: # <MCOperand Reg:301>> 199; MIPS4-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64 200; MIPS4-NEXT: # <MCOperand Reg:356> 201; MIPS4-NEXT: # <MCOperand Reg:30> 202; MIPS4-NEXT: # <MCOperand Expr:(%lo(b))>> 203; 204; MIPS64R6-LABEL: f2: 205; MIPS64R6: # %bb.0: 206; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64 207; MIPS64R6-NEXT: # <MCOperand Reg:30> 208; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(b))>> 209; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu 210; MIPS64R6-NEXT: # <MCOperand Reg:30> 211; MIPS64R6-NEXT: # <MCOperand Reg:30> 212; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(b))>> 213; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 214; MIPS64R6-NEXT: # <MCOperand Reg:30> 215; MIPS64R6-NEXT: # <MCOperand Reg:30> 216; MIPS64R6-NEXT: # <MCOperand Imm:16>> 217; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu 218; MIPS64R6-NEXT: # <MCOperand Reg:30> 219; MIPS64R6-NEXT: # <MCOperand Reg:30> 220; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(b))>> 221; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 222; MIPS64R6-NEXT: # <MCOperand Reg:30> 223; MIPS64R6-NEXT: # <MCOperand Reg:30> 224; MIPS64R6-NEXT: # <MCOperand Imm:16>> 225; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64 226; MIPS64R6-NEXT: # <MCOperand Reg:355> 227; MIPS64R6-NEXT: # <MCOperand Reg:301>> 228; MIPS64R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64 229; MIPS64R6-NEXT: # <MCOperand Reg:356> 230; MIPS64R6-NEXT: # <MCOperand Reg:30> 231; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(b))>> 232 store i16 %a, i16 * @b 233 ret void 234} 235 236define void @f3(i32 %a) { 237; MIPS32-LABEL: f3: 238; MIPS32: # %bb.0: 239; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi 240; MIPS32-NEXT: # <MCOperand Reg:1> 241; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>> 242; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR 243; MIPS32-NEXT: # <MCOperand Reg:19>> 244; MIPS32-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW 245; MIPS32-NEXT: # <MCOperand Reg:22> 246; MIPS32-NEXT: # <MCOperand Reg:1> 247; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>> 248; 249; MMR3-LABEL: f3: 250; MMR3: # %bb.0: 251; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi 252; MMR3-NEXT: # <MCOperand Reg:1> 253; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>> 254; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM 255; MMR3-NEXT: # <MCOperand Reg:19>> 256; MMR3-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM 257; MMR3-NEXT: # <MCOperand Reg:22> 258; MMR3-NEXT: # <MCOperand Reg:1> 259; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>> 260; 261; MIPS32R6-LABEL: f3: 262; MIPS32R6: # %bb.0: 263; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi 264; MIPS32R6-NEXT: # <MCOperand Reg:1> 265; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>> 266; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR 267; MIPS32R6-NEXT: # <MCOperand Reg:21> 268; MIPS32R6-NEXT: # <MCOperand Reg:19>> 269; MIPS32R6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW 270; MIPS32R6-NEXT: # <MCOperand Reg:22> 271; MIPS32R6-NEXT: # <MCOperand Reg:1> 272; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>> 273; 274; MMR6-LABEL: f3: 275; MMR6: # %bb.0: 276; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi 277; MMR6-NEXT: # <MCOperand Reg:1> 278; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>> 279; MMR6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM 280; MMR6-NEXT: # <MCOperand Reg:22> 281; MMR6-NEXT: # <MCOperand Reg:1> 282; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>> 283; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM 284; MMR6-NEXT: # <MCOperand Reg:19>> 285; 286; MIPS4-LABEL: f3: 287; MIPS4: # %bb.0: 288; MIPS4-NEXT: sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL 289; MIPS4-NEXT: # <MCOperand Reg:1> 290; MIPS4-NEXT: # <MCOperand Reg:22> 291; MIPS4-NEXT: # <MCOperand Imm:0>> 292; MIPS4-NEXT: lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64 293; MIPS4-NEXT: # <MCOperand Reg:416> 294; MIPS4-NEXT: # <MCOperand Expr:(%highest(c))>> 295; MIPS4-NEXT: daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu 296; MIPS4-NEXT: # <MCOperand Reg:416> 297; MIPS4-NEXT: # <MCOperand Reg:416> 298; MIPS4-NEXT: # <MCOperand Expr:(%higher(c))>> 299; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL 300; MIPS4-NEXT: # <MCOperand Reg:416> 301; MIPS4-NEXT: # <MCOperand Reg:416> 302; MIPS4-NEXT: # <MCOperand Imm:16>> 303; MIPS4-NEXT: daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu 304; MIPS4-NEXT: # <MCOperand Reg:416> 305; MIPS4-NEXT: # <MCOperand Reg:416> 306; MIPS4-NEXT: # <MCOperand Expr:(%hi(c))>> 307; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL 308; MIPS4-NEXT: # <MCOperand Reg:416> 309; MIPS4-NEXT: # <MCOperand Reg:416> 310; MIPS4-NEXT: # <MCOperand Imm:16>> 311; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR 312; MIPS4-NEXT: # <MCOperand Reg:301>> 313; MIPS4-NEXT: sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW 314; MIPS4-NEXT: # <MCOperand Reg:1> 315; MIPS4-NEXT: # <MCOperand Reg:416> 316; MIPS4-NEXT: # <MCOperand Expr:(%lo(c))>> 317; 318; MIPS64R6-LABEL: f3: 319; MIPS64R6: # %bb.0: 320; MIPS64R6-NEXT: sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL 321; MIPS64R6-NEXT: # <MCOperand Reg:1> 322; MIPS64R6-NEXT: # <MCOperand Reg:22> 323; MIPS64R6-NEXT: # <MCOperand Imm:0>> 324; MIPS64R6-NEXT: lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64 325; MIPS64R6-NEXT: # <MCOperand Reg:416> 326; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>> 327; MIPS64R6-NEXT: daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu 328; MIPS64R6-NEXT: # <MCOperand Reg:416> 329; MIPS64R6-NEXT: # <MCOperand Reg:416> 330; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>> 331; MIPS64R6-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL 332; MIPS64R6-NEXT: # <MCOperand Reg:416> 333; MIPS64R6-NEXT: # <MCOperand Reg:416> 334; MIPS64R6-NEXT: # <MCOperand Imm:16>> 335; MIPS64R6-NEXT: daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu 336; MIPS64R6-NEXT: # <MCOperand Reg:416> 337; MIPS64R6-NEXT: # <MCOperand Reg:416> 338; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>> 339; MIPS64R6-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL 340; MIPS64R6-NEXT: # <MCOperand Reg:416> 341; MIPS64R6-NEXT: # <MCOperand Reg:416> 342; MIPS64R6-NEXT: # <MCOperand Imm:16>> 343; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64 344; MIPS64R6-NEXT: # <MCOperand Reg:355> 345; MIPS64R6-NEXT: # <MCOperand Reg:301>> 346; MIPS64R6-NEXT: sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW 347; MIPS64R6-NEXT: # <MCOperand Reg:1> 348; MIPS64R6-NEXT: # <MCOperand Reg:416> 349; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>> 350 store i32 %a, i32 * @c 351 ret void 352} 353 354define void @f4(i64 %a) { 355; MIPS32-LABEL: f4: 356; MIPS32: # %bb.0: 357; MIPS32-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi 358; MIPS32-NEXT: # <MCOperand Reg:1> 359; MIPS32-NEXT: # <MCOperand Expr:(%hi(d))>> 360; MIPS32-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW 361; MIPS32-NEXT: # <MCOperand Reg:22> 362; MIPS32-NEXT: # <MCOperand Reg:1> 363; MIPS32-NEXT: # <MCOperand Expr:(%lo(d))>> 364; MIPS32-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu 365; MIPS32-NEXT: # <MCOperand Reg:1> 366; MIPS32-NEXT: # <MCOperand Reg:1> 367; MIPS32-NEXT: # <MCOperand Expr:(%lo(d))>> 368; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR 369; MIPS32-NEXT: # <MCOperand Reg:19>> 370; MIPS32-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW 371; MIPS32-NEXT: # <MCOperand Reg:23> 372; MIPS32-NEXT: # <MCOperand Reg:1> 373; MIPS32-NEXT: # <MCOperand Imm:4>> 374; 375; MMR3-LABEL: f4: 376; MMR3: # %bb.0: 377; MMR3-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi 378; MMR3-NEXT: # <MCOperand Reg:1> 379; MMR3-NEXT: # <MCOperand Expr:(%hi(d))>> 380; MMR3-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM 381; MMR3-NEXT: # <MCOperand Reg:22> 382; MMR3-NEXT: # <MCOperand Reg:1> 383; MMR3-NEXT: # <MCOperand Expr:(%lo(d))>> 384; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu 385; MMR3-NEXT: # <MCOperand Reg:321> 386; MMR3-NEXT: # <MCOperand Reg:1> 387; MMR3-NEXT: # <MCOperand Expr:(%lo(d))>> 388; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM 389; MMR3-NEXT: # <MCOperand Reg:23> 390; MMR3-NEXT: # <MCOperand Reg:321> 391; MMR3-NEXT: # <MCOperand Imm:4>> 392; MMR3-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM 393; MMR3-NEXT: # <MCOperand Reg:19>> 394; 395; MIPS32R6-LABEL: f4: 396; MIPS32R6: # %bb.0: 397; MIPS32R6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi 398; MIPS32R6-NEXT: # <MCOperand Reg:1> 399; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(d))>> 400; MIPS32R6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW 401; MIPS32R6-NEXT: # <MCOperand Reg:22> 402; MIPS32R6-NEXT: # <MCOperand Reg:1> 403; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(d))>> 404; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu 405; MIPS32R6-NEXT: # <MCOperand Reg:1> 406; MIPS32R6-NEXT: # <MCOperand Reg:1> 407; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(d))>> 408; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR 409; MIPS32R6-NEXT: # <MCOperand Reg:21> 410; MIPS32R6-NEXT: # <MCOperand Reg:19>> 411; MIPS32R6-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW 412; MIPS32R6-NEXT: # <MCOperand Reg:23> 413; MIPS32R6-NEXT: # <MCOperand Reg:1> 414; MIPS32R6-NEXT: # <MCOperand Imm:4>> 415; 416; MMR6-LABEL: f4: 417; MMR6: # %bb.0: 418; MMR6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi 419; MMR6-NEXT: # <MCOperand Reg:1> 420; MMR6-NEXT: # <MCOperand Expr:(%hi(d))>> 421; MMR6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM 422; MMR6-NEXT: # <MCOperand Reg:22> 423; MMR6-NEXT: # <MCOperand Reg:1> 424; MMR6-NEXT: # <MCOperand Expr:(%lo(d))>> 425; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu 426; MMR6-NEXT: # <MCOperand Reg:321> 427; MMR6-NEXT: # <MCOperand Reg:1> 428; MMR6-NEXT: # <MCOperand Expr:(%lo(d))>> 429; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM 430; MMR6-NEXT: # <MCOperand Reg:23> 431; MMR6-NEXT: # <MCOperand Reg:321> 432; MMR6-NEXT: # <MCOperand Imm:4>> 433; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM 434; MMR6-NEXT: # <MCOperand Reg:19>> 435; 436; MIPS4-LABEL: f4: 437; MIPS4: # %bb.0: 438; MIPS4-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64 439; MIPS4-NEXT: # <MCOperand Reg:30> 440; MIPS4-NEXT: # <MCOperand Expr:(%highest(d))>> 441; MIPS4-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu 442; MIPS4-NEXT: # <MCOperand Reg:30> 443; MIPS4-NEXT: # <MCOperand Reg:30> 444; MIPS4-NEXT: # <MCOperand Expr:(%higher(d))>> 445; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 446; MIPS4-NEXT: # <MCOperand Reg:30> 447; MIPS4-NEXT: # <MCOperand Reg:30> 448; MIPS4-NEXT: # <MCOperand Imm:16>> 449; MIPS4-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu 450; MIPS4-NEXT: # <MCOperand Reg:30> 451; MIPS4-NEXT: # <MCOperand Reg:30> 452; MIPS4-NEXT: # <MCOperand Expr:(%hi(d))>> 453; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 454; MIPS4-NEXT: # <MCOperand Reg:30> 455; MIPS4-NEXT: # <MCOperand Reg:30> 456; MIPS4-NEXT: # <MCOperand Imm:16>> 457; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR 458; MIPS4-NEXT: # <MCOperand Reg:301>> 459; MIPS4-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD 460; MIPS4-NEXT: # <MCOperand Reg:356> 461; MIPS4-NEXT: # <MCOperand Reg:30> 462; MIPS4-NEXT: # <MCOperand Expr:(%lo(d))>> 463; 464; MIPS64R6-LABEL: f4: 465; MIPS64R6: # %bb.0: 466; MIPS64R6-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64 467; MIPS64R6-NEXT: # <MCOperand Reg:30> 468; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(d))>> 469; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu 470; MIPS64R6-NEXT: # <MCOperand Reg:30> 471; MIPS64R6-NEXT: # <MCOperand Reg:30> 472; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(d))>> 473; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 474; MIPS64R6-NEXT: # <MCOperand Reg:30> 475; MIPS64R6-NEXT: # <MCOperand Reg:30> 476; MIPS64R6-NEXT: # <MCOperand Imm:16>> 477; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu 478; MIPS64R6-NEXT: # <MCOperand Reg:30> 479; MIPS64R6-NEXT: # <MCOperand Reg:30> 480; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(d))>> 481; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL 482; MIPS64R6-NEXT: # <MCOperand Reg:30> 483; MIPS64R6-NEXT: # <MCOperand Reg:30> 484; MIPS64R6-NEXT: # <MCOperand Imm:16>> 485; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64 486; MIPS64R6-NEXT: # <MCOperand Reg:355> 487; MIPS64R6-NEXT: # <MCOperand Reg:301>> 488; MIPS64R6-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD 489; MIPS64R6-NEXT: # <MCOperand Reg:356> 490; MIPS64R6-NEXT: # <MCOperand Reg:30> 491; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(d))>> 492 store i64 %a, i64 * @d 493 ret void 494} 495